2 * RTL8XXXU mac80211 USB driver
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
41 #include "rtl8xxxu_regs.h"
43 #define DRIVER_NAME "rtl8xxxu"
45 static int rtl8xxxu_debug
= RTL8XXXU_DEBUG_EFUSE
;
46 static bool rtl8xxxu_ht40_2g
;
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
61 module_param_named(debug
, rtl8xxxu_debug
, int, 0600);
62 MODULE_PARM_DESC(debug
, "Set debug mask");
63 module_param_named(ht40_2g
, rtl8xxxu_ht40_2g
, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g
, "Enable HT40 support on the 2.4GHz band");
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv
*priv
,
76 struct rtl8xxxu_rx_urb
*rx_urb
);
78 static struct ieee80211_rate rtl8xxxu_rates
[] = {
79 { .bitrate
= 10, .hw_value
= DESC_RATE_1M
, .flags
= 0 },
80 { .bitrate
= 20, .hw_value
= DESC_RATE_2M
, .flags
= 0 },
81 { .bitrate
= 55, .hw_value
= DESC_RATE_5_5M
, .flags
= 0 },
82 { .bitrate
= 110, .hw_value
= DESC_RATE_11M
, .flags
= 0 },
83 { .bitrate
= 60, .hw_value
= DESC_RATE_6M
, .flags
= 0 },
84 { .bitrate
= 90, .hw_value
= DESC_RATE_9M
, .flags
= 0 },
85 { .bitrate
= 120, .hw_value
= DESC_RATE_12M
, .flags
= 0 },
86 { .bitrate
= 180, .hw_value
= DESC_RATE_18M
, .flags
= 0 },
87 { .bitrate
= 240, .hw_value
= DESC_RATE_24M
, .flags
= 0 },
88 { .bitrate
= 360, .hw_value
= DESC_RATE_36M
, .flags
= 0 },
89 { .bitrate
= 480, .hw_value
= DESC_RATE_48M
, .flags
= 0 },
90 { .bitrate
= 540, .hw_value
= DESC_RATE_54M
, .flags
= 0 },
93 static struct ieee80211_channel rtl8xxxu_channels_2g
[] = {
94 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2412,
95 .hw_value
= 1, .max_power
= 30 },
96 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2417,
97 .hw_value
= 2, .max_power
= 30 },
98 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2422,
99 .hw_value
= 3, .max_power
= 30 },
100 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2427,
101 .hw_value
= 4, .max_power
= 30 },
102 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2432,
103 .hw_value
= 5, .max_power
= 30 },
104 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2437,
105 .hw_value
= 6, .max_power
= 30 },
106 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2442,
107 .hw_value
= 7, .max_power
= 30 },
108 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2447,
109 .hw_value
= 8, .max_power
= 30 },
110 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2452,
111 .hw_value
= 9, .max_power
= 30 },
112 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2457,
113 .hw_value
= 10, .max_power
= 30 },
114 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2462,
115 .hw_value
= 11, .max_power
= 30 },
116 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2467,
117 .hw_value
= 12, .max_power
= 30 },
118 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2472,
119 .hw_value
= 13, .max_power
= 30 },
120 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2484,
121 .hw_value
= 14, .max_power
= 30 }
124 static struct ieee80211_supported_band rtl8xxxu_supported_band
= {
125 .channels
= rtl8xxxu_channels_2g
,
126 .n_channels
= ARRAY_SIZE(rtl8xxxu_channels_2g
),
127 .bitrates
= rtl8xxxu_rates
,
128 .n_bitrates
= ARRAY_SIZE(rtl8xxxu_rates
),
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table
[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table
[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
187 static struct rtl8xxxu_reg8val rtl8192e_mac_init_table
[] = {
188 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
189 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
190 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
191 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
192 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
193 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
194 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
195 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
196 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
197 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
198 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
199 {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
200 {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
201 {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
202 {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
203 {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
204 {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
205 {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
206 {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
207 {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
208 {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
209 {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
210 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
211 {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
212 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
217 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table
[] = {
218 {0x800, 0x80040000}, {0x804, 0x00000003},
219 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
220 {0x810, 0x10001331}, {0x814, 0x020c3d10},
221 {0x818, 0x02200385}, {0x81c, 0x00000000},
222 {0x820, 0x01000100}, {0x824, 0x00390004},
223 {0x828, 0x00000000}, {0x82c, 0x00000000},
224 {0x830, 0x00000000}, {0x834, 0x00000000},
225 {0x838, 0x00000000}, {0x83c, 0x00000000},
226 {0x840, 0x00010000}, {0x844, 0x00000000},
227 {0x848, 0x00000000}, {0x84c, 0x00000000},
228 {0x850, 0x00000000}, {0x854, 0x00000000},
229 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
230 {0x860, 0x66f60110}, {0x864, 0x061f0130},
231 {0x868, 0x00000000}, {0x86c, 0x32323200},
232 {0x870, 0x07000760}, {0x874, 0x22004000},
233 {0x878, 0x00000808}, {0x87c, 0x00000000},
234 {0x880, 0xc0083070}, {0x884, 0x000004d5},
235 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
236 {0x890, 0x00000800}, {0x894, 0xfffffffe},
237 {0x898, 0x40302010}, {0x89c, 0x00706050},
238 {0x900, 0x00000000}, {0x904, 0x00000023},
239 {0x908, 0x00000000}, {0x90c, 0x81121111},
240 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
241 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
242 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
243 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
244 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
245 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
246 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
248 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
249 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
250 {0xc10, 0x08800000}, {0xc14, 0x40000100},
251 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
252 {0xc20, 0x00000000}, {0xc24, 0x00000000},
253 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
254 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
255 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
256 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
257 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
258 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
259 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
260 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
261 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
262 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
263 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
264 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
265 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
266 {0xc90, 0x00121820}, {0xc94, 0x00000000},
267 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
268 {0xca0, 0x00000000}, {0xca4, 0x00000080},
269 {0xca8, 0x00000000}, {0xcac, 0x00000000},
270 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
271 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
272 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
273 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
274 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
275 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
276 {0xce0, 0x00222222}, {0xce4, 0x00000000},
277 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
278 {0xd00, 0x00080740}, {0xd04, 0x00020401},
279 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
280 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
281 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
282 {0xd30, 0x00000000}, {0xd34, 0x80608000},
283 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
284 {0xd40, 0x00000000}, {0xd44, 0x00000000},
285 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
286 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
287 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
288 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
289 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
290 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
291 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
292 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
293 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
294 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
295 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
296 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
297 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
298 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
299 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
300 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
301 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
302 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
303 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
304 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
305 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
306 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
307 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
308 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
309 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
310 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
312 {0xffff, 0xffffffff},
315 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table
[] = {
316 {0x800, 0x80040000}, {0x804, 0x00000003},
317 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
318 {0x810, 0x10001331}, {0x814, 0x020c3d10},
319 {0x818, 0x02200385}, {0x81c, 0x00000000},
320 {0x820, 0x01000100}, {0x824, 0x00190204},
321 {0x828, 0x00000000}, {0x82c, 0x00000000},
322 {0x830, 0x00000000}, {0x834, 0x00000000},
323 {0x838, 0x00000000}, {0x83c, 0x00000000},
324 {0x840, 0x00010000}, {0x844, 0x00000000},
325 {0x848, 0x00000000}, {0x84c, 0x00000000},
326 {0x850, 0x00000000}, {0x854, 0x00000000},
327 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
328 {0x860, 0x66f60110}, {0x864, 0x061f0649},
329 {0x868, 0x00000000}, {0x86c, 0x27272700},
330 {0x870, 0x07000760}, {0x874, 0x25004000},
331 {0x878, 0x00000808}, {0x87c, 0x00000000},
332 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
333 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
334 {0x890, 0x00000800}, {0x894, 0xfffffffe},
335 {0x898, 0x40302010}, {0x89c, 0x00706050},
336 {0x900, 0x00000000}, {0x904, 0x00000023},
337 {0x908, 0x00000000}, {0x90c, 0x81121111},
338 {0x910, 0x00000002}, {0x914, 0x00000201},
339 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
340 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
341 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
342 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
343 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
344 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
345 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
346 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
347 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
348 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
349 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
350 {0xc10, 0x08800000}, {0xc14, 0x40000100},
351 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
352 {0xc20, 0x00000000}, {0xc24, 0x00000000},
353 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
354 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
355 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
356 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
357 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
358 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
359 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
360 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
361 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
362 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
363 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
364 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
365 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
366 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
367 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
368 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
369 {0xca8, 0x00000000}, {0xcac, 0x00000000},
370 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
371 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
372 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
373 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
374 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
375 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
376 {0xce0, 0x00222222}, {0xce4, 0x00000000},
377 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
378 {0xd00, 0x00000740}, {0xd04, 0x40020401},
379 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
380 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
381 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
382 {0xd30, 0x00000000}, {0xd34, 0x80608000},
383 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
384 {0xd40, 0x00000000}, {0xd44, 0x00000000},
385 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
386 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
387 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
388 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
389 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
390 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
391 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
392 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
393 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
394 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
395 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
396 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
397 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
398 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
399 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
400 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
401 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
402 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
403 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
404 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
405 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
406 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
407 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
408 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
409 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
410 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
412 {0x820, 0x01000100}, {0x800, 0x83040000},
413 {0xffff, 0xffffffff},
416 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table
[] = {
417 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
418 {0x800, 0x80040002}, {0x804, 0x00000003},
419 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
420 {0x810, 0x10000330}, {0x814, 0x020c3d10},
421 {0x818, 0x02200385}, {0x81c, 0x00000000},
422 {0x820, 0x01000100}, {0x824, 0x00390004},
423 {0x828, 0x01000100}, {0x82c, 0x00390004},
424 {0x830, 0x27272727}, {0x834, 0x27272727},
425 {0x838, 0x27272727}, {0x83c, 0x27272727},
426 {0x840, 0x00010000}, {0x844, 0x00010000},
427 {0x848, 0x27272727}, {0x84c, 0x27272727},
428 {0x850, 0x00000000}, {0x854, 0x00000000},
429 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
430 {0x860, 0x66e60230}, {0x864, 0x061f0130},
431 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
432 {0x870, 0x07000700}, {0x874, 0x22184000},
433 {0x878, 0x08080808}, {0x87c, 0x00000000},
434 {0x880, 0xc0083070}, {0x884, 0x000004d5},
435 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
436 {0x890, 0x00000800}, {0x894, 0xfffffffe},
437 {0x898, 0x40302010}, {0x89c, 0x00706050},
438 {0x900, 0x00000000}, {0x904, 0x00000023},
439 {0x908, 0x00000000}, {0x90c, 0x81121313},
440 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
441 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
442 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
443 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
444 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
445 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
446 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
447 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
448 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
449 {0xc10, 0x08800000}, {0xc14, 0x40000100},
450 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
451 {0xc20, 0x00000000}, {0xc24, 0x00000000},
452 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
453 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
454 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
455 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
456 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
457 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
458 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
459 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
460 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
461 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
462 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
463 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
464 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
465 {0xc90, 0x00121820}, {0xc94, 0x00000000},
466 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
467 {0xca0, 0x00000000}, {0xca4, 0x00000080},
468 {0xca8, 0x00000000}, {0xcac, 0x00000000},
469 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
470 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
471 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
472 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
473 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
474 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
475 {0xce0, 0x00222222}, {0xce4, 0x00000000},
476 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
477 {0xd00, 0x00080740}, {0xd04, 0x00020403},
478 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
479 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
480 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
481 {0xd30, 0x00000000}, {0xd34, 0x80608000},
482 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
483 {0xd40, 0x00000000}, {0xd44, 0x00000000},
484 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
485 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
486 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
487 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
488 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
489 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
490 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
491 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
492 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
493 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
494 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
495 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
496 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
497 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
498 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
499 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
500 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
501 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
502 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
503 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
504 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
505 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
506 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
507 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
508 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
509 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
511 {0xffff, 0xffffffff},
514 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table
[] = {
515 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
516 {0x040, 0x000c0004}, {0x800, 0x80040000},
517 {0x804, 0x00000001}, {0x808, 0x0000fc00},
518 {0x80c, 0x0000000a}, {0x810, 0x10005388},
519 {0x814, 0x020c3d10}, {0x818, 0x02200385},
520 {0x81c, 0x00000000}, {0x820, 0x01000100},
521 {0x824, 0x00390204}, {0x828, 0x00000000},
522 {0x82c, 0x00000000}, {0x830, 0x00000000},
523 {0x834, 0x00000000}, {0x838, 0x00000000},
524 {0x83c, 0x00000000}, {0x840, 0x00010000},
525 {0x844, 0x00000000}, {0x848, 0x00000000},
526 {0x84c, 0x00000000}, {0x850, 0x00000000},
527 {0x854, 0x00000000}, {0x858, 0x569a569a},
528 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
529 {0x864, 0x061f0130}, {0x868, 0x00000000},
530 {0x86c, 0x20202000}, {0x870, 0x03000300},
531 {0x874, 0x22004000}, {0x878, 0x00000808},
532 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
533 {0x884, 0x000004d5}, {0x888, 0x00000000},
534 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
535 {0x894, 0xfffffffe}, {0x898, 0x40302010},
536 {0x89c, 0x00706050}, {0x900, 0x00000000},
537 {0x904, 0x00000023}, {0x908, 0x00000000},
538 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
539 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
540 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
541 {0xa14, 0x11144028}, {0xa18, 0x00881117},
542 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
543 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
544 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
545 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
546 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
547 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
548 {0xc14, 0x40000100}, {0xc18, 0x08800000},
549 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
550 {0xc24, 0x00000000}, {0xc28, 0x00000000},
551 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
552 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
553 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
554 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
555 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
556 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
557 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
558 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
559 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
560 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
561 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
562 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
563 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
564 {0xc94, 0x00000000}, {0xc98, 0x00121820},
565 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
566 {0xca4, 0x00000080}, {0xca8, 0x00000000},
567 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
568 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
569 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
570 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
571 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
572 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
573 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
574 {0xce4, 0x00000000}, {0xce8, 0x37644302},
575 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
576 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
577 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
578 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
579 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
580 {0xd34, 0x80608000}, {0xd38, 0x00000000},
581 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
582 {0xd44, 0x00000000}, {0xd48, 0x00000000},
583 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
584 {0xd54, 0x00000000}, {0xd58, 0x00000000},
585 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
586 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
587 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
588 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
589 {0xe00, 0x24242424}, {0xe04, 0x24242424},
590 {0xe08, 0x03902024}, {0xe10, 0x24242424},
591 {0xe14, 0x24242424}, {0xe18, 0x24242424},
592 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
593 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
594 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
595 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
596 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
597 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
598 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
599 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
600 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
601 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
602 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
603 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
604 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
605 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
606 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
607 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
608 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
610 {0xffff, 0xffffffff},
613 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table
[] = {
614 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
615 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
616 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
617 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
618 {0xc78, 0x78080001}, {0xc78, 0x77090001},
619 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
620 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
621 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
622 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
623 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
624 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
625 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
626 {0xc78, 0x68180001}, {0xc78, 0x67190001},
627 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
628 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
629 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
630 {0xc78, 0x60200001}, {0xc78, 0x49210001},
631 {0xc78, 0x48220001}, {0xc78, 0x47230001},
632 {0xc78, 0x46240001}, {0xc78, 0x45250001},
633 {0xc78, 0x44260001}, {0xc78, 0x43270001},
634 {0xc78, 0x42280001}, {0xc78, 0x41290001},
635 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
636 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
637 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
638 {0xc78, 0x21300001}, {0xc78, 0x20310001},
639 {0xc78, 0x06320001}, {0xc78, 0x05330001},
640 {0xc78, 0x04340001}, {0xc78, 0x03350001},
641 {0xc78, 0x02360001}, {0xc78, 0x01370001},
642 {0xc78, 0x00380001}, {0xc78, 0x00390001},
643 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
644 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
645 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
646 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
647 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
648 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
649 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
650 {0xc78, 0x78480001}, {0xc78, 0x77490001},
651 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
652 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
653 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
654 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
655 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
656 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
657 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
658 {0xc78, 0x68580001}, {0xc78, 0x67590001},
659 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
660 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
661 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
662 {0xc78, 0x60600001}, {0xc78, 0x49610001},
663 {0xc78, 0x48620001}, {0xc78, 0x47630001},
664 {0xc78, 0x46640001}, {0xc78, 0x45650001},
665 {0xc78, 0x44660001}, {0xc78, 0x43670001},
666 {0xc78, 0x42680001}, {0xc78, 0x41690001},
667 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
668 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
669 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
670 {0xc78, 0x21700001}, {0xc78, 0x20710001},
671 {0xc78, 0x06720001}, {0xc78, 0x05730001},
672 {0xc78, 0x04740001}, {0xc78, 0x03750001},
673 {0xc78, 0x02760001}, {0xc78, 0x01770001},
674 {0xc78, 0x00780001}, {0xc78, 0x00790001},
675 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
676 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
677 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
678 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
679 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
680 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
681 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
682 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
683 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
684 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
685 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
686 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
687 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
688 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
689 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
690 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
691 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
692 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
693 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
697 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table
[] = {
698 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
699 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
700 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
701 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
702 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
703 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
704 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
705 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
706 {0xc78, 0x73100001}, {0xc78, 0x72110001},
707 {0xc78, 0x71120001}, {0xc78, 0x70130001},
708 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
709 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
710 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
711 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
712 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
713 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
714 {0xc78, 0x63200001}, {0xc78, 0x62210001},
715 {0xc78, 0x61220001}, {0xc78, 0x60230001},
716 {0xc78, 0x46240001}, {0xc78, 0x45250001},
717 {0xc78, 0x44260001}, {0xc78, 0x43270001},
718 {0xc78, 0x42280001}, {0xc78, 0x41290001},
719 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
720 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
721 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
722 {0xc78, 0x21300001}, {0xc78, 0x20310001},
723 {0xc78, 0x06320001}, {0xc78, 0x05330001},
724 {0xc78, 0x04340001}, {0xc78, 0x03350001},
725 {0xc78, 0x02360001}, {0xc78, 0x01370001},
726 {0xc78, 0x00380001}, {0xc78, 0x00390001},
727 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
728 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
729 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
730 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
731 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
732 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
733 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
734 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
735 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
736 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
737 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
738 {0xc78, 0x73500001}, {0xc78, 0x72510001},
739 {0xc78, 0x71520001}, {0xc78, 0x70530001},
740 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
741 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
742 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
743 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
744 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
745 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
746 {0xc78, 0x63600001}, {0xc78, 0x62610001},
747 {0xc78, 0x61620001}, {0xc78, 0x60630001},
748 {0xc78, 0x46640001}, {0xc78, 0x45650001},
749 {0xc78, 0x44660001}, {0xc78, 0x43670001},
750 {0xc78, 0x42680001}, {0xc78, 0x41690001},
751 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
752 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
753 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
754 {0xc78, 0x21700001}, {0xc78, 0x20710001},
755 {0xc78, 0x06720001}, {0xc78, 0x05730001},
756 {0xc78, 0x04740001}, {0xc78, 0x03750001},
757 {0xc78, 0x02760001}, {0xc78, 0x01770001},
758 {0xc78, 0x00780001}, {0xc78, 0x00790001},
759 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
760 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
761 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
762 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
763 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
764 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
765 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
766 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
767 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
768 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
769 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
770 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
771 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
772 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
773 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
774 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
775 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
776 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
777 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
781 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table
[] = {
782 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
783 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
784 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
785 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
786 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
787 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
788 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
789 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
790 {0xc78, 0xed100001}, {0xc78, 0xec110001},
791 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
792 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
793 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
794 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
795 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
796 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
797 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
798 {0xc78, 0x65200001}, {0xc78, 0x64210001},
799 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
800 {0xc78, 0x49240001}, {0xc78, 0x48250001},
801 {0xc78, 0x47260001}, {0xc78, 0x46270001},
802 {0xc78, 0x45280001}, {0xc78, 0x44290001},
803 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
804 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
805 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
806 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
807 {0xc78, 0x08320001}, {0xc78, 0x07330001},
808 {0xc78, 0x06340001}, {0xc78, 0x05350001},
809 {0xc78, 0x04360001}, {0xc78, 0x03370001},
810 {0xc78, 0x02380001}, {0xc78, 0x01390001},
811 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
812 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
813 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
814 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
815 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
816 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
817 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
818 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
819 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
820 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
821 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
822 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
823 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
824 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
825 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
826 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
827 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
828 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
829 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
830 {0xc78, 0x65600001}, {0xc78, 0x64610001},
831 {0xc78, 0x63620001}, {0xc78, 0x62630001},
832 {0xc78, 0x61640001}, {0xc78, 0x48650001},
833 {0xc78, 0x47660001}, {0xc78, 0x46670001},
834 {0xc78, 0x45680001}, {0xc78, 0x44690001},
835 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
836 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
837 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
838 {0xc78, 0x24700001}, {0xc78, 0x09710001},
839 {0xc78, 0x08720001}, {0xc78, 0x07730001},
840 {0xc78, 0x06740001}, {0xc78, 0x05750001},
841 {0xc78, 0x04760001}, {0xc78, 0x03770001},
842 {0xc78, 0x02780001}, {0xc78, 0x01790001},
843 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
844 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
845 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
852 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table
[] = {
853 {0x00, 0x00030159}, {0x01, 0x00031284},
854 {0x02, 0x00098000}, {0x03, 0x00039c63},
855 {0x04, 0x000210e7}, {0x09, 0x0002044f},
856 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
857 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
858 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
859 {0x19, 0x00000000}, {0x1a, 0x00030355},
860 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
861 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
862 {0x1f, 0x00000000}, {0x20, 0x0000b614},
863 {0x21, 0x0006c000}, {0x22, 0x00000000},
864 {0x23, 0x00001558}, {0x24, 0x00000060},
865 {0x25, 0x00000483}, {0x26, 0x0004f000},
866 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
867 {0x29, 0x00004783}, {0x2a, 0x00000001},
868 {0x2b, 0x00021334}, {0x2a, 0x00000000},
869 {0x2b, 0x00000054}, {0x2a, 0x00000001},
870 {0x2b, 0x00000808}, {0x2b, 0x00053333},
871 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
872 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
873 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
874 {0x2b, 0x00000808}, {0x2b, 0x00063333},
875 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
876 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
877 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
878 {0x2b, 0x00000808}, {0x2b, 0x00073333},
879 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
880 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
881 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
882 {0x2b, 0x00000709}, {0x2b, 0x00063333},
883 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
884 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
885 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
886 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
887 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
888 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
889 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
890 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
891 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
892 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
893 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
894 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
895 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
896 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
897 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
898 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
899 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
900 {0x10, 0x0002000f}, {0x11, 0x000203f9},
901 {0x10, 0x0003000f}, {0x11, 0x000ff500},
902 {0x10, 0x00000000}, {0x11, 0x00000000},
903 {0x10, 0x0008000f}, {0x11, 0x0003f100},
904 {0x10, 0x0009000f}, {0x11, 0x00023100},
905 {0x12, 0x00032000}, {0x12, 0x00071000},
906 {0x12, 0x000b0000}, {0x12, 0x000fc000},
907 {0x13, 0x000287b3}, {0x13, 0x000244b7},
908 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
909 {0x13, 0x00018493}, {0x13, 0x0001429b},
910 {0x13, 0x00010299}, {0x13, 0x0000c29c},
911 {0x13, 0x000081a0}, {0x13, 0x000040ac},
912 {0x13, 0x00000020}, {0x14, 0x0001944c},
913 {0x14, 0x00059444}, {0x14, 0x0009944c},
914 {0x14, 0x000d9444}, {0x15, 0x0000f474},
915 {0x15, 0x0004f477}, {0x15, 0x0008f455},
916 {0x15, 0x000cf455}, {0x16, 0x00000339},
917 {0x16, 0x00040339}, {0x16, 0x00080339},
918 {0x16, 0x000c0366}, {0x00, 0x00010159},
919 {0x18, 0x0000f401}, {0xfe, 0x00000000},
920 {0xfe, 0x00000000}, {0x1f, 0x00000003},
921 {0xfe, 0x00000000}, {0xfe, 0x00000000},
922 {0x1e, 0x00000247}, {0x1f, 0x00000000},
927 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table
[] = {
928 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
929 {0xfe, 0x00000000}, {0xfe, 0x00000000},
930 {0xfe, 0x00000000}, {0xb1, 0x00000018},
931 {0xfe, 0x00000000}, {0xfe, 0x00000000},
932 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
933 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
934 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
935 {0x5c, 0x00000002}, {0x7c, 0x00000002},
936 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
937 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
938 {0x1e, 0x00000000}, {0xdf, 0x00000780},
941 * The 8723bu vendor driver indicates that bit 8 should be set in
942 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
943 * they never actually check the package type - and just default
947 {0x52, 0x000007d2}, {0x53, 0x00000000},
948 {0x54, 0x00050400}, {0x55, 0x0004026e},
949 {0xdd, 0x0000004c}, {0x70, 0x00067435},
951 * 0x71 has same package type condition as for register 0x51
954 {0x72, 0x000007d2}, {0x73, 0x00000000},
955 {0x74, 0x00050400}, {0x75, 0x0004026e},
956 {0xef, 0x00000100}, {0x34, 0x0000add7},
957 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
958 {0x35, 0x00005000}, {0x34, 0x00008dd1},
959 {0x35, 0x00004400}, {0x34, 0x00007dce},
960 {0x35, 0x00003800}, {0x34, 0x00006cd1},
961 {0x35, 0x00004400}, {0x34, 0x00005cce},
962 {0x35, 0x00003800}, {0x34, 0x000048ce},
963 {0x35, 0x00004400}, {0x34, 0x000034ce},
964 {0x35, 0x00003800}, {0x34, 0x00002451},
965 {0x35, 0x00004400}, {0x34, 0x0000144e},
966 {0x35, 0x00003800}, {0x34, 0x00000051},
967 {0x35, 0x00004400}, {0xef, 0x00000000},
968 {0xef, 0x00000100}, {0xed, 0x00000010},
969 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
970 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
971 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
972 {0x44, 0x000044d1}, {0x44, 0x000034ce},
973 {0x44, 0x00002451}, {0x44, 0x0000144e},
974 {0x44, 0x00000051}, {0xef, 0x00000000},
975 {0xed, 0x00000000}, {0x7f, 0x00020080},
976 {0xef, 0x00002000}, {0x3b, 0x000380ef},
977 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
978 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
979 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
980 {0x3b, 0x00000900}, {0xef, 0x00000000},
981 {0xed, 0x00000001}, {0x40, 0x000380ef},
982 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
983 {0x40, 0x000200bc}, {0x40, 0x000188a5},
984 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
985 {0x40, 0x00000900}, {0xed, 0x00000000},
986 {0x82, 0x00080000}, {0x83, 0x00008000},
987 {0x84, 0x00048d80}, {0x85, 0x00068000},
988 {0xa2, 0x00080000}, {0xa3, 0x00008000},
989 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
990 {0xed, 0x00000002}, {0xef, 0x00000002},
991 {0x56, 0x00000032}, {0x76, 0x00000032},
996 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table
[] = {
997 {0x00, 0x00030159}, {0x01, 0x00031284},
998 {0x02, 0x00098000}, {0x03, 0x00018c63},
999 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1000 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1001 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1002 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1003 {0x19, 0x00000000}, {0x1a, 0x00010255},
1004 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1005 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1006 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1007 {0x21, 0x0006c000}, {0x22, 0x00000000},
1008 {0x23, 0x00001558}, {0x24, 0x00000060},
1009 {0x25, 0x00000483}, {0x26, 0x0004f000},
1010 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1011 {0x29, 0x00004783}, {0x2a, 0x00000001},
1012 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1013 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1014 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1015 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1016 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1017 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1018 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1019 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1020 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1021 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1022 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1023 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1024 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1025 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1026 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1027 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1028 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1029 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1030 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1031 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1032 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1033 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1034 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1035 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1036 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1037 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1038 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1039 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1040 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1041 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1042 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1043 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1044 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1045 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1046 {0x10, 0x00000000}, {0x11, 0x00000000},
1047 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1048 {0x10, 0x0009000f}, {0x11, 0x00023100},
1049 {0x12, 0x00032000}, {0x12, 0x00071000},
1050 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1051 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1052 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1053 {0x13, 0x00018493}, {0x13, 0x0001429b},
1054 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1055 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1056 {0x13, 0x00000020}, {0x14, 0x0001944c},
1057 {0x14, 0x00059444}, {0x14, 0x0009944c},
1058 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1059 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1060 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1061 {0x16, 0x000a0330}, {0x16, 0x00060330},
1062 {0x16, 0x00020330}, {0x00, 0x00010159},
1063 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1064 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1065 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1066 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1071 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table
[] = {
1072 {0x00, 0x00030159}, {0x01, 0x00031284},
1073 {0x02, 0x00098000}, {0x03, 0x00018c63},
1074 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1075 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1076 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1077 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1078 {0x12, 0x00032000}, {0x12, 0x00071000},
1079 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1080 {0x13, 0x000287af}, {0x13, 0x000244b7},
1081 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1082 {0x13, 0x00018493}, {0x13, 0x00014297},
1083 {0x13, 0x00010295}, {0x13, 0x0000c298},
1084 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1085 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1086 {0x14, 0x00059444}, {0x14, 0x0009944c},
1087 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1088 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1089 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1090 {0x16, 0x000a0330}, {0x16, 0x00060330},
1095 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table
[] = {
1096 {0x00, 0x00030159}, {0x01, 0x00031284},
1097 {0x02, 0x00098000}, {0x03, 0x00018c63},
1098 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1099 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1100 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1101 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1102 {0x19, 0x00000000}, {0x1a, 0x00010255},
1103 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1104 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1105 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1106 {0x21, 0x0006c000}, {0x22, 0x00000000},
1107 {0x23, 0x00001558}, {0x24, 0x00000060},
1108 {0x25, 0x00000483}, {0x26, 0x0004f000},
1109 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1110 {0x29, 0x00004783}, {0x2a, 0x00000001},
1111 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1112 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1113 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1114 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1115 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1116 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1117 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1118 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1119 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1120 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1121 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1122 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1123 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1124 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1125 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1126 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1127 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1128 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1129 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1130 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1131 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1132 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1133 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1134 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1135 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1136 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1137 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1138 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1139 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1140 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1141 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1142 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1143 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1144 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1145 {0x10, 0x00000000}, {0x11, 0x00000000},
1146 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1147 {0x10, 0x0009000f}, {0x11, 0x00023100},
1148 {0x12, 0x00032000}, {0x12, 0x00071000},
1149 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1150 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1151 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1152 {0x13, 0x00018493}, {0x13, 0x0001429b},
1153 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1154 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1155 {0x13, 0x00000020}, {0x14, 0x0001944c},
1156 {0x14, 0x00059444}, {0x14, 0x0009944c},
1157 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1158 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1159 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1160 {0x16, 0x000a0330}, {0x16, 0x00060330},
1161 {0x16, 0x00020330}, {0x00, 0x00010159},
1162 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1163 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1164 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1165 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1170 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table
[] = {
1171 {0x00, 0x00030159}, {0x01, 0x00031284},
1172 {0x02, 0x00098000}, {0x03, 0x00018c63},
1173 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1174 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1175 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1176 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1177 {0x19, 0x00000000}, {0x1a, 0x00000255},
1178 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1179 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1180 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1181 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1182 {0x23, 0x00001558}, {0x24, 0x00000060},
1183 {0x25, 0x00000483}, {0x26, 0x0004f000},
1184 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1185 {0x29, 0x00004783}, {0x2a, 0x00000001},
1186 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1187 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1188 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1189 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1190 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1191 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1192 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1193 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1194 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1195 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1196 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1197 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1198 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1199 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1200 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1201 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1202 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1203 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1204 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1205 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1206 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1207 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1208 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1209 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1210 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1211 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1212 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1213 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1214 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1215 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1216 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1217 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1218 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1219 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1220 {0x10, 0x00000000}, {0x11, 0x00000000},
1221 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1222 {0x10, 0x0009000f}, {0x11, 0x00023100},
1223 {0x12, 0x000d8000}, {0x12, 0x00090000},
1224 {0x12, 0x00051000}, {0x12, 0x00012000},
1225 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1226 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1227 {0x13, 0x000183a4}, {0x13, 0x00014398},
1228 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1229 {0x13, 0x000080a4}, {0x13, 0x00004098},
1230 {0x13, 0x00000000}, {0x14, 0x0001944c},
1231 {0x14, 0x00059444}, {0x14, 0x0009944c},
1232 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1233 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1234 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1235 {0x16, 0x000a0330}, {0x16, 0x00060330},
1236 {0x16, 0x00020330}, {0x00, 0x00010159},
1237 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1238 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1239 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1240 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1245 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs
[] = {
1247 .hssiparm1
= REG_FPGA0_XA_HSSI_PARM1
,
1248 .hssiparm2
= REG_FPGA0_XA_HSSI_PARM2
,
1249 .lssiparm
= REG_FPGA0_XA_LSSI_PARM
,
1250 .hspiread
= REG_HSPI_XA_READBACK
,
1251 .lssiread
= REG_FPGA0_XA_LSSI_READBACK
,
1252 .rf_sw_ctrl
= REG_FPGA0_XA_RF_SW_CTRL
,
1255 .hssiparm1
= REG_FPGA0_XB_HSSI_PARM1
,
1256 .hssiparm2
= REG_FPGA0_XB_HSSI_PARM2
,
1257 .lssiparm
= REG_FPGA0_XB_LSSI_PARM
,
1258 .hspiread
= REG_HSPI_XB_READBACK
,
1259 .lssiread
= REG_FPGA0_XB_LSSI_READBACK
,
1260 .rf_sw_ctrl
= REG_FPGA0_XB_RF_SW_CTRL
,
1264 static const u32 rtl8723au_iqk_phy_iq_bb_reg
[RTL8XXXU_BB_REGS
] = {
1265 REG_OFDM0_XA_RX_IQ_IMBALANCE
,
1266 REG_OFDM0_XB_RX_IQ_IMBALANCE
,
1267 REG_OFDM0_ENERGY_CCA_THRES
,
1268 REG_OFDM0_AGCR_SSI_TABLE
,
1269 REG_OFDM0_XA_TX_IQ_IMBALANCE
,
1270 REG_OFDM0_XB_TX_IQ_IMBALANCE
,
1271 REG_OFDM0_XC_TX_AFE
,
1272 REG_OFDM0_XD_TX_AFE
,
1273 REG_OFDM0_RX_IQ_EXT_ANTA
1276 static u8
rtl8xxxu_read8(struct rtl8xxxu_priv
*priv
, u16 addr
)
1278 struct usb_device
*udev
= priv
->udev
;
1282 mutex_lock(&priv
->usb_buf_mutex
);
1283 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1284 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1285 addr
, 0, &priv
->usb_buf
.val8
, sizeof(u8
),
1286 RTW_USB_CONTROL_MSG_TIMEOUT
);
1287 data
= priv
->usb_buf
.val8
;
1288 mutex_unlock(&priv
->usb_buf_mutex
);
1290 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1291 dev_info(&udev
->dev
, "%s(%04x) = 0x%02x, len %i\n",
1292 __func__
, addr
, data
, len
);
1296 static u16
rtl8xxxu_read16(struct rtl8xxxu_priv
*priv
, u16 addr
)
1298 struct usb_device
*udev
= priv
->udev
;
1302 mutex_lock(&priv
->usb_buf_mutex
);
1303 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1304 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1305 addr
, 0, &priv
->usb_buf
.val16
, sizeof(u16
),
1306 RTW_USB_CONTROL_MSG_TIMEOUT
);
1307 data
= le16_to_cpu(priv
->usb_buf
.val16
);
1308 mutex_unlock(&priv
->usb_buf_mutex
);
1310 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1311 dev_info(&udev
->dev
, "%s(%04x) = 0x%04x, len %i\n",
1312 __func__
, addr
, data
, len
);
1316 static u32
rtl8xxxu_read32(struct rtl8xxxu_priv
*priv
, u16 addr
)
1318 struct usb_device
*udev
= priv
->udev
;
1322 mutex_lock(&priv
->usb_buf_mutex
);
1323 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1324 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1325 addr
, 0, &priv
->usb_buf
.val32
, sizeof(u32
),
1326 RTW_USB_CONTROL_MSG_TIMEOUT
);
1327 data
= le32_to_cpu(priv
->usb_buf
.val32
);
1328 mutex_unlock(&priv
->usb_buf_mutex
);
1330 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1331 dev_info(&udev
->dev
, "%s(%04x) = 0x%08x, len %i\n",
1332 __func__
, addr
, data
, len
);
1336 static int rtl8xxxu_write8(struct rtl8xxxu_priv
*priv
, u16 addr
, u8 val
)
1338 struct usb_device
*udev
= priv
->udev
;
1341 mutex_lock(&priv
->usb_buf_mutex
);
1342 priv
->usb_buf
.val8
= val
;
1343 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1344 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1345 addr
, 0, &priv
->usb_buf
.val8
, sizeof(u8
),
1346 RTW_USB_CONTROL_MSG_TIMEOUT
);
1348 mutex_unlock(&priv
->usb_buf_mutex
);
1350 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1351 dev_info(&udev
->dev
, "%s(%04x) = 0x%02x\n",
1352 __func__
, addr
, val
);
1356 static int rtl8xxxu_write16(struct rtl8xxxu_priv
*priv
, u16 addr
, u16 val
)
1358 struct usb_device
*udev
= priv
->udev
;
1361 mutex_lock(&priv
->usb_buf_mutex
);
1362 priv
->usb_buf
.val16
= cpu_to_le16(val
);
1363 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1364 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1365 addr
, 0, &priv
->usb_buf
.val16
, sizeof(u16
),
1366 RTW_USB_CONTROL_MSG_TIMEOUT
);
1367 mutex_unlock(&priv
->usb_buf_mutex
);
1369 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1370 dev_info(&udev
->dev
, "%s(%04x) = 0x%04x\n",
1371 __func__
, addr
, val
);
1375 static int rtl8xxxu_write32(struct rtl8xxxu_priv
*priv
, u16 addr
, u32 val
)
1377 struct usb_device
*udev
= priv
->udev
;
1380 mutex_lock(&priv
->usb_buf_mutex
);
1381 priv
->usb_buf
.val32
= cpu_to_le32(val
);
1382 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1383 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1384 addr
, 0, &priv
->usb_buf
.val32
, sizeof(u32
),
1385 RTW_USB_CONTROL_MSG_TIMEOUT
);
1386 mutex_unlock(&priv
->usb_buf_mutex
);
1388 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1389 dev_info(&udev
->dev
, "%s(%04x) = 0x%08x\n",
1390 __func__
, addr
, val
);
1395 rtl8xxxu_writeN(struct rtl8xxxu_priv
*priv
, u16 addr
, u8
*buf
, u16 len
)
1397 struct usb_device
*udev
= priv
->udev
;
1398 int blocksize
= priv
->fops
->writeN_block_size
;
1399 int ret
, i
, count
, remainder
;
1401 count
= len
/ blocksize
;
1402 remainder
= len
% blocksize
;
1404 for (i
= 0; i
< count
; i
++) {
1405 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1406 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1407 addr
, 0, buf
, blocksize
,
1408 RTW_USB_CONTROL_MSG_TIMEOUT
);
1409 if (ret
!= blocksize
)
1417 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1418 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1419 addr
, 0, buf
, remainder
,
1420 RTW_USB_CONTROL_MSG_TIMEOUT
);
1421 if (ret
!= remainder
)
1428 dev_info(&udev
->dev
,
1429 "%s: Failed to write block at addr: %04x size: %04x\n",
1430 __func__
, addr
, blocksize
);
1434 static u32
rtl8xxxu_read_rfreg(struct rtl8xxxu_priv
*priv
,
1435 enum rtl8xxxu_rfpath path
, u8 reg
)
1437 u32 hssia
, val32
, retval
;
1439 hssia
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_HSSI_PARM2
);
1441 val32
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hssiparm2
);
1445 val32
&= ~FPGA0_HSSI_PARM2_ADDR_MASK
;
1446 val32
|= (reg
<< FPGA0_HSSI_PARM2_ADDR_SHIFT
);
1447 val32
|= FPGA0_HSSI_PARM2_EDGE_READ
;
1448 hssia
&= ~FPGA0_HSSI_PARM2_EDGE_READ
;
1449 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM2
, hssia
);
1453 rtl8xxxu_write32(priv
, rtl8xxxu_rfregs
[path
].hssiparm2
, val32
);
1456 hssia
|= FPGA0_HSSI_PARM2_EDGE_READ
;
1457 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM2
, hssia
);
1460 val32
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hssiparm1
);
1461 if (val32
& FPGA0_HSSI_PARM1_PI
)
1462 retval
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hspiread
);
1464 retval
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].lssiread
);
1468 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_RFREG_READ
)
1469 dev_info(&priv
->udev
->dev
, "%s(%02x) = 0x%06x\n",
1470 __func__
, reg
, retval
);
1475 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1476 * have write issues in high temperature conditions. We may have to
1477 * retry writing them.
1479 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv
*priv
,
1480 enum rtl8xxxu_rfpath path
, u8 reg
, u32 data
)
1485 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_RFREG_WRITE
)
1486 dev_info(&priv
->udev
->dev
, "%s(%02x) = 0x%06x\n",
1487 __func__
, reg
, data
);
1489 data
&= FPGA0_LSSI_PARM_DATA_MASK
;
1490 dataaddr
= (reg
<< FPGA0_LSSI_PARM_ADDR_SHIFT
) | data
;
1492 /* Use XB for path B */
1493 ret
= rtl8xxxu_write32(priv
, rtl8xxxu_rfregs
[path
].lssiparm
, dataaddr
);
1494 if (ret
!= sizeof(dataaddr
))
1504 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv
*priv
,
1505 struct h2c_cmd
*h2c
, int len
)
1507 struct device
*dev
= &priv
->udev
->dev
;
1508 int mbox_nr
, retry
, retval
= 0;
1509 int mbox_reg
, mbox_ext_reg
;
1512 mutex_lock(&priv
->h2c_mutex
);
1514 mbox_nr
= priv
->next_mbox
;
1515 mbox_reg
= REG_HMBOX_0
+ (mbox_nr
* 4);
1516 mbox_ext_reg
= priv
->fops
->mbox_ext_reg
+
1517 (mbox_nr
* priv
->fops
->mbox_ext_width
);
1524 val8
= rtl8xxxu_read8(priv
, REG_HMTFR
);
1525 if (!(val8
& BIT(mbox_nr
)))
1530 dev_info(dev
, "%s: Mailbox busy\n", __func__
);
1536 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1538 if (len
> sizeof(u32
)) {
1539 if (priv
->fops
->mbox_ext_width
== 4) {
1540 rtl8xxxu_write32(priv
, mbox_ext_reg
,
1541 le32_to_cpu(h2c
->raw_wide
.ext
));
1542 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1543 dev_info(dev
, "H2C_EXT %08x\n",
1544 le32_to_cpu(h2c
->raw_wide
.ext
));
1546 rtl8xxxu_write16(priv
, mbox_ext_reg
,
1547 le16_to_cpu(h2c
->raw
.ext
));
1548 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1549 dev_info(dev
, "H2C_EXT %04x\n",
1550 le16_to_cpu(h2c
->raw
.ext
));
1553 rtl8xxxu_write32(priv
, mbox_reg
, le32_to_cpu(h2c
->raw
.data
));
1554 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1555 dev_info(dev
, "H2C %08x\n", le32_to_cpu(h2c
->raw
.data
));
1557 priv
->next_mbox
= (mbox_nr
+ 1) % H2C_MAX_MBOX
;
1560 mutex_unlock(&priv
->h2c_mutex
);
1564 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv
*priv
, u8 reg
, u8 data
)
1569 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
1570 h2c
.bt_mp_oper
.cmd
= H2C_8723B_BT_MP_OPER
;
1571 h2c
.bt_mp_oper
.operreq
= 0 | (reqnum
<< 4);
1572 h2c
.bt_mp_oper
.opcode
= BT_MP_OP_WRITE_REG_VALUE
;
1573 h2c
.bt_mp_oper
.data
= data
;
1574 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_mp_oper
));
1577 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
1578 h2c
.bt_mp_oper
.cmd
= H2C_8723B_BT_MP_OPER
;
1579 h2c
.bt_mp_oper
.operreq
= 0 | (reqnum
<< 4);
1580 h2c
.bt_mp_oper
.opcode
= BT_MP_OP_WRITE_REG_VALUE
;
1581 h2c
.bt_mp_oper
.addr
= reg
;
1582 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_mp_oper
));
1585 static void rtl8723a_enable_rf(struct rtl8xxxu_priv
*priv
)
1590 val8
= rtl8xxxu_read8(priv
, REG_SPS0_CTRL
);
1591 val8
|= BIT(0) | BIT(3);
1592 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, val8
);
1594 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_PARM
);
1595 val32
&= ~(BIT(4) | BIT(5));
1597 if (priv
->rf_paths
== 2) {
1598 val32
&= ~(BIT(20) | BIT(21));
1601 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_PARM
, val32
);
1603 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
1604 val32
&= ~OFDM_RF_PATH_TX_MASK
;
1605 if (priv
->tx_paths
== 2)
1606 val32
|= OFDM_RF_PATH_TX_A
| OFDM_RF_PATH_TX_B
;
1607 else if (priv
->rtl_chip
== RTL8192C
|| priv
->rtl_chip
== RTL8191C
)
1608 val32
|= OFDM_RF_PATH_TX_B
;
1610 val32
|= OFDM_RF_PATH_TX_A
;
1611 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
1613 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1614 val32
&= ~FPGA_RF_MODE_JAPAN
;
1615 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1617 if (priv
->rf_paths
== 2)
1618 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x63db25a0);
1620 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x631b25a0);
1622 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0x32d95);
1623 if (priv
->rf_paths
== 2)
1624 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0x32d95);
1626 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0x00);
1629 static void rtl8723a_disable_rf(struct rtl8xxxu_priv
*priv
)
1634 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
1636 sps0
= rtl8xxxu_read8(priv
, REG_SPS0_CTRL
);
1638 /* RF RX code for preamble power saving */
1639 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_PARM
);
1640 val32
&= ~(BIT(3) | BIT(4) | BIT(5));
1641 if (priv
->rf_paths
== 2)
1642 val32
&= ~(BIT(19) | BIT(20) | BIT(21));
1643 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_PARM
, val32
);
1645 /* Disable TX for four paths */
1646 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
1647 val32
&= ~OFDM_RF_PATH_TX_MASK
;
1648 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
1650 /* Enable power saving */
1651 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1652 val32
|= FPGA_RF_MODE_JAPAN
;
1653 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1655 /* AFE control register to power down bits [30:22] */
1656 if (priv
->rf_paths
== 2)
1657 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x00db25a0);
1659 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x001b25a0);
1661 /* Power down RF module */
1662 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0);
1663 if (priv
->rf_paths
== 2)
1664 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0);
1666 sps0
&= ~(BIT(0) | BIT(3));
1667 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, sps0
);
1671 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv
*priv
)
1675 val8
= rtl8xxxu_read8(priv
, REG_FWHW_TXQ_CTRL
+ 2);
1677 rtl8xxxu_write8(priv
, REG_FWHW_TXQ_CTRL
+ 2, val8
);
1679 rtl8xxxu_write8(priv
, REG_TBTT_PROHIBIT
+ 1, 0x64);
1680 val8
= rtl8xxxu_read8(priv
, REG_TBTT_PROHIBIT
+ 2);
1682 rtl8xxxu_write8(priv
, REG_TBTT_PROHIBIT
+ 2, val8
);
1687 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1688 * supports the 2.4GHz band, so channels 1 - 14:
1689 * group 0: channels 1 - 3
1690 * group 1: channels 4 - 9
1691 * group 2: channels 10 - 14
1693 * Note: We index from 0 in the code
1695 static int rtl8723a_channel_to_group(int channel
)
1701 else if (channel
< 10)
1709 static int rtl8723b_channel_to_group(int channel
)
1715 else if (channel
< 6)
1717 else if (channel
< 9)
1719 else if (channel
< 12)
1727 static void rtl8723au_config_channel(struct ieee80211_hw
*hw
)
1729 struct rtl8xxxu_priv
*priv
= hw
->priv
;
1733 int sec_ch_above
, channel
;
1736 opmode
= rtl8xxxu_read8(priv
, REG_BW_OPMODE
);
1737 rsr
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
1738 channel
= hw
->conf
.chandef
.chan
->hw_value
;
1740 switch (hw
->conf
.chandef
.width
) {
1741 case NL80211_CHAN_WIDTH_20_NOHT
:
1743 case NL80211_CHAN_WIDTH_20
:
1744 opmode
|= BW_OPMODE_20MHZ
;
1745 rtl8xxxu_write8(priv
, REG_BW_OPMODE
, opmode
);
1747 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1748 val32
&= ~FPGA_RF_MODE
;
1749 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1751 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1752 val32
&= ~FPGA_RF_MODE
;
1753 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1755 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_ANALOG2
);
1756 val32
|= FPGA0_ANALOG2_20MHZ
;
1757 rtl8xxxu_write32(priv
, REG_FPGA0_ANALOG2
, val32
);
1759 case NL80211_CHAN_WIDTH_40
:
1760 if (hw
->conf
.chandef
.center_freq1
>
1761 hw
->conf
.chandef
.chan
->center_freq
) {
1769 opmode
&= ~BW_OPMODE_20MHZ
;
1770 rtl8xxxu_write8(priv
, REG_BW_OPMODE
, opmode
);
1771 rsr
&= ~RSR_RSC_BANDWIDTH_40M
;
1773 rsr
|= RSR_RSC_UPPER_SUB_CHANNEL
;
1775 rsr
|= RSR_RSC_LOWER_SUB_CHANNEL
;
1776 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, rsr
);
1778 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1779 val32
|= FPGA_RF_MODE
;
1780 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1782 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1783 val32
|= FPGA_RF_MODE
;
1784 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1787 * Set Control channel to upper or lower. These settings
1788 * are required only for 40MHz
1790 val32
= rtl8xxxu_read32(priv
, REG_CCK0_SYSTEM
);
1791 val32
&= ~CCK0_SIDEBAND
;
1793 val32
|= CCK0_SIDEBAND
;
1794 rtl8xxxu_write32(priv
, REG_CCK0_SYSTEM
, val32
);
1796 val32
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
1797 val32
&= ~OFDM_LSTF_PRIME_CH_MASK
; /* 0xc00 */
1799 val32
|= OFDM_LSTF_PRIME_CH_LOW
;
1801 val32
|= OFDM_LSTF_PRIME_CH_HIGH
;
1802 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
1804 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_ANALOG2
);
1805 val32
&= ~FPGA0_ANALOG2_20MHZ
;
1806 rtl8xxxu_write32(priv
, REG_FPGA0_ANALOG2
, val32
);
1808 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
1809 val32
&= ~(FPGA0_PS_LOWER_CHANNEL
| FPGA0_PS_UPPER_CHANNEL
);
1811 val32
|= FPGA0_PS_UPPER_CHANNEL
;
1813 val32
|= FPGA0_PS_LOWER_CHANNEL
;
1814 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
1821 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1822 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1823 val32
&= ~MODE_AG_CHANNEL_MASK
;
1825 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1833 rtl8xxxu_write8(priv
, REG_SIFS_CCK
+ 1, val8
);
1834 rtl8xxxu_write8(priv
, REG_SIFS_OFDM
+ 1, val8
);
1836 rtl8xxxu_write16(priv
, REG_R2T_SIFS
, 0x0808);
1837 rtl8xxxu_write16(priv
, REG_T2T_SIFS
, 0x0a0a);
1839 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1840 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1841 if (hw
->conf
.chandef
.width
== NL80211_CHAN_WIDTH_40
)
1842 val32
&= ~MODE_AG_CHANNEL_20MHZ
;
1844 val32
|= MODE_AG_CHANNEL_20MHZ
;
1845 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1849 static void rtl8723bu_config_channel(struct ieee80211_hw
*hw
)
1851 struct rtl8xxxu_priv
*priv
= hw
->priv
;
1853 u8 val8
, subchannel
;
1856 int sec_ch_above
, channel
;
1859 rf_mode_bw
= rtl8xxxu_read16(priv
, REG_WMAC_TRXPTCL_CTL
);
1860 rf_mode_bw
&= ~WMAC_TRXPTCL_CTL_BW_MASK
;
1861 rsr
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
1862 channel
= hw
->conf
.chandef
.chan
->hw_value
;
1867 switch (hw
->conf
.chandef
.width
) {
1868 case NL80211_CHAN_WIDTH_20_NOHT
:
1870 case NL80211_CHAN_WIDTH_20
:
1871 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_20
;
1874 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1875 val32
&= ~FPGA_RF_MODE
;
1876 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1878 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1879 val32
&= ~FPGA_RF_MODE
;
1880 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1882 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TX_PSDO_NOISE_WEIGHT
);
1883 val32
&= ~(BIT(30) | BIT(31));
1884 rtl8xxxu_write32(priv
, REG_OFDM0_TX_PSDO_NOISE_WEIGHT
, val32
);
1887 case NL80211_CHAN_WIDTH_40
:
1888 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_40
;
1890 if (hw
->conf
.chandef
.center_freq1
>
1891 hw
->conf
.chandef
.chan
->center_freq
) {
1899 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
1900 val32
|= FPGA_RF_MODE
;
1901 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
1903 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
1904 val32
|= FPGA_RF_MODE
;
1905 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
1908 * Set Control channel to upper or lower. These settings
1909 * are required only for 40MHz
1911 val32
= rtl8xxxu_read32(priv
, REG_CCK0_SYSTEM
);
1912 val32
&= ~CCK0_SIDEBAND
;
1914 val32
|= CCK0_SIDEBAND
;
1915 rtl8xxxu_write32(priv
, REG_CCK0_SYSTEM
, val32
);
1917 val32
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
1918 val32
&= ~OFDM_LSTF_PRIME_CH_MASK
; /* 0xc00 */
1920 val32
|= OFDM_LSTF_PRIME_CH_LOW
;
1922 val32
|= OFDM_LSTF_PRIME_CH_HIGH
;
1923 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
1925 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
1926 val32
&= ~(FPGA0_PS_LOWER_CHANNEL
| FPGA0_PS_UPPER_CHANNEL
);
1928 val32
|= FPGA0_PS_UPPER_CHANNEL
;
1930 val32
|= FPGA0_PS_LOWER_CHANNEL
;
1931 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
1933 case NL80211_CHAN_WIDTH_80
:
1934 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_80
;
1940 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1941 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1942 val32
&= ~MODE_AG_CHANNEL_MASK
;
1944 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1947 rtl8xxxu_write16(priv
, REG_WMAC_TRXPTCL_CTL
, rf_mode_bw
);
1948 rtl8xxxu_write8(priv
, REG_DATA_SUBCHANNEL
, subchannel
);
1955 rtl8xxxu_write8(priv
, REG_SIFS_CCK
+ 1, val8
);
1956 rtl8xxxu_write8(priv
, REG_SIFS_OFDM
+ 1, val8
);
1958 rtl8xxxu_write16(priv
, REG_R2T_SIFS
, 0x0808);
1959 rtl8xxxu_write16(priv
, REG_T2T_SIFS
, 0x0a0a);
1961 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
1962 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
1963 val32
&= ~MODE_AG_BW_MASK
;
1964 switch(hw
->conf
.chandef
.width
) {
1965 case NL80211_CHAN_WIDTH_80
:
1966 val32
|= MODE_AG_BW_80MHZ_8723B
;
1968 case NL80211_CHAN_WIDTH_40
:
1969 val32
|= MODE_AG_BW_40MHZ_8723B
;
1972 val32
|= MODE_AG_BW_20MHZ_8723B
;
1975 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
1980 rtl8723a_set_tx_power(struct rtl8xxxu_priv
*priv
, int channel
, bool ht40
)
1982 u8 cck
[RTL8723A_MAX_RF_PATHS
], ofdm
[RTL8723A_MAX_RF_PATHS
];
1983 u8 ofdmbase
[RTL8723A_MAX_RF_PATHS
], mcsbase
[RTL8723A_MAX_RF_PATHS
];
1984 u32 val32
, ofdm_a
, ofdm_b
, mcs_a
, mcs_b
;
1988 group
= rtl8723a_channel_to_group(channel
);
1990 cck
[0] = priv
->cck_tx_power_index_A
[group
];
1991 cck
[1] = priv
->cck_tx_power_index_B
[group
];
1993 ofdm
[0] = priv
->ht40_1s_tx_power_index_A
[group
];
1994 ofdm
[1] = priv
->ht40_1s_tx_power_index_B
[group
];
1996 ofdmbase
[0] = ofdm
[0] + priv
->ofdm_tx_power_index_diff
[group
].a
;
1997 ofdmbase
[1] = ofdm
[1] + priv
->ofdm_tx_power_index_diff
[group
].b
;
1999 mcsbase
[0] = ofdm
[0];
2000 mcsbase
[1] = ofdm
[1];
2002 mcsbase
[0] += priv
->ht20_tx_power_index_diff
[group
].a
;
2003 mcsbase
[1] += priv
->ht20_tx_power_index_diff
[group
].b
;
2006 if (priv
->tx_paths
> 1) {
2007 if (ofdm
[0] > priv
->ht40_2s_tx_power_index_diff
[group
].a
)
2008 ofdm
[0] -= priv
->ht40_2s_tx_power_index_diff
[group
].a
;
2009 if (ofdm
[1] > priv
->ht40_2s_tx_power_index_diff
[group
].b
)
2010 ofdm
[1] -= priv
->ht40_2s_tx_power_index_diff
[group
].b
;
2013 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_CHANNEL
)
2014 dev_info(&priv
->udev
->dev
,
2015 "%s: Setting TX power CCK A: %02x, "
2016 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
2017 __func__
, cck
[0], cck
[1], ofdm
[0], ofdm
[1]);
2019 for (i
= 0; i
< RTL8723A_MAX_RF_PATHS
; i
++) {
2020 if (cck
[i
] > RF6052_MAX_TX_PWR
)
2021 cck
[i
] = RF6052_MAX_TX_PWR
;
2022 if (ofdm
[i
] > RF6052_MAX_TX_PWR
)
2023 ofdm
[i
] = RF6052_MAX_TX_PWR
;
2026 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_A_CCK1_MCS32
);
2027 val32
&= 0xffff00ff;
2028 val32
|= (cck
[0] << 8);
2029 rtl8xxxu_write32(priv
, REG_TX_AGC_A_CCK1_MCS32
, val32
);
2031 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2033 val32
|= ((cck
[0] << 8) | (cck
[0] << 16) | (cck
[0] << 24));
2034 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2036 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2037 val32
&= 0xffffff00;
2039 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2041 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
);
2043 val32
|= ((cck
[1] << 8) | (cck
[1] << 16) | (cck
[1] << 24));
2044 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
, val32
);
2046 ofdm_a
= ofdmbase
[0] | ofdmbase
[0] << 8 |
2047 ofdmbase
[0] << 16 | ofdmbase
[0] << 24;
2048 ofdm_b
= ofdmbase
[1] | ofdmbase
[1] << 8 |
2049 ofdmbase
[1] << 16 | ofdmbase
[1] << 24;
2050 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE18_06
, ofdm_a
);
2051 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE18_06
, ofdm_b
);
2053 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE54_24
, ofdm_a
);
2054 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE54_24
, ofdm_b
);
2056 mcs_a
= mcsbase
[0] | mcsbase
[0] << 8 |
2057 mcsbase
[0] << 16 | mcsbase
[0] << 24;
2058 mcs_b
= mcsbase
[1] | mcsbase
[1] << 8 |
2059 mcsbase
[1] << 16 | mcsbase
[1] << 24;
2061 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS03_MCS00
, mcs_a
);
2062 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS03_MCS00
, mcs_b
);
2064 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS07_MCS04
, mcs_a
);
2065 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS07_MCS04
, mcs_b
);
2067 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS11_MCS08
, mcs_a
);
2068 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS11_MCS08
, mcs_b
);
2070 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS15_MCS12
, mcs_a
);
2071 for (i
= 0; i
< 3; i
++) {
2073 val8
= (mcsbase
[0] > 8) ? (mcsbase
[0] - 8) : 0;
2075 val8
= (mcsbase
[0] > 6) ? (mcsbase
[0] - 6) : 0;
2076 rtl8xxxu_write8(priv
, REG_OFDM0_XC_TX_IQ_IMBALANCE
+ i
, val8
);
2078 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS15_MCS12
, mcs_b
);
2079 for (i
= 0; i
< 3; i
++) {
2081 val8
= (mcsbase
[1] > 8) ? (mcsbase
[1] - 8) : 0;
2083 val8
= (mcsbase
[1] > 6) ? (mcsbase
[1] - 6) : 0;
2084 rtl8xxxu_write8(priv
, REG_OFDM0_XD_TX_IQ_IMBALANCE
+ i
, val8
);
2089 rtl8723b_set_tx_power(struct rtl8xxxu_priv
*priv
, int channel
, bool ht40
)
2091 u32 val32
, ofdm
, mcs
;
2092 u8 cck
, ofdmbase
, mcsbase
;
2096 group
= rtl8723b_channel_to_group(channel
);
2098 cck
= priv
->cck_tx_power_index_B
[group
];
2099 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_A_CCK1_MCS32
);
2100 val32
&= 0xffff00ff;
2101 val32
|= (cck
<< 8);
2102 rtl8xxxu_write32(priv
, REG_TX_AGC_A_CCK1_MCS32
, val32
);
2104 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2106 val32
|= ((cck
<< 8) | (cck
<< 16) | (cck
<< 24));
2107 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2109 ofdmbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2110 ofdmbase
+= priv
->ofdm_tx_power_diff
[tx_idx
].b
;
2111 ofdm
= ofdmbase
| ofdmbase
<< 8 | ofdmbase
<< 16 | ofdmbase
<< 24;
2113 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE18_06
, ofdm
);
2114 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE54_24
, ofdm
);
2116 mcsbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2118 mcsbase
+= priv
->ht40_tx_power_diff
[tx_idx
++].b
;
2120 mcsbase
+= priv
->ht20_tx_power_diff
[tx_idx
++].b
;
2121 mcs
= mcsbase
| mcsbase
<< 8 | mcsbase
<< 16 | mcsbase
<< 24;
2123 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS03_MCS00
, mcs
);
2124 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS07_MCS04
, mcs
);
2127 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv
*priv
,
2128 enum nl80211_iftype linktype
)
2132 val8
= rtl8xxxu_read8(priv
, REG_MSR
);
2133 val8
&= ~MSR_LINKTYPE_MASK
;
2136 case NL80211_IFTYPE_UNSPECIFIED
:
2137 val8
|= MSR_LINKTYPE_NONE
;
2139 case NL80211_IFTYPE_ADHOC
:
2140 val8
|= MSR_LINKTYPE_ADHOC
;
2142 case NL80211_IFTYPE_STATION
:
2143 val8
|= MSR_LINKTYPE_STATION
;
2145 case NL80211_IFTYPE_AP
:
2146 val8
|= MSR_LINKTYPE_AP
;
2152 rtl8xxxu_write8(priv
, REG_MSR
, val8
);
2158 rtl8xxxu_set_retry(struct rtl8xxxu_priv
*priv
, u16 short_retry
, u16 long_retry
)
2162 val16
= ((short_retry
<< RETRY_LIMIT_SHORT_SHIFT
) &
2163 RETRY_LIMIT_SHORT_MASK
) |
2164 ((long_retry
<< RETRY_LIMIT_LONG_SHIFT
) &
2165 RETRY_LIMIT_LONG_MASK
);
2167 rtl8xxxu_write16(priv
, REG_RETRY_LIMIT
, val16
);
2171 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv
*priv
, u16 cck
, u16 ofdm
)
2175 val16
= ((cck
<< SPEC_SIFS_CCK_SHIFT
) & SPEC_SIFS_CCK_MASK
) |
2176 ((ofdm
<< SPEC_SIFS_OFDM_SHIFT
) & SPEC_SIFS_OFDM_MASK
);
2178 rtl8xxxu_write16(priv
, REG_SPEC_SIFS
, val16
);
2181 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv
*priv
)
2183 struct device
*dev
= &priv
->udev
->dev
;
2186 switch (priv
->chip_cut
) {
2207 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2208 priv
->chip_name
, cut
, priv
->chip_vendor
, priv
->tx_paths
,
2209 priv
->rx_paths
, priv
->ep_tx_count
, priv
->has_wifi
,
2210 priv
->has_bluetooth
, priv
->has_gps
, priv
->hi_pa
);
2212 dev_info(dev
, "RTL%s MAC: %pM\n", priv
->chip_name
, priv
->mac_addr
);
2215 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv
*priv
)
2217 struct device
*dev
= &priv
->udev
->dev
;
2221 val32
= rtl8xxxu_read32(priv
, REG_SYS_CFG
);
2222 priv
->chip_cut
= (val32
& SYS_CFG_CHIP_VERSION_MASK
) >>
2223 SYS_CFG_CHIP_VERSION_SHIFT
;
2224 if (val32
& SYS_CFG_TRP_VAUX_EN
) {
2225 dev_info(dev
, "Unsupported test chip\n");
2229 if (val32
& SYS_CFG_BT_FUNC
) {
2230 if (priv
->chip_cut
>= 3) {
2231 sprintf(priv
->chip_name
, "8723BU");
2232 priv
->rtl_chip
= RTL8723B
;
2234 sprintf(priv
->chip_name
, "8723AU");
2235 priv
->usb_interrupts
= 1;
2236 priv
->rtl_chip
= RTL8723A
;
2243 val32
= rtl8xxxu_read32(priv
, REG_MULTI_FUNC_CTRL
);
2244 if (val32
& MULTI_WIFI_FUNC_EN
)
2246 if (val32
& MULTI_BT_FUNC_EN
)
2247 priv
->has_bluetooth
= 1;
2248 if (val32
& MULTI_GPS_FUNC_EN
)
2250 priv
->is_multi_func
= 1;
2251 } else if (val32
& SYS_CFG_TYPE_ID
) {
2252 bonding
= rtl8xxxu_read32(priv
, REG_HPON_FSM
);
2253 bonding
&= HPON_FSM_BONDING_MASK
;
2254 if (priv
->fops
->has_s0s1
) {
2255 if (bonding
== HPON_FSM_BONDING_1T2R
) {
2256 sprintf(priv
->chip_name
, "8191EU");
2260 priv
->rtl_chip
= RTL8191E
;
2262 sprintf(priv
->chip_name
, "8192EU");
2266 priv
->rtl_chip
= RTL8192E
;
2268 } else if (bonding
== HPON_FSM_BONDING_1T2R
) {
2269 sprintf(priv
->chip_name
, "8191CU");
2273 priv
->usb_interrupts
= 1;
2274 priv
->rtl_chip
= RTL8191C
;
2276 sprintf(priv
->chip_name
, "8192CU");
2280 priv
->usb_interrupts
= 1;
2281 priv
->rtl_chip
= RTL8192C
;
2285 sprintf(priv
->chip_name
, "8188CU");
2289 priv
->rtl_chip
= RTL8188C
;
2290 priv
->usb_interrupts
= 1;
2294 switch (priv
->rtl_chip
) {
2298 switch (val32
& SYS_CFG_VENDOR_EXT_MASK
) {
2299 case SYS_CFG_VENDOR_ID_TSMC
:
2300 sprintf(priv
->chip_vendor
, "TSMC");
2302 case SYS_CFG_VENDOR_ID_SMIC
:
2303 sprintf(priv
->chip_vendor
, "SMIC");
2304 priv
->vendor_smic
= 1;
2306 case SYS_CFG_VENDOR_ID_UMC
:
2307 sprintf(priv
->chip_vendor
, "UMC");
2308 priv
->vendor_umc
= 1;
2311 sprintf(priv
->chip_vendor
, "unknown");
2315 if (val32
& SYS_CFG_VENDOR_ID
) {
2316 sprintf(priv
->chip_vendor
, "UMC");
2317 priv
->vendor_umc
= 1;
2319 sprintf(priv
->chip_vendor
, "TSMC");
2323 val32
= rtl8xxxu_read32(priv
, REG_GPIO_OUTSTS
);
2324 priv
->rom_rev
= (val32
& GPIO_RF_RL_ID
) >> 28;
2326 val16
= rtl8xxxu_read16(priv
, REG_NORMAL_SIE_EP_TX
);
2327 if (val16
& NORMAL_SIE_EP_TX_HIGH_MASK
) {
2328 priv
->ep_tx_high_queue
= 1;
2329 priv
->ep_tx_count
++;
2332 if (val16
& NORMAL_SIE_EP_TX_NORMAL_MASK
) {
2333 priv
->ep_tx_normal_queue
= 1;
2334 priv
->ep_tx_count
++;
2337 if (val16
& NORMAL_SIE_EP_TX_LOW_MASK
) {
2338 priv
->ep_tx_low_queue
= 1;
2339 priv
->ep_tx_count
++;
2343 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2345 if (!priv
->ep_tx_count
) {
2346 switch (priv
->nr_out_eps
) {
2349 priv
->ep_tx_low_queue
= 1;
2350 priv
->ep_tx_count
++;
2352 priv
->ep_tx_normal_queue
= 1;
2353 priv
->ep_tx_count
++;
2355 priv
->ep_tx_high_queue
= 1;
2356 priv
->ep_tx_count
++;
2359 dev_info(dev
, "Unsupported USB TX end-points\n");
2367 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv
*priv
)
2369 struct rtl8723au_efuse
*efuse
= &priv
->efuse_wifi
.efuse8723
;
2371 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2374 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2376 memcpy(priv
->cck_tx_power_index_A
,
2377 efuse
->cck_tx_power_index_A
,
2378 sizeof(efuse
->cck_tx_power_index_A
));
2379 memcpy(priv
->cck_tx_power_index_B
,
2380 efuse
->cck_tx_power_index_B
,
2381 sizeof(efuse
->cck_tx_power_index_B
));
2383 memcpy(priv
->ht40_1s_tx_power_index_A
,
2384 efuse
->ht40_1s_tx_power_index_A
,
2385 sizeof(efuse
->ht40_1s_tx_power_index_A
));
2386 memcpy(priv
->ht40_1s_tx_power_index_B
,
2387 efuse
->ht40_1s_tx_power_index_B
,
2388 sizeof(efuse
->ht40_1s_tx_power_index_B
));
2390 memcpy(priv
->ht20_tx_power_index_diff
,
2391 efuse
->ht20_tx_power_index_diff
,
2392 sizeof(efuse
->ht20_tx_power_index_diff
));
2393 memcpy(priv
->ofdm_tx_power_index_diff
,
2394 efuse
->ofdm_tx_power_index_diff
,
2395 sizeof(efuse
->ofdm_tx_power_index_diff
));
2397 memcpy(priv
->ht40_max_power_offset
,
2398 efuse
->ht40_max_power_offset
,
2399 sizeof(efuse
->ht40_max_power_offset
));
2400 memcpy(priv
->ht20_max_power_offset
,
2401 efuse
->ht20_max_power_offset
,
2402 sizeof(efuse
->ht20_max_power_offset
));
2404 if (priv
->efuse_wifi
.efuse8723
.version
>= 0x01) {
2405 priv
->has_xtalk
= 1;
2406 priv
->xtalk
= priv
->efuse_wifi
.efuse8723
.xtal_k
& 0x3f;
2408 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n",
2409 efuse
->vendor_name
);
2410 dev_info(&priv
->udev
->dev
, "Product: %.41s\n",
2411 efuse
->device_name
);
2415 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2417 struct rtl8723bu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8723bu
;
2420 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2423 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2425 memcpy(priv
->cck_tx_power_index_A
, efuse
->tx_power_index_A
.cck_base
,
2426 sizeof(efuse
->tx_power_index_A
.cck_base
));
2427 memcpy(priv
->cck_tx_power_index_B
, efuse
->tx_power_index_B
.cck_base
,
2428 sizeof(efuse
->tx_power_index_B
.cck_base
));
2430 memcpy(priv
->ht40_1s_tx_power_index_A
,
2431 efuse
->tx_power_index_A
.ht40_base
,
2432 sizeof(efuse
->tx_power_index_A
.ht40_base
));
2433 memcpy(priv
->ht40_1s_tx_power_index_B
,
2434 efuse
->tx_power_index_B
.ht40_base
,
2435 sizeof(efuse
->tx_power_index_B
.ht40_base
));
2437 priv
->ofdm_tx_power_diff
[0].a
=
2438 efuse
->tx_power_index_A
.ht20_ofdm_1s_diff
.a
;
2439 priv
->ofdm_tx_power_diff
[0].b
=
2440 efuse
->tx_power_index_B
.ht20_ofdm_1s_diff
.a
;
2442 priv
->ht20_tx_power_diff
[0].a
=
2443 efuse
->tx_power_index_A
.ht20_ofdm_1s_diff
.b
;
2444 priv
->ht20_tx_power_diff
[0].b
=
2445 efuse
->tx_power_index_B
.ht20_ofdm_1s_diff
.b
;
2447 priv
->ht40_tx_power_diff
[0].a
= 0;
2448 priv
->ht40_tx_power_diff
[0].b
= 0;
2450 for (i
= 1; i
< RTL8723B_TX_COUNT
; i
++) {
2451 priv
->ofdm_tx_power_diff
[i
].a
=
2452 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ofdm
;
2453 priv
->ofdm_tx_power_diff
[i
].b
=
2454 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ofdm
;
2456 priv
->ht20_tx_power_diff
[i
].a
=
2457 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht20
;
2458 priv
->ht20_tx_power_diff
[i
].b
=
2459 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht20
;
2461 priv
->ht40_tx_power_diff
[i
].a
=
2462 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht40
;
2463 priv
->ht40_tx_power_diff
[i
].b
=
2464 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht40
;
2467 priv
->has_xtalk
= 1;
2468 priv
->xtalk
= priv
->efuse_wifi
.efuse8723bu
.xtal_k
& 0x3f;
2470 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n", efuse
->vendor_name
);
2471 dev_info(&priv
->udev
->dev
, "Product: %.41s\n", efuse
->device_name
);
2473 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2475 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2477 dev_info(&priv
->udev
->dev
,
2478 "%s: dumping efuse (0x%02zx bytes):\n",
2479 __func__
, sizeof(struct rtl8723bu_efuse
));
2480 for (i
= 0; i
< sizeof(struct rtl8723bu_efuse
); i
+= 8) {
2481 dev_info(&priv
->udev
->dev
, "%02x: "
2482 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2483 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2484 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2485 raw
[i
+ 6], raw
[i
+ 7]);
2492 #ifdef CONFIG_RTL8XXXU_UNTESTED
2494 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2496 struct rtl8192cu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8192
;
2499 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2502 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2504 memcpy(priv
->cck_tx_power_index_A
,
2505 efuse
->cck_tx_power_index_A
,
2506 sizeof(efuse
->cck_tx_power_index_A
));
2507 memcpy(priv
->cck_tx_power_index_B
,
2508 efuse
->cck_tx_power_index_B
,
2509 sizeof(efuse
->cck_tx_power_index_B
));
2511 memcpy(priv
->ht40_1s_tx_power_index_A
,
2512 efuse
->ht40_1s_tx_power_index_A
,
2513 sizeof(efuse
->ht40_1s_tx_power_index_A
));
2514 memcpy(priv
->ht40_1s_tx_power_index_B
,
2515 efuse
->ht40_1s_tx_power_index_B
,
2516 sizeof(efuse
->ht40_1s_tx_power_index_B
));
2517 memcpy(priv
->ht40_2s_tx_power_index_diff
,
2518 efuse
->ht40_2s_tx_power_index_diff
,
2519 sizeof(efuse
->ht40_2s_tx_power_index_diff
));
2521 memcpy(priv
->ht20_tx_power_index_diff
,
2522 efuse
->ht20_tx_power_index_diff
,
2523 sizeof(efuse
->ht20_tx_power_index_diff
));
2524 memcpy(priv
->ofdm_tx_power_index_diff
,
2525 efuse
->ofdm_tx_power_index_diff
,
2526 sizeof(efuse
->ofdm_tx_power_index_diff
));
2528 memcpy(priv
->ht40_max_power_offset
,
2529 efuse
->ht40_max_power_offset
,
2530 sizeof(efuse
->ht40_max_power_offset
));
2531 memcpy(priv
->ht20_max_power_offset
,
2532 efuse
->ht20_max_power_offset
,
2533 sizeof(efuse
->ht20_max_power_offset
));
2535 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n",
2536 efuse
->vendor_name
);
2537 dev_info(&priv
->udev
->dev
, "Product: %.20s\n",
2538 efuse
->device_name
);
2540 if (efuse
->rf_regulatory
& 0x20) {
2541 sprintf(priv
->chip_name
, "8188RU");
2545 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2546 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2548 dev_info(&priv
->udev
->dev
,
2549 "%s: dumping efuse (0x%02zx bytes):\n",
2550 __func__
, sizeof(struct rtl8192cu_efuse
));
2551 for (i
= 0; i
< sizeof(struct rtl8192cu_efuse
); i
+= 8) {
2552 dev_info(&priv
->udev
->dev
, "%02x: "
2553 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2554 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2555 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2556 raw
[i
+ 6], raw
[i
+ 7]);
2564 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2566 struct rtl8192eu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8192eu
;
2569 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2572 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2574 priv
->has_xtalk
= 1;
2575 priv
->xtalk
= priv
->efuse_wifi
.efuse8192eu
.xtal_k
& 0x3f;
2577 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n", efuse
->vendor_name
);
2578 dev_info(&priv
->udev
->dev
, "Product: %.11s\n", efuse
->device_name
);
2579 dev_info(&priv
->udev
->dev
, "Serial: %.11s\n", efuse
->serial
);
2581 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2582 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2584 dev_info(&priv
->udev
->dev
,
2585 "%s: dumping efuse (0x%02zx bytes):\n",
2586 __func__
, sizeof(struct rtl8192eu_efuse
));
2587 for (i
= 0; i
< sizeof(struct rtl8192eu_efuse
); i
+= 8) {
2588 dev_info(&priv
->udev
->dev
, "%02x: "
2589 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2590 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2591 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2592 raw
[i
+ 6], raw
[i
+ 7]);
2596 * Temporarily disable 8192eu support
2603 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv
*priv
, u16 offset
, u8
*data
)
2610 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 1, offset
& 0xff);
2611 val8
= rtl8xxxu_read8(priv
, REG_EFUSE_CTRL
+ 2);
2613 val8
|= (offset
>> 8) & 0x03;
2614 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 2, val8
);
2616 val8
= rtl8xxxu_read8(priv
, REG_EFUSE_CTRL
+ 3);
2617 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 3, val8
& 0x7f);
2619 /* Poll for data read */
2620 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
2621 for (i
= 0; i
< RTL8XXXU_MAX_REG_POLL
; i
++) {
2622 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
2623 if (val32
& BIT(31))
2627 if (i
== RTL8XXXU_MAX_REG_POLL
)
2631 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
2633 *data
= val32
& 0xff;
2637 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv
*priv
)
2639 struct device
*dev
= &priv
->udev
->dev
;
2641 u8 val8
, word_mask
, header
, extheader
;
2642 u16 val16
, efuse_addr
, offset
;
2645 val16
= rtl8xxxu_read16(priv
, REG_9346CR
);
2646 if (val16
& EEPROM_ENABLE
)
2647 priv
->has_eeprom
= 1;
2648 if (val16
& EEPROM_BOOT
)
2649 priv
->boot_eeprom
= 1;
2651 if (priv
->is_multi_func
) {
2652 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_TEST
);
2653 val32
= (val32
& ~EFUSE_SELECT_MASK
) | EFUSE_WIFI_SELECT
;
2654 rtl8xxxu_write32(priv
, REG_EFUSE_TEST
, val32
);
2657 dev_dbg(dev
, "Booting from %s\n",
2658 priv
->boot_eeprom
? "EEPROM" : "EFUSE");
2660 rtl8xxxu_write8(priv
, REG_EFUSE_ACCESS
, EFUSE_ACCESS_ENABLE
);
2662 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2663 val16
= rtl8xxxu_read16(priv
, REG_SYS_ISO_CTRL
);
2664 if (!(val16
& SYS_ISO_PWC_EV12V
)) {
2665 val16
|= SYS_ISO_PWC_EV12V
;
2666 rtl8xxxu_write16(priv
, REG_SYS_ISO_CTRL
, val16
);
2668 /* Reset: 0x0000[28], default valid */
2669 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2670 if (!(val16
& SYS_FUNC_ELDR
)) {
2671 val16
|= SYS_FUNC_ELDR
;
2672 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
2676 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2678 val16
= rtl8xxxu_read16(priv
, REG_SYS_CLKR
);
2679 if (!(val16
& SYS_CLK_LOADER_ENABLE
) || !(val16
& SYS_CLK_ANA8M
)) {
2680 val16
|= (SYS_CLK_LOADER_ENABLE
| SYS_CLK_ANA8M
);
2681 rtl8xxxu_write16(priv
, REG_SYS_CLKR
, val16
);
2684 /* Default value is 0xff */
2685 memset(priv
->efuse_wifi
.raw
, 0xff, EFUSE_MAP_LEN
);
2688 while (efuse_addr
< EFUSE_REAL_CONTENT_LEN_8723A
) {
2691 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &header
);
2692 if (ret
|| header
== 0xff)
2695 if ((header
& 0x1f) == 0x0f) { /* extended header */
2696 offset
= (header
& 0xe0) >> 5;
2698 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++,
2702 /* All words disabled */
2703 if ((extheader
& 0x0f) == 0x0f)
2706 offset
|= ((extheader
& 0xf0) >> 1);
2707 word_mask
= extheader
& 0x0f;
2709 offset
= (header
>> 4) & 0x0f;
2710 word_mask
= header
& 0x0f;
2713 /* Get word enable value from PG header */
2715 /* We have 8 bits to indicate validity */
2716 map_addr
= offset
* 8;
2717 if (map_addr
>= EFUSE_MAP_LEN
) {
2718 dev_warn(dev
, "%s: Illegal map_addr (%04x), "
2720 __func__
, map_addr
);
2724 for (i
= 0; i
< EFUSE_MAX_WORD_UNIT
; i
++) {
2725 /* Check word enable condition in the section */
2726 if (word_mask
& BIT(i
)) {
2731 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &val8
);
2734 priv
->efuse_wifi
.raw
[map_addr
++] = val8
;
2736 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &val8
);
2739 priv
->efuse_wifi
.raw
[map_addr
++] = val8
;
2744 rtl8xxxu_write8(priv
, REG_EFUSE_ACCESS
, EFUSE_ACCESS_DISABLE
);
2749 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv
*priv
)
2754 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
2756 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
2758 sys_func
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2759 sys_func
&= ~SYS_FUNC_CPU_ENABLE
;
2760 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
2762 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
2764 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
2766 sys_func
|= SYS_FUNC_CPU_ENABLE
;
2767 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
2770 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv
*priv
)
2775 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
);
2777 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, val8
);
2779 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
2781 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
2783 sys_func
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2784 sys_func
&= ~SYS_FUNC_CPU_ENABLE
;
2785 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
2787 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
);
2789 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, val8
);
2791 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
2793 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
2795 sys_func
|= SYS_FUNC_CPU_ENABLE
;
2796 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
2799 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv
*priv
)
2801 struct device
*dev
= &priv
->udev
->dev
;
2805 /* Poll checksum report */
2806 for (i
= 0; i
< RTL8XXXU_FIRMWARE_POLL_MAX
; i
++) {
2807 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2808 if (val32
& MCU_FW_DL_CSUM_REPORT
)
2812 if (i
== RTL8XXXU_FIRMWARE_POLL_MAX
) {
2813 dev_warn(dev
, "Firmware checksum poll timed out\n");
2818 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2819 val32
|= MCU_FW_DL_READY
;
2820 val32
&= ~MCU_WINT_INIT_READY
;
2821 rtl8xxxu_write32(priv
, REG_MCU_FW_DL
, val32
);
2824 * Reset the 8051 in order for the firmware to start running,
2825 * otherwise it won't come up on the 8192eu
2827 priv
->fops
->reset_8051(priv
);
2829 /* Wait for firmware to become ready */
2830 for (i
= 0; i
< RTL8XXXU_FIRMWARE_POLL_MAX
; i
++) {
2831 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2832 if (val32
& MCU_WINT_INIT_READY
)
2838 if (i
== RTL8XXXU_FIRMWARE_POLL_MAX
) {
2839 dev_warn(dev
, "Firmware failed to start\n");
2847 if (priv
->rtl_chip
== RTL8723B
)
2848 rtl8xxxu_write8(priv
, REG_HMTFR
, 0x0f);
2853 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv
*priv
)
2855 int pages
, remainder
, i
, ret
;
2861 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
+ 1);
2863 rtl8xxxu_write8(priv
, REG_SYS_FUNC
+ 1, val8
);
2866 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
2867 val16
|= SYS_FUNC_CPU_ENABLE
;
2868 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
2870 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
2871 if (val8
& MCU_FW_RAM_SEL
) {
2872 pr_info("do the RAM reset\n");
2873 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
2874 priv
->fops
->reset_8051(priv
);
2877 /* MCU firmware download enable */
2878 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
2879 val8
|= MCU_FW_DL_ENABLE
;
2880 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, val8
);
2883 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
2885 rtl8xxxu_write32(priv
, REG_MCU_FW_DL
, val32
);
2887 /* Reset firmware download checksum */
2888 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
2889 val8
|= MCU_FW_DL_CSUM_REPORT
;
2890 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, val8
);
2892 pages
= priv
->fw_size
/ RTL_FW_PAGE_SIZE
;
2893 remainder
= priv
->fw_size
% RTL_FW_PAGE_SIZE
;
2895 fwptr
= priv
->fw_data
->data
;
2897 for (i
= 0; i
< pages
; i
++) {
2898 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
+ 2) & 0xF8;
2900 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
+ 2, val8
);
2902 ret
= rtl8xxxu_writeN(priv
, REG_FW_START_ADDRESS
,
2903 fwptr
, RTL_FW_PAGE_SIZE
);
2904 if (ret
!= RTL_FW_PAGE_SIZE
) {
2909 fwptr
+= RTL_FW_PAGE_SIZE
;
2913 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
+ 2) & 0xF8;
2915 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
+ 2, val8
);
2916 ret
= rtl8xxxu_writeN(priv
, REG_FW_START_ADDRESS
,
2918 if (ret
!= remainder
) {
2926 /* MCU firmware download disable */
2927 val16
= rtl8xxxu_read16(priv
, REG_MCU_FW_DL
);
2928 val16
&= ~MCU_FW_DL_ENABLE
;
2929 rtl8xxxu_write16(priv
, REG_MCU_FW_DL
, val16
);
2934 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv
*priv
, char *fw_name
)
2936 struct device
*dev
= &priv
->udev
->dev
;
2937 const struct firmware
*fw
;
2941 dev_info(dev
, "%s: Loading firmware %s\n", DRIVER_NAME
, fw_name
);
2942 if (request_firmware(&fw
, fw_name
, &priv
->udev
->dev
)) {
2943 dev_warn(dev
, "request_firmware(%s) failed\n", fw_name
);
2948 dev_warn(dev
, "Firmware data not available\n");
2953 priv
->fw_data
= kmemdup(fw
->data
, fw
->size
, GFP_KERNEL
);
2954 if (!priv
->fw_data
) {
2958 priv
->fw_size
= fw
->size
- sizeof(struct rtl8xxxu_firmware_header
);
2960 signature
= le16_to_cpu(priv
->fw_data
->signature
);
2961 switch (signature
& 0xfff0) {
2970 dev_warn(dev
, "%s: Invalid firmware signature: 0x%04x\n",
2971 __func__
, signature
);
2974 dev_info(dev
, "Firmware revision %i.%i (signature 0x%04x)\n",
2975 le16_to_cpu(priv
->fw_data
->major_version
),
2976 priv
->fw_data
->minor_version
, signature
);
2979 release_firmware(fw
);
2983 static int rtl8723au_load_firmware(struct rtl8xxxu_priv
*priv
)
2988 switch (priv
->chip_cut
) {
2990 fw_name
= "rtlwifi/rtl8723aufw_A.bin";
2993 if (priv
->enable_bluetooth
)
2994 fw_name
= "rtlwifi/rtl8723aufw_B.bin";
2996 fw_name
= "rtlwifi/rtl8723aufw_B_NoBT.bin";
3003 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
3007 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv
*priv
)
3012 if (priv
->enable_bluetooth
)
3013 fw_name
= "rtlwifi/rtl8723bu_bt.bin";
3015 fw_name
= "rtlwifi/rtl8723bu_nic.bin";
3017 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
3021 #ifdef CONFIG_RTL8XXXU_UNTESTED
3023 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv
*priv
)
3028 if (!priv
->vendor_umc
)
3029 fw_name
= "rtlwifi/rtl8192cufw_TMSC.bin";
3030 else if (priv
->chip_cut
|| priv
->rtl_chip
== RTL8192C
)
3031 fw_name
= "rtlwifi/rtl8192cufw_B.bin";
3033 fw_name
= "rtlwifi/rtl8192cufw_A.bin";
3035 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
3042 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv
*priv
)
3047 fw_name
= "rtlwifi/rtl8192eu_nic.bin";
3049 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
3054 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv
*priv
)
3059 /* Inform 8051 to perform reset */
3060 rtl8xxxu_write8(priv
, REG_HMTFR
+ 3, 0x20);
3062 for (i
= 100; i
> 0; i
--) {
3063 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3065 if (!(val16
& SYS_FUNC_CPU_ENABLE
)) {
3066 dev_dbg(&priv
->udev
->dev
,
3067 "%s: Firmware self reset success!\n", __func__
);
3074 /* Force firmware reset */
3075 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3076 val16
&= ~SYS_FUNC_CPU_ENABLE
;
3077 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3081 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv
*priv
)
3085 val32
= rtl8xxxu_read32(priv
, 0x64);
3086 val32
&= ~(BIT(20) | BIT(24));
3087 rtl8xxxu_write32(priv
, 0x64, val32
);
3089 val32
= rtl8xxxu_read32(priv
, REG_GPIO_MUXCFG
);
3091 rtl8xxxu_write32(priv
, REG_GPIO_MUXCFG
, val32
);
3093 val32
= rtl8xxxu_read32(priv
, REG_GPIO_MUXCFG
);
3095 rtl8xxxu_write32(priv
, REG_GPIO_MUXCFG
, val32
);
3097 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
3099 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
3101 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
3103 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
3105 val32
= rtl8xxxu_read32(priv
, REG_RFE_BUFFER
);
3106 val32
|= (BIT(0) | BIT(1));
3107 rtl8xxxu_write32(priv
, REG_RFE_BUFFER
, val32
);
3109 val32
= rtl8xxxu_read32(priv
, REG_RFE_CTRL_ANTA_SRC
);
3110 val32
&= 0xffffff00;
3112 rtl8xxxu_write32(priv
, REG_RFE_CTRL_ANTA_SRC
, val32
);
3114 val32
= rtl8xxxu_read32(priv
, REG_PWR_DATA
);
3115 val32
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
3116 rtl8xxxu_write32(priv
, REG_PWR_DATA
, val32
);
3120 rtl8xxxu_init_mac(struct rtl8xxxu_priv
*priv
)
3122 struct rtl8xxxu_reg8val
*array
= priv
->fops
->mactable
;
3127 for (i
= 0; ; i
++) {
3131 if (reg
== 0xffff && val
== 0xff)
3134 ret
= rtl8xxxu_write8(priv
, reg
, val
);
3136 dev_warn(&priv
->udev
->dev
,
3137 "Failed to initialize MAC "
3138 "(reg: %04x, val %02x)\n", reg
, val
);
3143 if (priv
->rtl_chip
!= RTL8723B
)
3144 rtl8xxxu_write8(priv
, REG_MAX_AGGR_NUM
, 0x0a);
3149 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv
*priv
,
3150 struct rtl8xxxu_reg32val
*array
)
3156 for (i
= 0; ; i
++) {
3160 if (reg
== 0xffff && val
== 0xffffffff)
3163 ret
= rtl8xxxu_write32(priv
, reg
, val
);
3164 if (ret
!= sizeof(val
)) {
3165 dev_warn(&priv
->udev
->dev
,
3166 "Failed to initialize PHY\n");
3176 * Most of this is black magic retrieved from the old rtl8723au driver
3178 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv
*priv
)
3180 u8 val8
, ldoa15
, ldov12d
, lpldo
, ldohci12
;
3185 * Todo: The vendor driver maintains a table of PHY register
3186 * addresses, which is initialized here. Do we need this?
3189 if (priv
->rtl_chip
== RTL8723B
) {
3190 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3191 val16
|= SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
|
3193 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3195 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
3197 val8
= rtl8xxxu_read8(priv
, REG_AFE_PLL_CTRL
);
3199 val8
|= AFE_PLL_320_ENABLE
;
3200 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
, val8
);
3203 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
+ 1, 0xff);
3206 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3207 val16
|= SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
;
3208 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3211 if (priv
->rtl_chip
!= RTL8723B
&& priv
->rtl_chip
!= RTL8192E
) {
3212 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3213 val32
= rtl8xxxu_read32(priv
, REG_AFE_XTAL_CTRL
);
3214 val32
&= ~AFE_XTAL_RF_GATE
;
3215 if (priv
->has_bluetooth
)
3216 val32
&= ~AFE_XTAL_BT_GATE
;
3217 rtl8xxxu_write32(priv
, REG_AFE_XTAL_CTRL
, val32
);
3220 /* 6. 0x1f[7:0] = 0x07 */
3221 val8
= RF_ENABLE
| RF_RSTB
| RF_SDMRSTB
;
3222 rtl8xxxu_write8(priv
, REG_RF_CTRL
, val8
);
3225 rtl8xxxu_init_phy_regs(priv
, rtl8188ru_phy_1t_highpa_table
);
3226 else if (priv
->tx_paths
== 2)
3227 rtl8xxxu_init_phy_regs(priv
, rtl8192cu_phy_2t_init_table
);
3228 else if (priv
->rtl_chip
== RTL8723B
) {
3232 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, 0xe3);
3233 rtl8xxxu_write8(priv
, REG_AFE_XTAL_CTRL
+ 1, 0x80);
3234 rtl8xxxu_init_phy_regs(priv
, rtl8723b_phy_1t_init_table
);
3236 rtl8xxxu_init_phy_regs(priv
, rtl8723a_phy_1t_init_table
);
3239 if (priv
->rtl_chip
== RTL8188C
&& priv
->hi_pa
&&
3240 priv
->vendor_umc
&& priv
->chip_cut
== 1)
3241 rtl8xxxu_write8(priv
, REG_OFDM0_AGC_PARM1
+ 2, 0x50);
3243 if (priv
->tx_paths
== 1 && priv
->rx_paths
== 2) {
3245 * For 1T2R boards, patch the registers.
3247 * It looks like 8191/2 1T2R boards use path B for TX
3249 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_TX_INFO
);
3250 val32
&= ~(BIT(0) | BIT(1));
3252 rtl8xxxu_write32(priv
, REG_FPGA0_TX_INFO
, val32
);
3254 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_TX_INFO
);
3257 rtl8xxxu_write32(priv
, REG_FPGA1_TX_INFO
, val32
);
3259 val32
= rtl8xxxu_read32(priv
, REG_CCK0_AFE_SETTING
);
3260 val32
&= 0xff000000;
3261 val32
|= 0x45000000;
3262 rtl8xxxu_write32(priv
, REG_CCK0_AFE_SETTING
, val32
);
3264 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
3265 val32
&= ~(OFDM_RF_PATH_RX_MASK
| OFDM_RF_PATH_TX_MASK
);
3266 val32
|= (OFDM_RF_PATH_RX_A
| OFDM_RF_PATH_RX_B
|
3268 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
3270 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_AGC_PARM1
);
3271 val32
&= ~(BIT(4) | BIT(5));
3273 rtl8xxxu_write32(priv
, REG_OFDM0_AGC_PARM1
, val32
);
3275 val32
= rtl8xxxu_read32(priv
, REG_TX_CCK_RFON
);
3276 val32
&= ~(BIT(27) | BIT(26));
3278 rtl8xxxu_write32(priv
, REG_TX_CCK_RFON
, val32
);
3280 val32
= rtl8xxxu_read32(priv
, REG_TX_CCK_BBON
);
3281 val32
&= ~(BIT(27) | BIT(26));
3283 rtl8xxxu_write32(priv
, REG_TX_CCK_BBON
, val32
);
3285 val32
= rtl8xxxu_read32(priv
, REG_TX_OFDM_RFON
);
3286 val32
&= ~(BIT(27) | BIT(26));
3288 rtl8xxxu_write32(priv
, REG_TX_OFDM_RFON
, val32
);
3290 val32
= rtl8xxxu_read32(priv
, REG_TX_OFDM_BBON
);
3291 val32
&= ~(BIT(27) | BIT(26));
3293 rtl8xxxu_write32(priv
, REG_TX_OFDM_BBON
, val32
);
3295 val32
= rtl8xxxu_read32(priv
, REG_TX_TO_TX
);
3296 val32
&= ~(BIT(27) | BIT(26));
3298 rtl8xxxu_write32(priv
, REG_TX_TO_TX
, val32
);
3301 if (priv
->rtl_chip
== RTL8723B
)
3302 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_8723bu_table
);
3303 else if (priv
->hi_pa
)
3304 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_highpa_table
);
3306 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_standard_table
);
3308 if (priv
->has_xtalk
) {
3309 val32
= rtl8xxxu_read32(priv
, REG_MAC_PHY_CTRL
);
3312 val32
&= 0xff000fff;
3313 val32
|= ((val8
| (val8
<< 6)) << 12);
3315 rtl8xxxu_write32(priv
, REG_MAC_PHY_CTRL
, val32
);
3318 if (priv
->rtl_chip
!= RTL8723B
&& priv
->rtl_chip
!= RTL8192E
) {
3319 ldoa15
= LDOA15_ENABLE
| LDOA15_OBUF
;
3320 ldov12d
= LDOV12D_ENABLE
| BIT(2) | (2 << LDOV12D_VADJ_SHIFT
);
3323 val32
= (lpldo
<< 24) | (ldohci12
<< 16) |
3324 (ldov12d
<< 8) | ldoa15
;
3326 rtl8xxxu_write32(priv
, REG_LDOA15_CTRL
, val32
);
3332 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv
*priv
,
3333 struct rtl8xxxu_rfregval
*array
,
3334 enum rtl8xxxu_rfpath path
)
3340 for (i
= 0; ; i
++) {
3344 if (reg
== 0xff && val
== 0xffffffff)
3368 ret
= rtl8xxxu_write_rfreg(priv
, path
, reg
, val
);
3370 dev_warn(&priv
->udev
->dev
,
3371 "Failed to initialize RF\n");
3380 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv
*priv
,
3381 struct rtl8xxxu_rfregval
*table
,
3382 enum rtl8xxxu_rfpath path
)
3385 u16 val16
, rfsi_rfenv
;
3386 u16 reg_sw_ctrl
, reg_int_oe
, reg_hssi_parm2
;
3390 reg_sw_ctrl
= REG_FPGA0_XA_RF_SW_CTRL
;
3391 reg_int_oe
= REG_FPGA0_XA_RF_INT_OE
;
3392 reg_hssi_parm2
= REG_FPGA0_XA_HSSI_PARM2
;
3395 reg_sw_ctrl
= REG_FPGA0_XB_RF_SW_CTRL
;
3396 reg_int_oe
= REG_FPGA0_XB_RF_INT_OE
;
3397 reg_hssi_parm2
= REG_FPGA0_XB_HSSI_PARM2
;
3400 dev_err(&priv
->udev
->dev
, "%s:Unsupported RF path %c\n",
3401 __func__
, path
+ 'A');
3404 /* For path B, use XB */
3405 rfsi_rfenv
= rtl8xxxu_read16(priv
, reg_sw_ctrl
);
3406 rfsi_rfenv
&= FPGA0_RF_RFENV
;
3409 * These two we might be able to optimize into one
3411 val32
= rtl8xxxu_read32(priv
, reg_int_oe
);
3412 val32
|= BIT(20); /* 0x10 << 16 */
3413 rtl8xxxu_write32(priv
, reg_int_oe
, val32
);
3416 val32
= rtl8xxxu_read32(priv
, reg_int_oe
);
3418 rtl8xxxu_write32(priv
, reg_int_oe
, val32
);
3422 * These two we might be able to optimize into one
3424 val32
= rtl8xxxu_read32(priv
, reg_hssi_parm2
);
3425 val32
&= ~FPGA0_HSSI_3WIRE_ADDR_LEN
;
3426 rtl8xxxu_write32(priv
, reg_hssi_parm2
, val32
);
3429 val32
= rtl8xxxu_read32(priv
, reg_hssi_parm2
);
3430 val32
&= ~FPGA0_HSSI_3WIRE_DATA_LEN
;
3431 rtl8xxxu_write32(priv
, reg_hssi_parm2
, val32
);
3434 rtl8xxxu_init_rf_regs(priv
, table
, path
);
3436 /* For path B, use XB */
3437 val16
= rtl8xxxu_read16(priv
, reg_sw_ctrl
);
3438 val16
&= ~FPGA0_RF_RFENV
;
3439 val16
|= rfsi_rfenv
;
3440 rtl8xxxu_write16(priv
, reg_sw_ctrl
, val16
);
3445 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv
*priv
, u8 address
, u8 data
)
3451 value
= LLT_OP_WRITE
| address
<< 8 | data
;
3453 rtl8xxxu_write32(priv
, REG_LLT_INIT
, value
);
3456 value
= rtl8xxxu_read32(priv
, REG_LLT_INIT
);
3457 if ((value
& LLT_OP_MASK
) == LLT_OP_INACTIVE
) {
3461 } while (count
++ < 20);
3466 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv
*priv
, u8 last_tx_page
)
3471 for (i
= 0; i
< last_tx_page
; i
++) {
3472 ret
= rtl8xxxu_llt_write(priv
, i
, i
+ 1);
3477 ret
= rtl8xxxu_llt_write(priv
, last_tx_page
, 0xff);
3481 /* Mark remaining pages as a ring buffer */
3482 for (i
= last_tx_page
+ 1; i
< 0xff; i
++) {
3483 ret
= rtl8xxxu_llt_write(priv
, i
, (i
+ 1));
3488 /* Let last entry point to the start entry of ring buffer */
3489 ret
= rtl8xxxu_llt_write(priv
, 0xff, last_tx_page
+ 1);
3497 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv
*priv
, u8 last_tx_page
)
3503 val32
= rtl8xxxu_read32(priv
, REG_AUTO_LLT
);
3504 val32
|= AUTO_LLT_INIT_LLT
;
3505 rtl8xxxu_write32(priv
, REG_AUTO_LLT
, val32
);
3507 for (i
= 500; i
; i
--) {
3508 val32
= rtl8xxxu_read32(priv
, REG_AUTO_LLT
);
3509 if (!(val32
& AUTO_LLT_INIT_LLT
))
3516 dev_warn(&priv
->udev
->dev
, "LLT table init failed\n");
3522 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv
*priv
)
3525 u16 hiq
, mgq
, bkq
, beq
, viq
, voq
;
3526 int hip
, mgp
, bkp
, bep
, vip
, vop
;
3529 switch (priv
->ep_tx_count
) {
3531 if (priv
->ep_tx_high_queue
) {
3532 hi
= TRXDMA_QUEUE_HIGH
;
3533 } else if (priv
->ep_tx_low_queue
) {
3534 hi
= TRXDMA_QUEUE_LOW
;
3535 } else if (priv
->ep_tx_normal_queue
) {
3536 hi
= TRXDMA_QUEUE_NORMAL
;
3557 if (priv
->ep_tx_high_queue
&& priv
->ep_tx_low_queue
) {
3558 hi
= TRXDMA_QUEUE_HIGH
;
3559 lo
= TRXDMA_QUEUE_LOW
;
3560 } else if (priv
->ep_tx_normal_queue
&& priv
->ep_tx_low_queue
) {
3561 hi
= TRXDMA_QUEUE_NORMAL
;
3562 lo
= TRXDMA_QUEUE_LOW
;
3563 } else if (priv
->ep_tx_high_queue
&& priv
->ep_tx_normal_queue
) {
3564 hi
= TRXDMA_QUEUE_HIGH
;
3565 lo
= TRXDMA_QUEUE_NORMAL
;
3587 beq
= TRXDMA_QUEUE_LOW
;
3588 bkq
= TRXDMA_QUEUE_LOW
;
3589 viq
= TRXDMA_QUEUE_NORMAL
;
3590 voq
= TRXDMA_QUEUE_HIGH
;
3591 mgq
= TRXDMA_QUEUE_HIGH
;
3592 hiq
= TRXDMA_QUEUE_HIGH
;
3606 * None of the vendor drivers are configuring the beacon
3607 * queue here .... why?
3610 val16
= rtl8xxxu_read16(priv
, REG_TRXDMA_CTRL
);
3612 val16
|= (voq
<< TRXDMA_CTRL_VOQ_SHIFT
) |
3613 (viq
<< TRXDMA_CTRL_VIQ_SHIFT
) |
3614 (beq
<< TRXDMA_CTRL_BEQ_SHIFT
) |
3615 (bkq
<< TRXDMA_CTRL_BKQ_SHIFT
) |
3616 (mgq
<< TRXDMA_CTRL_MGQ_SHIFT
) |
3617 (hiq
<< TRXDMA_CTRL_HIQ_SHIFT
);
3618 rtl8xxxu_write16(priv
, REG_TRXDMA_CTRL
, val16
);
3620 priv
->pipe_out
[TXDESC_QUEUE_VO
] =
3621 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[vop
]);
3622 priv
->pipe_out
[TXDESC_QUEUE_VI
] =
3623 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[vip
]);
3624 priv
->pipe_out
[TXDESC_QUEUE_BE
] =
3625 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[bep
]);
3626 priv
->pipe_out
[TXDESC_QUEUE_BK
] =
3627 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[bkp
]);
3628 priv
->pipe_out
[TXDESC_QUEUE_BEACON
] =
3629 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[0]);
3630 priv
->pipe_out
[TXDESC_QUEUE_MGNT
] =
3631 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[mgp
]);
3632 priv
->pipe_out
[TXDESC_QUEUE_HIGH
] =
3633 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[hip
]);
3634 priv
->pipe_out
[TXDESC_QUEUE_CMD
] =
3635 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[0]);
3641 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv
*priv
,
3642 bool iqk_ok
, int result
[][8],
3643 int candidate
, bool tx_only
)
3645 u32 oldval
, x
, tx0_a
, reg
;
3652 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
3653 oldval
= val32
>> 22;
3655 x
= result
[candidate
][0];
3656 if ((x
& 0x00000200) != 0)
3658 tx0_a
= (x
* oldval
) >> 8;
3660 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
3663 rtl8xxxu_write32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
, val32
);
3665 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3667 if ((x
* oldval
>> 7) & 0x1)
3669 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3671 y
= result
[candidate
][1];
3672 if ((y
& 0x00000200) != 0)
3674 tx0_c
= (y
* oldval
) >> 8;
3676 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XC_TX_AFE
);
3677 val32
&= ~0xf0000000;
3678 val32
|= (((tx0_c
& 0x3c0) >> 6) << 28);
3679 rtl8xxxu_write32(priv
, REG_OFDM0_XC_TX_AFE
, val32
);
3681 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
3682 val32
&= ~0x003f0000;
3683 val32
|= ((tx0_c
& 0x3f) << 16);
3684 rtl8xxxu_write32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
, val32
);
3686 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3688 if ((y
* oldval
>> 7) & 0x1)
3690 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3693 dev_dbg(&priv
->udev
->dev
, "%s: only TX\n", __func__
);
3697 reg
= result
[candidate
][2];
3699 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
);
3701 val32
|= (reg
& 0x3ff);
3702 rtl8xxxu_write32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
, val32
);
3704 reg
= result
[candidate
][3] & 0x3F;
3706 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
);
3708 val32
|= ((reg
<< 10) & 0xfc00);
3709 rtl8xxxu_write32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
, val32
);
3711 reg
= (result
[candidate
][3] >> 6) & 0xF;
3713 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_RX_IQ_EXT_ANTA
);
3714 val32
&= ~0xf0000000;
3715 val32
|= (reg
<< 28);
3716 rtl8xxxu_write32(priv
, REG_OFDM0_RX_IQ_EXT_ANTA
, val32
);
3719 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv
*priv
,
3720 bool iqk_ok
, int result
[][8],
3721 int candidate
, bool tx_only
)
3723 u32 oldval
, x
, tx1_a
, reg
;
3730 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
3731 oldval
= val32
>> 22;
3733 x
= result
[candidate
][4];
3734 if ((x
& 0x00000200) != 0)
3736 tx1_a
= (x
* oldval
) >> 8;
3738 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
3741 rtl8xxxu_write32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
, val32
);
3743 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3745 if ((x
* oldval
>> 7) & 0x1)
3747 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3749 y
= result
[candidate
][5];
3750 if ((y
& 0x00000200) != 0)
3752 tx1_c
= (y
* oldval
) >> 8;
3754 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XD_TX_AFE
);
3755 val32
&= ~0xf0000000;
3756 val32
|= (((tx1_c
& 0x3c0) >> 6) << 28);
3757 rtl8xxxu_write32(priv
, REG_OFDM0_XD_TX_AFE
, val32
);
3759 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
3760 val32
&= ~0x003f0000;
3761 val32
|= ((tx1_c
& 0x3f) << 16);
3762 rtl8xxxu_write32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
, val32
);
3764 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
3766 if ((y
* oldval
>> 7) & 0x1)
3768 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
3771 dev_dbg(&priv
->udev
->dev
, "%s: only TX\n", __func__
);
3775 reg
= result
[candidate
][6];
3777 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
);
3779 val32
|= (reg
& 0x3ff);
3780 rtl8xxxu_write32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
, val32
);
3782 reg
= result
[candidate
][7] & 0x3f;
3784 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
);
3786 val32
|= ((reg
<< 10) & 0xfc00);
3787 rtl8xxxu_write32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
, val32
);
3789 reg
= (result
[candidate
][7] >> 6) & 0xf;
3791 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_AGCR_SSI_TABLE
);
3792 val32
&= ~0x0000f000;
3793 val32
|= (reg
<< 12);
3794 rtl8xxxu_write32(priv
, REG_OFDM0_AGCR_SSI_TABLE
, val32
);
3797 #define MAX_TOLERANCE 5
3799 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv
*priv
,
3800 int result
[][8], int c1
, int c2
)
3802 u32 i
, j
, diff
, simubitmap
, bound
= 0;
3803 int candidate
[2] = {-1, -1}; /* for path A and path B */
3806 if (priv
->tx_paths
> 1)
3813 for (i
= 0; i
< bound
; i
++) {
3814 diff
= (result
[c1
][i
] > result
[c2
][i
]) ?
3815 (result
[c1
][i
] - result
[c2
][i
]) :
3816 (result
[c2
][i
] - result
[c1
][i
]);
3817 if (diff
> MAX_TOLERANCE
) {
3818 if ((i
== 2 || i
== 6) && !simubitmap
) {
3819 if (result
[c1
][i
] + result
[c1
][i
+ 1] == 0)
3820 candidate
[(i
/ 4)] = c2
;
3821 else if (result
[c2
][i
] + result
[c2
][i
+ 1] == 0)
3822 candidate
[(i
/ 4)] = c1
;
3824 simubitmap
= simubitmap
| (1 << i
);
3826 simubitmap
= simubitmap
| (1 << i
);
3831 if (simubitmap
== 0) {
3832 for (i
= 0; i
< (bound
/ 4); i
++) {
3833 if (candidate
[i
] >= 0) {
3834 for (j
= i
* 4; j
< (i
+ 1) * 4 - 2; j
++)
3835 result
[3][j
] = result
[candidate
[i
]][j
];
3840 } else if (!(simubitmap
& 0x0f)) {
3842 for (i
= 0; i
< 4; i
++)
3843 result
[3][i
] = result
[c1
][i
];
3844 } else if (!(simubitmap
& 0xf0) && priv
->tx_paths
> 1) {
3846 for (i
= 4; i
< 8; i
++)
3847 result
[3][i
] = result
[c1
][i
];
3853 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv
*priv
,
3854 int result
[][8], int c1
, int c2
)
3856 u32 i
, j
, diff
, simubitmap
, bound
= 0;
3857 int candidate
[2] = {-1, -1}; /* for path A and path B */
3861 if (priv
->tx_paths
> 1)
3868 for (i
= 0; i
< bound
; i
++) {
3870 if ((result
[c1
][i
] & 0x00000200))
3871 tmp1
= result
[c1
][i
] | 0xfffffc00;
3873 tmp1
= result
[c1
][i
];
3875 if ((result
[c2
][i
]& 0x00000200))
3876 tmp2
= result
[c2
][i
] | 0xfffffc00;
3878 tmp2
= result
[c2
][i
];
3880 tmp1
= result
[c1
][i
];
3881 tmp2
= result
[c2
][i
];
3884 diff
= (tmp1
> tmp2
) ? (tmp1
- tmp2
) : (tmp2
- tmp1
);
3886 if (diff
> MAX_TOLERANCE
) {
3887 if ((i
== 2 || i
== 6) && !simubitmap
) {
3888 if (result
[c1
][i
] + result
[c1
][i
+ 1] == 0)
3889 candidate
[(i
/ 4)] = c2
;
3890 else if (result
[c2
][i
] + result
[c2
][i
+ 1] == 0)
3891 candidate
[(i
/ 4)] = c1
;
3893 simubitmap
= simubitmap
| (1 << i
);
3895 simubitmap
= simubitmap
| (1 << i
);
3900 if (simubitmap
== 0) {
3901 for (i
= 0; i
< (bound
/ 4); i
++) {
3902 if (candidate
[i
] >= 0) {
3903 for (j
= i
* 4; j
< (i
+ 1) * 4 - 2; j
++)
3904 result
[3][j
] = result
[candidate
[i
]][j
];
3910 if (!(simubitmap
& 0x03)) {
3912 for (i
= 0; i
< 2; i
++)
3913 result
[3][i
] = result
[c1
][i
];
3916 if (!(simubitmap
& 0x0c)) {
3918 for (i
= 2; i
< 4; i
++)
3919 result
[3][i
] = result
[c1
][i
];
3922 if (!(simubitmap
& 0x30) && priv
->tx_paths
> 1) {
3924 for (i
= 4; i
< 6; i
++)
3925 result
[3][i
] = result
[c1
][i
];
3928 if (!(simubitmap
& 0x30) && priv
->tx_paths
> 1) {
3930 for (i
= 6; i
< 8; i
++)
3931 result
[3][i
] = result
[c1
][i
];
3939 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv
*priv
, const u32
*reg
, u32
*backup
)
3943 for (i
= 0; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
3944 backup
[i
] = rtl8xxxu_read8(priv
, reg
[i
]);
3946 backup
[i
] = rtl8xxxu_read32(priv
, reg
[i
]);
3949 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv
*priv
,
3950 const u32
*reg
, u32
*backup
)
3954 for (i
= 0; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
3955 rtl8xxxu_write8(priv
, reg
[i
], backup
[i
]);
3957 rtl8xxxu_write32(priv
, reg
[i
], backup
[i
]);
3960 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
3961 u32
*backup
, int count
)
3965 for (i
= 0; i
< count
; i
++)
3966 backup
[i
] = rtl8xxxu_read32(priv
, regs
[i
]);
3969 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
3970 u32
*backup
, int count
)
3974 for (i
= 0; i
< count
; i
++)
3975 rtl8xxxu_write32(priv
, regs
[i
], backup
[i
]);
3979 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
3985 if (priv
->tx_paths
== 1) {
3986 path_on
= priv
->fops
->adda_1t_path_on
;
3987 rtl8xxxu_write32(priv
, regs
[0], priv
->fops
->adda_1t_init
);
3989 path_on
= path_a_on
? priv
->fops
->adda_2t_path_on_a
:
3990 priv
->fops
->adda_2t_path_on_b
;
3992 rtl8xxxu_write32(priv
, regs
[0], path_on
);
3995 for (i
= 1 ; i
< RTL8XXXU_ADDA_REGS
; i
++)
3996 rtl8xxxu_write32(priv
, regs
[i
], path_on
);
3999 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv
*priv
,
4000 const u32
*regs
, u32
*backup
)
4004 rtl8xxxu_write8(priv
, regs
[i
], 0x3f);
4006 for (i
= 1 ; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
4007 rtl8xxxu_write8(priv
, regs
[i
], (u8
)(backup
[i
] & ~BIT(3)));
4009 rtl8xxxu_write8(priv
, regs
[i
], (u8
)(backup
[i
] & ~BIT(5)));
4012 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4014 u32 reg_eac
, reg_e94
, reg_e9c
, reg_ea4
, val32
;
4017 /* path-A IQK setting */
4018 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x10008c1f);
4019 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x10008c1f);
4020 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82140102);
4022 val32
= (priv
->rf_paths
> 1) ? 0x28160202 :
4023 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
4025 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, val32
);
4027 /* path-B IQK setting */
4028 if (priv
->rf_paths
> 1) {
4029 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x10008c22);
4030 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x10008c22);
4031 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82140102);
4032 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28160202);
4035 /* LO calibration setting */
4036 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x001028d1);
4038 /* One shot, path A LOK & IQK */
4039 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4040 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4045 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4046 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4047 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4048 reg_ea4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_A_2
);
4050 if (!(reg_eac
& BIT(28)) &&
4051 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4052 ((reg_e9c
& 0x03ff0000) != 0x00420000))
4054 else /* If TX not OK, ignore RX */
4057 /* If TX is OK, check whether RX is OK */
4058 if (!(reg_eac
& BIT(27)) &&
4059 ((reg_ea4
& 0x03ff0000) != 0x01320000) &&
4060 ((reg_eac
& 0x03ff0000) != 0x00360000))
4063 dev_warn(&priv
->udev
->dev
, "%s: Path A RX IQK failed!\n",
4069 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv
*priv
)
4071 u32 reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
4074 /* One shot, path B LOK & IQK */
4075 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000002);
4076 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000000);
4081 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4082 reg_eb4
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4083 reg_ebc
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4084 reg_ec4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4085 reg_ecc
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4087 if (!(reg_eac
& BIT(31)) &&
4088 ((reg_eb4
& 0x03ff0000) != 0x01420000) &&
4089 ((reg_ebc
& 0x03ff0000) != 0x00420000))
4094 if (!(reg_eac
& BIT(30)) &&
4095 (((reg_ec4
& 0x03ff0000) >> 16) != 0x132) &&
4096 (((reg_ecc
& 0x03ff0000) >> 16) != 0x36))
4099 dev_warn(&priv
->udev
->dev
, "%s: Path B RX IQK failed!\n",
4105 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4107 u32 reg_eac
, reg_e94
, reg_e9c
, path_sel
, val32
;
4110 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4115 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4116 val32
&= 0x000000ff;
4117 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4120 * Enable path A PA in TX IQK mode
4122 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4124 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4125 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x20000);
4126 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0003f);
4127 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xc7f87);
4132 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4133 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4135 /* path-A IQK setting */
4136 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
4137 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
4138 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4139 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4141 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x821403ea);
4142 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28110000);
4143 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4144 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4146 /* LO calibration setting */
4147 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x00462911);
4152 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4153 val32
&= 0x000000ff;
4154 val32
|= 0x80800000;
4155 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4158 * The vendor driver indicates the USB module is always using
4159 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4161 if (priv
->rf_paths
> 1)
4162 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4164 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4167 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4168 * No trace of this in the 8192eu or 8188eu vendor drivers.
4170 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4172 /* One shot, path A LOK & IQK */
4173 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4174 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4178 /* Restore Ant Path */
4179 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4182 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4188 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4189 val32
&= 0x000000ff;
4190 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4193 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4194 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4195 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4197 val32
= (reg_e9c
>> 16) & 0x3ff;
4199 val32
= 0x400 - val32
;
4201 if (!(reg_eac
& BIT(28)) &&
4202 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4203 ((reg_e9c
& 0x03ff0000) != 0x00420000) &&
4204 ((reg_e94
& 0x03ff0000) < 0x01100000) &&
4205 ((reg_e94
& 0x03ff0000) > 0x00f00000) &&
4208 else /* If TX not OK, ignore RX */
4215 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4217 u32 reg_ea4
, reg_eac
, reg_e94
, reg_e9c
, path_sel
, val32
;
4220 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4225 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4226 val32
&= 0x000000ff;
4227 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4230 * Enable path A PA in TX IQK mode
4232 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4234 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4235 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4236 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4237 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7fb7);
4242 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4243 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4245 /* path-A IQK setting */
4246 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
4247 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
4248 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4249 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4251 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82160ff0);
4252 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28110000);
4253 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4254 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4256 /* LO calibration setting */
4257 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a911);
4262 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4263 val32
&= 0x000000ff;
4264 val32
|= 0x80800000;
4265 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4268 * The vendor driver indicates the USB module is always using
4269 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4271 if (priv
->rf_paths
> 1)
4272 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4274 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4277 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4278 * No trace of this in the 8192eu or 8188eu vendor drivers.
4280 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4282 /* One shot, path A LOK & IQK */
4283 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4284 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4288 /* Restore Ant Path */
4289 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4292 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4298 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4299 val32
&= 0x000000ff;
4300 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4303 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4304 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4305 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4307 val32
= (reg_e9c
>> 16) & 0x3ff;
4309 val32
= 0x400 - val32
;
4311 if (!(reg_eac
& BIT(28)) &&
4312 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4313 ((reg_e9c
& 0x03ff0000) != 0x00420000) &&
4314 ((reg_e94
& 0x03ff0000) < 0x01100000) &&
4315 ((reg_e94
& 0x03ff0000) > 0x00f00000) &&
4318 else /* If TX not OK, ignore RX */
4321 val32
= 0x80007c00 | (reg_e94
&0x3ff0000) |
4322 ((reg_e9c
& 0x3ff0000) >> 16);
4323 rtl8xxxu_write32(priv
, REG_TX_IQK
, val32
);
4326 * Modify RX IQK mode
4328 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4329 val32
&= 0x000000ff;
4330 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4331 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4333 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4334 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4335 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4336 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7d77);
4341 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0xf80);
4342 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_55
, 0x4021f);
4347 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4349 /* path-A IQK setting */
4350 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x38008c1c);
4351 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x18008c1c);
4352 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4353 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4355 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82110000);
4356 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x2816001f);
4357 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4358 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4360 /* LO calibration setting */
4361 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a8d1);
4366 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4367 val32
&= 0x000000ff;
4368 val32
|= 0x80800000;
4369 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4371 if (priv
->rf_paths
> 1)
4372 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4374 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4379 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4381 /* One shot, path A LOK & IQK */
4382 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4383 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4387 /* Restore Ant Path */
4388 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4391 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4397 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4398 val32
&= 0x000000ff;
4399 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4402 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4403 reg_ea4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_A_2
);
4405 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0x780);
4407 val32
= (reg_eac
>> 16) & 0x3ff;
4409 val32
= 0x400 - val32
;
4411 if (!(reg_eac
& BIT(27)) &&
4412 ((reg_ea4
& 0x03ff0000) != 0x01320000) &&
4413 ((reg_eac
& 0x03ff0000) != 0x00360000) &&
4414 ((reg_ea4
& 0x03ff0000) < 0x01100000) &&
4415 ((reg_ea4
& 0x03ff0000) > 0x00f00000) &&
4418 else /* If TX not OK, ignore RX */
4424 #ifdef RTL8723BU_PATH_B
4425 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv
*priv
)
4427 u32 reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
, path_sel
;
4430 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4432 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4433 val32
&= 0x000000ff;
4434 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4436 /* One shot, path B LOK & IQK */
4437 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000002);
4438 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000000);
4443 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4444 reg_eb4
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4445 reg_ebc
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4446 reg_ec4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4447 reg_ecc
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4449 if (!(reg_eac
& BIT(31)) &&
4450 ((reg_eb4
& 0x03ff0000) != 0x01420000) &&
4451 ((reg_ebc
& 0x03ff0000) != 0x00420000))
4456 if (!(reg_eac
& BIT(30)) &&
4457 (((reg_ec4
& 0x03ff0000) >> 16) != 0x132) &&
4458 (((reg_ecc
& 0x03ff0000) >> 16) != 0x36))
4461 dev_warn(&priv
->udev
->dev
, "%s: Path B RX IQK failed!\n",
4468 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv
*priv
,
4469 int result
[][8], int t
)
4471 struct device
*dev
= &priv
->udev
->dev
;
4473 int path_a_ok
, path_b_ok
;
4475 const u32 adda_regs
[RTL8XXXU_ADDA_REGS
] = {
4476 REG_FPGA0_XCD_SWITCH_CTRL
, REG_BLUETOOTH
,
4477 REG_RX_WAIT_CCA
, REG_TX_CCK_RFON
,
4478 REG_TX_CCK_BBON
, REG_TX_OFDM_RFON
,
4479 REG_TX_OFDM_BBON
, REG_TX_TO_RX
,
4480 REG_TX_TO_TX
, REG_RX_CCK
,
4481 REG_RX_OFDM
, REG_RX_WAIT_RIFS
,
4482 REG_RX_TO_RX
, REG_STANDBY
,
4483 REG_SLEEP
, REG_PMPD_ANAEN
4485 const u32 iqk_mac_regs
[RTL8XXXU_MAC_REGS
] = {
4486 REG_TXPAUSE
, REG_BEACON_CTRL
,
4487 REG_BEACON_CTRL_1
, REG_GPIO_MUXCFG
4489 const u32 iqk_bb_regs
[RTL8XXXU_BB_REGS
] = {
4490 REG_OFDM0_TRX_PATH_ENABLE
, REG_OFDM0_TR_MUX_PAR
,
4491 REG_FPGA0_XCD_RF_SW_CTRL
, REG_CONFIG_ANT_A
, REG_CONFIG_ANT_B
,
4492 REG_FPGA0_XAB_RF_SW_CTRL
, REG_FPGA0_XA_RF_INT_OE
,
4493 REG_FPGA0_XB_RF_INT_OE
, REG_FPGA0_RF_MODE
4497 * Note: IQ calibration must be performed after loading
4498 * PHY_REG.txt , and radio_a, radio_b.txt
4502 /* Save ADDA parameters, turn Path A ADDA on */
4503 rtl8xxxu_save_regs(priv
, adda_regs
, priv
->adda_backup
,
4504 RTL8XXXU_ADDA_REGS
);
4505 rtl8xxxu_save_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4506 rtl8xxxu_save_regs(priv
, iqk_bb_regs
,
4507 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4510 rtl8xxxu_path_adda_on(priv
, adda_regs
, true);
4513 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_HSSI_PARM1
);
4514 if (val32
& FPGA0_HSSI_PARM1_PI
)
4515 priv
->pi_enabled
= 1;
4518 if (!priv
->pi_enabled
) {
4519 /* Switch BB to PI mode to do IQ Calibration. */
4520 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM1
, 0x01000100);
4521 rtl8xxxu_write32(priv
, REG_FPGA0_XB_HSSI_PARM1
, 0x01000100);
4524 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
4525 val32
&= ~FPGA_RF_MODE_CCK
;
4526 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
4528 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, 0x03a05600);
4529 rtl8xxxu_write32(priv
, REG_OFDM0_TR_MUX_PAR
, 0x000800e4);
4530 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_SW_CTRL
, 0x22204000);
4532 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
);
4533 val32
|= (FPGA0_RF_PAPE
| (FPGA0_RF_PAPE
<< FPGA0_RF_BD_CTRL_SHIFT
));
4534 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
, val32
);
4536 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_RF_INT_OE
);
4538 rtl8xxxu_write32(priv
, REG_FPGA0_XA_RF_INT_OE
, val32
);
4539 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XB_RF_INT_OE
);
4541 rtl8xxxu_write32(priv
, REG_FPGA0_XB_RF_INT_OE
, val32
);
4543 if (priv
->tx_paths
> 1) {
4544 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00010000);
4545 rtl8xxxu_write32(priv
, REG_FPGA0_XB_LSSI_PARM
, 0x00010000);
4549 rtl8xxxu_mac_calibration(priv
, iqk_mac_regs
, priv
->mac_backup
);
4552 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_A
, 0x00080000);
4554 if (priv
->tx_paths
> 1)
4555 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_B
, 0x00080000);
4557 /* IQ calibration setting */
4558 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
4559 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4560 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4562 for (i
= 0; i
< retry
; i
++) {
4563 path_a_ok
= rtl8xxxu_iqk_path_a(priv
);
4564 if (path_a_ok
== 0x03) {
4565 val32
= rtl8xxxu_read32(priv
,
4566 REG_TX_POWER_BEFORE_IQK_A
);
4567 result
[t
][0] = (val32
>> 16) & 0x3ff;
4568 val32
= rtl8xxxu_read32(priv
,
4569 REG_TX_POWER_AFTER_IQK_A
);
4570 result
[t
][1] = (val32
>> 16) & 0x3ff;
4571 val32
= rtl8xxxu_read32(priv
,
4572 REG_RX_POWER_BEFORE_IQK_A_2
);
4573 result
[t
][2] = (val32
>> 16) & 0x3ff;
4574 val32
= rtl8xxxu_read32(priv
,
4575 REG_RX_POWER_AFTER_IQK_A_2
);
4576 result
[t
][3] = (val32
>> 16) & 0x3ff;
4578 } else if (i
== (retry
- 1) && path_a_ok
== 0x01) {
4580 dev_dbg(dev
, "%s: Path A IQK Only Tx Success!!\n",
4583 val32
= rtl8xxxu_read32(priv
,
4584 REG_TX_POWER_BEFORE_IQK_A
);
4585 result
[t
][0] = (val32
>> 16) & 0x3ff;
4586 val32
= rtl8xxxu_read32(priv
,
4587 REG_TX_POWER_AFTER_IQK_A
);
4588 result
[t
][1] = (val32
>> 16) & 0x3ff;
4593 dev_dbg(dev
, "%s: Path A IQK failed!\n", __func__
);
4595 if (priv
->tx_paths
> 1) {
4597 * Path A into standby
4599 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x0);
4600 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00010000);
4601 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
4603 /* Turn Path B ADDA on */
4604 rtl8xxxu_path_adda_on(priv
, adda_regs
, false);
4606 for (i
= 0; i
< retry
; i
++) {
4607 path_b_ok
= rtl8xxxu_iqk_path_b(priv
);
4608 if (path_b_ok
== 0x03) {
4609 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4610 result
[t
][4] = (val32
>> 16) & 0x3ff;
4611 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4612 result
[t
][5] = (val32
>> 16) & 0x3ff;
4613 val32
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4614 result
[t
][6] = (val32
>> 16) & 0x3ff;
4615 val32
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4616 result
[t
][7] = (val32
>> 16) & 0x3ff;
4618 } else if (i
== (retry
- 1) && path_b_ok
== 0x01) {
4620 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4621 result
[t
][4] = (val32
>> 16) & 0x3ff;
4622 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4623 result
[t
][5] = (val32
>> 16) & 0x3ff;
4628 dev_dbg(dev
, "%s: Path B IQK failed!\n", __func__
);
4631 /* Back to BB mode, load original value */
4632 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0);
4635 if (!priv
->pi_enabled
) {
4637 * Switch back BB to SI mode after finishing
4641 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM1
, val32
);
4642 rtl8xxxu_write32(priv
, REG_FPGA0_XB_HSSI_PARM1
, val32
);
4645 /* Reload ADDA power saving parameters */
4646 rtl8xxxu_restore_regs(priv
, adda_regs
, priv
->adda_backup
,
4647 RTL8XXXU_ADDA_REGS
);
4649 /* Reload MAC parameters */
4650 rtl8xxxu_restore_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4652 /* Reload BB parameters */
4653 rtl8xxxu_restore_regs(priv
, iqk_bb_regs
,
4654 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4656 /* Restore RX initial gain */
4657 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00032ed3);
4659 if (priv
->tx_paths
> 1) {
4660 rtl8xxxu_write32(priv
, REG_FPGA0_XB_LSSI_PARM
,
4664 /* Load 0xe30 IQC default value */
4665 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x01008c00);
4666 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x01008c00);
4670 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv
*priv
,
4671 int result
[][8], int t
)
4673 struct device
*dev
= &priv
->udev
->dev
;
4675 int path_a_ok
/*, path_b_ok */;
4677 const u32 adda_regs
[RTL8XXXU_ADDA_REGS
] = {
4678 REG_FPGA0_XCD_SWITCH_CTRL
, REG_BLUETOOTH
,
4679 REG_RX_WAIT_CCA
, REG_TX_CCK_RFON
,
4680 REG_TX_CCK_BBON
, REG_TX_OFDM_RFON
,
4681 REG_TX_OFDM_BBON
, REG_TX_TO_RX
,
4682 REG_TX_TO_TX
, REG_RX_CCK
,
4683 REG_RX_OFDM
, REG_RX_WAIT_RIFS
,
4684 REG_RX_TO_RX
, REG_STANDBY
,
4685 REG_SLEEP
, REG_PMPD_ANAEN
4687 const u32 iqk_mac_regs
[RTL8XXXU_MAC_REGS
] = {
4688 REG_TXPAUSE
, REG_BEACON_CTRL
,
4689 REG_BEACON_CTRL_1
, REG_GPIO_MUXCFG
4691 const u32 iqk_bb_regs
[RTL8XXXU_BB_REGS
] = {
4692 REG_OFDM0_TRX_PATH_ENABLE
, REG_OFDM0_TR_MUX_PAR
,
4693 REG_FPGA0_XCD_RF_SW_CTRL
, REG_CONFIG_ANT_A
, REG_CONFIG_ANT_B
,
4694 REG_FPGA0_XAB_RF_SW_CTRL
, REG_FPGA0_XA_RF_INT_OE
,
4695 REG_FPGA0_XB_RF_INT_OE
, REG_FPGA0_RF_MODE
4697 u8 xa_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
) & 0xff;
4698 u8 xb_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
) & 0xff;
4701 * Note: IQ calibration must be performed after loading
4702 * PHY_REG.txt , and radio_a, radio_b.txt
4706 /* Save ADDA parameters, turn Path A ADDA on */
4707 rtl8xxxu_save_regs(priv
, adda_regs
, priv
->adda_backup
,
4708 RTL8XXXU_ADDA_REGS
);
4709 rtl8xxxu_save_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4710 rtl8xxxu_save_regs(priv
, iqk_bb_regs
,
4711 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4714 rtl8xxxu_path_adda_on(priv
, adda_regs
, true);
4717 rtl8xxxu_mac_calibration(priv
, iqk_mac_regs
, priv
->mac_backup
);
4719 val32
= rtl8xxxu_read32(priv
, REG_CCK0_AFE_SETTING
);
4720 val32
|= 0x0f000000;
4721 rtl8xxxu_write32(priv
, REG_CCK0_AFE_SETTING
, val32
);
4723 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, 0x03a05600);
4724 rtl8xxxu_write32(priv
, REG_OFDM0_TR_MUX_PAR
, 0x000800e4);
4725 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_SW_CTRL
, 0x22204000);
4727 #ifdef RTL8723BU_PATH_B
4728 /* Set RF mode to standby Path B */
4729 if (priv
->tx_paths
> 1)
4730 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0x10000);
4735 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_A
, 0x0f600000);
4737 if (priv
->tx_paths
> 1)
4738 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_B
, 0x0f600000);
4742 * RX IQ calibration setting for 8723B D cut large current issue
4745 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4746 val32
&= 0x000000ff;
4747 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4749 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4751 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4753 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4754 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4755 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7fb7);
4757 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
);
4759 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
, val32
);
4761 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_43
, 0x60fbd);
4763 for (i
= 0; i
< retry
; i
++) {
4764 path_a_ok
= rtl8723bu_iqk_path_a(priv
);
4765 if (path_a_ok
== 0x01) {
4766 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4767 val32
&= 0x000000ff;
4768 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4770 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4771 priv
->RFCalibrateInfo
.TxLOK
[RF_A
] =
4772 rtl8xxxu_read_rfreg(priv
, RF_A
,
4773 RF6052_REG_TXM_IDAC
);
4776 val32
= rtl8xxxu_read32(priv
,
4777 REG_TX_POWER_BEFORE_IQK_A
);
4778 result
[t
][0] = (val32
>> 16) & 0x3ff;
4779 val32
= rtl8xxxu_read32(priv
,
4780 REG_TX_POWER_AFTER_IQK_A
);
4781 result
[t
][1] = (val32
>> 16) & 0x3ff;
4788 dev_dbg(dev
, "%s: Path A TX IQK failed!\n", __func__
);
4790 for (i
= 0; i
< retry
; i
++) {
4791 path_a_ok
= rtl8723bu_rx_iqk_path_a(priv
);
4792 if (path_a_ok
== 0x03) {
4793 val32
= rtl8xxxu_read32(priv
,
4794 REG_RX_POWER_BEFORE_IQK_A_2
);
4795 result
[t
][2] = (val32
>> 16) & 0x3ff;
4796 val32
= rtl8xxxu_read32(priv
,
4797 REG_RX_POWER_AFTER_IQK_A_2
);
4798 result
[t
][3] = (val32
>> 16) & 0x3ff;
4805 dev_dbg(dev
, "%s: Path A RX IQK failed!\n", __func__
);
4807 if (priv
->tx_paths
> 1) {
4809 dev_warn(dev
, "%s: Path B not supported\n", __func__
);
4813 * Path A into standby
4815 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4816 val32
&= 0x000000ff;
4817 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4818 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0x10000);
4820 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4821 val32
&= 0x000000ff;
4822 val32
|= 0x80800000;
4823 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4825 /* Turn Path B ADDA on */
4826 rtl8xxxu_path_adda_on(priv
, adda_regs
, false);
4828 for (i
= 0; i
< retry
; i
++) {
4829 path_b_ok
= rtl8xxxu_iqk_path_b(priv
);
4830 if (path_b_ok
== 0x03) {
4831 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4832 result
[t
][4] = (val32
>> 16) & 0x3ff;
4833 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4834 result
[t
][5] = (val32
>> 16) & 0x3ff;
4840 dev_dbg(dev
, "%s: Path B IQK failed!\n", __func__
);
4842 for (i
= 0; i
< retry
; i
++) {
4843 path_b_ok
= rtl8723bu_rx_iqk_path_b(priv
);
4844 if (path_a_ok
== 0x03) {
4845 val32
= rtl8xxxu_read32(priv
,
4846 REG_RX_POWER_BEFORE_IQK_B_2
);
4847 result
[t
][6] = (val32
>> 16) & 0x3ff;
4848 val32
= rtl8xxxu_read32(priv
,
4849 REG_RX_POWER_AFTER_IQK_B_2
);
4850 result
[t
][7] = (val32
>> 16) & 0x3ff;
4856 dev_dbg(dev
, "%s: Path B RX IQK failed!\n", __func__
);
4860 /* Back to BB mode, load original value */
4861 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4862 val32
&= 0x000000ff;
4863 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4866 /* Reload ADDA power saving parameters */
4867 rtl8xxxu_restore_regs(priv
, adda_regs
, priv
->adda_backup
,
4868 RTL8XXXU_ADDA_REGS
);
4870 /* Reload MAC parameters */
4871 rtl8xxxu_restore_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
4873 /* Reload BB parameters */
4874 rtl8xxxu_restore_regs(priv
, iqk_bb_regs
,
4875 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
4877 /* Restore RX initial gain */
4878 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
);
4879 val32
&= 0xffffff00;
4880 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| 0x50);
4881 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| xa_agc
);
4883 if (priv
->tx_paths
> 1) {
4884 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
);
4885 val32
&= 0xffffff00;
4886 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
4888 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
4892 /* Load 0xe30 IQC default value */
4893 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x01008c00);
4894 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x01008c00);
4898 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv
*priv
, u8 start
)
4902 if (priv
->fops
->mbox_ext_width
< 4)
4905 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
4906 h2c
.bt_wlan_calibration
.cmd
= H2C_8723B_BT_WLAN_CALIBRATION
;
4907 h2c
.bt_wlan_calibration
.data
= start
;
4909 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_wlan_calibration
));
4912 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv
*priv
)
4914 struct device
*dev
= &priv
->udev
->dev
;
4915 int result
[4][8]; /* last is final result */
4917 bool path_a_ok
, path_b_ok
;
4918 u32 reg_e94
, reg_e9c
, reg_ea4
, reg_eac
;
4919 u32 reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
4923 rtl8xxxu_prepare_calibrate(priv
, 1);
4925 memset(result
, 0, sizeof(result
));
4931 rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
4933 for (i
= 0; i
< 3; i
++) {
4934 rtl8xxxu_phy_iqcalibrate(priv
, result
, i
);
4937 simu
= rtl8xxxu_simularity_compare(priv
, result
, 0, 1);
4945 simu
= rtl8xxxu_simularity_compare(priv
, result
, 0, 2);
4951 simu
= rtl8xxxu_simularity_compare(priv
, result
, 1, 2);
4955 for (i
= 0; i
< 8; i
++)
4956 reg_tmp
+= result
[3][i
];
4966 for (i
= 0; i
< 4; i
++) {
4967 reg_e94
= result
[i
][0];
4968 reg_e9c
= result
[i
][1];
4969 reg_ea4
= result
[i
][2];
4970 reg_eac
= result
[i
][3];
4971 reg_eb4
= result
[i
][4];
4972 reg_ebc
= result
[i
][5];
4973 reg_ec4
= result
[i
][6];
4974 reg_ecc
= result
[i
][7];
4977 if (candidate
>= 0) {
4978 reg_e94
= result
[candidate
][0];
4979 priv
->rege94
= reg_e94
;
4980 reg_e9c
= result
[candidate
][1];
4981 priv
->rege9c
= reg_e9c
;
4982 reg_ea4
= result
[candidate
][2];
4983 reg_eac
= result
[candidate
][3];
4984 reg_eb4
= result
[candidate
][4];
4985 priv
->regeb4
= reg_eb4
;
4986 reg_ebc
= result
[candidate
][5];
4987 priv
->regebc
= reg_ebc
;
4988 reg_ec4
= result
[candidate
][6];
4989 reg_ecc
= result
[candidate
][7];
4990 dev_dbg(dev
, "%s: candidate is %x\n", __func__
, candidate
);
4992 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4993 "ecc=%x\n ", __func__
, reg_e94
, reg_e9c
,
4994 reg_ea4
, reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
);
4998 reg_e94
= reg_eb4
= priv
->rege94
= priv
->regeb4
= 0x100;
4999 reg_e9c
= reg_ebc
= priv
->rege9c
= priv
->regebc
= 0x0;
5002 if (reg_e94
&& candidate
>= 0)
5003 rtl8xxxu_fill_iqk_matrix_a(priv
, path_a_ok
, result
,
5004 candidate
, (reg_ea4
== 0));
5006 if (priv
->tx_paths
> 1 && reg_eb4
)
5007 rtl8xxxu_fill_iqk_matrix_b(priv
, path_b_ok
, result
,
5008 candidate
, (reg_ec4
== 0));
5010 rtl8xxxu_save_regs(priv
, rtl8723au_iqk_phy_iq_bb_reg
,
5011 priv
->bb_recovery_backup
, RTL8XXXU_BB_REGS
);
5013 rtl8xxxu_prepare_calibrate(priv
, 0);
5016 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv
*priv
)
5018 struct device
*dev
= &priv
->udev
->dev
;
5019 int result
[4][8]; /* last is final result */
5021 bool path_a_ok
, path_b_ok
;
5022 u32 reg_e94
, reg_e9c
, reg_ea4
, reg_eac
;
5023 u32 reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
5024 u32 val32
, bt_control
;
5028 rtl8xxxu_prepare_calibrate(priv
, 1);
5030 memset(result
, 0, sizeof(result
));
5036 bt_control
= rtl8xxxu_read32(priv
, REG_BT_CONTROL_8723BU
);
5038 for (i
= 0; i
< 3; i
++) {
5039 rtl8723bu_phy_iqcalibrate(priv
, result
, i
);
5042 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 1);
5050 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 2);
5056 simu
= rtl8723bu_simularity_compare(priv
, result
, 1, 2);
5060 for (i
= 0; i
< 8; i
++)
5061 reg_tmp
+= result
[3][i
];
5071 for (i
= 0; i
< 4; i
++) {
5072 reg_e94
= result
[i
][0];
5073 reg_e9c
= result
[i
][1];
5074 reg_ea4
= result
[i
][2];
5075 reg_eac
= result
[i
][3];
5076 reg_eb4
= result
[i
][4];
5077 reg_ebc
= result
[i
][5];
5078 reg_ec4
= result
[i
][6];
5079 reg_ecc
= result
[i
][7];
5082 if (candidate
>= 0) {
5083 reg_e94
= result
[candidate
][0];
5084 priv
->rege94
= reg_e94
;
5085 reg_e9c
= result
[candidate
][1];
5086 priv
->rege9c
= reg_e9c
;
5087 reg_ea4
= result
[candidate
][2];
5088 reg_eac
= result
[candidate
][3];
5089 reg_eb4
= result
[candidate
][4];
5090 priv
->regeb4
= reg_eb4
;
5091 reg_ebc
= result
[candidate
][5];
5092 priv
->regebc
= reg_ebc
;
5093 reg_ec4
= result
[candidate
][6];
5094 reg_ecc
= result
[candidate
][7];
5095 dev_dbg(dev
, "%s: candidate is %x\n", __func__
, candidate
);
5097 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5098 "ecc=%x\n ", __func__
, reg_e94
, reg_e9c
,
5099 reg_ea4
, reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
);
5103 reg_e94
= reg_eb4
= priv
->rege94
= priv
->regeb4
= 0x100;
5104 reg_e9c
= reg_ebc
= priv
->rege9c
= priv
->regebc
= 0x0;
5107 if (reg_e94
&& candidate
>= 0)
5108 rtl8xxxu_fill_iqk_matrix_a(priv
, path_a_ok
, result
,
5109 candidate
, (reg_ea4
== 0));
5111 if (priv
->tx_paths
> 1 && reg_eb4
)
5112 rtl8xxxu_fill_iqk_matrix_b(priv
, path_b_ok
, result
,
5113 candidate
, (reg_ec4
== 0));
5115 rtl8xxxu_save_regs(priv
, rtl8723au_iqk_phy_iq_bb_reg
,
5116 priv
->bb_recovery_backup
, RTL8XXXU_BB_REGS
);
5118 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, bt_control
);
5120 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
5122 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
5123 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x18000);
5124 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
5125 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xe6177);
5126 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
);
5128 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
, val32
);
5129 rtl8xxxu_write_rfreg(priv
, RF_A
, 0x43, 0x300bd);
5131 if (priv
->rf_paths
> 1) {
5132 dev_dbg(dev
, "%s: beware 2T not yet supported\n", __func__
);
5133 #ifdef RTL8723BU_PATH_B
5134 if (RF_Path
== 0x0) //S1
5135 ODM_SetIQCbyRFpath(pDM_Odm
, 0);
5137 ODM_SetIQCbyRFpath(pDM_Odm
, 1);
5140 rtl8xxxu_prepare_calibrate(priv
, 0);
5143 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv
*priv
)
5146 u32 rf_amode
, rf_bmode
= 0, lstf
;
5148 /* Check continuous TX and Packet TX */
5149 lstf
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
5151 if (lstf
& OFDM_LSTF_MASK
) {
5152 /* Disable all continuous TX */
5153 val32
= lstf
& ~OFDM_LSTF_MASK
;
5154 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
5156 /* Read original RF mode Path A */
5157 rf_amode
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_AC
);
5159 /* Set RF mode to standby Path A */
5160 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
,
5161 (rf_amode
& 0x8ffff) | 0x10000);
5164 if (priv
->tx_paths
> 1) {
5165 rf_bmode
= rtl8xxxu_read_rfreg(priv
, RF_B
,
5168 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
,
5169 (rf_bmode
& 0x8ffff) | 0x10000);
5172 /* Deal with Packet TX case */
5173 /* block all queues */
5174 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
5177 /* Start LC calibration */
5178 if (priv
->fops
->has_s0s1
)
5179 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_S0S1
, 0xdfbe0);
5180 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
);
5182 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
, val32
);
5186 if (priv
->fops
->has_s0s1
)
5187 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_S0S1
, 0xdffe0);
5189 /* Restore original parameters */
5190 if (lstf
& OFDM_LSTF_MASK
) {
5192 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, lstf
);
5193 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, rf_amode
);
5196 if (priv
->tx_paths
> 1)
5197 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
,
5199 } else /* Deal with Packet TX case */
5200 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0x00);
5203 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv
*priv
)
5210 for (i
= 0; i
< ETH_ALEN
; i
++)
5211 rtl8xxxu_write8(priv
, reg
+ i
, priv
->mac_addr
[i
]);
5216 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv
*priv
, const u8
*bssid
)
5221 dev_dbg(&priv
->udev
->dev
, "%s: (%pM)\n", __func__
, bssid
);
5225 for (i
= 0; i
< ETH_ALEN
; i
++)
5226 rtl8xxxu_write8(priv
, reg
+ i
, bssid
[i
]);
5232 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv
*priv
, u8 ampdu_factor
)
5234 u8 vals
[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5238 ampdu_factor
= 1 << (ampdu_factor
+ 2);
5239 if (ampdu_factor
> max_agg
)
5240 ampdu_factor
= max_agg
;
5242 for (i
= 0; i
< 4; i
++) {
5243 if ((vals
[i
] & 0xf0) > (ampdu_factor
<< 4))
5244 vals
[i
] = (vals
[i
] & 0x0f) | (ampdu_factor
<< 4);
5246 if ((vals
[i
] & 0x0f) > ampdu_factor
)
5247 vals
[i
] = (vals
[i
] & 0xf0) | ampdu_factor
;
5249 rtl8xxxu_write8(priv
, REG_AGGLEN_LMT
+ i
, vals
[i
]);
5253 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv
*priv
, u8 density
)
5257 val8
= rtl8xxxu_read8(priv
, REG_AMPDU_MIN_SPACE
);
5260 rtl8xxxu_write8(priv
, REG_AMPDU_MIN_SPACE
, val8
);
5263 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv
*priv
)
5268 /* Start of rtl8723AU_card_enable_flow */
5269 /* Act to Cardemu sequence*/
5271 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0);
5273 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5274 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
5275 val8
&= ~LEDCFG2_DPDT_SELECT
;
5276 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
5278 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5279 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5281 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5283 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5284 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5285 if ((val8
& BIT(1)) == 0)
5291 dev_warn(&priv
->udev
->dev
, "%s: Disabling MAC timed out\n",
5297 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5298 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5299 val8
|= SYS_ISO_ANALOG_IPS
;
5300 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5302 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5303 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5304 val8
&= ~LDOA15_ENABLE
;
5305 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5311 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv
*priv
)
5319 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0);
5321 /* Enable rising edge triggering interrupt */
5322 val16
= rtl8xxxu_read16(priv
, REG_GPIO_INTM
);
5323 val16
&= ~GPIO_INTM_EDGE_TRIG_IRQ
;
5324 rtl8xxxu_write16(priv
, REG_GPIO_INTM
, val16
);
5326 /* Release WLON reset 0x04[16]= 1*/
5327 val32
= rtl8xxxu_read32(priv
, REG_GPIO_INTM
);
5328 val32
|= APS_FSMCO_WLON_RESET
;
5329 rtl8xxxu_write32(priv
, REG_GPIO_INTM
, val32
);
5331 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5332 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5334 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5336 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5337 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5338 if ((val8
& BIT(1)) == 0)
5344 dev_warn(&priv
->udev
->dev
, "%s: Disabling MAC timed out\n",
5350 /* Enable BT control XTAL setting */
5351 val8
= rtl8xxxu_read8(priv
, REG_AFE_MISC
);
5352 val8
&= ~AFE_MISC_WL_XTAL_CTRL
;
5353 rtl8xxxu_write8(priv
, REG_AFE_MISC
, val8
);
5355 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5356 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5357 val8
|= SYS_ISO_ANALOG_IPS
;
5358 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5360 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5361 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5362 val8
&= ~LDOA15_ENABLE
;
5363 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5369 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv
*priv
)
5375 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
5378 * Poll - wait for RX packet to complete
5380 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5381 val32
= rtl8xxxu_read32(priv
, 0x5f8);
5388 dev_warn(&priv
->udev
->dev
,
5389 "%s: RX poll timed out (0x05f8)\n", __func__
);
5394 /* Disable CCK and OFDM, clock gated */
5395 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
);
5396 val8
&= ~SYS_FUNC_BBRSTB
;
5397 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, val8
);
5401 /* Reset baseband */
5402 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
);
5403 val8
&= ~SYS_FUNC_BB_GLB_RSTN
;
5404 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, val8
);
5407 val8
= rtl8xxxu_read8(priv
, REG_CR
);
5408 val8
= CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
;
5409 rtl8xxxu_write8(priv
, REG_CR
, val8
);
5412 val8
= rtl8xxxu_read8(priv
, REG_CR
+ 1);
5413 val8
&= ~BIT(1); /* CR_SECURITY_ENABLE */
5414 rtl8xxxu_write8(priv
, REG_CR
+ 1, val8
);
5416 /* Respond TX OK to scheduler */
5417 val8
= rtl8xxxu_read8(priv
, REG_DUAL_TSF_RST
);
5418 val8
|= DUAL_TSF_TX_OK
;
5419 rtl8xxxu_write8(priv
, REG_DUAL_TSF_RST
, val8
);
5425 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv
*priv
)
5429 /* Clear suspend enable and power down enable*/
5430 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5431 val8
&= ~(BIT(3) | BIT(7));
5432 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5434 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5435 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 2);
5437 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 2, val8
);
5439 /* 0x04[12:11] = 11 enable WL suspend*/
5440 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5441 val8
&= ~(BIT(3) | BIT(4));
5442 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5445 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv
*priv
)
5449 /* Clear suspend enable and power down enable*/
5450 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5451 val8
&= ~(BIT(3) | BIT(4));
5452 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5455 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv
*priv
)
5461 /* disable HWPDN 0x04[15]=0*/
5462 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5464 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5466 /* disable SW LPS 0x04[10]= 0 */
5467 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5469 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5471 /* disable WL suspend*/
5472 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5473 val8
&= ~(BIT(3) | BIT(4));
5474 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5476 /* wait till 0x04[17] = 1 power ready*/
5477 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5478 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5479 if (val32
& BIT(17))
5490 /* We should be able to optimize the following three entries into one */
5492 /* release WLON reset 0x04[16]= 1*/
5493 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
5495 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
5497 /* set, then poll until 0 */
5498 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5499 val32
|= APS_FSMCO_MAC_ENABLE
;
5500 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5502 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5503 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5504 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
5520 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv
*priv
)
5526 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5527 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5528 val8
|= LDOA15_ENABLE
;
5529 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5531 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5532 val8
= rtl8xxxu_read8(priv
, 0x0067);
5534 rtl8xxxu_write8(priv
, 0x0067, val8
);
5538 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5539 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5540 val8
&= ~SYS_ISO_ANALOG_IPS
;
5541 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5543 /* disable SW LPS 0x04[10]= 0 */
5544 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5546 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5548 /* wait till 0x04[17] = 1 power ready*/
5549 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5550 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5551 if (val32
& BIT(17))
5562 /* We should be able to optimize the following three entries into one */
5564 /* release WLON reset 0x04[16]= 1*/
5565 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
5567 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
5569 /* disable HWPDN 0x04[15]= 0*/
5570 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5572 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5574 /* disable WL suspend*/
5575 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5576 val8
&= ~(BIT(3) | BIT(4));
5577 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5579 /* set, then poll until 0 */
5580 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5581 val32
|= APS_FSMCO_MAC_ENABLE
;
5582 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5584 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5585 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5586 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
5598 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5600 * Note: Vendor driver actually clears this bit, despite the
5601 * documentation claims it's being set!
5603 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
5604 val8
|= LEDCFG2_DPDT_SELECT
;
5605 val8
&= ~LEDCFG2_DPDT_SELECT
;
5606 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
5612 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv
*priv
)
5618 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5619 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
5620 val8
|= LDOA15_ENABLE
;
5621 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
5623 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5624 val8
= rtl8xxxu_read8(priv
, 0x0067);
5626 rtl8xxxu_write8(priv
, 0x0067, val8
);
5630 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5631 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5632 val8
&= ~SYS_ISO_ANALOG_IPS
;
5633 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5635 /* Disable SW LPS 0x04[10]= 0 */
5636 val32
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
);
5637 val32
&= ~APS_FSMCO_SW_LPS
;
5638 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5640 /* Wait until 0x04[17] = 1 power ready */
5641 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5642 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5643 if (val32
& BIT(17))
5654 /* We should be able to optimize the following three entries into one */
5656 /* Release WLON reset 0x04[16]= 1*/
5657 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5658 val32
|= APS_FSMCO_WLON_RESET
;
5659 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5661 /* Disable HWPDN 0x04[15]= 0*/
5662 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5663 val32
&= ~APS_FSMCO_HW_POWERDOWN
;
5664 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5666 /* Disable WL suspend*/
5667 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5668 val32
&= ~(APS_FSMCO_HW_SUSPEND
| APS_FSMCO_PCIE
);
5669 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5671 /* Set, then poll until 0 */
5672 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5673 val32
|= APS_FSMCO_MAC_ENABLE
;
5674 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
5676 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
5677 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
5678 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
5690 /* Enable WL control XTAL setting */
5691 val8
= rtl8xxxu_read8(priv
, REG_AFE_MISC
);
5692 val8
|= AFE_MISC_WL_XTAL_CTRL
;
5693 rtl8xxxu_write8(priv
, REG_AFE_MISC
, val8
);
5695 /* Enable falling edge triggering interrupt */
5696 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 1);
5698 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 1, val8
);
5700 /* Enable GPIO9 interrupt mode */
5701 val8
= rtl8xxxu_read8(priv
, REG_GPIO_IO_SEL_2
+ 1);
5703 rtl8xxxu_write8(priv
, REG_GPIO_IO_SEL_2
+ 1, val8
);
5705 /* Enable GPIO9 input mode */
5706 val8
= rtl8xxxu_read8(priv
, REG_GPIO_IO_SEL_2
);
5708 rtl8xxxu_write8(priv
, REG_GPIO_IO_SEL_2
, val8
);
5710 /* Enable HSISR GPIO[C:0] interrupt */
5711 val8
= rtl8xxxu_read8(priv
, REG_HSIMR
);
5713 rtl8xxxu_write8(priv
, REG_HSIMR
, val8
);
5715 /* Enable HSISR GPIO9 interrupt */
5716 val8
= rtl8xxxu_read8(priv
, REG_HSIMR
+ 2);
5718 rtl8xxxu_write8(priv
, REG_HSIMR
+ 2, val8
);
5720 val8
= rtl8xxxu_read8(priv
, REG_MULTI_FUNC_CTRL
);
5721 val8
|= MULTI_WIFI_HW_ROF_EN
;
5722 rtl8xxxu_write8(priv
, REG_MULTI_FUNC_CTRL
, val8
);
5724 /* For GPIO9 internal pull high setting BIT(14) */
5725 val8
= rtl8xxxu_read8(priv
, REG_MULTI_FUNC_CTRL
+ 1);
5727 rtl8xxxu_write8(priv
, REG_MULTI_FUNC_CTRL
+ 1, val8
);
5733 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv
*priv
)
5737 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5738 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 3, 0x20);
5740 /* 0x04[12:11] = 01 enable WL suspend */
5741 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5744 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5746 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
5748 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
5750 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5751 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 2);
5753 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 2, val8
);
5758 static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv
*priv
)
5760 struct device
*dev
= &priv
->udev
->dev
;
5764 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
5766 val32
= rtl8xxxu_read32(priv
, REG_RXPKT_NUM
);
5767 val32
|= RXPKT_NUM_RW_RELEASE_EN
;
5768 rtl8xxxu_write32(priv
, REG_RXPKT_NUM
, val32
);
5774 val32
= rtl8xxxu_read32(priv
, REG_RXPKT_NUM
);
5775 if (val32
& RXPKT_NUM_RXDMA_IDLE
) {
5781 rtl8xxxu_write16(priv
, REG_RQPN_NPQ
, 0);
5782 rtl8xxxu_write32(priv
, REG_RQPN
, 0x80000000);
5786 dev_warn(dev
, "Failed to flush FIFO\n");
5791 static int rtl8723au_power_on(struct rtl8xxxu_priv
*priv
)
5799 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5801 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0);
5803 rtl8723a_disabled_to_emu(priv
);
5805 ret
= rtl8723a_emu_to_active(priv
);
5810 * 0x0004[19] = 1, reset 8051
5812 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
5814 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
5817 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5818 * Set CR bit10 to enable 32k calibration.
5820 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5821 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5822 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
5823 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
5824 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
5825 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
5826 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5829 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
5830 val32
&= ~(BIT(28) | BIT(29) | BIT(30));
5831 val32
|= (0x06 << 28);
5832 rtl8xxxu_write32(priv
, REG_EFUSE_CTRL
, val32
);
5837 static int rtl8723bu_power_on(struct rtl8xxxu_priv
*priv
)
5844 rtl8723a_disabled_to_emu(priv
);
5846 ret
= rtl8723b_emu_to_active(priv
);
5851 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5852 * Set CR bit10 to enable 32k calibration.
5854 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5855 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5856 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
5857 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
5858 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
5859 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
5860 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5863 * BT coexist power on settings. This is identical for 1 and 2
5866 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
+ 3, 0x20);
5868 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
5869 val16
|= SYS_FUNC_BBRSTB
| SYS_FUNC_BB_GLB_RSTN
;
5870 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
5872 rtl8xxxu_write8(priv
, REG_BT_CONTROL_8723BU
+ 1, 0x18);
5873 rtl8xxxu_write8(priv
, REG_WLAN_ACT_CONTROL_8723B
, 0x04);
5874 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
5875 /* Antenna inverse */
5876 rtl8xxxu_write8(priv
, 0xfe08, 0x01);
5878 val16
= rtl8xxxu_read16(priv
, REG_PWR_DATA
);
5879 val16
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
5880 rtl8xxxu_write16(priv
, REG_PWR_DATA
, val16
);
5882 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
5883 val32
|= LEDCFG0_DPDT_SELECT
;
5884 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
5886 val8
= rtl8xxxu_read8(priv
, REG_PAD_CTRL1
);
5887 val8
&= ~PAD_CTRL1_SW_DPDT_SEL_DATA
;
5888 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
, val8
);
5893 #ifdef CONFIG_RTL8XXXU_UNTESTED
5895 static int rtl8192cu_power_on(struct rtl8xxxu_priv
*priv
)
5902 for (i
= 100; i
; i
--) {
5903 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
);
5904 if (val8
& APS_FSMCO_PFM_ALDN
)
5909 pr_info("%s: Poll failed\n", __func__
);
5914 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5916 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0);
5917 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, 0x2b);
5920 val8
= rtl8xxxu_read8(priv
, REG_LDOV12D_CTRL
);
5921 if (!(val8
& LDOV12D_ENABLE
)) {
5922 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__
, val8
);
5923 val8
|= LDOV12D_ENABLE
;
5924 rtl8xxxu_write8(priv
, REG_LDOV12D_CTRL
, val8
);
5928 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
5929 val8
&= ~SYS_ISO_MD2PP
;
5930 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
5936 val16
= rtl8xxxu_read16(priv
, REG_APS_FSMCO
);
5937 val16
|= APS_FSMCO_MAC_ENABLE
;
5938 rtl8xxxu_write16(priv
, REG_APS_FSMCO
, val16
);
5940 for (i
= 1000; i
; i
--) {
5941 val16
= rtl8xxxu_read16(priv
, REG_APS_FSMCO
);
5942 if (!(val16
& APS_FSMCO_MAC_ENABLE
))
5946 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__
);
5951 * Enable radio, GPIO, LED
5953 val16
= APS_FSMCO_HW_SUSPEND
| APS_FSMCO_ENABLE_POWERDOWN
|
5955 rtl8xxxu_write16(priv
, REG_APS_FSMCO
, val16
);
5958 * Release RF digital isolation
5960 val16
= rtl8xxxu_read16(priv
, REG_SYS_ISO_CTRL
);
5961 val16
&= ~SYS_ISO_DIOR
;
5962 rtl8xxxu_write16(priv
, REG_SYS_ISO_CTRL
, val16
);
5964 val8
= rtl8xxxu_read8(priv
, REG_APSD_CTRL
);
5965 val8
&= ~APSD_CTRL_OFF
;
5966 rtl8xxxu_write8(priv
, REG_APSD_CTRL
, val8
);
5967 for (i
= 200; i
; i
--) {
5968 val8
= rtl8xxxu_read8(priv
, REG_APSD_CTRL
);
5969 if (!(val8
& APSD_CTRL_OFF_STATUS
))
5974 pr_info("%s: APSD_CTRL poll failed\n", __func__
);
5979 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5981 val16
= rtl8xxxu_read16(priv
, REG_CR
);
5982 val16
|= CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
5983 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
| CR_PROTOCOL_ENABLE
|
5984 CR_SCHEDULE_ENABLE
| CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
;
5985 rtl8xxxu_write16(priv
, REG_CR
, val16
);
5988 * Workaround for 8188RU LNA power leakage problem.
5990 if (priv
->rtl_chip
== RTL8188C
&& priv
->hi_pa
) {
5991 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XCD_RF_PARM
);
5993 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_PARM
, val32
);
6000 static int rtl8192eu_power_on(struct rtl8xxxu_priv
*priv
)
6008 val32
= rtl8xxxu_read32(priv
, REG_SYS_CFG
);
6009 if (val32
& SYS_CFG_SPS_LDO_SEL
) {
6010 rtl8xxxu_write8(priv
, REG_LDO_SW_CTRL
, 0xc3);
6013 * Raise 1.2V voltage
6015 val32
= rtl8xxxu_read32(priv
, REG_8192E_LDOV12_CTRL
);
6016 val32
&= 0xff0fffff;
6017 val32
|= 0x00500000;
6018 rtl8xxxu_write32(priv
, REG_8192E_LDOV12_CTRL
, val32
);
6019 rtl8xxxu_write8(priv
, REG_LDO_SW_CTRL
, 0x83);
6022 rtl8192e_disabled_to_emu(priv
);
6024 ret
= rtl8192e_emu_to_active(priv
);
6028 rtl8xxxu_write16(priv
, REG_CR
, 0x0000);
6031 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
6032 * Set CR bit10 to enable 32k calibration.
6034 val16
= rtl8xxxu_read16(priv
, REG_CR
);
6035 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
6036 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
6037 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
6038 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
6039 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
6040 rtl8xxxu_write16(priv
, REG_CR
, val16
);
6046 static void rtl8xxxu_power_off(struct rtl8xxxu_priv
*priv
)
6053 * Workaround for 8188RU LNA power leakage problem.
6055 if (priv
->rtl_chip
== RTL8188C
&& priv
->hi_pa
) {
6056 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XCD_RF_PARM
);
6058 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_PARM
, val32
);
6061 rtl8xxxu_flush_fifo(priv
);
6063 rtl8xxxu_active_to_lps(priv
);
6066 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0x00);
6068 /* Reset Firmware if running in RAM */
6069 if (rtl8xxxu_read8(priv
, REG_MCU_FW_DL
) & MCU_FW_RAM_SEL
)
6070 rtl8xxxu_firmware_self_reset(priv
);
6073 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
6074 val16
&= ~SYS_FUNC_CPU_ENABLE
;
6075 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
6077 /* Reset MCU ready status */
6078 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
6080 rtl8xxxu_active_to_emu(priv
);
6081 rtl8xxxu_emu_to_disabled(priv
);
6083 /* Reset MCU IO Wrapper */
6084 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
6086 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
6088 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
6090 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
6092 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
6093 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0e);
6096 static void rtl8723bu_power_off(struct rtl8xxxu_priv
*priv
)
6101 rtl8xxxu_flush_fifo(priv
);
6104 * Disable TX report timer
6106 val8
= rtl8xxxu_read8(priv
, REG_TX_REPORT_CTRL
);
6107 val8
&= ~TX_REPORT_CTRL_TIMER_ENABLE
;
6108 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
, val8
);
6110 rtl8xxxu_write16(priv
, REG_CR
, 0x0000);
6112 rtl8xxxu_active_to_lps(priv
);
6114 /* Reset Firmware if running in RAM */
6115 if (rtl8xxxu_read8(priv
, REG_MCU_FW_DL
) & MCU_FW_RAM_SEL
)
6116 rtl8xxxu_firmware_self_reset(priv
);
6119 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
6120 val16
&= ~SYS_FUNC_CPU_ENABLE
;
6121 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
6123 /* Reset MCU ready status */
6124 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
6126 rtl8723bu_active_to_emu(priv
);
6127 rtl8xxxu_emu_to_disabled(priv
);
6131 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv
*priv
,
6132 u8 arg1
, u8 arg2
, u8 arg3
, u8 arg4
, u8 arg5
)
6136 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6137 h2c
.b_type_dma
.cmd
= H2C_8723B_B_TYPE_TDMA
;
6138 h2c
.b_type_dma
.data1
= arg1
;
6139 h2c
.b_type_dma
.data2
= arg2
;
6140 h2c
.b_type_dma
.data3
= arg3
;
6141 h2c
.b_type_dma
.data4
= arg4
;
6142 h2c
.b_type_dma
.data5
= arg5
;
6143 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.b_type_dma
));
6147 static void rtl8723b_enable_rf(struct rtl8xxxu_priv
*priv
)
6154 * No indication anywhere as to what 0x0790 does. The 2 antenna
6155 * vendor code preserves bits 6-7 here.
6157 rtl8xxxu_write8(priv
, 0x0790, 0x05);
6159 * 0x0778 seems to be related to enabling the number of antennas
6160 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
6161 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
6163 rtl8xxxu_write8(priv
, 0x0778, 0x01);
6165 val8
= rtl8xxxu_read8(priv
, REG_GPIO_MUXCFG
);
6167 rtl8xxxu_write8(priv
, REG_GPIO_MUXCFG
, val8
);
6169 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_IQADJ_G1
, 0x780);
6171 rtl8723bu_write_btreg(priv
, 0x3c, 0x15); /* BT TRx Mask on */
6174 * Set BT grant to low
6176 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6177 h2c
.bt_grant
.cmd
= H2C_8723B_BT_GRANT
;
6178 h2c
.bt_grant
.data
= 0;
6179 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_grant
));
6182 * WLAN action by PTA
6184 rtl8xxxu_write8(priv
, REG_WLAN_ACT_CONTROL_8723B
, 0x04);
6187 * BT select S0/S1 controlled by WiFi
6189 val8
= rtl8xxxu_read8(priv
, 0x0067);
6191 rtl8xxxu_write8(priv
, 0x0067, val8
);
6193 val32
= rtl8xxxu_read32(priv
, REG_PWR_DATA
);
6194 val32
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
6195 rtl8xxxu_write32(priv
, REG_PWR_DATA
, val32
);
6198 * Bits 6/7 are marked in/out ... but for what?
6200 rtl8xxxu_write8(priv
, 0x0974, 0xff);
6202 val32
= rtl8xxxu_read32(priv
, REG_RFE_BUFFER
);
6203 val32
|= (BIT(0) | BIT(1));
6204 rtl8xxxu_write32(priv
, REG_RFE_BUFFER
, val32
);
6206 rtl8xxxu_write8(priv
, REG_RFE_CTRL_ANTA_SRC
, 0x77);
6208 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
6211 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
6214 * Fix external switch Main->S1, Aux->S0
6216 val8
= rtl8xxxu_read8(priv
, REG_PAD_CTRL1
);
6218 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
, val8
);
6220 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6221 h2c
.ant_sel_rsv
.cmd
= H2C_8723B_ANT_SEL_RSV
;
6222 h2c
.ant_sel_rsv
.ant_inverse
= 1;
6223 h2c
.ant_sel_rsv
.int_switch_type
= 0;
6224 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ant_sel_rsv
));
6227 * 0x280, 0x00, 0x200, 0x80 - not clear
6229 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
6232 * Software control, antenna at WiFi side
6235 rtl8723bu_set_ps_tdma(priv
, 0x08, 0x00, 0x00, 0x00, 0x00);
6238 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE1
, 0x55555555);
6239 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE2
, 0x55555555);
6240 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE3
, 0x00ffffff);
6241 rtl8xxxu_write8(priv
, REG_BT_COEX_TABLE4
, 0x03);
6243 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6244 h2c
.bt_info
.cmd
= H2C_8723B_BT_INFO
;
6245 h2c
.bt_info
.data
= BIT(0);
6246 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_info
));
6248 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6249 h2c
.ignore_wlan
.cmd
= H2C_8723B_BT_IGNORE_WLANACT
;
6250 h2c
.ignore_wlan
.data
= 0;
6251 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ignore_wlan
));
6254 static void rtl8723b_disable_rf(struct rtl8xxxu_priv
*priv
)
6258 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
6260 val32
= rtl8xxxu_read32(priv
, REG_RX_WAIT_CCA
);
6261 val32
&= ~(BIT(22) | BIT(23));
6262 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, val32
);
6265 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv
*priv
)
6271 * For now simply disable RX aggregation
6273 agg_ctrl
= rtl8xxxu_read8(priv
, REG_TRXDMA_CTRL
);
6274 agg_ctrl
&= ~TRXDMA_CTRL_RXDMA_AGG_EN
;
6276 agg_rx
= rtl8xxxu_read32(priv
, REG_RXDMA_AGG_PG_TH
);
6277 agg_rx
&= ~RXDMA_USB_AGG_ENABLE
;
6280 rtl8xxxu_write8(priv
, REG_TRXDMA_CTRL
, agg_ctrl
);
6281 rtl8xxxu_write32(priv
, REG_RXDMA_AGG_PG_TH
, agg_rx
);
6284 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv
*priv
)
6288 /* Time duration for NHM unit: 4us, 0x2710=40ms */
6289 rtl8xxxu_write16(priv
, REG_NHM_TIMER_8723B
+ 2, 0x2710);
6290 rtl8xxxu_write16(priv
, REG_NHM_TH9_TH10_8723B
+ 2, 0xffff);
6291 rtl8xxxu_write32(priv
, REG_NHM_TH3_TO_TH0_8723B
, 0xffffff52);
6292 rtl8xxxu_write32(priv
, REG_NHM_TH7_TO_TH4_8723B
, 0xffffffff);
6294 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
6296 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
6298 val32
= rtl8xxxu_read32(priv
, REG_NHM_TH9_TH10_8723B
);
6299 val32
|= BIT(8) | BIT(9) | BIT(10);
6300 rtl8xxxu_write32(priv
, REG_NHM_TH9_TH10_8723B
, val32
);
6301 /* Max power amongst all RX antennas */
6302 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_FA_RSTC
);
6304 rtl8xxxu_write32(priv
, REG_OFDM0_FA_RSTC
, val32
);
6307 static int rtl8xxxu_init_device(struct ieee80211_hw
*hw
)
6309 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6310 struct device
*dev
= &priv
->udev
->dev
;
6311 struct rtl8xxxu_rfregval
*rftable
;
6318 /* Check if MAC is already powered on */
6319 val8
= rtl8xxxu_read8(priv
, REG_CR
);
6322 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6323 * initialized. First MAC returns 0xea, second MAC returns 0x00
6330 ret
= priv
->fops
->power_on(priv
);
6332 dev_warn(dev
, "%s: Failed power on\n", __func__
);
6336 dev_dbg(dev
, "%s: macpower %i\n", __func__
, macpower
);
6338 ret
= priv
->fops
->llt_init(priv
, TX_TOTAL_PAGE_NUM
);
6340 dev_warn(dev
, "%s: LLT table init failed\n", __func__
);
6345 * Presumably this is for 8188EU as well
6346 * Enable TX report and TX report timer
6348 if (priv
->rtl_chip
== RTL8723B
) {
6349 val8
= rtl8xxxu_read8(priv
, REG_TX_REPORT_CTRL
);
6350 val8
|= TX_REPORT_CTRL_TIMER_ENABLE
;
6351 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
, val8
);
6352 /* Set MAX RPT MACID */
6353 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
+ 1, 0x02);
6354 /* TX report Timer. Unit: 32us */
6355 rtl8xxxu_write16(priv
, REG_TX_REPORT_TIME
, 0xcdf0);
6358 val8
= rtl8xxxu_read8(priv
, 0xa3);
6360 rtl8xxxu_write8(priv
, 0xa3, val8
);
6364 ret
= rtl8xxxu_download_firmware(priv
);
6365 dev_dbg(dev
, "%s: download_fiwmare %i\n", __func__
, ret
);
6368 ret
= rtl8xxxu_start_firmware(priv
);
6369 dev_dbg(dev
, "%s: start_fiwmare %i\n", __func__
, ret
);
6373 /* Solve too many protocol error on USB bus */
6374 /* Can't do this for 8188/8192 UMC A cut parts */
6375 if (priv
->rtl_chip
== RTL8723A
||
6376 ((priv
->rtl_chip
== RTL8192C
|| priv
->rtl_chip
== RTL8191C
||
6377 priv
->rtl_chip
== RTL8188C
) &&
6378 (priv
->chip_cut
|| !priv
->vendor_umc
))) {
6379 rtl8xxxu_write8(priv
, 0xfe40, 0xe6);
6380 rtl8xxxu_write8(priv
, 0xfe41, 0x94);
6381 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6383 rtl8xxxu_write8(priv
, 0xfe40, 0xe0);
6384 rtl8xxxu_write8(priv
, 0xfe41, 0x19);
6385 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6387 rtl8xxxu_write8(priv
, 0xfe40, 0xe5);
6388 rtl8xxxu_write8(priv
, 0xfe41, 0x91);
6389 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6391 rtl8xxxu_write8(priv
, 0xfe40, 0xe2);
6392 rtl8xxxu_write8(priv
, 0xfe41, 0x81);
6393 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6396 if (priv
->rtl_chip
== RTL8192E
) {
6397 rtl8xxxu_write32(priv
, REG_HIMR0
, 0x00);
6398 rtl8xxxu_write32(priv
, REG_HIMR1
, 0x00);
6401 if (priv
->fops
->phy_init_antenna_selection
)
6402 priv
->fops
->phy_init_antenna_selection(priv
);
6404 ret
= rtl8xxxu_init_mac(priv
);
6406 dev_dbg(dev
, "%s: init_mac %i\n", __func__
, ret
);
6410 ret
= rtl8xxxu_init_phy_bb(priv
);
6411 dev_dbg(dev
, "%s: init_phy_bb %i\n", __func__
, ret
);
6415 switch(priv
->rtl_chip
) {
6417 rftable
= rtl8723au_radioa_1t_init_table
;
6418 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6421 rftable
= rtl8723bu_radioa_1t_init_table
;
6422 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6426 rtl8xxxu_write_rfreg(priv
, RF_A
, 0xb0, 0xdfbe0);
6427 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
, 0x8c01);
6429 rtl8xxxu_write_rfreg(priv
, RF_A
, 0xb0, 0xdffe0);
6433 rftable
= rtl8188ru_radioa_1t_highpa_table
;
6435 rftable
= rtl8192cu_radioa_1t_init_table
;
6436 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6439 rftable
= rtl8192cu_radioa_1t_init_table
;
6440 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6443 rftable
= rtl8192cu_radioa_2t_init_table
;
6444 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
6447 rftable
= rtl8192cu_radiob_2t_init_table
;
6448 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_B
);
6458 * Chip specific quirks
6460 if (priv
->rtl_chip
== RTL8723A
) {
6461 /* Fix USB interface interference issue */
6462 rtl8xxxu_write8(priv
, 0xfe40, 0xe0);
6463 rtl8xxxu_write8(priv
, 0xfe41, 0x8d);
6464 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6465 rtl8xxxu_write32(priv
, REG_TXDMA_OFFSET_CHK
, 0xfd0320);
6467 /* Reduce 80M spur */
6468 rtl8xxxu_write32(priv
, REG_AFE_XTAL_CTRL
, 0x0381808d);
6469 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff83);
6470 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff82);
6471 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff83);
6473 val32
= rtl8xxxu_read32(priv
, REG_TXDMA_OFFSET_CHK
);
6474 val32
|= TXDMA_OFFSET_DROP_DATA_EN
;
6475 rtl8xxxu_write32(priv
, REG_TXDMA_OFFSET_CHK
, val32
);
6479 if (priv
->ep_tx_normal_queue
)
6480 val8
= TX_PAGE_NUM_NORM_PQ
;
6484 rtl8xxxu_write8(priv
, REG_RQPN_NPQ
, val8
);
6486 val32
= (TX_PAGE_NUM_PUBQ
<< RQPN_NORM_PQ_SHIFT
) | RQPN_LOAD
;
6488 if (priv
->ep_tx_high_queue
)
6489 val32
|= (TX_PAGE_NUM_HI_PQ
<< RQPN_HI_PQ_SHIFT
);
6490 if (priv
->ep_tx_low_queue
)
6491 val32
|= (TX_PAGE_NUM_LO_PQ
<< RQPN_LO_PQ_SHIFT
);
6493 rtl8xxxu_write32(priv
, REG_RQPN
, val32
);
6496 * Set TX buffer boundary
6498 if (priv
->rtl_chip
== RTL8192E
)
6499 val8
= TX_TOTAL_PAGE_NUM_8192E
+ 1;
6501 val8
= TX_TOTAL_PAGE_NUM
+ 1;
6503 if (priv
->rtl_chip
== RTL8723B
)
6506 rtl8xxxu_write8(priv
, REG_TXPKTBUF_BCNQ_BDNY
, val8
);
6507 rtl8xxxu_write8(priv
, REG_TXPKTBUF_MGQ_BDNY
, val8
);
6508 rtl8xxxu_write8(priv
, REG_TXPKTBUF_WMAC_LBK_BF_HD
, val8
);
6509 rtl8xxxu_write8(priv
, REG_TRXFF_BNDY
, val8
);
6510 rtl8xxxu_write8(priv
, REG_TDECTRL
+ 1, val8
);
6513 ret
= rtl8xxxu_init_queue_priority(priv
);
6514 dev_dbg(dev
, "%s: init_queue_priority %i\n", __func__
, ret
);
6518 /* RFSW Control - clear bit 14 ?? */
6519 if (priv
->rtl_chip
!= RTL8723B
)
6520 rtl8xxxu_write32(priv
, REG_FPGA0_TX_INFO
, 0x00000003);
6522 val32
= FPGA0_RF_TRSW
| FPGA0_RF_TRSWB
| FPGA0_RF_ANTSW
|
6523 FPGA0_RF_ANTSWB
| FPGA0_RF_PAPE
|
6524 ((FPGA0_RF_ANTSW
| FPGA0_RF_ANTSWB
| FPGA0_RF_PAPE
) <<
6525 FPGA0_RF_BD_CTRL_SHIFT
);
6526 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
, val32
);
6527 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6528 rtl8xxxu_write32(priv
, REG_FPGA0_XA_RF_INT_OE
, 0x66F60210);
6530 priv
->rf_mode_ag
[0] = rtl8xxxu_read_rfreg(priv
, RF_A
,
6531 RF6052_REG_MODE_AG
);
6534 * Set RX page boundary
6536 if (priv
->rtl_chip
== RTL8723B
)
6537 rtl8xxxu_write16(priv
, REG_TRXFF_BNDY
+ 2, 0x3f7f);
6538 else if (priv
->rtl_chip
== RTL8192E
)
6539 rtl8xxxu_write16(priv
, REG_TRXFF_BNDY
+ 2, 0x3cff);
6541 rtl8xxxu_write16(priv
, REG_TRXFF_BNDY
+ 2, 0x27ff);
6543 * Transfer page size is always 128
6545 if (priv
->rtl_chip
== RTL8723B
)
6546 val8
= (PBP_PAGE_SIZE_256
<< PBP_PAGE_SIZE_RX_SHIFT
) |
6547 (PBP_PAGE_SIZE_256
<< PBP_PAGE_SIZE_TX_SHIFT
);
6549 val8
= (PBP_PAGE_SIZE_128
<< PBP_PAGE_SIZE_RX_SHIFT
) |
6550 (PBP_PAGE_SIZE_128
<< PBP_PAGE_SIZE_TX_SHIFT
);
6551 rtl8xxxu_write8(priv
, REG_PBP
, val8
);
6554 * Unit in 8 bytes, not obvious what it is used for
6556 rtl8xxxu_write8(priv
, REG_RX_DRVINFO_SZ
, 4);
6559 * Enable all interrupts - not obvious USB needs to do this
6561 rtl8xxxu_write32(priv
, REG_HISR
, 0xffffffff);
6562 rtl8xxxu_write32(priv
, REG_HIMR
, 0xffffffff);
6564 rtl8xxxu_set_mac(priv
);
6565 rtl8xxxu_set_linktype(priv
, NL80211_IFTYPE_STATION
);
6568 * Configure initial WMAC settings
6570 val32
= RCR_ACCEPT_PHYS_MATCH
| RCR_ACCEPT_MCAST
| RCR_ACCEPT_BCAST
|
6571 RCR_ACCEPT_MGMT_FRAME
| RCR_HTC_LOC_CTRL
|
6572 RCR_APPEND_PHYSTAT
| RCR_APPEND_ICV
| RCR_APPEND_MIC
;
6573 rtl8xxxu_write32(priv
, REG_RCR
, val32
);
6576 * Accept all multicast
6578 rtl8xxxu_write32(priv
, REG_MAR
, 0xffffffff);
6579 rtl8xxxu_write32(priv
, REG_MAR
+ 4, 0xffffffff);
6582 * Init adaptive controls
6584 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
6585 val32
&= ~RESPONSE_RATE_BITMAP_ALL
;
6586 val32
|= RESPONSE_RATE_RRSR_CCK_ONLY_1M
;
6587 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
6589 /* CCK = 0x0a, OFDM = 0x10 */
6590 rtl8xxxu_set_spec_sifs(priv
, 0x10, 0x10);
6591 rtl8xxxu_set_retry(priv
, 0x30, 0x30);
6592 rtl8xxxu_set_spec_sifs(priv
, 0x0a, 0x10);
6597 rtl8xxxu_write16(priv
, REG_MAC_SPEC_SIFS
, 0x100a);
6600 rtl8xxxu_write16(priv
, REG_SIFS_CCK
, 0x100a);
6603 rtl8xxxu_write16(priv
, REG_SIFS_OFDM
, 0x100a);
6606 rtl8xxxu_write32(priv
, REG_EDCA_BE_PARAM
, 0x005ea42b);
6607 rtl8xxxu_write32(priv
, REG_EDCA_BK_PARAM
, 0x0000a44f);
6608 rtl8xxxu_write32(priv
, REG_EDCA_VI_PARAM
, 0x005ea324);
6609 rtl8xxxu_write32(priv
, REG_EDCA_VO_PARAM
, 0x002fa226);
6611 /* Set data auto rate fallback retry count */
6612 rtl8xxxu_write32(priv
, REG_DARFRC
, 0x00000000);
6613 rtl8xxxu_write32(priv
, REG_DARFRC
+ 4, 0x10080404);
6614 rtl8xxxu_write32(priv
, REG_RARFRC
, 0x04030201);
6615 rtl8xxxu_write32(priv
, REG_RARFRC
+ 4, 0x08070605);
6617 val8
= rtl8xxxu_read8(priv
, REG_FWHW_TXQ_CTRL
);
6618 val8
|= FWHW_TXQ_CTRL_AMPDU_RETRY
;
6619 rtl8xxxu_write8(priv
, REG_FWHW_TXQ_CTRL
, val8
);
6621 /* Set ACK timeout */
6622 rtl8xxxu_write8(priv
, REG_ACKTO
, 0x40);
6625 * Initialize beacon parameters
6627 val16
= BEACON_DISABLE_TSF_UPDATE
| (BEACON_DISABLE_TSF_UPDATE
<< 8);
6628 rtl8xxxu_write16(priv
, REG_BEACON_CTRL
, val16
);
6629 rtl8xxxu_write16(priv
, REG_TBTT_PROHIBIT
, 0x6404);
6630 rtl8xxxu_write8(priv
, REG_DRIVER_EARLY_INT
, DRIVER_EARLY_INT_TIME
);
6631 rtl8xxxu_write8(priv
, REG_BEACON_DMA_TIME
, BEACON_DMA_ATIME_INT_TIME
);
6632 rtl8xxxu_write16(priv
, REG_BEACON_TCFG
, 0x660F);
6635 * Initialize burst parameters
6637 if (priv
->rtl_chip
== RTL8723B
) {
6639 * For USB high speed set 512B packets
6641 val8
= rtl8xxxu_read8(priv
, REG_RXDMA_PRO_8723B
);
6642 val8
&= ~(BIT(4) | BIT(5));
6644 val8
|= BIT(1) | BIT(2) | BIT(3);
6645 rtl8xxxu_write8(priv
, REG_RXDMA_PRO_8723B
, val8
);
6648 * For USB high speed set 512B packets
6650 val8
= rtl8xxxu_read8(priv
, REG_HT_SINGLE_AMPDU_8723B
);
6652 rtl8xxxu_write8(priv
, REG_HT_SINGLE_AMPDU_8723B
, val8
);
6654 rtl8xxxu_write16(priv
, REG_MAX_AGGR_NUM
, 0x0c14);
6655 rtl8xxxu_write8(priv
, REG_AMPDU_MAX_TIME_8723B
, 0x5e);
6656 rtl8xxxu_write32(priv
, REG_AGGLEN_LMT
, 0xffffffff);
6657 rtl8xxxu_write8(priv
, REG_RX_PKT_LIMIT
, 0x18);
6658 rtl8xxxu_write8(priv
, REG_PIFS
, 0x00);
6659 rtl8xxxu_write8(priv
, REG_USTIME_TSF_8723B
, 0x50);
6660 rtl8xxxu_write8(priv
, REG_USTIME_EDCA
, 0x50);
6662 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
);
6663 val8
|= BIT(5) | BIT(6);
6664 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, val8
);
6667 if (priv
->fops
->init_aggregation
)
6668 priv
->fops
->init_aggregation(priv
);
6671 * Enable CCK and OFDM block
6673 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
6674 val32
|= (FPGA_RF_MODE_CCK
| FPGA_RF_MODE_OFDM
);
6675 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
6678 * Invalidate all CAM entries - bit 30 is undocumented
6680 rtl8xxxu_write32(priv
, REG_CAM_CMD
, CAM_CMD_POLLING
| BIT(30));
6683 * Start out with default power levels for channel 6, 20MHz
6685 priv
->fops
->set_tx_power(priv
, 1, false);
6687 /* Let the 8051 take control of antenna setting */
6688 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
6689 val8
|= LEDCFG2_DPDT_SELECT
;
6690 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
6692 rtl8xxxu_write8(priv
, REG_HWSEQ_CTRL
, 0xff);
6694 /* Disable BAR - not sure if this has any effect on USB */
6695 rtl8xxxu_write32(priv
, REG_BAR_MODE_CTRL
, 0x0201ffff);
6697 rtl8xxxu_write16(priv
, REG_FAST_EDCA_CTRL
, 0);
6699 if (priv
->fops
->init_statistics
)
6700 priv
->fops
->init_statistics(priv
);
6702 rtl8723a_phy_lc_calibrate(priv
);
6704 priv
->fops
->phy_iq_calibrate(priv
);
6707 * This should enable thermal meter
6709 if (priv
->fops
->has_s0s1
)
6710 rtl8xxxu_write_rfreg(priv
,
6711 RF_A
, RF6052_REG_T_METER_8723B
, 0x37cf8);
6713 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_T_METER
, 0x60);
6715 /* Set NAV_UPPER to 30000us */
6716 val8
= ((30000 + NAV_UPPER_UNIT
- 1) / NAV_UPPER_UNIT
);
6717 rtl8xxxu_write8(priv
, REG_NAV_UPPER
, val8
);
6719 if (priv
->rtl_chip
== RTL8723A
) {
6721 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6722 * but we need to find root cause.
6723 * This is 8723au only.
6725 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
6726 if ((val32
& 0xff000000) != 0x83000000) {
6727 val32
|= FPGA_RF_MODE_CCK
;
6728 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
6732 val32
= rtl8xxxu_read32(priv
, REG_FWHW_TXQ_CTRL
);
6733 val32
|= FWHW_TXQ_CTRL_XMIT_MGMT_ACK
;
6734 /* ack for xmit mgmt frames. */
6735 rtl8xxxu_write32(priv
, REG_FWHW_TXQ_CTRL
, val32
);
6741 static void rtl8xxxu_disable_device(struct ieee80211_hw
*hw
)
6743 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6745 priv
->fops
->power_off(priv
);
6748 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv
*priv
,
6749 struct ieee80211_key_conf
*key
, const u8
*mac
)
6751 u32 cmd
, val32
, addr
, ctrl
;
6752 int j
, i
, tmp_debug
;
6754 tmp_debug
= rtl8xxxu_debug
;
6755 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_KEY
)
6756 rtl8xxxu_debug
|= RTL8XXXU_DEBUG_REG_WRITE
;
6759 * This is a bit of a hack - the lower bits of the cipher
6760 * suite selector happens to match the cipher index in the CAM
6762 addr
= key
->keyidx
<< CAM_CMD_KEY_SHIFT
;
6763 ctrl
= (key
->cipher
& 0x0f) << 2 | key
->keyidx
| CAM_WRITE_VALID
;
6765 for (j
= 5; j
>= 0; j
--) {
6768 val32
= ctrl
| (mac
[0] << 16) | (mac
[1] << 24);
6771 val32
= mac
[2] | (mac
[3] << 8) |
6772 (mac
[4] << 16) | (mac
[5] << 24);
6776 val32
= key
->key
[i
] | (key
->key
[i
+ 1] << 8) |
6777 key
->key
[i
+ 2] << 16 | key
->key
[i
+ 3] << 24;
6781 rtl8xxxu_write32(priv
, REG_CAM_WRITE
, val32
);
6782 cmd
= CAM_CMD_POLLING
| CAM_CMD_WRITE
| (addr
+ j
);
6783 rtl8xxxu_write32(priv
, REG_CAM_CMD
, cmd
);
6787 rtl8xxxu_debug
= tmp_debug
;
6790 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw
*hw
,
6791 struct ieee80211_vif
*vif
, const u8
*mac
)
6793 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6796 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
6797 val8
|= BEACON_DISABLE_TSF_UPDATE
;
6798 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
6801 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw
*hw
,
6802 struct ieee80211_vif
*vif
)
6804 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6807 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
6808 val8
&= ~BEACON_DISABLE_TSF_UPDATE
;
6809 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
6812 static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv
*priv
,
6813 u32 ramask
, int sgi
)
6817 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6819 h2c
.ramask
.cmd
= H2C_SET_RATE_MASK
;
6820 h2c
.ramask
.mask_lo
= cpu_to_le16(ramask
& 0xffff);
6821 h2c
.ramask
.mask_hi
= cpu_to_le16(ramask
>> 16);
6823 h2c
.ramask
.arg
= 0x80;
6825 h2c
.ramask
.arg
|= 0x20;
6827 dev_dbg(&priv
->udev
->dev
, "%s: rate mask %08x, arg %02x, size %zi\n",
6828 __func__
, ramask
, h2c
.ramask
.arg
, sizeof(h2c
.ramask
));
6829 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ramask
));
6832 static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv
*priv
,
6833 u32 ramask
, int sgi
)
6838 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6840 h2c
.b_macid_cfg
.cmd
= H2C_8723B_MACID_CFG_RAID
;
6841 h2c
.b_macid_cfg
.ramask0
= ramask
& 0xff;
6842 h2c
.b_macid_cfg
.ramask1
= (ramask
>> 8) & 0xff;
6843 h2c
.b_macid_cfg
.ramask2
= (ramask
>> 16) & 0xff;
6844 h2c
.b_macid_cfg
.ramask3
= (ramask
>> 24) & 0xff;
6846 h2c
.ramask
.arg
= 0x80;
6847 h2c
.b_macid_cfg
.data1
= 0;
6849 h2c
.b_macid_cfg
.data1
|= BIT(7);
6851 h2c
.b_macid_cfg
.data2
= bw
;
6853 dev_dbg(&priv
->udev
->dev
, "%s: rate mask %08x, arg %02x, size %zi\n",
6854 __func__
, ramask
, h2c
.ramask
.arg
, sizeof(h2c
.b_macid_cfg
));
6855 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.b_macid_cfg
));
6858 static void rtl8723au_report_connect(struct rtl8xxxu_priv
*priv
,
6859 u8 macid
, bool connect
)
6863 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6865 h2c
.joinbss
.cmd
= H2C_JOIN_BSS_REPORT
;
6868 h2c
.joinbss
.data
= H2C_JOIN_BSS_CONNECT
;
6870 h2c
.joinbss
.data
= H2C_JOIN_BSS_DISCONNECT
;
6872 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.joinbss
));
6875 static void rtl8723bu_report_connect(struct rtl8xxxu_priv
*priv
,
6876 u8 macid
, bool connect
)
6880 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
6882 h2c
.media_status_rpt
.cmd
= H2C_8723B_MEDIA_STATUS_RPT
;
6884 h2c
.media_status_rpt
.parm
|= BIT(0);
6886 h2c
.media_status_rpt
.parm
&= ~BIT(0);
6888 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.media_status_rpt
));
6891 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv
*priv
, u32 rate_cfg
)
6896 rate_cfg
&= RESPONSE_RATE_BITMAP_ALL
;
6898 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
6899 val32
&= ~RESPONSE_RATE_BITMAP_ALL
;
6901 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
6903 dev_dbg(&priv
->udev
->dev
, "%s: rates %08x\n", __func__
, rate_cfg
);
6906 rate_cfg
= (rate_cfg
>> 1);
6909 rtl8xxxu_write8(priv
, REG_INIRTS_RATE_SEL
, rate_idx
);
6913 rtl8xxxu_bss_info_changed(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
6914 struct ieee80211_bss_conf
*bss_conf
, u32 changed
)
6916 struct rtl8xxxu_priv
*priv
= hw
->priv
;
6917 struct device
*dev
= &priv
->udev
->dev
;
6918 struct ieee80211_sta
*sta
;
6922 if (changed
& BSS_CHANGED_ASSOC
) {
6923 dev_dbg(dev
, "Changed ASSOC: %i!\n", bss_conf
->assoc
);
6925 rtl8xxxu_set_linktype(priv
, vif
->type
);
6927 if (bss_conf
->assoc
) {
6932 sta
= ieee80211_find_sta(vif
, bss_conf
->bssid
);
6934 dev_info(dev
, "%s: ASSOC no sta found\n",
6940 if (sta
->ht_cap
.ht_supported
)
6941 dev_info(dev
, "%s: HT supported\n", __func__
);
6942 if (sta
->vht_cap
.vht_supported
)
6943 dev_info(dev
, "%s: VHT supported\n", __func__
);
6945 /* TODO: Set bits 28-31 for rate adaptive id */
6946 ramask
= (sta
->supp_rates
[0] & 0xfff) |
6947 sta
->ht_cap
.mcs
.rx_mask
[0] << 12 |
6948 sta
->ht_cap
.mcs
.rx_mask
[1] << 20;
6949 if (sta
->ht_cap
.cap
&
6950 (IEEE80211_HT_CAP_SGI_40
| IEEE80211_HT_CAP_SGI_20
))
6954 priv
->fops
->update_rate_mask(priv
, ramask
, sgi
);
6956 rtl8xxxu_write8(priv
, REG_BCN_MAX_ERR
, 0xff);
6958 rtl8723a_stop_tx_beacon(priv
);
6960 /* joinbss sequence */
6961 rtl8xxxu_write16(priv
, REG_BCN_PSR_RPT
,
6962 0xc000 | bss_conf
->aid
);
6964 priv
->fops
->report_connect(priv
, 0, true);
6966 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
6967 val8
|= BEACON_DISABLE_TSF_UPDATE
;
6968 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
6970 priv
->fops
->report_connect(priv
, 0, false);
6974 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
6975 dev_dbg(dev
, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6976 bss_conf
->use_short_preamble
);
6977 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
6978 if (bss_conf
->use_short_preamble
)
6979 val32
|= RSR_ACK_SHORT_PREAMBLE
;
6981 val32
&= ~RSR_ACK_SHORT_PREAMBLE
;
6982 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
6985 if (changed
& BSS_CHANGED_ERP_SLOT
) {
6986 dev_dbg(dev
, "Changed ERP_SLOT: short_slot_time %i\n",
6987 bss_conf
->use_short_slot
);
6989 if (bss_conf
->use_short_slot
)
6993 rtl8xxxu_write8(priv
, REG_SLOT
, val8
);
6996 if (changed
& BSS_CHANGED_BSSID
) {
6997 dev_dbg(dev
, "Changed BSSID!\n");
6998 rtl8xxxu_set_bssid(priv
, bss_conf
->bssid
);
7001 if (changed
& BSS_CHANGED_BASIC_RATES
) {
7002 dev_dbg(dev
, "Changed BASIC_RATES!\n");
7003 rtl8xxxu_set_basic_rates(priv
, bss_conf
->basic_rates
);
7009 static u32
rtl8xxxu_80211_to_rtl_queue(u32 queue
)
7014 case IEEE80211_AC_VO
:
7015 rtlqueue
= TXDESC_QUEUE_VO
;
7017 case IEEE80211_AC_VI
:
7018 rtlqueue
= TXDESC_QUEUE_VI
;
7020 case IEEE80211_AC_BE
:
7021 rtlqueue
= TXDESC_QUEUE_BE
;
7023 case IEEE80211_AC_BK
:
7024 rtlqueue
= TXDESC_QUEUE_BK
;
7027 rtlqueue
= TXDESC_QUEUE_BE
;
7033 static u32
rtl8xxxu_queue_select(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
7035 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
7038 if (ieee80211_is_mgmt(hdr
->frame_control
))
7039 queue
= TXDESC_QUEUE_MGNT
;
7041 queue
= rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb
));
7047 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
7048 * format. The descriptor checksum is still only calculated over the
7049 * initial 32 bytes of the descriptor!
7051 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32
*tx_desc
)
7053 __le16
*ptr
= (__le16
*)tx_desc
;
7058 * Clear csum field before calculation, as the csum field is
7059 * in the middle of the struct.
7061 tx_desc
->csum
= cpu_to_le16(0);
7063 for (i
= 0; i
< (sizeof(struct rtl8xxxu_txdesc32
) / sizeof(u16
)); i
++)
7064 csum
= csum
^ le16_to_cpu(ptr
[i
]);
7066 tx_desc
->csum
|= cpu_to_le16(csum
);
7069 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv
*priv
)
7071 struct rtl8xxxu_tx_urb
*tx_urb
, *tmp
;
7072 unsigned long flags
;
7074 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
7075 list_for_each_entry_safe(tx_urb
, tmp
, &priv
->tx_urb_free_list
, list
) {
7076 list_del(&tx_urb
->list
);
7077 priv
->tx_urb_free_count
--;
7078 usb_free_urb(&tx_urb
->urb
);
7080 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
7083 static struct rtl8xxxu_tx_urb
*
7084 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv
*priv
)
7086 struct rtl8xxxu_tx_urb
*tx_urb
;
7087 unsigned long flags
;
7089 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
7090 tx_urb
= list_first_entry_or_null(&priv
->tx_urb_free_list
,
7091 struct rtl8xxxu_tx_urb
, list
);
7093 list_del(&tx_urb
->list
);
7094 priv
->tx_urb_free_count
--;
7095 if (priv
->tx_urb_free_count
< RTL8XXXU_TX_URB_LOW_WATER
&&
7096 !priv
->tx_stopped
) {
7097 priv
->tx_stopped
= true;
7098 ieee80211_stop_queues(priv
->hw
);
7102 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
7107 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv
*priv
,
7108 struct rtl8xxxu_tx_urb
*tx_urb
)
7110 unsigned long flags
;
7112 INIT_LIST_HEAD(&tx_urb
->list
);
7114 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
7116 list_add(&tx_urb
->list
, &priv
->tx_urb_free_list
);
7117 priv
->tx_urb_free_count
++;
7118 if (priv
->tx_urb_free_count
> RTL8XXXU_TX_URB_HIGH_WATER
&&
7120 priv
->tx_stopped
= false;
7121 ieee80211_wake_queues(priv
->hw
);
7124 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
7127 static void rtl8xxxu_tx_complete(struct urb
*urb
)
7129 struct sk_buff
*skb
= (struct sk_buff
*)urb
->context
;
7130 struct ieee80211_tx_info
*tx_info
;
7131 struct ieee80211_hw
*hw
;
7132 struct rtl8xxxu_priv
*priv
;
7133 struct rtl8xxxu_tx_urb
*tx_urb
=
7134 container_of(urb
, struct rtl8xxxu_tx_urb
, urb
);
7136 tx_info
= IEEE80211_SKB_CB(skb
);
7137 hw
= tx_info
->rate_driver_data
[0];
7140 skb_pull(skb
, priv
->fops
->tx_desc_size
);
7142 ieee80211_tx_info_clear_status(tx_info
);
7143 tx_info
->status
.rates
[0].idx
= -1;
7144 tx_info
->status
.rates
[0].count
= 0;
7147 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
7149 ieee80211_tx_status_irqsafe(hw
, skb
);
7151 rtl8xxxu_free_tx_urb(priv
, tx_urb
);
7154 static void rtl8xxxu_dump_action(struct device
*dev
,
7155 struct ieee80211_hdr
*hdr
)
7157 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)hdr
;
7160 if (!(rtl8xxxu_debug
& RTL8XXXU_DEBUG_ACTION
))
7163 switch (mgmt
->u
.action
.u
.addba_resp
.action_code
) {
7164 case WLAN_ACTION_ADDBA_RESP
:
7165 cap
= le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.capab
);
7166 timeout
= le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.timeout
);
7167 dev_info(dev
, "WLAN_ACTION_ADDBA_RESP: "
7168 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
7171 (cap
& IEEE80211_ADDBA_PARAM_TID_MASK
) >> 2,
7172 (cap
& IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
) >> 6,
7174 le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.status
));
7176 case WLAN_ACTION_ADDBA_REQ
:
7177 cap
= le16_to_cpu(mgmt
->u
.action
.u
.addba_req
.capab
);
7178 timeout
= le16_to_cpu(mgmt
->u
.action
.u
.addba_req
.timeout
);
7179 dev_info(dev
, "WLAN_ACTION_ADDBA_REQ: "
7180 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
7182 (cap
& IEEE80211_ADDBA_PARAM_TID_MASK
) >> 2,
7183 (cap
& IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
) >> 6,
7187 dev_info(dev
, "action frame %02x\n",
7188 mgmt
->u
.action
.u
.addba_resp
.action_code
);
7193 static void rtl8xxxu_tx(struct ieee80211_hw
*hw
,
7194 struct ieee80211_tx_control
*control
,
7195 struct sk_buff
*skb
)
7197 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
7198 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
7199 struct ieee80211_rate
*tx_rate
= ieee80211_get_tx_rate(hw
, tx_info
);
7200 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7201 struct rtl8xxxu_txdesc32
*tx_desc
;
7202 struct rtl8xxxu_txdesc40
*tx_desc40
;
7203 struct rtl8xxxu_tx_urb
*tx_urb
;
7204 struct ieee80211_sta
*sta
= NULL
;
7205 struct ieee80211_vif
*vif
= tx_info
->control
.vif
;
7206 struct device
*dev
= &priv
->udev
->dev
;
7208 u16 pktlen
= skb
->len
;
7210 u16 rate_flag
= tx_info
->control
.rates
[0].flags
;
7211 int tx_desc_size
= priv
->fops
->tx_desc_size
;
7213 bool usedesc40
, ampdu_enable
;
7215 if (skb_headroom(skb
) < tx_desc_size
) {
7217 "%s: Not enough headroom (%i) for tx descriptor\n",
7218 __func__
, skb_headroom(skb
));
7222 if (unlikely(skb
->len
> (65535 - tx_desc_size
))) {
7223 dev_warn(dev
, "%s: Trying to send over-sized skb (%i)\n",
7224 __func__
, skb
->len
);
7228 tx_urb
= rtl8xxxu_alloc_tx_urb(priv
);
7230 dev_warn(dev
, "%s: Unable to allocate tx urb\n", __func__
);
7234 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_TX
)
7235 dev_info(dev
, "%s: TX rate: %d (%d), pkt size %d\n",
7236 __func__
, tx_rate
->bitrate
, tx_rate
->hw_value
, pktlen
);
7238 if (ieee80211_is_action(hdr
->frame_control
))
7239 rtl8xxxu_dump_action(dev
, hdr
);
7241 usedesc40
= (tx_desc_size
== 40);
7242 tx_info
->rate_driver_data
[0] = hw
;
7244 if (control
&& control
->sta
)
7247 tx_desc
= (struct rtl8xxxu_txdesc32
*)skb_push(skb
, tx_desc_size
);
7249 memset(tx_desc
, 0, tx_desc_size
);
7250 tx_desc
->pkt_size
= cpu_to_le16(pktlen
);
7251 tx_desc
->pkt_offset
= tx_desc_size
;
7254 TXDESC_OWN
| TXDESC_FIRST_SEGMENT
| TXDESC_LAST_SEGMENT
;
7255 if (is_multicast_ether_addr(ieee80211_get_DA(hdr
)) ||
7256 is_broadcast_ether_addr(ieee80211_get_DA(hdr
)))
7257 tx_desc
->txdw0
|= TXDESC_BROADMULTICAST
;
7259 queue
= rtl8xxxu_queue_select(hw
, skb
);
7260 tx_desc
->txdw1
= cpu_to_le32(queue
<< TXDESC_QUEUE_SHIFT
);
7262 if (tx_info
->control
.hw_key
) {
7263 switch (tx_info
->control
.hw_key
->cipher
) {
7264 case WLAN_CIPHER_SUITE_WEP40
:
7265 case WLAN_CIPHER_SUITE_WEP104
:
7266 case WLAN_CIPHER_SUITE_TKIP
:
7267 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_SEC_RC4
);
7269 case WLAN_CIPHER_SUITE_CCMP
:
7270 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_SEC_AES
);
7277 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
7278 ampdu_enable
= false;
7279 if (ieee80211_is_data_qos(hdr
->frame_control
) && sta
) {
7280 if (sta
->ht_cap
.ht_supported
) {
7283 ampdu
= (u32
)sta
->ht_cap
.ampdu_density
;
7284 val32
= ampdu
<< TXDESC_AMPDU_DENSITY_SHIFT
;
7285 tx_desc
->txdw2
|= cpu_to_le32(val32
);
7287 ampdu_enable
= true;
7291 if (rate_flag
& IEEE80211_TX_RC_MCS
)
7292 rate
= tx_info
->control
.rates
[0].idx
+ DESC_RATE_MCS0
;
7294 rate
= tx_rate
->hw_value
;
7296 seq_number
= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
7298 tx_desc
->txdw5
= cpu_to_le32(rate
);
7300 if (ieee80211_is_data(hdr
->frame_control
))
7301 tx_desc
->txdw5
|= cpu_to_le32(0x0001ff00);
7304 cpu_to_le32((u32
)seq_number
<< TXDESC32_SEQ_SHIFT
);
7307 tx_desc
->txdw1
|= cpu_to_le32(TXDESC32_AGG_ENABLE
);
7309 tx_desc
->txdw1
|= cpu_to_le32(TXDESC32_AGG_BREAK
);
7311 if (ieee80211_is_mgmt(hdr
->frame_control
)) {
7312 tx_desc
->txdw5
= cpu_to_le32(tx_rate
->hw_value
);
7314 cpu_to_le32(TXDESC32_USE_DRIVER_RATE
);
7316 cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT
);
7318 cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE
);
7321 if (ieee80211_is_data_qos(hdr
->frame_control
))
7322 tx_desc
->txdw4
|= cpu_to_le32(TXDESC32_QOS
);
7324 if (rate_flag
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
||
7325 (sta
&& vif
&& vif
->bss_conf
.use_short_preamble
))
7326 tx_desc
->txdw4
|= cpu_to_le32(TXDESC32_SHORT_PREAMBLE
);
7328 if (rate_flag
& IEEE80211_TX_RC_SHORT_GI
||
7329 (ieee80211_is_data_qos(hdr
->frame_control
) &&
7330 sta
&& sta
->ht_cap
.cap
&
7331 (IEEE80211_HT_CAP_SGI_40
| IEEE80211_HT_CAP_SGI_20
))) {
7332 tx_desc
->txdw5
|= cpu_to_le32(TXDESC32_SHORT_GI
);
7335 if (rate_flag
& IEEE80211_TX_RC_USE_RTS_CTS
) {
7337 * Use RTS rate 24M - does the mac80211 tell
7341 cpu_to_le32(DESC_RATE_24M
<<
7342 TXDESC32_RTS_RATE_SHIFT
);
7344 cpu_to_le32(TXDESC32_RTS_CTS_ENABLE
);
7345 tx_desc
->txdw4
|= cpu_to_le32(TXDESC32_HW_RTS_ENABLE
);
7348 tx_desc40
= (struct rtl8xxxu_txdesc40
*)tx_desc
;
7350 tx_desc40
->txdw4
= cpu_to_le32(rate
);
7351 if (ieee80211_is_data(hdr
->frame_control
)) {
7354 TXDESC40_DATA_RATE_FB_SHIFT
);
7358 cpu_to_le32((u32
)seq_number
<< TXDESC40_SEQ_SHIFT
);
7361 tx_desc40
->txdw2
|= cpu_to_le32(TXDESC40_AGG_ENABLE
);
7363 tx_desc40
->txdw2
|= cpu_to_le32(TXDESC40_AGG_BREAK
);
7365 if (ieee80211_is_mgmt(hdr
->frame_control
)) {
7366 tx_desc40
->txdw4
= cpu_to_le32(tx_rate
->hw_value
);
7368 cpu_to_le32(TXDESC40_USE_DRIVER_RATE
);
7370 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT
);
7372 cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE
);
7375 if (rate_flag
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
||
7376 (sta
&& vif
&& vif
->bss_conf
.use_short_preamble
))
7378 cpu_to_le32(TXDESC40_SHORT_PREAMBLE
);
7380 if (rate_flag
& IEEE80211_TX_RC_USE_RTS_CTS
) {
7382 * Use RTS rate 24M - does the mac80211 tell
7386 cpu_to_le32(DESC_RATE_24M
<<
7387 TXDESC40_RTS_RATE_SHIFT
);
7388 tx_desc
->txdw3
|= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE
);
7389 tx_desc
->txdw3
|= cpu_to_le32(TXDESC40_HW_RTS_ENABLE
);
7393 rtl8xxxu_calc_tx_desc_csum(tx_desc
);
7395 usb_fill_bulk_urb(&tx_urb
->urb
, priv
->udev
, priv
->pipe_out
[queue
],
7396 skb
->data
, skb
->len
, rtl8xxxu_tx_complete
, skb
);
7398 usb_anchor_urb(&tx_urb
->urb
, &priv
->tx_anchor
);
7399 ret
= usb_submit_urb(&tx_urb
->urb
, GFP_ATOMIC
);
7401 usb_unanchor_urb(&tx_urb
->urb
);
7402 rtl8xxxu_free_tx_urb(priv
, tx_urb
);
7410 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv
*priv
,
7411 struct ieee80211_rx_status
*rx_status
,
7412 struct rtl8723au_phy_stats
*phy_stats
,
7415 if (phy_stats
->sgi_en
)
7416 rx_status
->flag
|= RX_FLAG_SHORT_GI
;
7418 if (rxmcs
< DESC_RATE_6M
) {
7420 * Handle PHY stats for CCK rates
7422 u8 cck_agc_rpt
= phy_stats
->cck_agc_rpt_ofdm_cfosho_a
;
7424 switch (cck_agc_rpt
& 0xc0) {
7426 rx_status
->signal
= -46 - (cck_agc_rpt
& 0x3e);
7429 rx_status
->signal
= -26 - (cck_agc_rpt
& 0x3e);
7432 rx_status
->signal
= -12 - (cck_agc_rpt
& 0x3e);
7435 rx_status
->signal
= 16 - (cck_agc_rpt
& 0x3e);
7440 (phy_stats
->cck_sig_qual_ofdm_pwdb_all
>> 1) - 110;
7444 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv
*priv
)
7446 struct rtl8xxxu_rx_urb
*rx_urb
, *tmp
;
7447 unsigned long flags
;
7449 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7451 list_for_each_entry_safe(rx_urb
, tmp
,
7452 &priv
->rx_urb_pending_list
, list
) {
7453 list_del(&rx_urb
->list
);
7454 priv
->rx_urb_pending_count
--;
7455 usb_free_urb(&rx_urb
->urb
);
7458 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7461 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv
*priv
,
7462 struct rtl8xxxu_rx_urb
*rx_urb
)
7464 struct sk_buff
*skb
;
7465 unsigned long flags
;
7468 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7470 if (!priv
->shutdown
) {
7471 list_add_tail(&rx_urb
->list
, &priv
->rx_urb_pending_list
);
7472 priv
->rx_urb_pending_count
++;
7473 pending
= priv
->rx_urb_pending_count
;
7475 skb
= (struct sk_buff
*)rx_urb
->urb
.context
;
7477 usb_free_urb(&rx_urb
->urb
);
7480 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7482 if (pending
> RTL8XXXU_RX_URB_PENDING_WATER
)
7483 schedule_work(&priv
->rx_urb_wq
);
7486 static void rtl8xxxu_rx_urb_work(struct work_struct
*work
)
7488 struct rtl8xxxu_priv
*priv
;
7489 struct rtl8xxxu_rx_urb
*rx_urb
, *tmp
;
7490 struct list_head local
;
7491 struct sk_buff
*skb
;
7492 unsigned long flags
;
7495 priv
= container_of(work
, struct rtl8xxxu_priv
, rx_urb_wq
);
7496 INIT_LIST_HEAD(&local
);
7498 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
7500 list_splice_init(&priv
->rx_urb_pending_list
, &local
);
7501 priv
->rx_urb_pending_count
= 0;
7503 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
7505 list_for_each_entry_safe(rx_urb
, tmp
, &local
, list
) {
7506 list_del_init(&rx_urb
->list
);
7507 ret
= rtl8xxxu_submit_rx_urb(priv
, rx_urb
);
7509 * If out of memory or temporary error, put it back on the
7510 * queue and try again. Otherwise the device is dead/gone
7511 * and we should drop it.
7518 rtl8xxxu_queue_rx_urb(priv
, rx_urb
);
7521 pr_info("failed to requeue urb %i\n", ret
);
7522 skb
= (struct sk_buff
*)rx_urb
->urb
.context
;
7524 usb_free_urb(&rx_urb
->urb
);
7529 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv
*priv
,
7530 struct sk_buff
*skb
,
7531 struct ieee80211_rx_status
*rx_status
)
7533 struct rtl8xxxu_rx_desc
*rx_desc
= (struct rtl8xxxu_rx_desc
*)skb
->data
;
7534 struct rtl8723au_phy_stats
*phy_stats
;
7535 int drvinfo_sz
, desc_shift
;
7537 skb_pull(skb
, sizeof(struct rtl8xxxu_rx_desc
));
7539 phy_stats
= (struct rtl8723au_phy_stats
*)skb
->data
;
7541 drvinfo_sz
= rx_desc
->drvinfo_sz
* 8;
7542 desc_shift
= rx_desc
->shift
;
7543 skb_pull(skb
, drvinfo_sz
+ desc_shift
);
7545 if (rx_desc
->phy_stats
)
7546 rtl8xxxu_rx_parse_phystats(priv
, rx_status
, phy_stats
,
7549 rx_status
->mactime
= le32_to_cpu(rx_desc
->tsfl
);
7550 rx_status
->flag
|= RX_FLAG_MACTIME_START
;
7552 if (!rx_desc
->swdec
)
7553 rx_status
->flag
|= RX_FLAG_DECRYPTED
;
7555 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
7557 rx_status
->flag
|= RX_FLAG_40MHZ
;
7559 if (rx_desc
->rxht
) {
7560 rx_status
->flag
|= RX_FLAG_HT
;
7561 rx_status
->rate_idx
= rx_desc
->rxmcs
- DESC_RATE_MCS0
;
7563 rx_status
->rate_idx
= rx_desc
->rxmcs
;
7566 return RX_TYPE_DATA_PKT
;
7569 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv
*priv
,
7570 struct sk_buff
*skb
,
7571 struct ieee80211_rx_status
*rx_status
)
7573 struct rtl8723bu_rx_desc
*rx_desc
=
7574 (struct rtl8723bu_rx_desc
*)skb
->data
;
7575 struct rtl8723au_phy_stats
*phy_stats
;
7576 int drvinfo_sz
, desc_shift
;
7578 skb_pull(skb
, sizeof(struct rtl8723bu_rx_desc
));
7580 phy_stats
= (struct rtl8723au_phy_stats
*)skb
->data
;
7582 drvinfo_sz
= rx_desc
->drvinfo_sz
* 8;
7583 desc_shift
= rx_desc
->shift
;
7584 skb_pull(skb
, drvinfo_sz
+ desc_shift
);
7586 if (rx_desc
->rpt_sel
) {
7587 struct device
*dev
= &priv
->udev
->dev
;
7588 dev_dbg(dev
, "%s: C2H packet\n", __func__
);
7592 if (rx_desc
->phy_stats
)
7593 rtl8xxxu_rx_parse_phystats(priv
, rx_status
, phy_stats
,
7596 rx_status
->mactime
= le32_to_cpu(rx_desc
->tsfl
);
7597 rx_status
->flag
|= RX_FLAG_MACTIME_START
;
7599 if (!rx_desc
->swdec
)
7600 rx_status
->flag
|= RX_FLAG_DECRYPTED
;
7602 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
7604 rx_status
->flag
|= RX_FLAG_40MHZ
;
7606 if (rx_desc
->rxmcs
>= DESC_RATE_MCS0
) {
7607 rx_status
->flag
|= RX_FLAG_HT
;
7608 rx_status
->rate_idx
= rx_desc
->rxmcs
- DESC_RATE_MCS0
;
7610 rx_status
->rate_idx
= rx_desc
->rxmcs
;
7613 return RX_TYPE_DATA_PKT
;
7616 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv
*priv
,
7617 struct sk_buff
*skb
)
7619 struct rtl8723bu_c2h
*c2h
= (struct rtl8723bu_c2h
*)skb
->data
;
7620 struct device
*dev
= &priv
->udev
->dev
;
7625 dev_dbg(dev
, "C2H ID %02x seq %02x, len %02x source %02x\n",
7626 c2h
->id
, c2h
->seq
, len
, c2h
->bt_info
.response_source
);
7629 case C2H_8723B_BT_INFO
:
7630 if (c2h
->bt_info
.response_source
>
7631 BT_INFO_SRC_8723B_BT_ACTIVE_SEND
)
7632 dev_dbg(dev
, "C2H_BT_INFO WiFi only firmware\n");
7634 dev_dbg(dev
, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7636 if (c2h
->bt_info
.bt_has_reset
)
7637 dev_dbg(dev
, "BT has been reset\n");
7638 if (c2h
->bt_info
.tx_rx_mask
)
7639 dev_dbg(dev
, "BT TRx mask\n");
7642 case C2H_8723B_BT_MP_INFO
:
7643 dev_dbg(dev
, "C2H_MP_INFO ext ID %02x, status %02x\n",
7644 c2h
->bt_mp_info
.ext_id
, c2h
->bt_mp_info
.status
);
7646 case C2H_8723B_RA_REPORT
:
7648 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
7649 c2h
->ra_report
.rate
, c2h
->ra_report
.dummy0_0
,
7650 c2h
->ra_report
.macid
, c2h
->ra_report
.noisy_state
);
7653 dev_info(dev
, "Unhandled C2H event %02x seq %02x\n",
7655 print_hex_dump(KERN_INFO
, "C2H content: ", DUMP_PREFIX_NONE
,
7656 16, 1, c2h
->raw
.payload
, len
, false);
7661 static void rtl8xxxu_rx_complete(struct urb
*urb
)
7663 struct rtl8xxxu_rx_urb
*rx_urb
=
7664 container_of(urb
, struct rtl8xxxu_rx_urb
, urb
);
7665 struct ieee80211_hw
*hw
= rx_urb
->hw
;
7666 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7667 struct sk_buff
*skb
= (struct sk_buff
*)urb
->context
;
7668 struct ieee80211_rx_status
*rx_status
= IEEE80211_SKB_RXCB(skb
);
7669 struct device
*dev
= &priv
->udev
->dev
;
7670 __le32
*_rx_desc_le
= (__le32
*)skb
->data
;
7671 u32
*_rx_desc
= (u32
*)skb
->data
;
7674 for (i
= 0; i
< (sizeof(struct rtl8xxxu_rx_desc
) / sizeof(u32
)); i
++)
7675 _rx_desc
[i
] = le32_to_cpu(_rx_desc_le
[i
]);
7677 skb_put(skb
, urb
->actual_length
);
7679 if (urb
->status
== 0) {
7680 memset(rx_status
, 0, sizeof(struct ieee80211_rx_status
));
7682 rx_type
= priv
->fops
->parse_rx_desc(priv
, skb
, rx_status
);
7684 rx_status
->freq
= hw
->conf
.chandef
.chan
->center_freq
;
7685 rx_status
->band
= hw
->conf
.chandef
.chan
->band
;
7687 if (rx_type
== RX_TYPE_DATA_PKT
)
7688 ieee80211_rx_irqsafe(hw
, skb
);
7690 rtl8723bu_handle_c2h(priv
, skb
);
7695 rx_urb
->urb
.context
= NULL
;
7696 rtl8xxxu_queue_rx_urb(priv
, rx_urb
);
7698 dev_dbg(dev
, "%s: status %i\n", __func__
, urb
->status
);
7709 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv
*priv
,
7710 struct rtl8xxxu_rx_urb
*rx_urb
)
7712 struct sk_buff
*skb
;
7716 skb_size
= sizeof(struct rtl8xxxu_rx_desc
) + RTL_RX_BUFFER_SIZE
;
7717 skb
= __netdev_alloc_skb(NULL
, skb_size
, GFP_KERNEL
);
7721 memset(skb
->data
, 0, sizeof(struct rtl8xxxu_rx_desc
));
7722 usb_fill_bulk_urb(&rx_urb
->urb
, priv
->udev
, priv
->pipe_in
, skb
->data
,
7723 skb_size
, rtl8xxxu_rx_complete
, skb
);
7724 usb_anchor_urb(&rx_urb
->urb
, &priv
->rx_anchor
);
7725 ret
= usb_submit_urb(&rx_urb
->urb
, GFP_ATOMIC
);
7727 usb_unanchor_urb(&rx_urb
->urb
);
7731 static void rtl8xxxu_int_complete(struct urb
*urb
)
7733 struct rtl8xxxu_priv
*priv
= (struct rtl8xxxu_priv
*)urb
->context
;
7734 struct device
*dev
= &priv
->udev
->dev
;
7737 dev_dbg(dev
, "%s: status %i\n", __func__
, urb
->status
);
7738 if (urb
->status
== 0) {
7739 usb_anchor_urb(urb
, &priv
->int_anchor
);
7740 ret
= usb_submit_urb(urb
, GFP_ATOMIC
);
7742 usb_unanchor_urb(urb
);
7744 dev_info(dev
, "%s: Error %i\n", __func__
, urb
->status
);
7749 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw
*hw
)
7751 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7756 urb
= usb_alloc_urb(0, GFP_KERNEL
);
7760 usb_fill_int_urb(urb
, priv
->udev
, priv
->pipe_interrupt
,
7761 priv
->int_buf
, USB_INTR_CONTENT_LENGTH
,
7762 rtl8xxxu_int_complete
, priv
, 1);
7763 usb_anchor_urb(urb
, &priv
->int_anchor
);
7764 ret
= usb_submit_urb(urb
, GFP_KERNEL
);
7766 usb_unanchor_urb(urb
);
7770 val32
= rtl8xxxu_read32(priv
, REG_USB_HIMR
);
7771 val32
|= USB_HIMR_CPWM
;
7772 rtl8xxxu_write32(priv
, REG_USB_HIMR
, val32
);
7778 static int rtl8xxxu_add_interface(struct ieee80211_hw
*hw
,
7779 struct ieee80211_vif
*vif
)
7781 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7785 switch (vif
->type
) {
7786 case NL80211_IFTYPE_STATION
:
7787 rtl8723a_stop_tx_beacon(priv
);
7789 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
7790 val8
|= BEACON_ATIM
| BEACON_FUNCTION_ENABLE
|
7791 BEACON_DISABLE_TSF_UPDATE
;
7792 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
7799 rtl8xxxu_set_linktype(priv
, vif
->type
);
7804 static void rtl8xxxu_remove_interface(struct ieee80211_hw
*hw
,
7805 struct ieee80211_vif
*vif
)
7807 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7809 dev_dbg(&priv
->udev
->dev
, "%s\n", __func__
);
7812 static int rtl8xxxu_config(struct ieee80211_hw
*hw
, u32 changed
)
7814 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7815 struct device
*dev
= &priv
->udev
->dev
;
7817 int ret
= 0, channel
;
7820 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_CHANNEL
)
7822 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7823 __func__
, hw
->conf
.chandef
.chan
->hw_value
,
7824 changed
, hw
->conf
.chandef
.width
);
7826 if (changed
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
) {
7827 val16
= ((hw
->conf
.long_frame_max_tx_count
<<
7828 RETRY_LIMIT_LONG_SHIFT
) & RETRY_LIMIT_LONG_MASK
) |
7829 ((hw
->conf
.short_frame_max_tx_count
<<
7830 RETRY_LIMIT_SHORT_SHIFT
) & RETRY_LIMIT_SHORT_MASK
);
7831 rtl8xxxu_write16(priv
, REG_RETRY_LIMIT
, val16
);
7834 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
7835 switch (hw
->conf
.chandef
.width
) {
7836 case NL80211_CHAN_WIDTH_20_NOHT
:
7837 case NL80211_CHAN_WIDTH_20
:
7840 case NL80211_CHAN_WIDTH_40
:
7848 channel
= hw
->conf
.chandef
.chan
->hw_value
;
7850 priv
->fops
->set_tx_power(priv
, channel
, ht40
);
7852 priv
->fops
->config_channel(hw
);
7859 static int rtl8xxxu_conf_tx(struct ieee80211_hw
*hw
,
7860 struct ieee80211_vif
*vif
, u16 queue
,
7861 const struct ieee80211_tx_queue_params
*param
)
7863 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7864 struct device
*dev
= &priv
->udev
->dev
;
7866 u8 aifs
, acm_ctrl
, acm_bit
;
7871 fls(param
->cw_min
) << EDCA_PARAM_ECW_MIN_SHIFT
|
7872 fls(param
->cw_max
) << EDCA_PARAM_ECW_MAX_SHIFT
|
7873 (u32
)param
->txop
<< EDCA_PARAM_TXOP_SHIFT
;
7875 acm_ctrl
= rtl8xxxu_read8(priv
, REG_ACM_HW_CTRL
);
7877 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7878 __func__
, queue
, val32
, param
->acm
, acm_ctrl
);
7881 case IEEE80211_AC_VO
:
7882 acm_bit
= ACM_HW_CTRL_VO
;
7883 rtl8xxxu_write32(priv
, REG_EDCA_VO_PARAM
, val32
);
7885 case IEEE80211_AC_VI
:
7886 acm_bit
= ACM_HW_CTRL_VI
;
7887 rtl8xxxu_write32(priv
, REG_EDCA_VI_PARAM
, val32
);
7889 case IEEE80211_AC_BE
:
7890 acm_bit
= ACM_HW_CTRL_BE
;
7891 rtl8xxxu_write32(priv
, REG_EDCA_BE_PARAM
, val32
);
7893 case IEEE80211_AC_BK
:
7894 acm_bit
= ACM_HW_CTRL_BK
;
7895 rtl8xxxu_write32(priv
, REG_EDCA_BK_PARAM
, val32
);
7903 acm_ctrl
|= acm_bit
;
7905 acm_ctrl
&= ~acm_bit
;
7906 rtl8xxxu_write8(priv
, REG_ACM_HW_CTRL
, acm_ctrl
);
7911 static void rtl8xxxu_configure_filter(struct ieee80211_hw
*hw
,
7912 unsigned int changed_flags
,
7913 unsigned int *total_flags
, u64 multicast
)
7915 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7916 u32 rcr
= rtl8xxxu_read32(priv
, REG_RCR
);
7918 dev_dbg(&priv
->udev
->dev
, "%s: changed_flags %08x, total_flags %08x\n",
7919 __func__
, changed_flags
, *total_flags
);
7922 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7925 if (*total_flags
& FIF_FCSFAIL
)
7926 rcr
|= RCR_ACCEPT_CRC32
;
7928 rcr
&= ~RCR_ACCEPT_CRC32
;
7931 * FIF_PLCPFAIL not supported?
7934 if (*total_flags
& FIF_BCN_PRBRESP_PROMISC
)
7935 rcr
&= ~RCR_CHECK_BSSID_BEACON
;
7937 rcr
|= RCR_CHECK_BSSID_BEACON
;
7939 if (*total_flags
& FIF_CONTROL
)
7940 rcr
|= RCR_ACCEPT_CTRL_FRAME
;
7942 rcr
&= ~RCR_ACCEPT_CTRL_FRAME
;
7944 if (*total_flags
& FIF_OTHER_BSS
) {
7945 rcr
|= RCR_ACCEPT_AP
;
7946 rcr
&= ~RCR_CHECK_BSSID_MATCH
;
7948 rcr
&= ~RCR_ACCEPT_AP
;
7949 rcr
|= RCR_CHECK_BSSID_MATCH
;
7952 if (*total_flags
& FIF_PSPOLL
)
7953 rcr
|= RCR_ACCEPT_PM
;
7955 rcr
&= ~RCR_ACCEPT_PM
;
7958 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7961 rtl8xxxu_write32(priv
, REG_RCR
, rcr
);
7963 *total_flags
&= (FIF_ALLMULTI
| FIF_FCSFAIL
| FIF_BCN_PRBRESP_PROMISC
|
7964 FIF_CONTROL
| FIF_OTHER_BSS
| FIF_PSPOLL
|
7968 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw
*hw
, u32 rts
)
7976 static int rtl8xxxu_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
7977 struct ieee80211_vif
*vif
,
7978 struct ieee80211_sta
*sta
,
7979 struct ieee80211_key_conf
*key
)
7981 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7982 struct device
*dev
= &priv
->udev
->dev
;
7983 u8 mac_addr
[ETH_ALEN
];
7987 int retval
= -EOPNOTSUPP
;
7989 dev_dbg(dev
, "%s: cmd %02x, cipher %08x, index %i\n",
7990 __func__
, cmd
, key
->cipher
, key
->keyidx
);
7992 if (vif
->type
!= NL80211_IFTYPE_STATION
)
7995 if (key
->keyidx
> 3)
7998 switch (key
->cipher
) {
7999 case WLAN_CIPHER_SUITE_WEP40
:
8000 case WLAN_CIPHER_SUITE_WEP104
:
8003 case WLAN_CIPHER_SUITE_CCMP
:
8004 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT_TX
;
8006 case WLAN_CIPHER_SUITE_TKIP
:
8007 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
8012 if (key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) {
8013 dev_dbg(dev
, "%s: pairwise key\n", __func__
);
8014 ether_addr_copy(mac_addr
, sta
->addr
);
8016 dev_dbg(dev
, "%s: group key\n", __func__
);
8017 eth_broadcast_addr(mac_addr
);
8020 val16
= rtl8xxxu_read16(priv
, REG_CR
);
8021 val16
|= CR_SECURITY_ENABLE
;
8022 rtl8xxxu_write16(priv
, REG_CR
, val16
);
8024 val8
= SEC_CFG_TX_SEC_ENABLE
| SEC_CFG_TXBC_USE_DEFKEY
|
8025 SEC_CFG_RX_SEC_ENABLE
| SEC_CFG_RXBC_USE_DEFKEY
;
8026 val8
|= SEC_CFG_TX_USE_DEFKEY
| SEC_CFG_RX_USE_DEFKEY
;
8027 rtl8xxxu_write8(priv
, REG_SECURITY_CFG
, val8
);
8031 key
->hw_key_idx
= key
->keyidx
;
8032 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
8033 rtl8xxxu_cam_write(priv
, key
, mac_addr
);
8037 rtl8xxxu_write32(priv
, REG_CAM_WRITE
, 0x00000000);
8038 val32
= CAM_CMD_POLLING
| CAM_CMD_WRITE
|
8039 key
->keyidx
<< CAM_CMD_KEY_SHIFT
;
8040 rtl8xxxu_write32(priv
, REG_CAM_CMD
, val32
);
8044 dev_warn(dev
, "%s: Unsupported command %02x\n", __func__
, cmd
);
8051 rtl8xxxu_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
8052 struct ieee80211_ampdu_params
*params
)
8054 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8055 struct device
*dev
= &priv
->udev
->dev
;
8056 u8 ampdu_factor
, ampdu_density
;
8057 struct ieee80211_sta
*sta
= params
->sta
;
8058 enum ieee80211_ampdu_mlme_action action
= params
->action
;
8061 case IEEE80211_AMPDU_TX_START
:
8062 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_START\n", __func__
);
8063 ampdu_factor
= sta
->ht_cap
.ampdu_factor
;
8064 ampdu_density
= sta
->ht_cap
.ampdu_density
;
8065 rtl8xxxu_set_ampdu_factor(priv
, ampdu_factor
);
8066 rtl8xxxu_set_ampdu_min_space(priv
, ampdu_density
);
8068 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
8069 ampdu_factor
, ampdu_density
);
8071 case IEEE80211_AMPDU_TX_STOP_FLUSH
:
8072 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__
);
8073 rtl8xxxu_set_ampdu_factor(priv
, 0);
8074 rtl8xxxu_set_ampdu_min_space(priv
, 0);
8076 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
:
8077 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
8079 rtl8xxxu_set_ampdu_factor(priv
, 0);
8080 rtl8xxxu_set_ampdu_min_space(priv
, 0);
8082 case IEEE80211_AMPDU_RX_START
:
8083 dev_info(dev
, "%s: IEEE80211_AMPDU_RX_START\n", __func__
);
8085 case IEEE80211_AMPDU_RX_STOP
:
8086 dev_info(dev
, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__
);
8094 static int rtl8xxxu_start(struct ieee80211_hw
*hw
)
8096 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8097 struct rtl8xxxu_rx_urb
*rx_urb
;
8098 struct rtl8xxxu_tx_urb
*tx_urb
;
8099 unsigned long flags
;
8104 init_usb_anchor(&priv
->rx_anchor
);
8105 init_usb_anchor(&priv
->tx_anchor
);
8106 init_usb_anchor(&priv
->int_anchor
);
8108 priv
->fops
->enable_rf(priv
);
8109 if (priv
->usb_interrupts
) {
8110 ret
= rtl8xxxu_submit_int_urb(hw
);
8115 for (i
= 0; i
< RTL8XXXU_TX_URBS
; i
++) {
8116 tx_urb
= kmalloc(sizeof(struct rtl8xxxu_tx_urb
), GFP_KERNEL
);
8123 usb_init_urb(&tx_urb
->urb
);
8124 INIT_LIST_HEAD(&tx_urb
->list
);
8126 list_add(&tx_urb
->list
, &priv
->tx_urb_free_list
);
8127 priv
->tx_urb_free_count
++;
8130 priv
->tx_stopped
= false;
8132 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
8133 priv
->shutdown
= false;
8134 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
8136 for (i
= 0; i
< RTL8XXXU_RX_URBS
; i
++) {
8137 rx_urb
= kmalloc(sizeof(struct rtl8xxxu_rx_urb
), GFP_KERNEL
);
8144 usb_init_urb(&rx_urb
->urb
);
8145 INIT_LIST_HEAD(&rx_urb
->list
);
8148 ret
= rtl8xxxu_submit_rx_urb(priv
, rx_urb
);
8152 * Accept all data and mgmt frames
8154 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0xffff);
8155 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0xffff);
8157 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, 0x6954341e);
8162 rtl8xxxu_free_tx_resources(priv
);
8164 * Disable all data and mgmt frames
8166 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0x0000);
8167 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0x0000);
8172 static void rtl8xxxu_stop(struct ieee80211_hw
*hw
)
8174 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8175 unsigned long flags
;
8177 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
8179 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0x0000);
8180 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0x0000);
8182 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
8183 priv
->shutdown
= true;
8184 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
8186 usb_kill_anchored_urbs(&priv
->rx_anchor
);
8187 usb_kill_anchored_urbs(&priv
->tx_anchor
);
8188 if (priv
->usb_interrupts
)
8189 usb_kill_anchored_urbs(&priv
->int_anchor
);
8191 priv
->fops
->disable_rf(priv
);
8194 * Disable interrupts
8196 if (priv
->usb_interrupts
)
8197 rtl8xxxu_write32(priv
, REG_USB_HIMR
, 0);
8199 rtl8xxxu_free_rx_resources(priv
);
8200 rtl8xxxu_free_tx_resources(priv
);
8203 static const struct ieee80211_ops rtl8xxxu_ops
= {
8205 .add_interface
= rtl8xxxu_add_interface
,
8206 .remove_interface
= rtl8xxxu_remove_interface
,
8207 .config
= rtl8xxxu_config
,
8208 .conf_tx
= rtl8xxxu_conf_tx
,
8209 .bss_info_changed
= rtl8xxxu_bss_info_changed
,
8210 .configure_filter
= rtl8xxxu_configure_filter
,
8211 .set_rts_threshold
= rtl8xxxu_set_rts_threshold
,
8212 .start
= rtl8xxxu_start
,
8213 .stop
= rtl8xxxu_stop
,
8214 .sw_scan_start
= rtl8xxxu_sw_scan_start
,
8215 .sw_scan_complete
= rtl8xxxu_sw_scan_complete
,
8216 .set_key
= rtl8xxxu_set_key
,
8217 .ampdu_action
= rtl8xxxu_ampdu_action
,
8220 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv
*priv
,
8221 struct usb_interface
*interface
)
8223 struct usb_interface_descriptor
*interface_desc
;
8224 struct usb_host_interface
*host_interface
;
8225 struct usb_endpoint_descriptor
*endpoint
;
8226 struct device
*dev
= &priv
->udev
->dev
;
8227 int i
, j
= 0, endpoints
;
8231 host_interface
= &interface
->altsetting
[0];
8232 interface_desc
= &host_interface
->desc
;
8233 endpoints
= interface_desc
->bNumEndpoints
;
8235 for (i
= 0; i
< endpoints
; i
++) {
8236 endpoint
= &host_interface
->endpoint
[i
].desc
;
8238 dir
= endpoint
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
;
8239 num
= usb_endpoint_num(endpoint
);
8240 xtype
= usb_endpoint_type(endpoint
);
8241 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
8243 "%s: endpoint: dir %02x, # %02x, type %02x\n",
8244 __func__
, dir
, num
, xtype
);
8245 if (usb_endpoint_dir_in(endpoint
) &&
8246 usb_endpoint_xfer_bulk(endpoint
)) {
8247 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
8248 dev_dbg(dev
, "%s: in endpoint num %i\n",
8251 if (priv
->pipe_in
) {
8253 "%s: Too many IN pipes\n", __func__
);
8258 priv
->pipe_in
= usb_rcvbulkpipe(priv
->udev
, num
);
8261 if (usb_endpoint_dir_in(endpoint
) &&
8262 usb_endpoint_xfer_int(endpoint
)) {
8263 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
8264 dev_dbg(dev
, "%s: interrupt endpoint num %i\n",
8267 if (priv
->pipe_interrupt
) {
8268 dev_warn(dev
, "%s: Too many INTERRUPT pipes\n",
8274 priv
->pipe_interrupt
= usb_rcvintpipe(priv
->udev
, num
);
8277 if (usb_endpoint_dir_out(endpoint
) &&
8278 usb_endpoint_xfer_bulk(endpoint
)) {
8279 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
8280 dev_dbg(dev
, "%s: out endpoint num %i\n",
8282 if (j
>= RTL8XXXU_OUT_ENDPOINTS
) {
8284 "%s: Too many OUT pipes\n", __func__
);
8288 priv
->out_ep
[j
++] = num
;
8292 priv
->nr_out_eps
= j
;
8296 static int rtl8xxxu_probe(struct usb_interface
*interface
,
8297 const struct usb_device_id
*id
)
8299 struct rtl8xxxu_priv
*priv
;
8300 struct ieee80211_hw
*hw
;
8301 struct usb_device
*udev
;
8302 struct ieee80211_supported_band
*sband
;
8306 udev
= usb_get_dev(interface_to_usbdev(interface
));
8308 switch (id
->idVendor
) {
8309 case USB_VENDOR_ID_REALTEK
:
8310 switch(id
->idProduct
) {
8320 if (id
->idProduct
== 0x7811)
8328 rtl8xxxu_debug
|= RTL8XXXU_DEBUG_EFUSE
;
8329 dev_info(&udev
->dev
,
8330 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
8331 id
->idVendor
, id
->idProduct
);
8332 dev_info(&udev
->dev
,
8333 "Please report results to Jes.Sorensen@gmail.com\n");
8336 hw
= ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv
), &rtl8xxxu_ops
);
8345 priv
->fops
= (struct rtl8xxxu_fileops
*)id
->driver_info
;
8346 mutex_init(&priv
->usb_buf_mutex
);
8347 mutex_init(&priv
->h2c_mutex
);
8348 INIT_LIST_HEAD(&priv
->tx_urb_free_list
);
8349 spin_lock_init(&priv
->tx_urb_lock
);
8350 INIT_LIST_HEAD(&priv
->rx_urb_pending_list
);
8351 spin_lock_init(&priv
->rx_urb_lock
);
8352 INIT_WORK(&priv
->rx_urb_wq
, rtl8xxxu_rx_urb_work
);
8354 usb_set_intfdata(interface
, hw
);
8356 ret
= rtl8xxxu_parse_usb(priv
, interface
);
8360 ret
= rtl8xxxu_identify_chip(priv
);
8362 dev_err(&udev
->dev
, "Fatal - failed to identify chip\n");
8366 ret
= rtl8xxxu_read_efuse(priv
);
8368 dev_err(&udev
->dev
, "Fatal - failed to read EFuse\n");
8372 ret
= priv
->fops
->parse_efuse(priv
);
8374 dev_err(&udev
->dev
, "Fatal - failed to parse EFuse\n");
8378 rtl8xxxu_print_chipinfo(priv
);
8380 ret
= priv
->fops
->load_firmware(priv
);
8382 dev_err(&udev
->dev
, "Fatal - failed to load firmware\n");
8386 ret
= rtl8xxxu_init_device(hw
);
8388 hw
->wiphy
->max_scan_ssids
= 1;
8389 hw
->wiphy
->max_scan_ie_len
= IEEE80211_MAX_DATA_LEN
;
8390 hw
->wiphy
->interface_modes
= BIT(NL80211_IFTYPE_STATION
);
8393 sband
= &rtl8xxxu_supported_band
;
8394 sband
->ht_cap
.ht_supported
= true;
8395 sband
->ht_cap
.ampdu_factor
= IEEE80211_HT_MAX_AMPDU_64K
;
8396 sband
->ht_cap
.ampdu_density
= IEEE80211_HT_MPDU_DENSITY_16
;
8397 sband
->ht_cap
.cap
= IEEE80211_HT_CAP_SGI_20
| IEEE80211_HT_CAP_SGI_40
;
8398 memset(&sband
->ht_cap
.mcs
, 0, sizeof(sband
->ht_cap
.mcs
));
8399 sband
->ht_cap
.mcs
.rx_mask
[0] = 0xff;
8400 sband
->ht_cap
.mcs
.rx_mask
[4] = 0x01;
8401 if (priv
->rf_paths
> 1) {
8402 sband
->ht_cap
.mcs
.rx_mask
[1] = 0xff;
8403 sband
->ht_cap
.cap
|= IEEE80211_HT_CAP_SGI_40
;
8405 sband
->ht_cap
.mcs
.tx_params
= IEEE80211_HT_MCS_TX_DEFINED
;
8407 * Some APs will negotiate HT20_40 in a noisy environment leading
8408 * to miserable performance. Rather than defaulting to this, only
8409 * enable it if explicitly requested at module load time.
8411 if (rtl8xxxu_ht40_2g
) {
8412 dev_info(&udev
->dev
, "Enabling HT_20_40 on the 2.4GHz band\n");
8413 sband
->ht_cap
.cap
|= IEEE80211_HT_CAP_SUP_WIDTH_20_40
;
8415 hw
->wiphy
->bands
[NL80211_BAND_2GHZ
] = sband
;
8417 hw
->wiphy
->rts_threshold
= 2347;
8419 SET_IEEE80211_DEV(priv
->hw
, &interface
->dev
);
8420 SET_IEEE80211_PERM_ADDR(hw
, priv
->mac_addr
);
8422 hw
->extra_tx_headroom
= priv
->fops
->tx_desc_size
;
8423 ieee80211_hw_set(hw
, SIGNAL_DBM
);
8425 * The firmware handles rate control
8427 ieee80211_hw_set(hw
, HAS_RATE_CONTROL
);
8428 ieee80211_hw_set(hw
, AMPDU_AGGREGATION
);
8430 ret
= ieee80211_register_hw(priv
->hw
);
8432 dev_err(&udev
->dev
, "%s: Failed to register: %i\n",
8443 static void rtl8xxxu_disconnect(struct usb_interface
*interface
)
8445 struct rtl8xxxu_priv
*priv
;
8446 struct ieee80211_hw
*hw
;
8448 hw
= usb_get_intfdata(interface
);
8451 rtl8xxxu_disable_device(hw
);
8452 usb_set_intfdata(interface
, NULL
);
8454 dev_info(&priv
->udev
->dev
, "disconnecting\n");
8456 ieee80211_unregister_hw(hw
);
8458 kfree(priv
->fw_data
);
8459 mutex_destroy(&priv
->usb_buf_mutex
);
8460 mutex_destroy(&priv
->h2c_mutex
);
8462 usb_put_dev(priv
->udev
);
8463 ieee80211_free_hw(hw
);
8466 static struct rtl8xxxu_fileops rtl8723au_fops
= {
8467 .parse_efuse
= rtl8723au_parse_efuse
,
8468 .load_firmware
= rtl8723au_load_firmware
,
8469 .power_on
= rtl8723au_power_on
,
8470 .power_off
= rtl8xxxu_power_off
,
8471 .reset_8051
= rtl8xxxu_reset_8051
,
8472 .llt_init
= rtl8xxxu_init_llt_table
,
8473 .phy_iq_calibrate
= rtl8723au_phy_iq_calibrate
,
8474 .config_channel
= rtl8723au_config_channel
,
8475 .parse_rx_desc
= rtl8723au_parse_rx_desc
,
8476 .enable_rf
= rtl8723a_enable_rf
,
8477 .disable_rf
= rtl8723a_disable_rf
,
8478 .set_tx_power
= rtl8723a_set_tx_power
,
8479 .update_rate_mask
= rtl8723au_update_rate_mask
,
8480 .report_connect
= rtl8723au_report_connect
,
8481 .writeN_block_size
= 1024,
8482 .mbox_ext_reg
= REG_HMBOX_EXT_0
,
8483 .mbox_ext_width
= 2,
8484 .tx_desc_size
= sizeof(struct rtl8xxxu_txdesc32
),
8485 .adda_1t_init
= 0x0b1b25a0,
8486 .adda_1t_path_on
= 0x0bdb25a0,
8487 .adda_2t_path_on_a
= 0x04db25a4,
8488 .adda_2t_path_on_b
= 0x0b1b25a4,
8489 .mactable
= rtl8723a_mac_init_table
,
8492 static struct rtl8xxxu_fileops rtl8723bu_fops
= {
8493 .parse_efuse
= rtl8723bu_parse_efuse
,
8494 .load_firmware
= rtl8723bu_load_firmware
,
8495 .power_on
= rtl8723bu_power_on
,
8496 .power_off
= rtl8723bu_power_off
,
8497 .reset_8051
= rtl8723bu_reset_8051
,
8498 .llt_init
= rtl8xxxu_auto_llt_table
,
8499 .phy_init_antenna_selection
= rtl8723bu_phy_init_antenna_selection
,
8500 .phy_iq_calibrate
= rtl8723bu_phy_iq_calibrate
,
8501 .config_channel
= rtl8723bu_config_channel
,
8502 .parse_rx_desc
= rtl8723bu_parse_rx_desc
,
8503 .init_aggregation
= rtl8723bu_init_aggregation
,
8504 .init_statistics
= rtl8723bu_init_statistics
,
8505 .enable_rf
= rtl8723b_enable_rf
,
8506 .disable_rf
= rtl8723b_disable_rf
,
8507 .set_tx_power
= rtl8723b_set_tx_power
,
8508 .update_rate_mask
= rtl8723bu_update_rate_mask
,
8509 .report_connect
= rtl8723bu_report_connect
,
8510 .writeN_block_size
= 1024,
8511 .mbox_ext_reg
= REG_HMBOX_EXT0_8723B
,
8512 .mbox_ext_width
= 4,
8513 .tx_desc_size
= sizeof(struct rtl8xxxu_txdesc40
),
8515 .adda_1t_init
= 0x01c00014,
8516 .adda_1t_path_on
= 0x01c00014,
8517 .adda_2t_path_on_a
= 0x01c00014,
8518 .adda_2t_path_on_b
= 0x01c00014,
8519 .mactable
= rtl8723b_mac_init_table
,
8522 #ifdef CONFIG_RTL8XXXU_UNTESTED
8524 static struct rtl8xxxu_fileops rtl8192cu_fops
= {
8525 .parse_efuse
= rtl8192cu_parse_efuse
,
8526 .load_firmware
= rtl8192cu_load_firmware
,
8527 .power_on
= rtl8192cu_power_on
,
8528 .power_off
= rtl8xxxu_power_off
,
8529 .reset_8051
= rtl8xxxu_reset_8051
,
8530 .llt_init
= rtl8xxxu_init_llt_table
,
8531 .phy_iq_calibrate
= rtl8723au_phy_iq_calibrate
,
8532 .config_channel
= rtl8723au_config_channel
,
8533 .parse_rx_desc
= rtl8723au_parse_rx_desc
,
8534 .enable_rf
= rtl8723a_enable_rf
,
8535 .disable_rf
= rtl8723a_disable_rf
,
8536 .set_tx_power
= rtl8723a_set_tx_power
,
8537 .update_rate_mask
= rtl8723au_update_rate_mask
,
8538 .report_connect
= rtl8723au_report_connect
,
8539 .writeN_block_size
= 128,
8540 .mbox_ext_reg
= REG_HMBOX_EXT_0
,
8541 .mbox_ext_width
= 2,
8542 .tx_desc_size
= sizeof(struct rtl8xxxu_txdesc32
),
8543 .adda_1t_init
= 0x0b1b25a0,
8544 .adda_1t_path_on
= 0x0bdb25a0,
8545 .adda_2t_path_on_a
= 0x04db25a4,
8546 .adda_2t_path_on_b
= 0x0b1b25a4,
8547 .mactable
= rtl8723a_mac_init_table
,
8552 static struct rtl8xxxu_fileops rtl8192eu_fops
= {
8553 .parse_efuse
= rtl8192eu_parse_efuse
,
8554 .load_firmware
= rtl8192eu_load_firmware
,
8555 .power_on
= rtl8192eu_power_on
,
8556 .power_off
= rtl8xxxu_power_off
,
8557 .reset_8051
= rtl8xxxu_reset_8051
,
8558 .llt_init
= rtl8xxxu_auto_llt_table
,
8559 .phy_iq_calibrate
= rtl8723bu_phy_iq_calibrate
,
8560 .config_channel
= rtl8723bu_config_channel
,
8561 .parse_rx_desc
= rtl8723bu_parse_rx_desc
,
8562 .enable_rf
= rtl8723b_enable_rf
,
8563 .disable_rf
= rtl8723b_disable_rf
,
8564 .set_tx_power
= rtl8723b_set_tx_power
,
8565 .update_rate_mask
= rtl8723bu_update_rate_mask
,
8566 .report_connect
= rtl8723bu_report_connect
,
8567 .writeN_block_size
= 128,
8568 .mbox_ext_reg
= REG_HMBOX_EXT0_8723B
,
8569 .mbox_ext_width
= 4,
8570 .tx_desc_size
= sizeof(struct rtl8xxxu_txdesc40
),
8572 .adda_1t_init
= 0x0fc01616,
8573 .adda_1t_path_on
= 0x0fc01616,
8574 .adda_2t_path_on_a
= 0x0fc01616,
8575 .adda_2t_path_on_b
= 0x0fc01616,
8576 .mactable
= rtl8192e_mac_init_table
,
8579 static struct usb_device_id dev_table
[] = {
8580 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8724, 0xff, 0xff, 0xff),
8581 .driver_info
= (unsigned long)&rtl8723au_fops
},
8582 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x1724, 0xff, 0xff, 0xff),
8583 .driver_info
= (unsigned long)&rtl8723au_fops
},
8584 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x0724, 0xff, 0xff, 0xff),
8585 .driver_info
= (unsigned long)&rtl8723au_fops
},
8586 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x818b, 0xff, 0xff, 0xff),
8587 .driver_info
= (unsigned long)&rtl8192eu_fops
},
8588 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0xb720, 0xff, 0xff, 0xff),
8589 .driver_info
= (unsigned long)&rtl8723bu_fops
},
8590 #ifdef CONFIG_RTL8XXXU_UNTESTED
8591 /* Still supported by rtlwifi */
8592 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8176, 0xff, 0xff, 0xff),
8593 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8594 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8178, 0xff, 0xff, 0xff),
8595 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8596 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817f, 0xff, 0xff, 0xff),
8597 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8598 /* Tested by Larry Finger */
8599 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8600 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8601 /* Currently untested 8188 series devices */
8602 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8191, 0xff, 0xff, 0xff),
8603 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8604 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8170, 0xff, 0xff, 0xff),
8605 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8606 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8177, 0xff, 0xff, 0xff),
8607 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8608 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817a, 0xff, 0xff, 0xff),
8609 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8610 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817b, 0xff, 0xff, 0xff),
8611 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8612 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817d, 0xff, 0xff, 0xff),
8613 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8614 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817e, 0xff, 0xff, 0xff),
8615 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8616 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x818a, 0xff, 0xff, 0xff),
8617 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8618 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x317f, 0xff, 0xff, 0xff),
8619 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8620 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8621 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8622 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8623 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8624 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8625 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8626 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8627 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8628 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8629 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8630 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8631 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8632 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8633 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8634 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x1e1e, 0xff, 0xff, 0xff),
8635 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8636 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x5088, 0xff, 0xff, 0xff),
8637 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8638 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8639 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8640 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8641 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8642 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8643 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8644 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8645 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8646 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8647 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8648 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8649 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8650 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8651 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8652 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8653 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8654 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8655 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8656 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8657 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8658 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8659 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8660 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8661 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8662 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8663 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8664 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8665 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8666 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8667 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8668 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8669 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8670 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8671 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8672 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8673 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8674 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8675 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8676 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8677 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8678 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8679 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8680 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8681 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8682 /* Currently untested 8192 series devices */
8683 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8684 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8685 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8686 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8687 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8688 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8689 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8690 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8691 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8692 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8693 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8694 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8695 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8696 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8697 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8698 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8699 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8700 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8701 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8702 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8703 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8704 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8705 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8706 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8707 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8708 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8709 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8710 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8711 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x2e2e, 0xff, 0xff, 0xff),
8712 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8713 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8714 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8715 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8716 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8717 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8718 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8719 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8720 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8721 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8722 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8723 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8724 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8725 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8726 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8727 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8728 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8729 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8730 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8731 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8732 .driver_info
= (unsigned long)&rtl8192cu_fops
},
8737 static struct usb_driver rtl8xxxu_driver
= {
8738 .name
= DRIVER_NAME
,
8739 .probe
= rtl8xxxu_probe
,
8740 .disconnect
= rtl8xxxu_disconnect
,
8741 .id_table
= dev_table
,
8742 .disable_hub_initiated_lpm
= 1,
8745 static int __init
rtl8xxxu_module_init(void)
8749 res
= usb_register(&rtl8xxxu_driver
);
8751 pr_err(DRIVER_NAME
": usb_register() failed (%i)\n", res
);
8756 static void __exit
rtl8xxxu_module_exit(void)
8758 usb_deregister(&rtl8xxxu_driver
);
8762 MODULE_DEVICE_TABLE(usb
, dev_table
);
8764 module_init(rtl8xxxu_module_init
);
8765 module_exit(rtl8xxxu_module_exit
);