2 * RTL8XXXU mac80211 USB driver
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
41 #include "rtl8xxxu_regs.h"
43 #define DRIVER_NAME "rtl8xxxu"
45 static int rtl8xxxu_debug
= RTL8XXXU_DEBUG_EFUSE
;
46 static bool rtl8xxxu_ht40_2g
;
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
61 module_param_named(debug
, rtl8xxxu_debug
, int, 0600);
62 MODULE_PARM_DESC(debug
, "Set debug mask");
63 module_param_named(ht40_2g
, rtl8xxxu_ht40_2g
, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g
, "Enable HT40 support on the 2.4GHz band");
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv
*priv
,
76 struct rtl8xxxu_rx_urb
*rx_urb
);
78 static struct ieee80211_rate rtl8xxxu_rates
[] = {
79 { .bitrate
= 10, .hw_value
= DESC_RATE_1M
, .flags
= 0 },
80 { .bitrate
= 20, .hw_value
= DESC_RATE_2M
, .flags
= 0 },
81 { .bitrate
= 55, .hw_value
= DESC_RATE_5_5M
, .flags
= 0 },
82 { .bitrate
= 110, .hw_value
= DESC_RATE_11M
, .flags
= 0 },
83 { .bitrate
= 60, .hw_value
= DESC_RATE_6M
, .flags
= 0 },
84 { .bitrate
= 90, .hw_value
= DESC_RATE_9M
, .flags
= 0 },
85 { .bitrate
= 120, .hw_value
= DESC_RATE_12M
, .flags
= 0 },
86 { .bitrate
= 180, .hw_value
= DESC_RATE_18M
, .flags
= 0 },
87 { .bitrate
= 240, .hw_value
= DESC_RATE_24M
, .flags
= 0 },
88 { .bitrate
= 360, .hw_value
= DESC_RATE_36M
, .flags
= 0 },
89 { .bitrate
= 480, .hw_value
= DESC_RATE_48M
, .flags
= 0 },
90 { .bitrate
= 540, .hw_value
= DESC_RATE_54M
, .flags
= 0 },
93 static struct ieee80211_channel rtl8xxxu_channels_2g
[] = {
94 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2412,
95 .hw_value
= 1, .max_power
= 30 },
96 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2417,
97 .hw_value
= 2, .max_power
= 30 },
98 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2422,
99 .hw_value
= 3, .max_power
= 30 },
100 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2427,
101 .hw_value
= 4, .max_power
= 30 },
102 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2432,
103 .hw_value
= 5, .max_power
= 30 },
104 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2437,
105 .hw_value
= 6, .max_power
= 30 },
106 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2442,
107 .hw_value
= 7, .max_power
= 30 },
108 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2447,
109 .hw_value
= 8, .max_power
= 30 },
110 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2452,
111 .hw_value
= 9, .max_power
= 30 },
112 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2457,
113 .hw_value
= 10, .max_power
= 30 },
114 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2462,
115 .hw_value
= 11, .max_power
= 30 },
116 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2467,
117 .hw_value
= 12, .max_power
= 30 },
118 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2472,
119 .hw_value
= 13, .max_power
= 30 },
120 { .band
= NL80211_BAND_2GHZ
, .center_freq
= 2484,
121 .hw_value
= 14, .max_power
= 30 }
124 static struct ieee80211_supported_band rtl8xxxu_supported_band
= {
125 .channels
= rtl8xxxu_channels_2g
,
126 .n_channels
= ARRAY_SIZE(rtl8xxxu_channels_2g
),
127 .bitrates
= rtl8xxxu_rates
,
128 .n_bitrates
= ARRAY_SIZE(rtl8xxxu_rates
),
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table
[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table
[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
187 static struct rtl8xxxu_reg8val rtl8192e_mac_init_table
[] = {
188 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
189 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
190 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
191 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
192 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
193 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
194 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
195 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
196 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
197 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
198 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
199 {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
200 {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
201 {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
202 {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
203 {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
204 {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
205 {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
206 {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
207 {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
208 {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
209 {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
210 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
211 {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
212 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
217 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table
[] = {
218 {0x800, 0x80040000}, {0x804, 0x00000003},
219 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
220 {0x810, 0x10001331}, {0x814, 0x020c3d10},
221 {0x818, 0x02200385}, {0x81c, 0x00000000},
222 {0x820, 0x01000100}, {0x824, 0x00390004},
223 {0x828, 0x00000000}, {0x82c, 0x00000000},
224 {0x830, 0x00000000}, {0x834, 0x00000000},
225 {0x838, 0x00000000}, {0x83c, 0x00000000},
226 {0x840, 0x00010000}, {0x844, 0x00000000},
227 {0x848, 0x00000000}, {0x84c, 0x00000000},
228 {0x850, 0x00000000}, {0x854, 0x00000000},
229 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
230 {0x860, 0x66f60110}, {0x864, 0x061f0130},
231 {0x868, 0x00000000}, {0x86c, 0x32323200},
232 {0x870, 0x07000760}, {0x874, 0x22004000},
233 {0x878, 0x00000808}, {0x87c, 0x00000000},
234 {0x880, 0xc0083070}, {0x884, 0x000004d5},
235 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
236 {0x890, 0x00000800}, {0x894, 0xfffffffe},
237 {0x898, 0x40302010}, {0x89c, 0x00706050},
238 {0x900, 0x00000000}, {0x904, 0x00000023},
239 {0x908, 0x00000000}, {0x90c, 0x81121111},
240 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
241 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
242 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
243 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
244 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
245 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
246 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
248 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
249 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
250 {0xc10, 0x08800000}, {0xc14, 0x40000100},
251 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
252 {0xc20, 0x00000000}, {0xc24, 0x00000000},
253 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
254 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
255 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
256 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
257 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
258 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
259 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
260 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
261 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
262 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
263 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
264 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
265 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
266 {0xc90, 0x00121820}, {0xc94, 0x00000000},
267 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
268 {0xca0, 0x00000000}, {0xca4, 0x00000080},
269 {0xca8, 0x00000000}, {0xcac, 0x00000000},
270 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
271 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
272 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
273 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
274 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
275 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
276 {0xce0, 0x00222222}, {0xce4, 0x00000000},
277 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
278 {0xd00, 0x00080740}, {0xd04, 0x00020401},
279 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
280 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
281 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
282 {0xd30, 0x00000000}, {0xd34, 0x80608000},
283 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
284 {0xd40, 0x00000000}, {0xd44, 0x00000000},
285 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
286 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
287 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
288 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
289 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
290 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
291 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
292 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
293 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
294 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
295 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
296 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
297 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
298 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
299 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
300 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
301 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
302 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
303 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
304 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
305 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
306 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
307 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
308 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
309 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
310 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
312 {0xffff, 0xffffffff},
315 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table
[] = {
316 {0x800, 0x80040000}, {0x804, 0x00000003},
317 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
318 {0x810, 0x10001331}, {0x814, 0x020c3d10},
319 {0x818, 0x02200385}, {0x81c, 0x00000000},
320 {0x820, 0x01000100}, {0x824, 0x00190204},
321 {0x828, 0x00000000}, {0x82c, 0x00000000},
322 {0x830, 0x00000000}, {0x834, 0x00000000},
323 {0x838, 0x00000000}, {0x83c, 0x00000000},
324 {0x840, 0x00010000}, {0x844, 0x00000000},
325 {0x848, 0x00000000}, {0x84c, 0x00000000},
326 {0x850, 0x00000000}, {0x854, 0x00000000},
327 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
328 {0x860, 0x66f60110}, {0x864, 0x061f0649},
329 {0x868, 0x00000000}, {0x86c, 0x27272700},
330 {0x870, 0x07000760}, {0x874, 0x25004000},
331 {0x878, 0x00000808}, {0x87c, 0x00000000},
332 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
333 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
334 {0x890, 0x00000800}, {0x894, 0xfffffffe},
335 {0x898, 0x40302010}, {0x89c, 0x00706050},
336 {0x900, 0x00000000}, {0x904, 0x00000023},
337 {0x908, 0x00000000}, {0x90c, 0x81121111},
338 {0x910, 0x00000002}, {0x914, 0x00000201},
339 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
340 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
341 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
342 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
343 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
344 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
345 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
346 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
347 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
348 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
349 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
350 {0xc10, 0x08800000}, {0xc14, 0x40000100},
351 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
352 {0xc20, 0x00000000}, {0xc24, 0x00000000},
353 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
354 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
355 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
356 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
357 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
358 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
359 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
360 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
361 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
362 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
363 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
364 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
365 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
366 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
367 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
368 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
369 {0xca8, 0x00000000}, {0xcac, 0x00000000},
370 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
371 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
372 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
373 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
374 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
375 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
376 {0xce0, 0x00222222}, {0xce4, 0x00000000},
377 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
378 {0xd00, 0x00000740}, {0xd04, 0x40020401},
379 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
380 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
381 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
382 {0xd30, 0x00000000}, {0xd34, 0x80608000},
383 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
384 {0xd40, 0x00000000}, {0xd44, 0x00000000},
385 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
386 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
387 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
388 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
389 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
390 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
391 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
392 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
393 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
394 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
395 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
396 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
397 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
398 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
399 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
400 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
401 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
402 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
403 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
404 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
405 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
406 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
407 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
408 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
409 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
410 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
412 {0x820, 0x01000100}, {0x800, 0x83040000},
413 {0xffff, 0xffffffff},
416 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table
[] = {
417 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
418 {0x800, 0x80040002}, {0x804, 0x00000003},
419 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
420 {0x810, 0x10000330}, {0x814, 0x020c3d10},
421 {0x818, 0x02200385}, {0x81c, 0x00000000},
422 {0x820, 0x01000100}, {0x824, 0x00390004},
423 {0x828, 0x01000100}, {0x82c, 0x00390004},
424 {0x830, 0x27272727}, {0x834, 0x27272727},
425 {0x838, 0x27272727}, {0x83c, 0x27272727},
426 {0x840, 0x00010000}, {0x844, 0x00010000},
427 {0x848, 0x27272727}, {0x84c, 0x27272727},
428 {0x850, 0x00000000}, {0x854, 0x00000000},
429 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
430 {0x860, 0x66e60230}, {0x864, 0x061f0130},
431 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
432 {0x870, 0x07000700}, {0x874, 0x22184000},
433 {0x878, 0x08080808}, {0x87c, 0x00000000},
434 {0x880, 0xc0083070}, {0x884, 0x000004d5},
435 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
436 {0x890, 0x00000800}, {0x894, 0xfffffffe},
437 {0x898, 0x40302010}, {0x89c, 0x00706050},
438 {0x900, 0x00000000}, {0x904, 0x00000023},
439 {0x908, 0x00000000}, {0x90c, 0x81121313},
440 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
441 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
442 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
443 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
444 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
445 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
446 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
447 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
448 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
449 {0xc10, 0x08800000}, {0xc14, 0x40000100},
450 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
451 {0xc20, 0x00000000}, {0xc24, 0x00000000},
452 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
453 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
454 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
455 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
456 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
457 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
458 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
459 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
460 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
461 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
462 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
463 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
464 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
465 {0xc90, 0x00121820}, {0xc94, 0x00000000},
466 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
467 {0xca0, 0x00000000}, {0xca4, 0x00000080},
468 {0xca8, 0x00000000}, {0xcac, 0x00000000},
469 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
470 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
471 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
472 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
473 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
474 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
475 {0xce0, 0x00222222}, {0xce4, 0x00000000},
476 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
477 {0xd00, 0x00080740}, {0xd04, 0x00020403},
478 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
479 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
480 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
481 {0xd30, 0x00000000}, {0xd34, 0x80608000},
482 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
483 {0xd40, 0x00000000}, {0xd44, 0x00000000},
484 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
485 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
486 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
487 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
488 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
489 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
490 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
491 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
492 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
493 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
494 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
495 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
496 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
497 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
498 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
499 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
500 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
501 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
502 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
503 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
504 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
505 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
506 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
507 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
508 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
509 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
511 {0xffff, 0xffffffff},
514 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table
[] = {
515 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
516 {0x040, 0x000c0004}, {0x800, 0x80040000},
517 {0x804, 0x00000001}, {0x808, 0x0000fc00},
518 {0x80c, 0x0000000a}, {0x810, 0x10005388},
519 {0x814, 0x020c3d10}, {0x818, 0x02200385},
520 {0x81c, 0x00000000}, {0x820, 0x01000100},
521 {0x824, 0x00390204}, {0x828, 0x00000000},
522 {0x82c, 0x00000000}, {0x830, 0x00000000},
523 {0x834, 0x00000000}, {0x838, 0x00000000},
524 {0x83c, 0x00000000}, {0x840, 0x00010000},
525 {0x844, 0x00000000}, {0x848, 0x00000000},
526 {0x84c, 0x00000000}, {0x850, 0x00000000},
527 {0x854, 0x00000000}, {0x858, 0x569a569a},
528 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
529 {0x864, 0x061f0130}, {0x868, 0x00000000},
530 {0x86c, 0x20202000}, {0x870, 0x03000300},
531 {0x874, 0x22004000}, {0x878, 0x00000808},
532 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
533 {0x884, 0x000004d5}, {0x888, 0x00000000},
534 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
535 {0x894, 0xfffffffe}, {0x898, 0x40302010},
536 {0x89c, 0x00706050}, {0x900, 0x00000000},
537 {0x904, 0x00000023}, {0x908, 0x00000000},
538 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
539 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
540 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
541 {0xa14, 0x11144028}, {0xa18, 0x00881117},
542 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
543 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
544 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
545 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
546 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
547 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
548 {0xc14, 0x40000100}, {0xc18, 0x08800000},
549 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
550 {0xc24, 0x00000000}, {0xc28, 0x00000000},
551 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
552 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
553 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
554 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
555 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
556 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
557 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
558 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
559 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
560 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
561 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
562 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
563 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
564 {0xc94, 0x00000000}, {0xc98, 0x00121820},
565 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
566 {0xca4, 0x00000080}, {0xca8, 0x00000000},
567 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
568 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
569 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
570 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
571 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
572 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
573 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
574 {0xce4, 0x00000000}, {0xce8, 0x37644302},
575 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
576 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
577 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
578 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
579 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
580 {0xd34, 0x80608000}, {0xd38, 0x00000000},
581 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
582 {0xd44, 0x00000000}, {0xd48, 0x00000000},
583 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
584 {0xd54, 0x00000000}, {0xd58, 0x00000000},
585 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
586 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
587 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
588 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
589 {0xe00, 0x24242424}, {0xe04, 0x24242424},
590 {0xe08, 0x03902024}, {0xe10, 0x24242424},
591 {0xe14, 0x24242424}, {0xe18, 0x24242424},
592 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
593 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
594 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
595 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
596 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
597 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
598 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
599 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
600 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
601 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
602 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
603 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
604 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
605 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
606 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
607 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
608 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
610 {0xffff, 0xffffffff},
613 static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table
[] = {
614 {0x800, 0x80040000}, {0x804, 0x00000003},
615 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
616 {0x810, 0x10001331}, {0x814, 0x020c3d10},
617 {0x818, 0x02220385}, {0x81c, 0x00000000},
618 {0x820, 0x01000100}, {0x824, 0x00390204},
619 {0x828, 0x01000100}, {0x82c, 0x00390204},
620 {0x830, 0x32323232}, {0x834, 0x30303030},
621 {0x838, 0x30303030}, {0x83c, 0x30303030},
622 {0x840, 0x00010000}, {0x844, 0x00010000},
623 {0x848, 0x28282828}, {0x84c, 0x28282828},
624 {0x850, 0x00000000}, {0x854, 0x00000000},
625 {0x858, 0x009a009a}, {0x85c, 0x01000014},
626 {0x860, 0x66f60000}, {0x864, 0x061f0000},
627 {0x868, 0x30303030}, {0x86c, 0x30303030},
628 {0x870, 0x00000000}, {0x874, 0x55004200},
629 {0x878, 0x08080808}, {0x87c, 0x00000000},
630 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
631 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
632 {0x890, 0x00000800}, {0x894, 0xfffffffe},
633 {0x898, 0x40302010}, {0x900, 0x00000000},
634 {0x904, 0x00000023}, {0x908, 0x00000000},
635 {0x90c, 0x81121313}, {0x910, 0x806c0001},
636 {0x914, 0x00000001}, {0x918, 0x00000000},
637 {0x91c, 0x00010000}, {0x924, 0x00000001},
638 {0x928, 0x00000000}, {0x92c, 0x00000000},
639 {0x930, 0x00000000}, {0x934, 0x00000000},
640 {0x938, 0x00000000}, {0x93c, 0x00000000},
641 {0x940, 0x00000000}, {0x944, 0x00000000},
642 {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},
643 {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},
644 {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},
645 {0xa14, 0x1114d028}, {0xa18, 0x00881117},
646 {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},
647 {0xa24, 0x090e1317}, {0xa28, 0x00000204},
648 {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},
649 {0xa74, 0x00000007}, {0xa78, 0x00000900},
650 {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},
651 {0xb38, 0x00000000}, {0xc00, 0x48071d40},
652 {0xc04, 0x03a05633}, {0xc08, 0x000000e4},
653 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
654 {0xc14, 0x40000100}, {0xc18, 0x08800000},
655 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
656 {0xc24, 0x00000000}, {0xc28, 0x00000000},
657 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},
658 {0xc34, 0x469652af}, {0xc38, 0x49795994},
659 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
660 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
663 /* External PA or external LNA */
670 /* External PA or external LNA */
675 {0xc5c, 0x00248492}, {0xc60, 0x00000000},
676 {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},
677 {0xc6c, 0x00000036}, {0xc70, 0x00000600},
678 {0xc74, 0x02013169}, {0xc78, 0x0000001f},
681 /* External PA or external LNA */
688 /* External PA or external LNA */
693 {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},
694 {0xc94, 0x00000000}, {0xc98, 0x00121820},
695 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
696 {0xca4, 0x000300a0}, {0xca8, 0x00000000},
697 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
698 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
699 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
700 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
701 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
702 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
703 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
704 {0xce4, 0x00040000}, {0xce8, 0x77644302},
705 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
706 {0xd04, 0x00020403}, {0xd08, 0x0000907f},
707 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
708 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
709 {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},
710 {0xd30, 0x00000000}, {0xd34, 0x80608000},
711 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
712 {0xd40, 0x00000000}, {0xd44, 0x00000000},
713 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
714 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
715 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
716 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
717 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
718 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
719 {0xd78, 0x000e3c24}, {0xd80, 0x01081008},
720 {0xd84, 0x00000800}, {0xd88, 0xf0b50000},
721 {0xe00, 0x30303030}, {0xe04, 0x30303030},
722 {0xe08, 0x03903030}, {0xe10, 0x30303030},
723 {0xe14, 0x30303030}, {0xe18, 0x30303030},
724 {0xe1c, 0x30303030}, {0xe28, 0x00000000},
725 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
726 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
727 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
728 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
729 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
730 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
731 {0xe60, 0x00000008}, {0xe68, 0x0fc05656},
732 {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},
733 {0xe74, 0x0c005656}, {0xe78, 0x0c005656},
734 {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},
735 {0xe84, 0x03c09696}, {0xe88, 0x0c005656},
736 {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},
737 {0xed4, 0x03c09696}, {0xed8, 0x03c09696},
738 {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},
739 {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},
740 {0xee8, 0x00000001}, {0xf14, 0x00000003},
741 {0xf4c, 0x00000000}, {0xf00, 0x00000300},
742 {0xffff, 0xffffffff},
745 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table
[] = {
746 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
747 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
748 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
749 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
750 {0xc78, 0x78080001}, {0xc78, 0x77090001},
751 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
752 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
753 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
754 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
755 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
756 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
757 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
758 {0xc78, 0x68180001}, {0xc78, 0x67190001},
759 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
760 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
761 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
762 {0xc78, 0x60200001}, {0xc78, 0x49210001},
763 {0xc78, 0x48220001}, {0xc78, 0x47230001},
764 {0xc78, 0x46240001}, {0xc78, 0x45250001},
765 {0xc78, 0x44260001}, {0xc78, 0x43270001},
766 {0xc78, 0x42280001}, {0xc78, 0x41290001},
767 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
768 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
769 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
770 {0xc78, 0x21300001}, {0xc78, 0x20310001},
771 {0xc78, 0x06320001}, {0xc78, 0x05330001},
772 {0xc78, 0x04340001}, {0xc78, 0x03350001},
773 {0xc78, 0x02360001}, {0xc78, 0x01370001},
774 {0xc78, 0x00380001}, {0xc78, 0x00390001},
775 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
776 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
777 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
778 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
779 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
780 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
781 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
782 {0xc78, 0x78480001}, {0xc78, 0x77490001},
783 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
784 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
785 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
786 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
787 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
788 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
789 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
790 {0xc78, 0x68580001}, {0xc78, 0x67590001},
791 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
792 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
793 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
794 {0xc78, 0x60600001}, {0xc78, 0x49610001},
795 {0xc78, 0x48620001}, {0xc78, 0x47630001},
796 {0xc78, 0x46640001}, {0xc78, 0x45650001},
797 {0xc78, 0x44660001}, {0xc78, 0x43670001},
798 {0xc78, 0x42680001}, {0xc78, 0x41690001},
799 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
800 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
801 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
802 {0xc78, 0x21700001}, {0xc78, 0x20710001},
803 {0xc78, 0x06720001}, {0xc78, 0x05730001},
804 {0xc78, 0x04740001}, {0xc78, 0x03750001},
805 {0xc78, 0x02760001}, {0xc78, 0x01770001},
806 {0xc78, 0x00780001}, {0xc78, 0x00790001},
807 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
808 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
809 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
810 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
811 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
812 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
813 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
814 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
815 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
816 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
817 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
818 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
819 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
820 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
821 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
822 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
823 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
824 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
825 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
829 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table
[] = {
830 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
831 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
832 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
833 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
834 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
835 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
836 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
837 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
838 {0xc78, 0x73100001}, {0xc78, 0x72110001},
839 {0xc78, 0x71120001}, {0xc78, 0x70130001},
840 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
841 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
842 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
843 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
844 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
845 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
846 {0xc78, 0x63200001}, {0xc78, 0x62210001},
847 {0xc78, 0x61220001}, {0xc78, 0x60230001},
848 {0xc78, 0x46240001}, {0xc78, 0x45250001},
849 {0xc78, 0x44260001}, {0xc78, 0x43270001},
850 {0xc78, 0x42280001}, {0xc78, 0x41290001},
851 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
852 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
853 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
854 {0xc78, 0x21300001}, {0xc78, 0x20310001},
855 {0xc78, 0x06320001}, {0xc78, 0x05330001},
856 {0xc78, 0x04340001}, {0xc78, 0x03350001},
857 {0xc78, 0x02360001}, {0xc78, 0x01370001},
858 {0xc78, 0x00380001}, {0xc78, 0x00390001},
859 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
860 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
861 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
862 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
863 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
864 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
865 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
866 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
867 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
868 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
869 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
870 {0xc78, 0x73500001}, {0xc78, 0x72510001},
871 {0xc78, 0x71520001}, {0xc78, 0x70530001},
872 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
873 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
874 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
875 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
876 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
877 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
878 {0xc78, 0x63600001}, {0xc78, 0x62610001},
879 {0xc78, 0x61620001}, {0xc78, 0x60630001},
880 {0xc78, 0x46640001}, {0xc78, 0x45650001},
881 {0xc78, 0x44660001}, {0xc78, 0x43670001},
882 {0xc78, 0x42680001}, {0xc78, 0x41690001},
883 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
884 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
885 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
886 {0xc78, 0x21700001}, {0xc78, 0x20710001},
887 {0xc78, 0x06720001}, {0xc78, 0x05730001},
888 {0xc78, 0x04740001}, {0xc78, 0x03750001},
889 {0xc78, 0x02760001}, {0xc78, 0x01770001},
890 {0xc78, 0x00780001}, {0xc78, 0x00790001},
891 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
892 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
893 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
894 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
895 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
896 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
897 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
898 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
899 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
900 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
901 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
902 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
903 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
904 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
905 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
906 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
907 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
908 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
909 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
913 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table
[] = {
914 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
915 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
916 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
917 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
918 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
919 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
920 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
921 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
922 {0xc78, 0xed100001}, {0xc78, 0xec110001},
923 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
924 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
925 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
926 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
927 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
928 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
929 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
930 {0xc78, 0x65200001}, {0xc78, 0x64210001},
931 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
932 {0xc78, 0x49240001}, {0xc78, 0x48250001},
933 {0xc78, 0x47260001}, {0xc78, 0x46270001},
934 {0xc78, 0x45280001}, {0xc78, 0x44290001},
935 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
936 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
937 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
938 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
939 {0xc78, 0x08320001}, {0xc78, 0x07330001},
940 {0xc78, 0x06340001}, {0xc78, 0x05350001},
941 {0xc78, 0x04360001}, {0xc78, 0x03370001},
942 {0xc78, 0x02380001}, {0xc78, 0x01390001},
943 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
944 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
945 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
946 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
947 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
948 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
949 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
950 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
951 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
952 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
953 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
954 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
955 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
956 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
957 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
958 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
959 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
960 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
961 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
962 {0xc78, 0x65600001}, {0xc78, 0x64610001},
963 {0xc78, 0x63620001}, {0xc78, 0x62630001},
964 {0xc78, 0x61640001}, {0xc78, 0x48650001},
965 {0xc78, 0x47660001}, {0xc78, 0x46670001},
966 {0xc78, 0x45680001}, {0xc78, 0x44690001},
967 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
968 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
969 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
970 {0xc78, 0x24700001}, {0xc78, 0x09710001},
971 {0xc78, 0x08720001}, {0xc78, 0x07730001},
972 {0xc78, 0x06740001}, {0xc78, 0x05750001},
973 {0xc78, 0x04760001}, {0xc78, 0x03770001},
974 {0xc78, 0x02780001}, {0xc78, 0x01790001},
975 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
976 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
977 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
984 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table
[] = {
985 {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
986 {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
987 {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
988 {0xc78, 0xfa060001}, {0xc78, 0xf9070001},
989 {0xc78, 0xf8080001}, {0xc78, 0xf7090001},
990 {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},
991 {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},
992 {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},
993 {0xc78, 0xf0100001}, {0xc78, 0xef110001},
994 {0xc78, 0xee120001}, {0xc78, 0xed130001},
995 {0xc78, 0xec140001}, {0xc78, 0xeb150001},
996 {0xc78, 0xea160001}, {0xc78, 0xe9170001},
997 {0xc78, 0xe8180001}, {0xc78, 0xe7190001},
998 {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},
999 {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},
1000 {0xc78, 0x061e0001}, {0xc78, 0x051f0001},
1001 {0xc78, 0x04200001}, {0xc78, 0x03210001},
1002 {0xc78, 0xaa220001}, {0xc78, 0xa9230001},
1003 {0xc78, 0xa8240001}, {0xc78, 0xa7250001},
1004 {0xc78, 0xa6260001}, {0xc78, 0x85270001},
1005 {0xc78, 0x84280001}, {0xc78, 0x83290001},
1006 {0xc78, 0x252a0001}, {0xc78, 0x242b0001},
1007 {0xc78, 0x232c0001}, {0xc78, 0x222d0001},
1008 {0xc78, 0x672e0001}, {0xc78, 0x662f0001},
1009 {0xc78, 0x65300001}, {0xc78, 0x64310001},
1010 {0xc78, 0x63320001}, {0xc78, 0x62330001},
1011 {0xc78, 0x61340001}, {0xc78, 0x45350001},
1012 {0xc78, 0x44360001}, {0xc78, 0x43370001},
1013 {0xc78, 0x42380001}, {0xc78, 0x41390001},
1014 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
1015 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
1016 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
1017 {0xc78, 0xfb400001}, {0xc78, 0xfb410001},
1018 {0xc78, 0xfb420001}, {0xc78, 0xfb430001},
1019 {0xc78, 0xfb440001}, {0xc78, 0xfb450001},
1020 {0xc78, 0xfa460001}, {0xc78, 0xf9470001},
1021 {0xc78, 0xf8480001}, {0xc78, 0xf7490001},
1022 {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},
1023 {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},
1024 {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},
1025 {0xc78, 0xf0500001}, {0xc78, 0xef510001},
1026 {0xc78, 0xee520001}, {0xc78, 0xed530001},
1027 {0xc78, 0xec540001}, {0xc78, 0xeb550001},
1028 {0xc78, 0xea560001}, {0xc78, 0xe9570001},
1029 {0xc78, 0xe8580001}, {0xc78, 0xe7590001},
1030 {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},
1031 {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},
1032 {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},
1033 {0xc78, 0x8a600001}, {0xc78, 0x89610001},
1034 {0xc78, 0x88620001}, {0xc78, 0x87630001},
1035 {0xc78, 0x86640001}, {0xc78, 0x85650001},
1036 {0xc78, 0x84660001}, {0xc78, 0x83670001},
1037 {0xc78, 0x82680001}, {0xc78, 0x6b690001},
1038 {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},
1039 {0xc78, 0x686c0001}, {0xc78, 0x676d0001},
1040 {0xc78, 0x666e0001}, {0xc78, 0x656f0001},
1041 {0xc78, 0x64700001}, {0xc78, 0x63710001},
1042 {0xc78, 0x62720001}, {0xc78, 0x61730001},
1043 {0xc78, 0x49740001}, {0xc78, 0x48750001},
1044 {0xc78, 0x47760001}, {0xc78, 0x46770001},
1045 {0xc78, 0x45780001}, {0xc78, 0x44790001},
1046 {0xc78, 0x437a0001}, {0xc78, 0x427b0001},
1047 {0xc78, 0x417c0001}, {0xc78, 0x407d0001},
1048 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
1049 {0xc50, 0x00040022}, {0xc50, 0x00040020},
1050 {0xffff, 0xffffffff}
1053 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table
[] = {
1054 {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
1055 {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
1056 {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
1057 {0xc78, 0xf4060001}, {0xc78, 0xf3070001},
1058 {0xc78, 0xf2080001}, {0xc78, 0xf1090001},
1059 {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},
1060 {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},
1061 {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},
1062 {0xc78, 0xea100001}, {0xc78, 0xe9110001},
1063 {0xc78, 0xe8120001}, {0xc78, 0xe7130001},
1064 {0xc78, 0xe6140001}, {0xc78, 0xe5150001},
1065 {0xc78, 0xe4160001}, {0xc78, 0xe3170001},
1066 {0xc78, 0xe2180001}, {0xc78, 0xe1190001},
1067 {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},
1068 {0xc78, 0x881c0001}, {0xc78, 0x871d0001},
1069 {0xc78, 0x861e0001}, {0xc78, 0x851f0001},
1070 {0xc78, 0x84200001}, {0xc78, 0x83210001},
1071 {0xc78, 0x82220001}, {0xc78, 0x6a230001},
1072 {0xc78, 0x69240001}, {0xc78, 0x68250001},
1073 {0xc78, 0x67260001}, {0xc78, 0x66270001},
1074 {0xc78, 0x65280001}, {0xc78, 0x64290001},
1075 {0xc78, 0x632a0001}, {0xc78, 0x622b0001},
1076 {0xc78, 0x612c0001}, {0xc78, 0x602d0001},
1077 {0xc78, 0x472e0001}, {0xc78, 0x462f0001},
1078 {0xc78, 0x45300001}, {0xc78, 0x44310001},
1079 {0xc78, 0x43320001}, {0xc78, 0x42330001},
1080 {0xc78, 0x41340001}, {0xc78, 0x40350001},
1081 {0xc78, 0x40360001}, {0xc78, 0x40370001},
1082 {0xc78, 0x40380001}, {0xc78, 0x40390001},
1083 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
1084 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
1085 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
1086 {0xc78, 0xfa400001}, {0xc78, 0xf9410001},
1087 {0xc78, 0xf8420001}, {0xc78, 0xf7430001},
1088 {0xc78, 0xf6440001}, {0xc78, 0xf5450001},
1089 {0xc78, 0xf4460001}, {0xc78, 0xf3470001},
1090 {0xc78, 0xf2480001}, {0xc78, 0xf1490001},
1091 {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},
1092 {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},
1093 {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},
1094 {0xc78, 0xea500001}, {0xc78, 0xe9510001},
1095 {0xc78, 0xe8520001}, {0xc78, 0xe7530001},
1096 {0xc78, 0xe6540001}, {0xc78, 0xe5550001},
1097 {0xc78, 0xe4560001}, {0xc78, 0xe3570001},
1098 {0xc78, 0xe2580001}, {0xc78, 0xe1590001},
1099 {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},
1100 {0xc78, 0x885c0001}, {0xc78, 0x875d0001},
1101 {0xc78, 0x865e0001}, {0xc78, 0x855f0001},
1102 {0xc78, 0x84600001}, {0xc78, 0x83610001},
1103 {0xc78, 0x82620001}, {0xc78, 0x6a630001},
1104 {0xc78, 0x69640001}, {0xc78, 0x68650001},
1105 {0xc78, 0x67660001}, {0xc78, 0x66670001},
1106 {0xc78, 0x65680001}, {0xc78, 0x64690001},
1107 {0xc78, 0x636a0001}, {0xc78, 0x626b0001},
1108 {0xc78, 0x616c0001}, {0xc78, 0x606d0001},
1109 {0xc78, 0x476e0001}, {0xc78, 0x466f0001},
1110 {0xc78, 0x45700001}, {0xc78, 0x44710001},
1111 {0xc78, 0x43720001}, {0xc78, 0x42730001},
1112 {0xc78, 0x41740001}, {0xc78, 0x40750001},
1113 {0xc78, 0x40760001}, {0xc78, 0x40770001},
1114 {0xc78, 0x40780001}, {0xc78, 0x40790001},
1115 {0xc78, 0x407a0001}, {0xc78, 0x407b0001},
1116 {0xc78, 0x407c0001}, {0xc78, 0x407d0001},
1117 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
1118 {0xc50, 0x00040222}, {0xc50, 0x00040220},
1119 {0xffff, 0xffffffff}
1122 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table
[] = {
1123 {0x00, 0x00030159}, {0x01, 0x00031284},
1124 {0x02, 0x00098000}, {0x03, 0x00039c63},
1125 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1126 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
1127 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
1128 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1129 {0x19, 0x00000000}, {0x1a, 0x00030355},
1130 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1131 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
1132 {0x1f, 0x00000000}, {0x20, 0x0000b614},
1133 {0x21, 0x0006c000}, {0x22, 0x00000000},
1134 {0x23, 0x00001558}, {0x24, 0x00000060},
1135 {0x25, 0x00000483}, {0x26, 0x0004f000},
1136 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
1137 {0x29, 0x00004783}, {0x2a, 0x00000001},
1138 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1139 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1140 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1141 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1142 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1143 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1144 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1145 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1146 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1147 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1148 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1149 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1150 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1151 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1152 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1153 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1154 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1155 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1156 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1157 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1158 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1159 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1160 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1162 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1164 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1166 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1167 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1168 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1169 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1170 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1171 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1172 {0x10, 0x00000000}, {0x11, 0x00000000},
1173 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1174 {0x10, 0x0009000f}, {0x11, 0x00023100},
1175 {0x12, 0x00032000}, {0x12, 0x00071000},
1176 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1177 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1178 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1179 {0x13, 0x00018493}, {0x13, 0x0001429b},
1180 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1181 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1182 {0x13, 0x00000020}, {0x14, 0x0001944c},
1183 {0x14, 0x00059444}, {0x14, 0x0009944c},
1184 {0x14, 0x000d9444}, {0x15, 0x0000f474},
1185 {0x15, 0x0004f477}, {0x15, 0x0008f455},
1186 {0x15, 0x000cf455}, {0x16, 0x00000339},
1187 {0x16, 0x00040339}, {0x16, 0x00080339},
1188 {0x16, 0x000c0366}, {0x00, 0x00010159},
1189 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1190 {0xfe, 0x00000000}, {0x1f, 0x00000003},
1191 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1192 {0x1e, 0x00000247}, {0x1f, 0x00000000},
1197 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table
[] = {
1198 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
1199 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1200 {0xfe, 0x00000000}, {0xb1, 0x00000018},
1201 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1202 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
1203 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
1204 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
1205 {0x5c, 0x00000002}, {0x7c, 0x00000002},
1206 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
1207 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
1208 {0x1e, 0x00000000}, {0xdf, 0x00000780},
1211 * The 8723bu vendor driver indicates that bit 8 should be set in
1212 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
1213 * they never actually check the package type - and just default
1214 * to not setting it.
1217 {0x52, 0x000007d2}, {0x53, 0x00000000},
1218 {0x54, 0x00050400}, {0x55, 0x0004026e},
1219 {0xdd, 0x0000004c}, {0x70, 0x00067435},
1221 * 0x71 has same package type condition as for register 0x51
1224 {0x72, 0x000007d2}, {0x73, 0x00000000},
1225 {0x74, 0x00050400}, {0x75, 0x0004026e},
1226 {0xef, 0x00000100}, {0x34, 0x0000add7},
1227 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
1228 {0x35, 0x00005000}, {0x34, 0x00008dd1},
1229 {0x35, 0x00004400}, {0x34, 0x00007dce},
1230 {0x35, 0x00003800}, {0x34, 0x00006cd1},
1231 {0x35, 0x00004400}, {0x34, 0x00005cce},
1232 {0x35, 0x00003800}, {0x34, 0x000048ce},
1233 {0x35, 0x00004400}, {0x34, 0x000034ce},
1234 {0x35, 0x00003800}, {0x34, 0x00002451},
1235 {0x35, 0x00004400}, {0x34, 0x0000144e},
1236 {0x35, 0x00003800}, {0x34, 0x00000051},
1237 {0x35, 0x00004400}, {0xef, 0x00000000},
1238 {0xef, 0x00000100}, {0xed, 0x00000010},
1239 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
1240 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
1241 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
1242 {0x44, 0x000044d1}, {0x44, 0x000034ce},
1243 {0x44, 0x00002451}, {0x44, 0x0000144e},
1244 {0x44, 0x00000051}, {0xef, 0x00000000},
1245 {0xed, 0x00000000}, {0x7f, 0x00020080},
1246 {0xef, 0x00002000}, {0x3b, 0x000380ef},
1247 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
1248 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
1249 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
1250 {0x3b, 0x00000900}, {0xef, 0x00000000},
1251 {0xed, 0x00000001}, {0x40, 0x000380ef},
1252 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
1253 {0x40, 0x000200bc}, {0x40, 0x000188a5},
1254 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
1255 {0x40, 0x00000900}, {0xed, 0x00000000},
1256 {0x82, 0x00080000}, {0x83, 0x00008000},
1257 {0x84, 0x00048d80}, {0x85, 0x00068000},
1258 {0xa2, 0x00080000}, {0xa3, 0x00008000},
1259 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
1260 {0xed, 0x00000002}, {0xef, 0x00000002},
1261 {0x56, 0x00000032}, {0x76, 0x00000032},
1266 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table
[] = {
1267 {0x00, 0x00030159}, {0x01, 0x00031284},
1268 {0x02, 0x00098000}, {0x03, 0x00018c63},
1269 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1270 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1271 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1272 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1273 {0x19, 0x00000000}, {0x1a, 0x00010255},
1274 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1275 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1276 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1277 {0x21, 0x0006c000}, {0x22, 0x00000000},
1278 {0x23, 0x00001558}, {0x24, 0x00000060},
1279 {0x25, 0x00000483}, {0x26, 0x0004f000},
1280 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1281 {0x29, 0x00004783}, {0x2a, 0x00000001},
1282 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1283 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1284 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1285 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1286 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1287 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1288 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1289 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1290 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1291 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1292 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1293 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1294 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1295 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1296 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1297 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1298 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1299 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1300 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1301 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1302 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1303 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1304 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1305 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1306 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1307 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1308 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1309 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1310 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1311 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1312 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1313 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1314 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1315 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1316 {0x10, 0x00000000}, {0x11, 0x00000000},
1317 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1318 {0x10, 0x0009000f}, {0x11, 0x00023100},
1319 {0x12, 0x00032000}, {0x12, 0x00071000},
1320 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1321 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1322 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1323 {0x13, 0x00018493}, {0x13, 0x0001429b},
1324 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1325 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1326 {0x13, 0x00000020}, {0x14, 0x0001944c},
1327 {0x14, 0x00059444}, {0x14, 0x0009944c},
1328 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1329 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1330 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1331 {0x16, 0x000a0330}, {0x16, 0x00060330},
1332 {0x16, 0x00020330}, {0x00, 0x00010159},
1333 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1334 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1335 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1336 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1341 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table
[] = {
1342 {0x00, 0x00030159}, {0x01, 0x00031284},
1343 {0x02, 0x00098000}, {0x03, 0x00018c63},
1344 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1345 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1346 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1347 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1348 {0x12, 0x00032000}, {0x12, 0x00071000},
1349 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1350 {0x13, 0x000287af}, {0x13, 0x000244b7},
1351 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1352 {0x13, 0x00018493}, {0x13, 0x00014297},
1353 {0x13, 0x00010295}, {0x13, 0x0000c298},
1354 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1355 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1356 {0x14, 0x00059444}, {0x14, 0x0009944c},
1357 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1358 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1359 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1360 {0x16, 0x000a0330}, {0x16, 0x00060330},
1365 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table
[] = {
1366 {0x00, 0x00030159}, {0x01, 0x00031284},
1367 {0x02, 0x00098000}, {0x03, 0x00018c63},
1368 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1369 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1370 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1371 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1372 {0x19, 0x00000000}, {0x1a, 0x00010255},
1373 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1374 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1375 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1376 {0x21, 0x0006c000}, {0x22, 0x00000000},
1377 {0x23, 0x00001558}, {0x24, 0x00000060},
1378 {0x25, 0x00000483}, {0x26, 0x0004f000},
1379 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1380 {0x29, 0x00004783}, {0x2a, 0x00000001},
1381 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1382 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1383 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1384 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1385 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1386 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1387 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1388 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1389 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1390 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1391 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1392 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1393 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1394 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1395 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1396 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1397 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1398 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1399 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1400 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1401 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1402 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1403 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1404 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1405 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1406 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1407 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1408 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1409 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1410 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1411 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1412 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1413 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1414 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1415 {0x10, 0x00000000}, {0x11, 0x00000000},
1416 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1417 {0x10, 0x0009000f}, {0x11, 0x00023100},
1418 {0x12, 0x00032000}, {0x12, 0x00071000},
1419 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1420 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1421 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1422 {0x13, 0x00018493}, {0x13, 0x0001429b},
1423 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1424 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1425 {0x13, 0x00000020}, {0x14, 0x0001944c},
1426 {0x14, 0x00059444}, {0x14, 0x0009944c},
1427 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1428 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1429 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1430 {0x16, 0x000a0330}, {0x16, 0x00060330},
1431 {0x16, 0x00020330}, {0x00, 0x00010159},
1432 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1433 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1434 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1435 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1440 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table
[] = {
1441 {0x00, 0x00030159}, {0x01, 0x00031284},
1442 {0x02, 0x00098000}, {0x03, 0x00018c63},
1443 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1444 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1445 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1446 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1447 {0x19, 0x00000000}, {0x1a, 0x00000255},
1448 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1449 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1450 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1451 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1452 {0x23, 0x00001558}, {0x24, 0x00000060},
1453 {0x25, 0x00000483}, {0x26, 0x0004f000},
1454 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1455 {0x29, 0x00004783}, {0x2a, 0x00000001},
1456 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1457 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1458 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1459 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1460 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1461 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1462 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1463 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1464 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1465 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1466 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1467 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1468 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1469 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1470 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1471 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1472 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1473 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1474 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1475 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1476 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1477 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1478 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1479 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1480 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1481 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1482 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1483 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1484 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1485 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1486 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1487 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1488 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1489 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1490 {0x10, 0x00000000}, {0x11, 0x00000000},
1491 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1492 {0x10, 0x0009000f}, {0x11, 0x00023100},
1493 {0x12, 0x000d8000}, {0x12, 0x00090000},
1494 {0x12, 0x00051000}, {0x12, 0x00012000},
1495 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1496 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1497 {0x13, 0x000183a4}, {0x13, 0x00014398},
1498 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1499 {0x13, 0x000080a4}, {0x13, 0x00004098},
1500 {0x13, 0x00000000}, {0x14, 0x0001944c},
1501 {0x14, 0x00059444}, {0x14, 0x0009944c},
1502 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1503 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1504 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1505 {0x16, 0x000a0330}, {0x16, 0x00060330},
1506 {0x16, 0x00020330}, {0x00, 0x00010159},
1507 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1508 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1509 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1510 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1515 static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table
[] = {
1516 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1517 {0x00, 0x00030000}, {0x08, 0x00008400},
1518 {0x18, 0x00000407}, {0x19, 0x00000012},
1519 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1520 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1521 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1522 {0x57, 0x000d0000}, {0x58, 0x000be180},
1523 {0x67, 0x00001552}, {0x83, 0x00000000},
1524 {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
1525 {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
1526 {0xb5, 0x00008166}, {0xb6, 0x0000803e},
1527 {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
1528 {0xb9, 0x00080001}, {0xba, 0x00040001},
1529 {0xbb, 0x00000400}, {0xbf, 0x000c0000},
1530 {0xc2, 0x00002400}, {0xc3, 0x00000009},
1531 {0xc4, 0x00040c91}, {0xc5, 0x00099999},
1532 {0xc6, 0x000000a3}, {0xc7, 0x00088820},
1533 {0xc8, 0x00076c06}, {0xc9, 0x00000000},
1534 {0xca, 0x00080000}, {0xdf, 0x00000180},
1535 {0xef, 0x000001a0}, {0x51, 0x00069545},
1536 {0x52, 0x0007e45e}, {0x53, 0x00000071},
1537 {0x56, 0x00051ff3}, {0x35, 0x000000a8},
1538 {0x35, 0x000001e2}, {0x35, 0x000002a8},
1539 {0x36, 0x00001c24}, {0x36, 0x00009c24},
1540 {0x36, 0x00011c24}, {0x36, 0x00019c24},
1541 {0x18, 0x00000c07}, {0x5a, 0x00048000},
1543 #ifdef EXT_PA_8192EU
1544 /* External PA or external LNA */
1545 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1546 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1547 {0x34, 0x0000604a}, {0x34, 0x00005047},
1548 {0x34, 0x0000400a}, {0x34, 0x00003007},
1549 {0x34, 0x00002004}, {0x34, 0x00001001},
1553 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1554 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1555 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1556 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1557 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1567 #ifdef EXT_PA_8192EU
1568 /* External PA or external LNA */
1573 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1574 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1575 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1577 #ifdef EXT_PA_8192EU
1578 /* External PA or external LNA */
1583 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1584 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1585 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1586 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1587 {0xfe, 0x00000000}, {0x18, 0x0000fc07},
1588 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1589 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1590 {0x1e, 0x00000001}, {0x1f, 0x00080000},
1595 static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table
[] = {
1596 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1597 {0x00, 0x00030000}, {0x08, 0x00008400},
1598 {0x18, 0x00000407}, {0x19, 0x00000012},
1599 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1600 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1601 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1602 {0x57, 0x000d0000}, {0x58, 0x000be180},
1603 {0x67, 0x00001552}, {0x7f, 0x00000082},
1604 {0x81, 0x0003f000}, {0x83, 0x00000000},
1605 {0xdf, 0x00000180}, {0xef, 0x000001a0},
1606 {0x51, 0x00069545}, {0x52, 0x0007e42e},
1607 {0x53, 0x00000071}, {0x56, 0x00051ff3},
1608 {0x35, 0x000000a8}, {0x35, 0x000001e0},
1609 {0x35, 0x000002a8}, {0x36, 0x00001ca8},
1610 {0x36, 0x00009c24}, {0x36, 0x00011c24},
1611 {0x36, 0x00019c24}, {0x18, 0x00000c07},
1612 {0x5a, 0x00048000}, {0x19, 0x000739d0},
1613 #ifdef EXT_PA_8192EU
1614 /* External PA or external LNA */
1615 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1616 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1617 {0x34, 0x0000604a}, {0x34, 0x00005047},
1618 {0x34, 0x0000400a}, {0x34, 0x00003007},
1619 {0x34, 0x00002004}, {0x34, 0x00001001},
1622 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1623 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1624 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1625 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1626 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1629 {0x00, 0x00030159}, {0x84, 0x00068180},
1630 {0x86, 0x000000ce}, {0x87, 0x00048a00},
1631 {0x8e, 0x00065540}, {0x8f, 0x00088000},
1633 #ifdef EXT_PA_8192EU
1634 /* External PA or external LNA */
1640 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1641 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1642 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1644 #ifdef EXT_PA_8192EU
1645 /* External PA or external LNA */
1650 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1651 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1652 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1653 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1654 {0x00, 0x00010159}, {0xfe, 0x00000000},
1655 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1656 {0xfe, 0x00000000}, {0x1e, 0x00000001},
1657 {0x1f, 0x00080000}, {0x00, 0x00033e70},
1661 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs
[] = {
1663 .hssiparm1
= REG_FPGA0_XA_HSSI_PARM1
,
1664 .hssiparm2
= REG_FPGA0_XA_HSSI_PARM2
,
1665 .lssiparm
= REG_FPGA0_XA_LSSI_PARM
,
1666 .hspiread
= REG_HSPI_XA_READBACK
,
1667 .lssiread
= REG_FPGA0_XA_LSSI_READBACK
,
1668 .rf_sw_ctrl
= REG_FPGA0_XA_RF_SW_CTRL
,
1671 .hssiparm1
= REG_FPGA0_XB_HSSI_PARM1
,
1672 .hssiparm2
= REG_FPGA0_XB_HSSI_PARM2
,
1673 .lssiparm
= REG_FPGA0_XB_LSSI_PARM
,
1674 .hspiread
= REG_HSPI_XB_READBACK
,
1675 .lssiread
= REG_FPGA0_XB_LSSI_READBACK
,
1676 .rf_sw_ctrl
= REG_FPGA0_XB_RF_SW_CTRL
,
1680 static const u32 rtl8723au_iqk_phy_iq_bb_reg
[RTL8XXXU_BB_REGS
] = {
1681 REG_OFDM0_XA_RX_IQ_IMBALANCE
,
1682 REG_OFDM0_XB_RX_IQ_IMBALANCE
,
1683 REG_OFDM0_ENERGY_CCA_THRES
,
1684 REG_OFDM0_AGCR_SSI_TABLE
,
1685 REG_OFDM0_XA_TX_IQ_IMBALANCE
,
1686 REG_OFDM0_XB_TX_IQ_IMBALANCE
,
1687 REG_OFDM0_XC_TX_AFE
,
1688 REG_OFDM0_XD_TX_AFE
,
1689 REG_OFDM0_RX_IQ_EXT_ANTA
1692 static u8
rtl8xxxu_read8(struct rtl8xxxu_priv
*priv
, u16 addr
)
1694 struct usb_device
*udev
= priv
->udev
;
1698 mutex_lock(&priv
->usb_buf_mutex
);
1699 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1700 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1701 addr
, 0, &priv
->usb_buf
.val8
, sizeof(u8
),
1702 RTW_USB_CONTROL_MSG_TIMEOUT
);
1703 data
= priv
->usb_buf
.val8
;
1704 mutex_unlock(&priv
->usb_buf_mutex
);
1706 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1707 dev_info(&udev
->dev
, "%s(%04x) = 0x%02x, len %i\n",
1708 __func__
, addr
, data
, len
);
1712 static u16
rtl8xxxu_read16(struct rtl8xxxu_priv
*priv
, u16 addr
)
1714 struct usb_device
*udev
= priv
->udev
;
1718 mutex_lock(&priv
->usb_buf_mutex
);
1719 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1720 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1721 addr
, 0, &priv
->usb_buf
.val16
, sizeof(u16
),
1722 RTW_USB_CONTROL_MSG_TIMEOUT
);
1723 data
= le16_to_cpu(priv
->usb_buf
.val16
);
1724 mutex_unlock(&priv
->usb_buf_mutex
);
1726 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1727 dev_info(&udev
->dev
, "%s(%04x) = 0x%04x, len %i\n",
1728 __func__
, addr
, data
, len
);
1732 static u32
rtl8xxxu_read32(struct rtl8xxxu_priv
*priv
, u16 addr
)
1734 struct usb_device
*udev
= priv
->udev
;
1738 mutex_lock(&priv
->usb_buf_mutex
);
1739 len
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
1740 REALTEK_USB_CMD_REQ
, REALTEK_USB_READ
,
1741 addr
, 0, &priv
->usb_buf
.val32
, sizeof(u32
),
1742 RTW_USB_CONTROL_MSG_TIMEOUT
);
1743 data
= le32_to_cpu(priv
->usb_buf
.val32
);
1744 mutex_unlock(&priv
->usb_buf_mutex
);
1746 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_READ
)
1747 dev_info(&udev
->dev
, "%s(%04x) = 0x%08x, len %i\n",
1748 __func__
, addr
, data
, len
);
1752 static int rtl8xxxu_write8(struct rtl8xxxu_priv
*priv
, u16 addr
, u8 val
)
1754 struct usb_device
*udev
= priv
->udev
;
1757 mutex_lock(&priv
->usb_buf_mutex
);
1758 priv
->usb_buf
.val8
= val
;
1759 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1760 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1761 addr
, 0, &priv
->usb_buf
.val8
, sizeof(u8
),
1762 RTW_USB_CONTROL_MSG_TIMEOUT
);
1764 mutex_unlock(&priv
->usb_buf_mutex
);
1766 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1767 dev_info(&udev
->dev
, "%s(%04x) = 0x%02x\n",
1768 __func__
, addr
, val
);
1772 static int rtl8xxxu_write16(struct rtl8xxxu_priv
*priv
, u16 addr
, u16 val
)
1774 struct usb_device
*udev
= priv
->udev
;
1777 mutex_lock(&priv
->usb_buf_mutex
);
1778 priv
->usb_buf
.val16
= cpu_to_le16(val
);
1779 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1780 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1781 addr
, 0, &priv
->usb_buf
.val16
, sizeof(u16
),
1782 RTW_USB_CONTROL_MSG_TIMEOUT
);
1783 mutex_unlock(&priv
->usb_buf_mutex
);
1785 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1786 dev_info(&udev
->dev
, "%s(%04x) = 0x%04x\n",
1787 __func__
, addr
, val
);
1791 static int rtl8xxxu_write32(struct rtl8xxxu_priv
*priv
, u16 addr
, u32 val
)
1793 struct usb_device
*udev
= priv
->udev
;
1796 mutex_lock(&priv
->usb_buf_mutex
);
1797 priv
->usb_buf
.val32
= cpu_to_le32(val
);
1798 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1799 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1800 addr
, 0, &priv
->usb_buf
.val32
, sizeof(u32
),
1801 RTW_USB_CONTROL_MSG_TIMEOUT
);
1802 mutex_unlock(&priv
->usb_buf_mutex
);
1804 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_REG_WRITE
)
1805 dev_info(&udev
->dev
, "%s(%04x) = 0x%08x\n",
1806 __func__
, addr
, val
);
1811 rtl8xxxu_writeN(struct rtl8xxxu_priv
*priv
, u16 addr
, u8
*buf
, u16 len
)
1813 struct usb_device
*udev
= priv
->udev
;
1814 int blocksize
= priv
->fops
->writeN_block_size
;
1815 int ret
, i
, count
, remainder
;
1817 count
= len
/ blocksize
;
1818 remainder
= len
% blocksize
;
1820 for (i
= 0; i
< count
; i
++) {
1821 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1822 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1823 addr
, 0, buf
, blocksize
,
1824 RTW_USB_CONTROL_MSG_TIMEOUT
);
1825 if (ret
!= blocksize
)
1833 ret
= usb_control_msg(udev
, usb_sndctrlpipe(udev
, 0),
1834 REALTEK_USB_CMD_REQ
, REALTEK_USB_WRITE
,
1835 addr
, 0, buf
, remainder
,
1836 RTW_USB_CONTROL_MSG_TIMEOUT
);
1837 if (ret
!= remainder
)
1844 dev_info(&udev
->dev
,
1845 "%s: Failed to write block at addr: %04x size: %04x\n",
1846 __func__
, addr
, blocksize
);
1850 static u32
rtl8xxxu_read_rfreg(struct rtl8xxxu_priv
*priv
,
1851 enum rtl8xxxu_rfpath path
, u8 reg
)
1853 u32 hssia
, val32
, retval
;
1855 hssia
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_HSSI_PARM2
);
1857 val32
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hssiparm2
);
1861 val32
&= ~FPGA0_HSSI_PARM2_ADDR_MASK
;
1862 val32
|= (reg
<< FPGA0_HSSI_PARM2_ADDR_SHIFT
);
1863 val32
|= FPGA0_HSSI_PARM2_EDGE_READ
;
1864 hssia
&= ~FPGA0_HSSI_PARM2_EDGE_READ
;
1865 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM2
, hssia
);
1869 rtl8xxxu_write32(priv
, rtl8xxxu_rfregs
[path
].hssiparm2
, val32
);
1872 hssia
|= FPGA0_HSSI_PARM2_EDGE_READ
;
1873 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM2
, hssia
);
1876 val32
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hssiparm1
);
1877 if (val32
& FPGA0_HSSI_PARM1_PI
)
1878 retval
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].hspiread
);
1880 retval
= rtl8xxxu_read32(priv
, rtl8xxxu_rfregs
[path
].lssiread
);
1884 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_RFREG_READ
)
1885 dev_info(&priv
->udev
->dev
, "%s(%02x) = 0x%06x\n",
1886 __func__
, reg
, retval
);
1891 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1892 * have write issues in high temperature conditions. We may have to
1893 * retry writing them.
1895 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv
*priv
,
1896 enum rtl8xxxu_rfpath path
, u8 reg
, u32 data
)
1899 u32 dataaddr
, val32
;
1901 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_RFREG_WRITE
)
1902 dev_info(&priv
->udev
->dev
, "%s(%02x) = 0x%06x\n",
1903 __func__
, reg
, data
);
1905 data
&= FPGA0_LSSI_PARM_DATA_MASK
;
1906 dataaddr
= (reg
<< FPGA0_LSSI_PARM_ADDR_SHIFT
) | data
;
1908 if (priv
->rtl_chip
== RTL8192E
) {
1909 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
1911 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
1914 /* Use XB for path B */
1915 ret
= rtl8xxxu_write32(priv
, rtl8xxxu_rfregs
[path
].lssiparm
, dataaddr
);
1916 if (ret
!= sizeof(dataaddr
))
1923 if (priv
->rtl_chip
== RTL8192E
) {
1924 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
1926 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
1932 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv
*priv
,
1933 struct h2c_cmd
*h2c
, int len
)
1935 struct device
*dev
= &priv
->udev
->dev
;
1936 int mbox_nr
, retry
, retval
= 0;
1937 int mbox_reg
, mbox_ext_reg
;
1940 mutex_lock(&priv
->h2c_mutex
);
1942 mbox_nr
= priv
->next_mbox
;
1943 mbox_reg
= REG_HMBOX_0
+ (mbox_nr
* 4);
1944 mbox_ext_reg
= priv
->fops
->mbox_ext_reg
+
1945 (mbox_nr
* priv
->fops
->mbox_ext_width
);
1952 val8
= rtl8xxxu_read8(priv
, REG_HMTFR
);
1953 if (!(val8
& BIT(mbox_nr
)))
1958 dev_info(dev
, "%s: Mailbox busy\n", __func__
);
1964 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1966 if (len
> sizeof(u32
)) {
1967 if (priv
->fops
->mbox_ext_width
== 4) {
1968 rtl8xxxu_write32(priv
, mbox_ext_reg
,
1969 le32_to_cpu(h2c
->raw_wide
.ext
));
1970 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1971 dev_info(dev
, "H2C_EXT %08x\n",
1972 le32_to_cpu(h2c
->raw_wide
.ext
));
1974 rtl8xxxu_write16(priv
, mbox_ext_reg
,
1975 le16_to_cpu(h2c
->raw
.ext
));
1976 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1977 dev_info(dev
, "H2C_EXT %04x\n",
1978 le16_to_cpu(h2c
->raw
.ext
));
1981 rtl8xxxu_write32(priv
, mbox_reg
, le32_to_cpu(h2c
->raw
.data
));
1982 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_H2C
)
1983 dev_info(dev
, "H2C %08x\n", le32_to_cpu(h2c
->raw
.data
));
1985 priv
->next_mbox
= (mbox_nr
+ 1) % H2C_MAX_MBOX
;
1988 mutex_unlock(&priv
->h2c_mutex
);
1992 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv
*priv
, u8 reg
, u8 data
)
1997 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
1998 h2c
.bt_mp_oper
.cmd
= H2C_8723B_BT_MP_OPER
;
1999 h2c
.bt_mp_oper
.operreq
= 0 | (reqnum
<< 4);
2000 h2c
.bt_mp_oper
.opcode
= BT_MP_OP_WRITE_REG_VALUE
;
2001 h2c
.bt_mp_oper
.data
= data
;
2002 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_mp_oper
));
2005 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
2006 h2c
.bt_mp_oper
.cmd
= H2C_8723B_BT_MP_OPER
;
2007 h2c
.bt_mp_oper
.operreq
= 0 | (reqnum
<< 4);
2008 h2c
.bt_mp_oper
.opcode
= BT_MP_OP_WRITE_REG_VALUE
;
2009 h2c
.bt_mp_oper
.addr
= reg
;
2010 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_mp_oper
));
2013 static void rtl8723a_enable_rf(struct rtl8xxxu_priv
*priv
)
2018 val8
= rtl8xxxu_read8(priv
, REG_SPS0_CTRL
);
2019 val8
|= BIT(0) | BIT(3);
2020 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, val8
);
2022 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_PARM
);
2023 val32
&= ~(BIT(4) | BIT(5));
2025 if (priv
->rf_paths
== 2) {
2026 val32
&= ~(BIT(20) | BIT(21));
2029 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_PARM
, val32
);
2031 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
2032 val32
&= ~OFDM_RF_PATH_TX_MASK
;
2033 if (priv
->tx_paths
== 2)
2034 val32
|= OFDM_RF_PATH_TX_A
| OFDM_RF_PATH_TX_B
;
2035 else if (priv
->rtl_chip
== RTL8192C
|| priv
->rtl_chip
== RTL8191C
)
2036 val32
|= OFDM_RF_PATH_TX_B
;
2038 val32
|= OFDM_RF_PATH_TX_A
;
2039 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
2041 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
2042 val32
&= ~FPGA_RF_MODE_JAPAN
;
2043 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
2045 if (priv
->rf_paths
== 2)
2046 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x63db25a0);
2048 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x631b25a0);
2050 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0x32d95);
2051 if (priv
->rf_paths
== 2)
2052 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0x32d95);
2054 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0x00);
2057 static void rtl8723a_disable_rf(struct rtl8xxxu_priv
*priv
)
2062 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
2064 sps0
= rtl8xxxu_read8(priv
, REG_SPS0_CTRL
);
2066 /* RF RX code for preamble power saving */
2067 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_PARM
);
2068 val32
&= ~(BIT(3) | BIT(4) | BIT(5));
2069 if (priv
->rf_paths
== 2)
2070 val32
&= ~(BIT(19) | BIT(20) | BIT(21));
2071 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_PARM
, val32
);
2073 /* Disable TX for four paths */
2074 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
2075 val32
&= ~OFDM_RF_PATH_TX_MASK
;
2076 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
2078 /* Enable power saving */
2079 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
2080 val32
|= FPGA_RF_MODE_JAPAN
;
2081 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
2083 /* AFE control register to power down bits [30:22] */
2084 if (priv
->rf_paths
== 2)
2085 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x00db25a0);
2087 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, 0x001b25a0);
2089 /* Power down RF module */
2090 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0);
2091 if (priv
->rf_paths
== 2)
2092 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
, 0);
2094 sps0
&= ~(BIT(0) | BIT(3));
2095 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, sps0
);
2099 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv
*priv
)
2103 val8
= rtl8xxxu_read8(priv
, REG_FWHW_TXQ_CTRL
+ 2);
2105 rtl8xxxu_write8(priv
, REG_FWHW_TXQ_CTRL
+ 2, val8
);
2107 rtl8xxxu_write8(priv
, REG_TBTT_PROHIBIT
+ 1, 0x64);
2108 val8
= rtl8xxxu_read8(priv
, REG_TBTT_PROHIBIT
+ 2);
2110 rtl8xxxu_write8(priv
, REG_TBTT_PROHIBIT
+ 2, val8
);
2115 * The rtl8723a has 3 channel groups for it's efuse settings. It only
2116 * supports the 2.4GHz band, so channels 1 - 14:
2117 * group 0: channels 1 - 3
2118 * group 1: channels 4 - 9
2119 * group 2: channels 10 - 14
2121 * Note: We index from 0 in the code
2123 static int rtl8723a_channel_to_group(int channel
)
2129 else if (channel
< 10)
2138 * Valid for rtl8723bu and rtl8192eu
2140 static int rtl8723b_channel_to_group(int channel
)
2146 else if (channel
< 6)
2148 else if (channel
< 9)
2150 else if (channel
< 12)
2158 static void rtl8723au_config_channel(struct ieee80211_hw
*hw
)
2160 struct rtl8xxxu_priv
*priv
= hw
->priv
;
2164 int sec_ch_above
, channel
;
2167 opmode
= rtl8xxxu_read8(priv
, REG_BW_OPMODE
);
2168 rsr
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
2169 channel
= hw
->conf
.chandef
.chan
->hw_value
;
2171 switch (hw
->conf
.chandef
.width
) {
2172 case NL80211_CHAN_WIDTH_20_NOHT
:
2174 case NL80211_CHAN_WIDTH_20
:
2175 opmode
|= BW_OPMODE_20MHZ
;
2176 rtl8xxxu_write8(priv
, REG_BW_OPMODE
, opmode
);
2178 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
2179 val32
&= ~FPGA_RF_MODE
;
2180 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
2182 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
2183 val32
&= ~FPGA_RF_MODE
;
2184 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
2186 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_ANALOG2
);
2187 val32
|= FPGA0_ANALOG2_20MHZ
;
2188 rtl8xxxu_write32(priv
, REG_FPGA0_ANALOG2
, val32
);
2190 case NL80211_CHAN_WIDTH_40
:
2191 if (hw
->conf
.chandef
.center_freq1
>
2192 hw
->conf
.chandef
.chan
->center_freq
) {
2200 opmode
&= ~BW_OPMODE_20MHZ
;
2201 rtl8xxxu_write8(priv
, REG_BW_OPMODE
, opmode
);
2202 rsr
&= ~RSR_RSC_BANDWIDTH_40M
;
2204 rsr
|= RSR_RSC_UPPER_SUB_CHANNEL
;
2206 rsr
|= RSR_RSC_LOWER_SUB_CHANNEL
;
2207 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, rsr
);
2209 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
2210 val32
|= FPGA_RF_MODE
;
2211 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
2213 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
2214 val32
|= FPGA_RF_MODE
;
2215 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
2218 * Set Control channel to upper or lower. These settings
2219 * are required only for 40MHz
2221 val32
= rtl8xxxu_read32(priv
, REG_CCK0_SYSTEM
);
2222 val32
&= ~CCK0_SIDEBAND
;
2224 val32
|= CCK0_SIDEBAND
;
2225 rtl8xxxu_write32(priv
, REG_CCK0_SYSTEM
, val32
);
2227 val32
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
2228 val32
&= ~OFDM_LSTF_PRIME_CH_MASK
; /* 0xc00 */
2230 val32
|= OFDM_LSTF_PRIME_CH_LOW
;
2232 val32
|= OFDM_LSTF_PRIME_CH_HIGH
;
2233 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
2235 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_ANALOG2
);
2236 val32
&= ~FPGA0_ANALOG2_20MHZ
;
2237 rtl8xxxu_write32(priv
, REG_FPGA0_ANALOG2
, val32
);
2239 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
2240 val32
&= ~(FPGA0_PS_LOWER_CHANNEL
| FPGA0_PS_UPPER_CHANNEL
);
2242 val32
|= FPGA0_PS_UPPER_CHANNEL
;
2244 val32
|= FPGA0_PS_LOWER_CHANNEL
;
2245 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
2252 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
2253 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
2254 val32
&= ~MODE_AG_CHANNEL_MASK
;
2256 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
2264 rtl8xxxu_write8(priv
, REG_SIFS_CCK
+ 1, val8
);
2265 rtl8xxxu_write8(priv
, REG_SIFS_OFDM
+ 1, val8
);
2267 rtl8xxxu_write16(priv
, REG_R2T_SIFS
, 0x0808);
2268 rtl8xxxu_write16(priv
, REG_T2T_SIFS
, 0x0a0a);
2270 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
2271 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
2272 if (hw
->conf
.chandef
.width
== NL80211_CHAN_WIDTH_40
)
2273 val32
&= ~MODE_AG_CHANNEL_20MHZ
;
2275 val32
|= MODE_AG_CHANNEL_20MHZ
;
2276 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
2280 static void rtl8723bu_config_channel(struct ieee80211_hw
*hw
)
2282 struct rtl8xxxu_priv
*priv
= hw
->priv
;
2284 u8 val8
, subchannel
;
2287 int sec_ch_above
, channel
;
2290 rf_mode_bw
= rtl8xxxu_read16(priv
, REG_WMAC_TRXPTCL_CTL
);
2291 rf_mode_bw
&= ~WMAC_TRXPTCL_CTL_BW_MASK
;
2292 rsr
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
2293 channel
= hw
->conf
.chandef
.chan
->hw_value
;
2298 switch (hw
->conf
.chandef
.width
) {
2299 case NL80211_CHAN_WIDTH_20_NOHT
:
2301 case NL80211_CHAN_WIDTH_20
:
2302 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_20
;
2305 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
2306 val32
&= ~FPGA_RF_MODE
;
2307 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
2309 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
2310 val32
&= ~FPGA_RF_MODE
;
2311 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
2313 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TX_PSDO_NOISE_WEIGHT
);
2314 val32
&= ~(BIT(30) | BIT(31));
2315 rtl8xxxu_write32(priv
, REG_OFDM0_TX_PSDO_NOISE_WEIGHT
, val32
);
2318 case NL80211_CHAN_WIDTH_40
:
2319 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_40
;
2321 if (hw
->conf
.chandef
.center_freq1
>
2322 hw
->conf
.chandef
.chan
->center_freq
) {
2330 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
2331 val32
|= FPGA_RF_MODE
;
2332 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
2334 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_RF_MODE
);
2335 val32
|= FPGA_RF_MODE
;
2336 rtl8xxxu_write32(priv
, REG_FPGA1_RF_MODE
, val32
);
2339 * Set Control channel to upper or lower. These settings
2340 * are required only for 40MHz
2342 val32
= rtl8xxxu_read32(priv
, REG_CCK0_SYSTEM
);
2343 val32
&= ~CCK0_SIDEBAND
;
2345 val32
|= CCK0_SIDEBAND
;
2346 rtl8xxxu_write32(priv
, REG_CCK0_SYSTEM
, val32
);
2348 val32
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
2349 val32
&= ~OFDM_LSTF_PRIME_CH_MASK
; /* 0xc00 */
2351 val32
|= OFDM_LSTF_PRIME_CH_LOW
;
2353 val32
|= OFDM_LSTF_PRIME_CH_HIGH
;
2354 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
2356 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_POWER_SAVE
);
2357 val32
&= ~(FPGA0_PS_LOWER_CHANNEL
| FPGA0_PS_UPPER_CHANNEL
);
2359 val32
|= FPGA0_PS_UPPER_CHANNEL
;
2361 val32
|= FPGA0_PS_LOWER_CHANNEL
;
2362 rtl8xxxu_write32(priv
, REG_FPGA0_POWER_SAVE
, val32
);
2364 case NL80211_CHAN_WIDTH_80
:
2365 rf_mode_bw
|= WMAC_TRXPTCL_CTL_BW_80
;
2371 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
2372 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
2373 val32
&= ~MODE_AG_CHANNEL_MASK
;
2375 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
2378 rtl8xxxu_write16(priv
, REG_WMAC_TRXPTCL_CTL
, rf_mode_bw
);
2379 rtl8xxxu_write8(priv
, REG_DATA_SUBCHANNEL
, subchannel
);
2386 rtl8xxxu_write8(priv
, REG_SIFS_CCK
+ 1, val8
);
2387 rtl8xxxu_write8(priv
, REG_SIFS_OFDM
+ 1, val8
);
2389 rtl8xxxu_write16(priv
, REG_R2T_SIFS
, 0x0808);
2390 rtl8xxxu_write16(priv
, REG_T2T_SIFS
, 0x0a0a);
2392 for (i
= RF_A
; i
< priv
->rf_paths
; i
++) {
2393 val32
= rtl8xxxu_read_rfreg(priv
, i
, RF6052_REG_MODE_AG
);
2394 val32
&= ~MODE_AG_BW_MASK
;
2395 switch(hw
->conf
.chandef
.width
) {
2396 case NL80211_CHAN_WIDTH_80
:
2397 val32
|= MODE_AG_BW_80MHZ_8723B
;
2399 case NL80211_CHAN_WIDTH_40
:
2400 val32
|= MODE_AG_BW_40MHZ_8723B
;
2403 val32
|= MODE_AG_BW_20MHZ_8723B
;
2406 rtl8xxxu_write_rfreg(priv
, i
, RF6052_REG_MODE_AG
, val32
);
2411 rtl8723a_set_tx_power(struct rtl8xxxu_priv
*priv
, int channel
, bool ht40
)
2413 u8 cck
[RTL8723A_MAX_RF_PATHS
], ofdm
[RTL8723A_MAX_RF_PATHS
];
2414 u8 ofdmbase
[RTL8723A_MAX_RF_PATHS
], mcsbase
[RTL8723A_MAX_RF_PATHS
];
2415 u32 val32
, ofdm_a
, ofdm_b
, mcs_a
, mcs_b
;
2419 group
= rtl8723a_channel_to_group(channel
);
2421 cck
[0] = priv
->cck_tx_power_index_A
[group
];
2422 cck
[1] = priv
->cck_tx_power_index_B
[group
];
2424 ofdm
[0] = priv
->ht40_1s_tx_power_index_A
[group
];
2425 ofdm
[1] = priv
->ht40_1s_tx_power_index_B
[group
];
2427 ofdmbase
[0] = ofdm
[0] + priv
->ofdm_tx_power_index_diff
[group
].a
;
2428 ofdmbase
[1] = ofdm
[1] + priv
->ofdm_tx_power_index_diff
[group
].b
;
2430 mcsbase
[0] = ofdm
[0];
2431 mcsbase
[1] = ofdm
[1];
2433 mcsbase
[0] += priv
->ht20_tx_power_index_diff
[group
].a
;
2434 mcsbase
[1] += priv
->ht20_tx_power_index_diff
[group
].b
;
2437 if (priv
->tx_paths
> 1) {
2438 if (ofdm
[0] > priv
->ht40_2s_tx_power_index_diff
[group
].a
)
2439 ofdm
[0] -= priv
->ht40_2s_tx_power_index_diff
[group
].a
;
2440 if (ofdm
[1] > priv
->ht40_2s_tx_power_index_diff
[group
].b
)
2441 ofdm
[1] -= priv
->ht40_2s_tx_power_index_diff
[group
].b
;
2444 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_CHANNEL
)
2445 dev_info(&priv
->udev
->dev
,
2446 "%s: Setting TX power CCK A: %02x, "
2447 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
2448 __func__
, cck
[0], cck
[1], ofdm
[0], ofdm
[1]);
2450 for (i
= 0; i
< RTL8723A_MAX_RF_PATHS
; i
++) {
2451 if (cck
[i
] > RF6052_MAX_TX_PWR
)
2452 cck
[i
] = RF6052_MAX_TX_PWR
;
2453 if (ofdm
[i
] > RF6052_MAX_TX_PWR
)
2454 ofdm
[i
] = RF6052_MAX_TX_PWR
;
2457 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_A_CCK1_MCS32
);
2458 val32
&= 0xffff00ff;
2459 val32
|= (cck
[0] << 8);
2460 rtl8xxxu_write32(priv
, REG_TX_AGC_A_CCK1_MCS32
, val32
);
2462 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2464 val32
|= ((cck
[0] << 8) | (cck
[0] << 16) | (cck
[0] << 24));
2465 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2467 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2468 val32
&= 0xffffff00;
2470 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2472 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
);
2474 val32
|= ((cck
[1] << 8) | (cck
[1] << 16) | (cck
[1] << 24));
2475 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
, val32
);
2477 ofdm_a
= ofdmbase
[0] | ofdmbase
[0] << 8 |
2478 ofdmbase
[0] << 16 | ofdmbase
[0] << 24;
2479 ofdm_b
= ofdmbase
[1] | ofdmbase
[1] << 8 |
2480 ofdmbase
[1] << 16 | ofdmbase
[1] << 24;
2481 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE18_06
, ofdm_a
);
2482 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE18_06
, ofdm_b
);
2484 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE54_24
, ofdm_a
);
2485 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE54_24
, ofdm_b
);
2487 mcs_a
= mcsbase
[0] | mcsbase
[0] << 8 |
2488 mcsbase
[0] << 16 | mcsbase
[0] << 24;
2489 mcs_b
= mcsbase
[1] | mcsbase
[1] << 8 |
2490 mcsbase
[1] << 16 | mcsbase
[1] << 24;
2492 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS03_MCS00
, mcs_a
);
2493 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS03_MCS00
, mcs_b
);
2495 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS07_MCS04
, mcs_a
);
2496 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS07_MCS04
, mcs_b
);
2498 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS11_MCS08
, mcs_a
);
2499 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS11_MCS08
, mcs_b
);
2501 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS15_MCS12
, mcs_a
);
2502 for (i
= 0; i
< 3; i
++) {
2504 val8
= (mcsbase
[0] > 8) ? (mcsbase
[0] - 8) : 0;
2506 val8
= (mcsbase
[0] > 6) ? (mcsbase
[0] - 6) : 0;
2507 rtl8xxxu_write8(priv
, REG_OFDM0_XC_TX_IQ_IMBALANCE
+ i
, val8
);
2509 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS15_MCS12
, mcs_b
);
2510 for (i
= 0; i
< 3; i
++) {
2512 val8
= (mcsbase
[1] > 8) ? (mcsbase
[1] - 8) : 0;
2514 val8
= (mcsbase
[1] > 6) ? (mcsbase
[1] - 6) : 0;
2515 rtl8xxxu_write8(priv
, REG_OFDM0_XD_TX_IQ_IMBALANCE
+ i
, val8
);
2520 rtl8723b_set_tx_power(struct rtl8xxxu_priv
*priv
, int channel
, bool ht40
)
2522 u32 val32
, ofdm
, mcs
;
2523 u8 cck
, ofdmbase
, mcsbase
;
2527 group
= rtl8723b_channel_to_group(channel
);
2529 cck
= priv
->cck_tx_power_index_B
[group
];
2530 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_A_CCK1_MCS32
);
2531 val32
&= 0xffff00ff;
2532 val32
|= (cck
<< 8);
2533 rtl8xxxu_write32(priv
, REG_TX_AGC_A_CCK1_MCS32
, val32
);
2535 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2537 val32
|= ((cck
<< 8) | (cck
<< 16) | (cck
<< 24));
2538 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2540 ofdmbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2541 ofdmbase
+= priv
->ofdm_tx_power_diff
[tx_idx
].b
;
2542 ofdm
= ofdmbase
| ofdmbase
<< 8 | ofdmbase
<< 16 | ofdmbase
<< 24;
2544 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE18_06
, ofdm
);
2545 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE54_24
, ofdm
);
2547 mcsbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2549 mcsbase
+= priv
->ht40_tx_power_diff
[tx_idx
++].b
;
2551 mcsbase
+= priv
->ht20_tx_power_diff
[tx_idx
++].b
;
2552 mcs
= mcsbase
| mcsbase
<< 8 | mcsbase
<< 16 | mcsbase
<< 24;
2554 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS03_MCS00
, mcs
);
2555 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS07_MCS04
, mcs
);
2559 rtl8192e_set_tx_power(struct rtl8xxxu_priv
*priv
, int channel
, bool ht40
)
2561 u32 val32
, ofdm
, mcs
;
2562 u8 cck
, ofdmbase
, mcsbase
;
2566 group
= rtl8723b_channel_to_group(channel
);
2568 cck
= priv
->cck_tx_power_index_A
[group
];
2570 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_A_CCK1_MCS32
);
2571 val32
&= 0xffff00ff;
2572 val32
|= (cck
<< 8);
2573 rtl8xxxu_write32(priv
, REG_TX_AGC_A_CCK1_MCS32
, val32
);
2575 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2577 val32
|= ((cck
<< 8) | (cck
<< 16) | (cck
<< 24));
2578 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2580 ofdmbase
= priv
->ht40_1s_tx_power_index_A
[group
];
2581 ofdmbase
+= priv
->ofdm_tx_power_diff
[tx_idx
].a
;
2582 ofdm
= ofdmbase
| ofdmbase
<< 8 | ofdmbase
<< 16 | ofdmbase
<< 24;
2584 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE18_06
, ofdm
);
2585 rtl8xxxu_write32(priv
, REG_TX_AGC_A_RATE54_24
, ofdm
);
2587 mcsbase
= priv
->ht40_1s_tx_power_index_A
[group
];
2589 mcsbase
+= priv
->ht40_tx_power_diff
[tx_idx
++].a
;
2591 mcsbase
+= priv
->ht20_tx_power_diff
[tx_idx
++].a
;
2592 mcs
= mcsbase
| mcsbase
<< 8 | mcsbase
<< 16 | mcsbase
<< 24;
2594 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS03_MCS00
, mcs
);
2595 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS07_MCS04
, mcs
);
2596 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS11_MCS08
, mcs
);
2597 rtl8xxxu_write32(priv
, REG_TX_AGC_A_MCS15_MCS12
, mcs
);
2599 if (priv
->tx_paths
> 1) {
2600 cck
= priv
->cck_tx_power_index_B
[group
];
2602 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
);
2604 val32
|= ((cck
<< 8) | (cck
<< 16) | (cck
<< 24));
2605 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK1_55_MCS32
, val32
);
2607 val32
= rtl8xxxu_read32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
);
2608 val32
&= 0xffffff00;
2610 rtl8xxxu_write32(priv
, REG_TX_AGC_B_CCK11_A_CCK2_11
, val32
);
2612 ofdmbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2613 ofdmbase
+= priv
->ofdm_tx_power_diff
[tx_idx
].b
;
2614 ofdm
= ofdmbase
| ofdmbase
<< 8 |
2615 ofdmbase
<< 16 | ofdmbase
<< 24;
2617 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE18_06
, ofdm
);
2618 rtl8xxxu_write32(priv
, REG_TX_AGC_B_RATE54_24
, ofdm
);
2620 mcsbase
= priv
->ht40_1s_tx_power_index_B
[group
];
2622 mcsbase
+= priv
->ht40_tx_power_diff
[tx_idx
++].b
;
2624 mcsbase
+= priv
->ht20_tx_power_diff
[tx_idx
++].b
;
2625 mcs
= mcsbase
| mcsbase
<< 8 | mcsbase
<< 16 | mcsbase
<< 24;
2627 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS03_MCS00
, mcs
);
2628 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS07_MCS04
, mcs
);
2629 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS11_MCS08
, mcs
);
2630 rtl8xxxu_write32(priv
, REG_TX_AGC_B_MCS15_MCS12
, mcs
);
2634 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv
*priv
,
2635 enum nl80211_iftype linktype
)
2639 val8
= rtl8xxxu_read8(priv
, REG_MSR
);
2640 val8
&= ~MSR_LINKTYPE_MASK
;
2643 case NL80211_IFTYPE_UNSPECIFIED
:
2644 val8
|= MSR_LINKTYPE_NONE
;
2646 case NL80211_IFTYPE_ADHOC
:
2647 val8
|= MSR_LINKTYPE_ADHOC
;
2649 case NL80211_IFTYPE_STATION
:
2650 val8
|= MSR_LINKTYPE_STATION
;
2652 case NL80211_IFTYPE_AP
:
2653 val8
|= MSR_LINKTYPE_AP
;
2659 rtl8xxxu_write8(priv
, REG_MSR
, val8
);
2665 rtl8xxxu_set_retry(struct rtl8xxxu_priv
*priv
, u16 short_retry
, u16 long_retry
)
2669 val16
= ((short_retry
<< RETRY_LIMIT_SHORT_SHIFT
) &
2670 RETRY_LIMIT_SHORT_MASK
) |
2671 ((long_retry
<< RETRY_LIMIT_LONG_SHIFT
) &
2672 RETRY_LIMIT_LONG_MASK
);
2674 rtl8xxxu_write16(priv
, REG_RETRY_LIMIT
, val16
);
2678 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv
*priv
, u16 cck
, u16 ofdm
)
2682 val16
= ((cck
<< SPEC_SIFS_CCK_SHIFT
) & SPEC_SIFS_CCK_MASK
) |
2683 ((ofdm
<< SPEC_SIFS_OFDM_SHIFT
) & SPEC_SIFS_OFDM_MASK
);
2685 rtl8xxxu_write16(priv
, REG_SPEC_SIFS
, val16
);
2688 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv
*priv
)
2690 struct device
*dev
= &priv
->udev
->dev
;
2693 switch (priv
->chip_cut
) {
2714 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2715 priv
->chip_name
, cut
, priv
->chip_vendor
, priv
->tx_paths
,
2716 priv
->rx_paths
, priv
->ep_tx_count
, priv
->has_wifi
,
2717 priv
->has_bluetooth
, priv
->has_gps
, priv
->hi_pa
);
2719 dev_info(dev
, "RTL%s MAC: %pM\n", priv
->chip_name
, priv
->mac_addr
);
2722 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv
*priv
)
2724 struct device
*dev
= &priv
->udev
->dev
;
2728 val32
= rtl8xxxu_read32(priv
, REG_SYS_CFG
);
2729 priv
->chip_cut
= (val32
& SYS_CFG_CHIP_VERSION_MASK
) >>
2730 SYS_CFG_CHIP_VERSION_SHIFT
;
2731 if (val32
& SYS_CFG_TRP_VAUX_EN
) {
2732 dev_info(dev
, "Unsupported test chip\n");
2736 if (val32
& SYS_CFG_BT_FUNC
) {
2737 if (priv
->chip_cut
>= 3) {
2738 sprintf(priv
->chip_name
, "8723BU");
2739 priv
->rtl_chip
= RTL8723B
;
2741 sprintf(priv
->chip_name
, "8723AU");
2742 priv
->usb_interrupts
= 1;
2743 priv
->rtl_chip
= RTL8723A
;
2750 val32
= rtl8xxxu_read32(priv
, REG_MULTI_FUNC_CTRL
);
2751 if (val32
& MULTI_WIFI_FUNC_EN
)
2753 if (val32
& MULTI_BT_FUNC_EN
)
2754 priv
->has_bluetooth
= 1;
2755 if (val32
& MULTI_GPS_FUNC_EN
)
2757 priv
->is_multi_func
= 1;
2758 } else if (val32
& SYS_CFG_TYPE_ID
) {
2759 bonding
= rtl8xxxu_read32(priv
, REG_HPON_FSM
);
2760 bonding
&= HPON_FSM_BONDING_MASK
;
2761 if (priv
->fops
->tx_desc_size
==
2762 sizeof(struct rtl8xxxu_txdesc40
)) {
2763 if (bonding
== HPON_FSM_BONDING_1T2R
) {
2764 sprintf(priv
->chip_name
, "8191EU");
2768 priv
->rtl_chip
= RTL8191E
;
2770 sprintf(priv
->chip_name
, "8192EU");
2774 priv
->rtl_chip
= RTL8192E
;
2776 } else if (bonding
== HPON_FSM_BONDING_1T2R
) {
2777 sprintf(priv
->chip_name
, "8191CU");
2781 priv
->usb_interrupts
= 1;
2782 priv
->rtl_chip
= RTL8191C
;
2784 sprintf(priv
->chip_name
, "8192CU");
2788 priv
->usb_interrupts
= 1;
2789 priv
->rtl_chip
= RTL8192C
;
2793 sprintf(priv
->chip_name
, "8188CU");
2797 priv
->rtl_chip
= RTL8188C
;
2798 priv
->usb_interrupts
= 1;
2802 switch (priv
->rtl_chip
) {
2806 switch (val32
& SYS_CFG_VENDOR_EXT_MASK
) {
2807 case SYS_CFG_VENDOR_ID_TSMC
:
2808 sprintf(priv
->chip_vendor
, "TSMC");
2810 case SYS_CFG_VENDOR_ID_SMIC
:
2811 sprintf(priv
->chip_vendor
, "SMIC");
2812 priv
->vendor_smic
= 1;
2814 case SYS_CFG_VENDOR_ID_UMC
:
2815 sprintf(priv
->chip_vendor
, "UMC");
2816 priv
->vendor_umc
= 1;
2819 sprintf(priv
->chip_vendor
, "unknown");
2823 if (val32
& SYS_CFG_VENDOR_ID
) {
2824 sprintf(priv
->chip_vendor
, "UMC");
2825 priv
->vendor_umc
= 1;
2827 sprintf(priv
->chip_vendor
, "TSMC");
2831 val32
= rtl8xxxu_read32(priv
, REG_GPIO_OUTSTS
);
2832 priv
->rom_rev
= (val32
& GPIO_RF_RL_ID
) >> 28;
2834 val16
= rtl8xxxu_read16(priv
, REG_NORMAL_SIE_EP_TX
);
2835 if (val16
& NORMAL_SIE_EP_TX_HIGH_MASK
) {
2836 priv
->ep_tx_high_queue
= 1;
2837 priv
->ep_tx_count
++;
2840 if (val16
& NORMAL_SIE_EP_TX_NORMAL_MASK
) {
2841 priv
->ep_tx_normal_queue
= 1;
2842 priv
->ep_tx_count
++;
2845 if (val16
& NORMAL_SIE_EP_TX_LOW_MASK
) {
2846 priv
->ep_tx_low_queue
= 1;
2847 priv
->ep_tx_count
++;
2851 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2853 if (!priv
->ep_tx_count
) {
2854 switch (priv
->nr_out_eps
) {
2857 priv
->ep_tx_low_queue
= 1;
2858 priv
->ep_tx_count
++;
2860 priv
->ep_tx_normal_queue
= 1;
2861 priv
->ep_tx_count
++;
2863 priv
->ep_tx_high_queue
= 1;
2864 priv
->ep_tx_count
++;
2867 dev_info(dev
, "Unsupported USB TX end-points\n");
2875 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv
*priv
)
2877 struct rtl8723au_efuse
*efuse
= &priv
->efuse_wifi
.efuse8723
;
2879 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2882 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2884 memcpy(priv
->cck_tx_power_index_A
,
2885 efuse
->cck_tx_power_index_A
,
2886 sizeof(efuse
->cck_tx_power_index_A
));
2887 memcpy(priv
->cck_tx_power_index_B
,
2888 efuse
->cck_tx_power_index_B
,
2889 sizeof(efuse
->cck_tx_power_index_B
));
2891 memcpy(priv
->ht40_1s_tx_power_index_A
,
2892 efuse
->ht40_1s_tx_power_index_A
,
2893 sizeof(efuse
->ht40_1s_tx_power_index_A
));
2894 memcpy(priv
->ht40_1s_tx_power_index_B
,
2895 efuse
->ht40_1s_tx_power_index_B
,
2896 sizeof(efuse
->ht40_1s_tx_power_index_B
));
2898 memcpy(priv
->ht20_tx_power_index_diff
,
2899 efuse
->ht20_tx_power_index_diff
,
2900 sizeof(efuse
->ht20_tx_power_index_diff
));
2901 memcpy(priv
->ofdm_tx_power_index_diff
,
2902 efuse
->ofdm_tx_power_index_diff
,
2903 sizeof(efuse
->ofdm_tx_power_index_diff
));
2905 memcpy(priv
->ht40_max_power_offset
,
2906 efuse
->ht40_max_power_offset
,
2907 sizeof(efuse
->ht40_max_power_offset
));
2908 memcpy(priv
->ht20_max_power_offset
,
2909 efuse
->ht20_max_power_offset
,
2910 sizeof(efuse
->ht20_max_power_offset
));
2912 if (priv
->efuse_wifi
.efuse8723
.version
>= 0x01) {
2913 priv
->has_xtalk
= 1;
2914 priv
->xtalk
= priv
->efuse_wifi
.efuse8723
.xtal_k
& 0x3f;
2916 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n",
2917 efuse
->vendor_name
);
2918 dev_info(&priv
->udev
->dev
, "Product: %.41s\n",
2919 efuse
->device_name
);
2923 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv
*priv
)
2925 struct rtl8723bu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8723bu
;
2928 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
2931 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
2933 memcpy(priv
->cck_tx_power_index_A
, efuse
->tx_power_index_A
.cck_base
,
2934 sizeof(efuse
->tx_power_index_A
.cck_base
));
2935 memcpy(priv
->cck_tx_power_index_B
, efuse
->tx_power_index_B
.cck_base
,
2936 sizeof(efuse
->tx_power_index_B
.cck_base
));
2938 memcpy(priv
->ht40_1s_tx_power_index_A
,
2939 efuse
->tx_power_index_A
.ht40_base
,
2940 sizeof(efuse
->tx_power_index_A
.ht40_base
));
2941 memcpy(priv
->ht40_1s_tx_power_index_B
,
2942 efuse
->tx_power_index_B
.ht40_base
,
2943 sizeof(efuse
->tx_power_index_B
.ht40_base
));
2945 priv
->ofdm_tx_power_diff
[0].a
=
2946 efuse
->tx_power_index_A
.ht20_ofdm_1s_diff
.a
;
2947 priv
->ofdm_tx_power_diff
[0].b
=
2948 efuse
->tx_power_index_B
.ht20_ofdm_1s_diff
.a
;
2950 priv
->ht20_tx_power_diff
[0].a
=
2951 efuse
->tx_power_index_A
.ht20_ofdm_1s_diff
.b
;
2952 priv
->ht20_tx_power_diff
[0].b
=
2953 efuse
->tx_power_index_B
.ht20_ofdm_1s_diff
.b
;
2955 priv
->ht40_tx_power_diff
[0].a
= 0;
2956 priv
->ht40_tx_power_diff
[0].b
= 0;
2958 for (i
= 1; i
< RTL8723B_TX_COUNT
; i
++) {
2959 priv
->ofdm_tx_power_diff
[i
].a
=
2960 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ofdm
;
2961 priv
->ofdm_tx_power_diff
[i
].b
=
2962 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ofdm
;
2964 priv
->ht20_tx_power_diff
[i
].a
=
2965 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht20
;
2966 priv
->ht20_tx_power_diff
[i
].b
=
2967 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht20
;
2969 priv
->ht40_tx_power_diff
[i
].a
=
2970 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht40
;
2971 priv
->ht40_tx_power_diff
[i
].b
=
2972 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht40
;
2975 priv
->has_xtalk
= 1;
2976 priv
->xtalk
= priv
->efuse_wifi
.efuse8723bu
.xtal_k
& 0x3f;
2978 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n", efuse
->vendor_name
);
2979 dev_info(&priv
->udev
->dev
, "Product: %.41s\n", efuse
->device_name
);
2981 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
2983 unsigned char *raw
= priv
->efuse_wifi
.raw
;
2985 dev_info(&priv
->udev
->dev
,
2986 "%s: dumping efuse (0x%02zx bytes):\n",
2987 __func__
, sizeof(struct rtl8723bu_efuse
));
2988 for (i
= 0; i
< sizeof(struct rtl8723bu_efuse
); i
+= 8) {
2989 dev_info(&priv
->udev
->dev
, "%02x: "
2990 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
2991 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
2992 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
2993 raw
[i
+ 6], raw
[i
+ 7]);
3000 #ifdef CONFIG_RTL8XXXU_UNTESTED
3002 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv
*priv
)
3004 struct rtl8192cu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8192
;
3007 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
3010 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
3012 memcpy(priv
->cck_tx_power_index_A
,
3013 efuse
->cck_tx_power_index_A
,
3014 sizeof(efuse
->cck_tx_power_index_A
));
3015 memcpy(priv
->cck_tx_power_index_B
,
3016 efuse
->cck_tx_power_index_B
,
3017 sizeof(efuse
->cck_tx_power_index_B
));
3019 memcpy(priv
->ht40_1s_tx_power_index_A
,
3020 efuse
->ht40_1s_tx_power_index_A
,
3021 sizeof(efuse
->ht40_1s_tx_power_index_A
));
3022 memcpy(priv
->ht40_1s_tx_power_index_B
,
3023 efuse
->ht40_1s_tx_power_index_B
,
3024 sizeof(efuse
->ht40_1s_tx_power_index_B
));
3025 memcpy(priv
->ht40_2s_tx_power_index_diff
,
3026 efuse
->ht40_2s_tx_power_index_diff
,
3027 sizeof(efuse
->ht40_2s_tx_power_index_diff
));
3029 memcpy(priv
->ht20_tx_power_index_diff
,
3030 efuse
->ht20_tx_power_index_diff
,
3031 sizeof(efuse
->ht20_tx_power_index_diff
));
3032 memcpy(priv
->ofdm_tx_power_index_diff
,
3033 efuse
->ofdm_tx_power_index_diff
,
3034 sizeof(efuse
->ofdm_tx_power_index_diff
));
3036 memcpy(priv
->ht40_max_power_offset
,
3037 efuse
->ht40_max_power_offset
,
3038 sizeof(efuse
->ht40_max_power_offset
));
3039 memcpy(priv
->ht20_max_power_offset
,
3040 efuse
->ht20_max_power_offset
,
3041 sizeof(efuse
->ht20_max_power_offset
));
3043 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n",
3044 efuse
->vendor_name
);
3045 dev_info(&priv
->udev
->dev
, "Product: %.20s\n",
3046 efuse
->device_name
);
3048 if (efuse
->rf_regulatory
& 0x20) {
3049 sprintf(priv
->chip_name
, "8188RU");
3053 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
3054 unsigned char *raw
= priv
->efuse_wifi
.raw
;
3056 dev_info(&priv
->udev
->dev
,
3057 "%s: dumping efuse (0x%02zx bytes):\n",
3058 __func__
, sizeof(struct rtl8192cu_efuse
));
3059 for (i
= 0; i
< sizeof(struct rtl8192cu_efuse
); i
+= 8) {
3060 dev_info(&priv
->udev
->dev
, "%02x: "
3061 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
3062 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
3063 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
3064 raw
[i
+ 6], raw
[i
+ 7]);
3072 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv
*priv
)
3074 struct rtl8192eu_efuse
*efuse
= &priv
->efuse_wifi
.efuse8192eu
;
3077 if (efuse
->rtl_id
!= cpu_to_le16(0x8129))
3080 ether_addr_copy(priv
->mac_addr
, efuse
->mac_addr
);
3082 memcpy(priv
->cck_tx_power_index_A
, efuse
->tx_power_index_A
.cck_base
,
3083 sizeof(efuse
->tx_power_index_A
.cck_base
));
3084 memcpy(priv
->cck_tx_power_index_B
, efuse
->tx_power_index_B
.cck_base
,
3085 sizeof(efuse
->tx_power_index_B
.cck_base
));
3087 memcpy(priv
->ht40_1s_tx_power_index_A
,
3088 efuse
->tx_power_index_A
.ht40_base
,
3089 sizeof(efuse
->tx_power_index_A
.ht40_base
));
3090 memcpy(priv
->ht40_1s_tx_power_index_B
,
3091 efuse
->tx_power_index_B
.ht40_base
,
3092 sizeof(efuse
->tx_power_index_B
.ht40_base
));
3094 priv
->ht20_tx_power_diff
[0].a
=
3095 efuse
->tx_power_index_A
.ht20_ofdm_1s_diff
.b
;
3096 priv
->ht20_tx_power_diff
[0].b
=
3097 efuse
->tx_power_index_B
.ht20_ofdm_1s_diff
.b
;
3099 priv
->ht40_tx_power_diff
[0].a
= 0;
3100 priv
->ht40_tx_power_diff
[0].b
= 0;
3102 for (i
= 1; i
< RTL8723B_TX_COUNT
; i
++) {
3103 priv
->ofdm_tx_power_diff
[i
].a
=
3104 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ofdm
;
3105 priv
->ofdm_tx_power_diff
[i
].b
=
3106 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ofdm
;
3108 priv
->ht20_tx_power_diff
[i
].a
=
3109 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht20
;
3110 priv
->ht20_tx_power_diff
[i
].b
=
3111 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht20
;
3113 priv
->ht40_tx_power_diff
[i
].a
=
3114 efuse
->tx_power_index_A
.pwr_diff
[i
- 1].ht40
;
3115 priv
->ht40_tx_power_diff
[i
].b
=
3116 efuse
->tx_power_index_B
.pwr_diff
[i
- 1].ht40
;
3119 priv
->has_xtalk
= 1;
3120 priv
->xtalk
= priv
->efuse_wifi
.efuse8192eu
.xtal_k
& 0x3f;
3122 dev_info(&priv
->udev
->dev
, "Vendor: %.7s\n", efuse
->vendor_name
);
3123 dev_info(&priv
->udev
->dev
, "Product: %.11s\n", efuse
->device_name
);
3124 dev_info(&priv
->udev
->dev
, "Serial: %.11s\n", efuse
->serial
);
3126 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_EFUSE
) {
3127 unsigned char *raw
= priv
->efuse_wifi
.raw
;
3129 dev_info(&priv
->udev
->dev
,
3130 "%s: dumping efuse (0x%02zx bytes):\n",
3131 __func__
, sizeof(struct rtl8192eu_efuse
));
3132 for (i
= 0; i
< sizeof(struct rtl8192eu_efuse
); i
+= 8) {
3133 dev_info(&priv
->udev
->dev
, "%02x: "
3134 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i
,
3135 raw
[i
], raw
[i
+ 1], raw
[i
+ 2],
3136 raw
[i
+ 3], raw
[i
+ 4], raw
[i
+ 5],
3137 raw
[i
+ 6], raw
[i
+ 7]);
3141 * Temporarily disable 8192eu support
3148 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv
*priv
, u16 offset
, u8
*data
)
3155 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 1, offset
& 0xff);
3156 val8
= rtl8xxxu_read8(priv
, REG_EFUSE_CTRL
+ 2);
3158 val8
|= (offset
>> 8) & 0x03;
3159 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 2, val8
);
3161 val8
= rtl8xxxu_read8(priv
, REG_EFUSE_CTRL
+ 3);
3162 rtl8xxxu_write8(priv
, REG_EFUSE_CTRL
+ 3, val8
& 0x7f);
3164 /* Poll for data read */
3165 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
3166 for (i
= 0; i
< RTL8XXXU_MAX_REG_POLL
; i
++) {
3167 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
3168 if (val32
& BIT(31))
3172 if (i
== RTL8XXXU_MAX_REG_POLL
)
3176 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
3178 *data
= val32
& 0xff;
3182 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv
*priv
)
3184 struct device
*dev
= &priv
->udev
->dev
;
3186 u8 val8
, word_mask
, header
, extheader
;
3187 u16 val16
, efuse_addr
, offset
;
3190 val16
= rtl8xxxu_read16(priv
, REG_9346CR
);
3191 if (val16
& EEPROM_ENABLE
)
3192 priv
->has_eeprom
= 1;
3193 if (val16
& EEPROM_BOOT
)
3194 priv
->boot_eeprom
= 1;
3196 if (priv
->is_multi_func
) {
3197 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_TEST
);
3198 val32
= (val32
& ~EFUSE_SELECT_MASK
) | EFUSE_WIFI_SELECT
;
3199 rtl8xxxu_write32(priv
, REG_EFUSE_TEST
, val32
);
3202 dev_dbg(dev
, "Booting from %s\n",
3203 priv
->boot_eeprom
? "EEPROM" : "EFUSE");
3205 rtl8xxxu_write8(priv
, REG_EFUSE_ACCESS
, EFUSE_ACCESS_ENABLE
);
3207 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
3208 val16
= rtl8xxxu_read16(priv
, REG_SYS_ISO_CTRL
);
3209 if (!(val16
& SYS_ISO_PWC_EV12V
)) {
3210 val16
|= SYS_ISO_PWC_EV12V
;
3211 rtl8xxxu_write16(priv
, REG_SYS_ISO_CTRL
, val16
);
3213 /* Reset: 0x0000[28], default valid */
3214 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3215 if (!(val16
& SYS_FUNC_ELDR
)) {
3216 val16
|= SYS_FUNC_ELDR
;
3217 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3221 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
3223 val16
= rtl8xxxu_read16(priv
, REG_SYS_CLKR
);
3224 if (!(val16
& SYS_CLK_LOADER_ENABLE
) || !(val16
& SYS_CLK_ANA8M
)) {
3225 val16
|= (SYS_CLK_LOADER_ENABLE
| SYS_CLK_ANA8M
);
3226 rtl8xxxu_write16(priv
, REG_SYS_CLKR
, val16
);
3229 /* Default value is 0xff */
3230 memset(priv
->efuse_wifi
.raw
, 0xff, EFUSE_MAP_LEN
);
3233 while (efuse_addr
< EFUSE_REAL_CONTENT_LEN_8723A
) {
3236 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &header
);
3237 if (ret
|| header
== 0xff)
3240 if ((header
& 0x1f) == 0x0f) { /* extended header */
3241 offset
= (header
& 0xe0) >> 5;
3243 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++,
3247 /* All words disabled */
3248 if ((extheader
& 0x0f) == 0x0f)
3251 offset
|= ((extheader
& 0xf0) >> 1);
3252 word_mask
= extheader
& 0x0f;
3254 offset
= (header
>> 4) & 0x0f;
3255 word_mask
= header
& 0x0f;
3258 /* Get word enable value from PG header */
3260 /* We have 8 bits to indicate validity */
3261 map_addr
= offset
* 8;
3262 if (map_addr
>= EFUSE_MAP_LEN
) {
3263 dev_warn(dev
, "%s: Illegal map_addr (%04x), "
3265 __func__
, map_addr
);
3269 for (i
= 0; i
< EFUSE_MAX_WORD_UNIT
; i
++) {
3270 /* Check word enable condition in the section */
3271 if (word_mask
& BIT(i
)) {
3276 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &val8
);
3279 priv
->efuse_wifi
.raw
[map_addr
++] = val8
;
3281 ret
= rtl8xxxu_read_efuse8(priv
, efuse_addr
++, &val8
);
3284 priv
->efuse_wifi
.raw
[map_addr
++] = val8
;
3289 rtl8xxxu_write8(priv
, REG_EFUSE_ACCESS
, EFUSE_ACCESS_DISABLE
);
3294 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv
*priv
)
3299 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
3301 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
3303 sys_func
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3304 sys_func
&= ~SYS_FUNC_CPU_ENABLE
;
3305 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
3307 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
3309 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
3311 sys_func
|= SYS_FUNC_CPU_ENABLE
;
3312 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
3315 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv
*priv
)
3320 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
);
3322 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, val8
);
3324 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
3326 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
3328 sys_func
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3329 sys_func
&= ~SYS_FUNC_CPU_ENABLE
;
3330 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
3332 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
);
3334 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, val8
);
3336 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
3338 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
3340 sys_func
|= SYS_FUNC_CPU_ENABLE
;
3341 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, sys_func
);
3344 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv
*priv
)
3346 struct device
*dev
= &priv
->udev
->dev
;
3350 /* Poll checksum report */
3351 for (i
= 0; i
< RTL8XXXU_FIRMWARE_POLL_MAX
; i
++) {
3352 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
3353 if (val32
& MCU_FW_DL_CSUM_REPORT
)
3357 if (i
== RTL8XXXU_FIRMWARE_POLL_MAX
) {
3358 dev_warn(dev
, "Firmware checksum poll timed out\n");
3363 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
3364 val32
|= MCU_FW_DL_READY
;
3365 val32
&= ~MCU_WINT_INIT_READY
;
3366 rtl8xxxu_write32(priv
, REG_MCU_FW_DL
, val32
);
3369 * Reset the 8051 in order for the firmware to start running,
3370 * otherwise it won't come up on the 8192eu
3372 priv
->fops
->reset_8051(priv
);
3374 /* Wait for firmware to become ready */
3375 for (i
= 0; i
< RTL8XXXU_FIRMWARE_POLL_MAX
; i
++) {
3376 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
3377 if (val32
& MCU_WINT_INIT_READY
)
3383 if (i
== RTL8XXXU_FIRMWARE_POLL_MAX
) {
3384 dev_warn(dev
, "Firmware failed to start\n");
3392 if (priv
->rtl_chip
== RTL8723B
)
3393 rtl8xxxu_write8(priv
, REG_HMTFR
, 0x0f);
3398 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv
*priv
)
3400 int pages
, remainder
, i
, ret
;
3406 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
+ 1);
3408 rtl8xxxu_write8(priv
, REG_SYS_FUNC
+ 1, val8
);
3411 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3412 val16
|= SYS_FUNC_CPU_ENABLE
;
3413 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3415 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
3416 if (val8
& MCU_FW_RAM_SEL
) {
3417 pr_info("do the RAM reset\n");
3418 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
3419 priv
->fops
->reset_8051(priv
);
3422 /* MCU firmware download enable */
3423 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
3424 val8
|= MCU_FW_DL_ENABLE
;
3425 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, val8
);
3428 val32
= rtl8xxxu_read32(priv
, REG_MCU_FW_DL
);
3430 rtl8xxxu_write32(priv
, REG_MCU_FW_DL
, val32
);
3432 /* Reset firmware download checksum */
3433 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
);
3434 val8
|= MCU_FW_DL_CSUM_REPORT
;
3435 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, val8
);
3437 pages
= priv
->fw_size
/ RTL_FW_PAGE_SIZE
;
3438 remainder
= priv
->fw_size
% RTL_FW_PAGE_SIZE
;
3440 fwptr
= priv
->fw_data
->data
;
3442 for (i
= 0; i
< pages
; i
++) {
3443 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
+ 2) & 0xF8;
3445 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
+ 2, val8
);
3447 ret
= rtl8xxxu_writeN(priv
, REG_FW_START_ADDRESS
,
3448 fwptr
, RTL_FW_PAGE_SIZE
);
3449 if (ret
!= RTL_FW_PAGE_SIZE
) {
3454 fwptr
+= RTL_FW_PAGE_SIZE
;
3458 val8
= rtl8xxxu_read8(priv
, REG_MCU_FW_DL
+ 2) & 0xF8;
3460 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
+ 2, val8
);
3461 ret
= rtl8xxxu_writeN(priv
, REG_FW_START_ADDRESS
,
3463 if (ret
!= remainder
) {
3471 /* MCU firmware download disable */
3472 val16
= rtl8xxxu_read16(priv
, REG_MCU_FW_DL
);
3473 val16
&= ~MCU_FW_DL_ENABLE
;
3474 rtl8xxxu_write16(priv
, REG_MCU_FW_DL
, val16
);
3479 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv
*priv
, char *fw_name
)
3481 struct device
*dev
= &priv
->udev
->dev
;
3482 const struct firmware
*fw
;
3486 dev_info(dev
, "%s: Loading firmware %s\n", DRIVER_NAME
, fw_name
);
3487 if (request_firmware(&fw
, fw_name
, &priv
->udev
->dev
)) {
3488 dev_warn(dev
, "request_firmware(%s) failed\n", fw_name
);
3493 dev_warn(dev
, "Firmware data not available\n");
3498 priv
->fw_data
= kmemdup(fw
->data
, fw
->size
, GFP_KERNEL
);
3499 if (!priv
->fw_data
) {
3503 priv
->fw_size
= fw
->size
- sizeof(struct rtl8xxxu_firmware_header
);
3505 signature
= le16_to_cpu(priv
->fw_data
->signature
);
3506 switch (signature
& 0xfff0) {
3515 dev_warn(dev
, "%s: Invalid firmware signature: 0x%04x\n",
3516 __func__
, signature
);
3519 dev_info(dev
, "Firmware revision %i.%i (signature 0x%04x)\n",
3520 le16_to_cpu(priv
->fw_data
->major_version
),
3521 priv
->fw_data
->minor_version
, signature
);
3524 release_firmware(fw
);
3528 static int rtl8723au_load_firmware(struct rtl8xxxu_priv
*priv
)
3533 switch (priv
->chip_cut
) {
3535 fw_name
= "rtlwifi/rtl8723aufw_A.bin";
3538 if (priv
->enable_bluetooth
)
3539 fw_name
= "rtlwifi/rtl8723aufw_B.bin";
3541 fw_name
= "rtlwifi/rtl8723aufw_B_NoBT.bin";
3548 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
3552 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv
*priv
)
3557 if (priv
->enable_bluetooth
)
3558 fw_name
= "rtlwifi/rtl8723bu_bt.bin";
3560 fw_name
= "rtlwifi/rtl8723bu_nic.bin";
3562 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
3566 #ifdef CONFIG_RTL8XXXU_UNTESTED
3568 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv
*priv
)
3573 if (!priv
->vendor_umc
)
3574 fw_name
= "rtlwifi/rtl8192cufw_TMSC.bin";
3575 else if (priv
->chip_cut
|| priv
->rtl_chip
== RTL8192C
)
3576 fw_name
= "rtlwifi/rtl8192cufw_B.bin";
3578 fw_name
= "rtlwifi/rtl8192cufw_A.bin";
3580 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
3587 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv
*priv
)
3592 fw_name
= "rtlwifi/rtl8192eu_nic.bin";
3594 ret
= rtl8xxxu_load_firmware(priv
, fw_name
);
3599 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv
*priv
)
3604 /* Inform 8051 to perform reset */
3605 rtl8xxxu_write8(priv
, REG_HMTFR
+ 3, 0x20);
3607 for (i
= 100; i
> 0; i
--) {
3608 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3610 if (!(val16
& SYS_FUNC_CPU_ENABLE
)) {
3611 dev_dbg(&priv
->udev
->dev
,
3612 "%s: Firmware self reset success!\n", __func__
);
3619 /* Force firmware reset */
3620 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3621 val16
&= ~SYS_FUNC_CPU_ENABLE
;
3622 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3626 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv
*priv
)
3630 val32
= rtl8xxxu_read32(priv
, REG_PAD_CTRL1
);
3631 val32
&= ~(BIT(20) | BIT(24));
3632 rtl8xxxu_write32(priv
, REG_PAD_CTRL1
, val32
);
3634 val32
= rtl8xxxu_read32(priv
, REG_GPIO_MUXCFG
);
3636 rtl8xxxu_write32(priv
, REG_GPIO_MUXCFG
, val32
);
3638 val32
= rtl8xxxu_read32(priv
, REG_GPIO_MUXCFG
);
3640 rtl8xxxu_write32(priv
, REG_GPIO_MUXCFG
, val32
);
3642 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
3644 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
3646 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
3648 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
3650 val32
= rtl8xxxu_read32(priv
, REG_RFE_BUFFER
);
3651 val32
|= (BIT(0) | BIT(1));
3652 rtl8xxxu_write32(priv
, REG_RFE_BUFFER
, val32
);
3654 val32
= rtl8xxxu_read32(priv
, REG_RFE_CTRL_ANTA_SRC
);
3655 val32
&= 0xffffff00;
3657 rtl8xxxu_write32(priv
, REG_RFE_CTRL_ANTA_SRC
, val32
);
3659 val32
= rtl8xxxu_read32(priv
, REG_PWR_DATA
);
3660 val32
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
3661 rtl8xxxu_write32(priv
, REG_PWR_DATA
, val32
);
3665 rtl8xxxu_init_mac(struct rtl8xxxu_priv
*priv
)
3667 struct rtl8xxxu_reg8val
*array
= priv
->fops
->mactable
;
3672 for (i
= 0; ; i
++) {
3676 if (reg
== 0xffff && val
== 0xff)
3679 ret
= rtl8xxxu_write8(priv
, reg
, val
);
3681 dev_warn(&priv
->udev
->dev
,
3682 "Failed to initialize MAC "
3683 "(reg: %04x, val %02x)\n", reg
, val
);
3688 if (priv
->rtl_chip
!= RTL8723B
&& priv
->rtl_chip
!= RTL8192E
)
3689 rtl8xxxu_write8(priv
, REG_MAX_AGGR_NUM
, 0x0a);
3694 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv
*priv
,
3695 struct rtl8xxxu_reg32val
*array
)
3701 for (i
= 0; ; i
++) {
3705 if (reg
== 0xffff && val
== 0xffffffff)
3708 ret
= rtl8xxxu_write32(priv
, reg
, val
);
3709 if (ret
!= sizeof(val
)) {
3710 dev_warn(&priv
->udev
->dev
,
3711 "Failed to initialize PHY\n");
3720 static void rtl8723au_init_phy_bb(struct rtl8xxxu_priv
*priv
)
3722 u8 val8
, ldoa15
, ldov12d
, lpldo
, ldohci12
;
3726 val8
= rtl8xxxu_read8(priv
, REG_AFE_PLL_CTRL
);
3728 val8
|= AFE_PLL_320_ENABLE
;
3729 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
, val8
);
3732 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
+ 1, 0xff);
3735 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3736 val16
|= SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
;
3737 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3739 val32
= rtl8xxxu_read32(priv
, REG_AFE_XTAL_CTRL
);
3740 val32
&= ~AFE_XTAL_RF_GATE
;
3741 if (priv
->has_bluetooth
)
3742 val32
&= ~AFE_XTAL_BT_GATE
;
3743 rtl8xxxu_write32(priv
, REG_AFE_XTAL_CTRL
, val32
);
3745 /* 6. 0x1f[7:0] = 0x07 */
3746 val8
= RF_ENABLE
| RF_RSTB
| RF_SDMRSTB
;
3747 rtl8xxxu_write8(priv
, REG_RF_CTRL
, val8
);
3750 rtl8xxxu_init_phy_regs(priv
, rtl8188ru_phy_1t_highpa_table
);
3751 else if (priv
->tx_paths
== 2)
3752 rtl8xxxu_init_phy_regs(priv
, rtl8192cu_phy_2t_init_table
);
3754 rtl8xxxu_init_phy_regs(priv
, rtl8723a_phy_1t_init_table
);
3756 if (priv
->rtl_chip
== RTL8188C
&& priv
->hi_pa
&&
3757 priv
->vendor_umc
&& priv
->chip_cut
== 1)
3758 rtl8xxxu_write8(priv
, REG_OFDM0_AGC_PARM1
+ 2, 0x50);
3761 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_highpa_table
);
3763 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_standard_table
);
3765 ldoa15
= LDOA15_ENABLE
| LDOA15_OBUF
;
3766 ldov12d
= LDOV12D_ENABLE
| BIT(2) | (2 << LDOV12D_VADJ_SHIFT
);
3769 val32
= (lpldo
<< 24) | (ldohci12
<< 16) | (ldov12d
<< 8) | ldoa15
;
3770 rtl8xxxu_write32(priv
, REG_LDOA15_CTRL
, val32
);
3773 static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv
*priv
)
3778 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3779 val16
|= SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
| SYS_FUNC_DIO_RF
;
3780 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3782 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
3784 /* 6. 0x1f[7:0] = 0x07 */
3785 val8
= RF_ENABLE
| RF_RSTB
| RF_SDMRSTB
;
3786 rtl8xxxu_write8(priv
, REG_RF_CTRL
, val8
);
3789 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, 0xe3);
3790 rtl8xxxu_write8(priv
, REG_AFE_XTAL_CTRL
+ 1, 0x80);
3791 rtl8xxxu_init_phy_regs(priv
, rtl8723b_phy_1t_init_table
);
3793 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_8723bu_table
);
3796 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv
*priv
)
3801 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3802 val16
|= SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
| SYS_FUNC_DIO_RF
;
3803 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3805 /* 6. 0x1f[7:0] = 0x07 */
3806 val8
= RF_ENABLE
| RF_RSTB
| RF_SDMRSTB
;
3807 rtl8xxxu_write8(priv
, REG_RF_CTRL
, val8
);
3809 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
3810 val16
|= (SYS_FUNC_USBA
| SYS_FUNC_USBD
| SYS_FUNC_DIO_RF
|
3811 SYS_FUNC_BB_GLB_RSTN
| SYS_FUNC_BBRSTB
);
3812 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
3813 val8
= RF_ENABLE
| RF_RSTB
| RF_SDMRSTB
;
3814 rtl8xxxu_write8(priv
, REG_RF_CTRL
, val8
);
3815 rtl8xxxu_init_phy_regs(priv
, rtl8192eu_phy_init_table
);
3818 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_8192eu_highpa_table
);
3820 rtl8xxxu_init_phy_regs(priv
, rtl8xxx_agc_8192eu_std_table
);
3824 * Most of this is black magic retrieved from the old rtl8723au driver
3826 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv
*priv
)
3831 priv
->fops
->init_phy_bb(priv
);
3833 if (priv
->tx_paths
== 1 && priv
->rx_paths
== 2) {
3835 * For 1T2R boards, patch the registers.
3837 * It looks like 8191/2 1T2R boards use path B for TX
3839 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_TX_INFO
);
3840 val32
&= ~(BIT(0) | BIT(1));
3842 rtl8xxxu_write32(priv
, REG_FPGA0_TX_INFO
, val32
);
3844 val32
= rtl8xxxu_read32(priv
, REG_FPGA1_TX_INFO
);
3847 rtl8xxxu_write32(priv
, REG_FPGA1_TX_INFO
, val32
);
3849 val32
= rtl8xxxu_read32(priv
, REG_CCK0_AFE_SETTING
);
3850 val32
&= ~CCK0_AFE_RX_MASK
;
3851 val32
&= 0x00ffffff;
3852 val32
|= 0x40000000;
3853 val32
|= CCK0_AFE_RX_ANT_B
;
3854 rtl8xxxu_write32(priv
, REG_CCK0_AFE_SETTING
, val32
);
3856 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_TRX_PATH_ENABLE
);
3857 val32
&= ~(OFDM_RF_PATH_RX_MASK
| OFDM_RF_PATH_TX_MASK
);
3858 val32
|= (OFDM_RF_PATH_RX_A
| OFDM_RF_PATH_RX_B
|
3860 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, val32
);
3862 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_AGC_PARM1
);
3863 val32
&= ~(BIT(4) | BIT(5));
3865 rtl8xxxu_write32(priv
, REG_OFDM0_AGC_PARM1
, val32
);
3867 val32
= rtl8xxxu_read32(priv
, REG_TX_CCK_RFON
);
3868 val32
&= ~(BIT(27) | BIT(26));
3870 rtl8xxxu_write32(priv
, REG_TX_CCK_RFON
, val32
);
3872 val32
= rtl8xxxu_read32(priv
, REG_TX_CCK_BBON
);
3873 val32
&= ~(BIT(27) | BIT(26));
3875 rtl8xxxu_write32(priv
, REG_TX_CCK_BBON
, val32
);
3877 val32
= rtl8xxxu_read32(priv
, REG_TX_OFDM_RFON
);
3878 val32
&= ~(BIT(27) | BIT(26));
3880 rtl8xxxu_write32(priv
, REG_TX_OFDM_RFON
, val32
);
3882 val32
= rtl8xxxu_read32(priv
, REG_TX_OFDM_BBON
);
3883 val32
&= ~(BIT(27) | BIT(26));
3885 rtl8xxxu_write32(priv
, REG_TX_OFDM_BBON
, val32
);
3887 val32
= rtl8xxxu_read32(priv
, REG_TX_TO_TX
);
3888 val32
&= ~(BIT(27) | BIT(26));
3890 rtl8xxxu_write32(priv
, REG_TX_TO_TX
, val32
);
3893 if (priv
->has_xtalk
) {
3894 val32
= rtl8xxxu_read32(priv
, REG_MAC_PHY_CTRL
);
3897 val32
&= 0xff000fff;
3898 val32
|= ((val8
| (val8
<< 6)) << 12);
3900 rtl8xxxu_write32(priv
, REG_MAC_PHY_CTRL
, val32
);
3903 if (priv
->rtl_chip
== RTL8192E
)
3904 rtl8xxxu_write32(priv
, REG_AFE_XTAL_CTRL
, 0x000f81fb);
3909 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv
*priv
,
3910 struct rtl8xxxu_rfregval
*array
,
3911 enum rtl8xxxu_rfpath path
)
3917 for (i
= 0; ; i
++) {
3921 if (reg
== 0xff && val
== 0xffffffff)
3945 ret
= rtl8xxxu_write_rfreg(priv
, path
, reg
, val
);
3947 dev_warn(&priv
->udev
->dev
,
3948 "Failed to initialize RF\n");
3957 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv
*priv
,
3958 struct rtl8xxxu_rfregval
*table
,
3959 enum rtl8xxxu_rfpath path
)
3962 u16 val16
, rfsi_rfenv
;
3963 u16 reg_sw_ctrl
, reg_int_oe
, reg_hssi_parm2
;
3967 reg_sw_ctrl
= REG_FPGA0_XA_RF_SW_CTRL
;
3968 reg_int_oe
= REG_FPGA0_XA_RF_INT_OE
;
3969 reg_hssi_parm2
= REG_FPGA0_XA_HSSI_PARM2
;
3972 reg_sw_ctrl
= REG_FPGA0_XB_RF_SW_CTRL
;
3973 reg_int_oe
= REG_FPGA0_XB_RF_INT_OE
;
3974 reg_hssi_parm2
= REG_FPGA0_XB_HSSI_PARM2
;
3977 dev_err(&priv
->udev
->dev
, "%s:Unsupported RF path %c\n",
3978 __func__
, path
+ 'A');
3981 /* For path B, use XB */
3982 rfsi_rfenv
= rtl8xxxu_read16(priv
, reg_sw_ctrl
);
3983 rfsi_rfenv
&= FPGA0_RF_RFENV
;
3986 * These two we might be able to optimize into one
3988 val32
= rtl8xxxu_read32(priv
, reg_int_oe
);
3989 val32
|= BIT(20); /* 0x10 << 16 */
3990 rtl8xxxu_write32(priv
, reg_int_oe
, val32
);
3993 val32
= rtl8xxxu_read32(priv
, reg_int_oe
);
3995 rtl8xxxu_write32(priv
, reg_int_oe
, val32
);
3999 * These two we might be able to optimize into one
4001 val32
= rtl8xxxu_read32(priv
, reg_hssi_parm2
);
4002 val32
&= ~FPGA0_HSSI_3WIRE_ADDR_LEN
;
4003 rtl8xxxu_write32(priv
, reg_hssi_parm2
, val32
);
4006 val32
= rtl8xxxu_read32(priv
, reg_hssi_parm2
);
4007 val32
&= ~FPGA0_HSSI_3WIRE_DATA_LEN
;
4008 rtl8xxxu_write32(priv
, reg_hssi_parm2
, val32
);
4011 rtl8xxxu_init_rf_regs(priv
, table
, path
);
4013 /* For path B, use XB */
4014 val16
= rtl8xxxu_read16(priv
, reg_sw_ctrl
);
4015 val16
&= ~FPGA0_RF_RFENV
;
4016 val16
|= rfsi_rfenv
;
4017 rtl8xxxu_write16(priv
, reg_sw_ctrl
, val16
);
4022 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv
*priv
, u8 address
, u8 data
)
4028 value
= LLT_OP_WRITE
| address
<< 8 | data
;
4030 rtl8xxxu_write32(priv
, REG_LLT_INIT
, value
);
4033 value
= rtl8xxxu_read32(priv
, REG_LLT_INIT
);
4034 if ((value
& LLT_OP_MASK
) == LLT_OP_INACTIVE
) {
4038 } while (count
++ < 20);
4043 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv
*priv
, u8 last_tx_page
)
4048 for (i
= 0; i
< last_tx_page
; i
++) {
4049 ret
= rtl8xxxu_llt_write(priv
, i
, i
+ 1);
4054 ret
= rtl8xxxu_llt_write(priv
, last_tx_page
, 0xff);
4058 /* Mark remaining pages as a ring buffer */
4059 for (i
= last_tx_page
+ 1; i
< 0xff; i
++) {
4060 ret
= rtl8xxxu_llt_write(priv
, i
, (i
+ 1));
4065 /* Let last entry point to the start entry of ring buffer */
4066 ret
= rtl8xxxu_llt_write(priv
, 0xff, last_tx_page
+ 1);
4074 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv
*priv
, u8 last_tx_page
)
4080 val32
= rtl8xxxu_read32(priv
, REG_AUTO_LLT
);
4081 val32
|= AUTO_LLT_INIT_LLT
;
4082 rtl8xxxu_write32(priv
, REG_AUTO_LLT
, val32
);
4084 for (i
= 500; i
; i
--) {
4085 val32
= rtl8xxxu_read32(priv
, REG_AUTO_LLT
);
4086 if (!(val32
& AUTO_LLT_INIT_LLT
))
4093 dev_warn(&priv
->udev
->dev
, "LLT table init failed\n");
4099 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv
*priv
)
4102 u16 hiq
, mgq
, bkq
, beq
, viq
, voq
;
4103 int hip
, mgp
, bkp
, bep
, vip
, vop
;
4106 switch (priv
->ep_tx_count
) {
4108 if (priv
->ep_tx_high_queue
) {
4109 hi
= TRXDMA_QUEUE_HIGH
;
4110 } else if (priv
->ep_tx_low_queue
) {
4111 hi
= TRXDMA_QUEUE_LOW
;
4112 } else if (priv
->ep_tx_normal_queue
) {
4113 hi
= TRXDMA_QUEUE_NORMAL
;
4134 if (priv
->ep_tx_high_queue
&& priv
->ep_tx_low_queue
) {
4135 hi
= TRXDMA_QUEUE_HIGH
;
4136 lo
= TRXDMA_QUEUE_LOW
;
4137 } else if (priv
->ep_tx_normal_queue
&& priv
->ep_tx_low_queue
) {
4138 hi
= TRXDMA_QUEUE_NORMAL
;
4139 lo
= TRXDMA_QUEUE_LOW
;
4140 } else if (priv
->ep_tx_high_queue
&& priv
->ep_tx_normal_queue
) {
4141 hi
= TRXDMA_QUEUE_HIGH
;
4142 lo
= TRXDMA_QUEUE_NORMAL
;
4164 beq
= TRXDMA_QUEUE_LOW
;
4165 bkq
= TRXDMA_QUEUE_LOW
;
4166 viq
= TRXDMA_QUEUE_NORMAL
;
4167 voq
= TRXDMA_QUEUE_HIGH
;
4168 mgq
= TRXDMA_QUEUE_HIGH
;
4169 hiq
= TRXDMA_QUEUE_HIGH
;
4183 * None of the vendor drivers are configuring the beacon
4184 * queue here .... why?
4187 val16
= rtl8xxxu_read16(priv
, REG_TRXDMA_CTRL
);
4189 val16
|= (voq
<< TRXDMA_CTRL_VOQ_SHIFT
) |
4190 (viq
<< TRXDMA_CTRL_VIQ_SHIFT
) |
4191 (beq
<< TRXDMA_CTRL_BEQ_SHIFT
) |
4192 (bkq
<< TRXDMA_CTRL_BKQ_SHIFT
) |
4193 (mgq
<< TRXDMA_CTRL_MGQ_SHIFT
) |
4194 (hiq
<< TRXDMA_CTRL_HIQ_SHIFT
);
4195 rtl8xxxu_write16(priv
, REG_TRXDMA_CTRL
, val16
);
4197 priv
->pipe_out
[TXDESC_QUEUE_VO
] =
4198 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[vop
]);
4199 priv
->pipe_out
[TXDESC_QUEUE_VI
] =
4200 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[vip
]);
4201 priv
->pipe_out
[TXDESC_QUEUE_BE
] =
4202 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[bep
]);
4203 priv
->pipe_out
[TXDESC_QUEUE_BK
] =
4204 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[bkp
]);
4205 priv
->pipe_out
[TXDESC_QUEUE_BEACON
] =
4206 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[0]);
4207 priv
->pipe_out
[TXDESC_QUEUE_MGNT
] =
4208 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[mgp
]);
4209 priv
->pipe_out
[TXDESC_QUEUE_HIGH
] =
4210 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[hip
]);
4211 priv
->pipe_out
[TXDESC_QUEUE_CMD
] =
4212 usb_sndbulkpipe(priv
->udev
, priv
->out_ep
[0]);
4218 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv
*priv
,
4219 bool iqk_ok
, int result
[][8],
4220 int candidate
, bool tx_only
)
4222 u32 oldval
, x
, tx0_a
, reg
;
4229 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
4230 oldval
= val32
>> 22;
4232 x
= result
[candidate
][0];
4233 if ((x
& 0x00000200) != 0)
4235 tx0_a
= (x
* oldval
) >> 8;
4237 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
4240 rtl8xxxu_write32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
, val32
);
4242 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
4244 if ((x
* oldval
>> 7) & 0x1)
4246 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
4248 y
= result
[candidate
][1];
4249 if ((y
& 0x00000200) != 0)
4251 tx0_c
= (y
* oldval
) >> 8;
4253 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XC_TX_AFE
);
4254 val32
&= ~0xf0000000;
4255 val32
|= (((tx0_c
& 0x3c0) >> 6) << 28);
4256 rtl8xxxu_write32(priv
, REG_OFDM0_XC_TX_AFE
, val32
);
4258 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
);
4259 val32
&= ~0x003f0000;
4260 val32
|= ((tx0_c
& 0x3f) << 16);
4261 rtl8xxxu_write32(priv
, REG_OFDM0_XA_TX_IQ_IMBALANCE
, val32
);
4263 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
4265 if ((y
* oldval
>> 7) & 0x1)
4267 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
4270 dev_dbg(&priv
->udev
->dev
, "%s: only TX\n", __func__
);
4274 reg
= result
[candidate
][2];
4276 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
);
4278 val32
|= (reg
& 0x3ff);
4279 rtl8xxxu_write32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
, val32
);
4281 reg
= result
[candidate
][3] & 0x3F;
4283 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
);
4285 val32
|= ((reg
<< 10) & 0xfc00);
4286 rtl8xxxu_write32(priv
, REG_OFDM0_XA_RX_IQ_IMBALANCE
, val32
);
4288 reg
= (result
[candidate
][3] >> 6) & 0xF;
4290 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_RX_IQ_EXT_ANTA
);
4291 val32
&= ~0xf0000000;
4292 val32
|= (reg
<< 28);
4293 rtl8xxxu_write32(priv
, REG_OFDM0_RX_IQ_EXT_ANTA
, val32
);
4296 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv
*priv
,
4297 bool iqk_ok
, int result
[][8],
4298 int candidate
, bool tx_only
)
4300 u32 oldval
, x
, tx1_a
, reg
;
4307 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
4308 oldval
= val32
>> 22;
4310 x
= result
[candidate
][4];
4311 if ((x
& 0x00000200) != 0)
4313 tx1_a
= (x
* oldval
) >> 8;
4315 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
4318 rtl8xxxu_write32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
, val32
);
4320 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
4322 if ((x
* oldval
>> 7) & 0x1)
4324 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
4326 y
= result
[candidate
][5];
4327 if ((y
& 0x00000200) != 0)
4329 tx1_c
= (y
* oldval
) >> 8;
4331 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XD_TX_AFE
);
4332 val32
&= ~0xf0000000;
4333 val32
|= (((tx1_c
& 0x3c0) >> 6) << 28);
4334 rtl8xxxu_write32(priv
, REG_OFDM0_XD_TX_AFE
, val32
);
4336 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
);
4337 val32
&= ~0x003f0000;
4338 val32
|= ((tx1_c
& 0x3f) << 16);
4339 rtl8xxxu_write32(priv
, REG_OFDM0_XB_TX_IQ_IMBALANCE
, val32
);
4341 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_ENERGY_CCA_THRES
);
4343 if ((y
* oldval
>> 7) & 0x1)
4345 rtl8xxxu_write32(priv
, REG_OFDM0_ENERGY_CCA_THRES
, val32
);
4348 dev_dbg(&priv
->udev
->dev
, "%s: only TX\n", __func__
);
4352 reg
= result
[candidate
][6];
4354 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
);
4356 val32
|= (reg
& 0x3ff);
4357 rtl8xxxu_write32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
, val32
);
4359 reg
= result
[candidate
][7] & 0x3f;
4361 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
);
4363 val32
|= ((reg
<< 10) & 0xfc00);
4364 rtl8xxxu_write32(priv
, REG_OFDM0_XB_RX_IQ_IMBALANCE
, val32
);
4366 reg
= (result
[candidate
][7] >> 6) & 0xf;
4368 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_AGCR_SSI_TABLE
);
4369 val32
&= ~0x0000f000;
4370 val32
|= (reg
<< 12);
4371 rtl8xxxu_write32(priv
, REG_OFDM0_AGCR_SSI_TABLE
, val32
);
4374 #define MAX_TOLERANCE 5
4376 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv
*priv
,
4377 int result
[][8], int c1
, int c2
)
4379 u32 i
, j
, diff
, simubitmap
, bound
= 0;
4380 int candidate
[2] = {-1, -1}; /* for path A and path B */
4383 if (priv
->tx_paths
> 1)
4390 for (i
= 0; i
< bound
; i
++) {
4391 diff
= (result
[c1
][i
] > result
[c2
][i
]) ?
4392 (result
[c1
][i
] - result
[c2
][i
]) :
4393 (result
[c2
][i
] - result
[c1
][i
]);
4394 if (diff
> MAX_TOLERANCE
) {
4395 if ((i
== 2 || i
== 6) && !simubitmap
) {
4396 if (result
[c1
][i
] + result
[c1
][i
+ 1] == 0)
4397 candidate
[(i
/ 4)] = c2
;
4398 else if (result
[c2
][i
] + result
[c2
][i
+ 1] == 0)
4399 candidate
[(i
/ 4)] = c1
;
4401 simubitmap
= simubitmap
| (1 << i
);
4403 simubitmap
= simubitmap
| (1 << i
);
4408 if (simubitmap
== 0) {
4409 for (i
= 0; i
< (bound
/ 4); i
++) {
4410 if (candidate
[i
] >= 0) {
4411 for (j
= i
* 4; j
< (i
+ 1) * 4 - 2; j
++)
4412 result
[3][j
] = result
[candidate
[i
]][j
];
4417 } else if (!(simubitmap
& 0x0f)) {
4419 for (i
= 0; i
< 4; i
++)
4420 result
[3][i
] = result
[c1
][i
];
4421 } else if (!(simubitmap
& 0xf0) && priv
->tx_paths
> 1) {
4423 for (i
= 4; i
< 8; i
++)
4424 result
[3][i
] = result
[c1
][i
];
4430 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv
*priv
,
4431 int result
[][8], int c1
, int c2
)
4433 u32 i
, j
, diff
, simubitmap
, bound
= 0;
4434 int candidate
[2] = {-1, -1}; /* for path A and path B */
4438 if (priv
->tx_paths
> 1)
4445 for (i
= 0; i
< bound
; i
++) {
4447 if ((result
[c1
][i
] & 0x00000200))
4448 tmp1
= result
[c1
][i
] | 0xfffffc00;
4450 tmp1
= result
[c1
][i
];
4452 if ((result
[c2
][i
]& 0x00000200))
4453 tmp2
= result
[c2
][i
] | 0xfffffc00;
4455 tmp2
= result
[c2
][i
];
4457 tmp1
= result
[c1
][i
];
4458 tmp2
= result
[c2
][i
];
4461 diff
= (tmp1
> tmp2
) ? (tmp1
- tmp2
) : (tmp2
- tmp1
);
4463 if (diff
> MAX_TOLERANCE
) {
4464 if ((i
== 2 || i
== 6) && !simubitmap
) {
4465 if (result
[c1
][i
] + result
[c1
][i
+ 1] == 0)
4466 candidate
[(i
/ 4)] = c2
;
4467 else if (result
[c2
][i
] + result
[c2
][i
+ 1] == 0)
4468 candidate
[(i
/ 4)] = c1
;
4470 simubitmap
= simubitmap
| (1 << i
);
4472 simubitmap
= simubitmap
| (1 << i
);
4477 if (simubitmap
== 0) {
4478 for (i
= 0; i
< (bound
/ 4); i
++) {
4479 if (candidate
[i
] >= 0) {
4480 for (j
= i
* 4; j
< (i
+ 1) * 4 - 2; j
++)
4481 result
[3][j
] = result
[candidate
[i
]][j
];
4487 if (!(simubitmap
& 0x03)) {
4489 for (i
= 0; i
< 2; i
++)
4490 result
[3][i
] = result
[c1
][i
];
4493 if (!(simubitmap
& 0x0c)) {
4495 for (i
= 2; i
< 4; i
++)
4496 result
[3][i
] = result
[c1
][i
];
4499 if (!(simubitmap
& 0x30) && priv
->tx_paths
> 1) {
4501 for (i
= 4; i
< 6; i
++)
4502 result
[3][i
] = result
[c1
][i
];
4505 if (!(simubitmap
& 0x30) && priv
->tx_paths
> 1) {
4507 for (i
= 6; i
< 8; i
++)
4508 result
[3][i
] = result
[c1
][i
];
4516 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv
*priv
, const u32
*reg
, u32
*backup
)
4520 for (i
= 0; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
4521 backup
[i
] = rtl8xxxu_read8(priv
, reg
[i
]);
4523 backup
[i
] = rtl8xxxu_read32(priv
, reg
[i
]);
4526 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv
*priv
,
4527 const u32
*reg
, u32
*backup
)
4531 for (i
= 0; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
4532 rtl8xxxu_write8(priv
, reg
[i
], backup
[i
]);
4534 rtl8xxxu_write32(priv
, reg
[i
], backup
[i
]);
4537 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
4538 u32
*backup
, int count
)
4542 for (i
= 0; i
< count
; i
++)
4543 backup
[i
] = rtl8xxxu_read32(priv
, regs
[i
]);
4546 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
4547 u32
*backup
, int count
)
4551 for (i
= 0; i
< count
; i
++)
4552 rtl8xxxu_write32(priv
, regs
[i
], backup
[i
]);
4556 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv
*priv
, const u32
*regs
,
4562 if (priv
->tx_paths
== 1) {
4563 path_on
= priv
->fops
->adda_1t_path_on
;
4564 rtl8xxxu_write32(priv
, regs
[0], priv
->fops
->adda_1t_init
);
4566 path_on
= path_a_on
? priv
->fops
->adda_2t_path_on_a
:
4567 priv
->fops
->adda_2t_path_on_b
;
4569 rtl8xxxu_write32(priv
, regs
[0], path_on
);
4572 for (i
= 1 ; i
< RTL8XXXU_ADDA_REGS
; i
++)
4573 rtl8xxxu_write32(priv
, regs
[i
], path_on
);
4576 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv
*priv
,
4577 const u32
*regs
, u32
*backup
)
4581 rtl8xxxu_write8(priv
, regs
[i
], 0x3f);
4583 for (i
= 1 ; i
< (RTL8XXXU_MAC_REGS
- 1); i
++)
4584 rtl8xxxu_write8(priv
, regs
[i
], (u8
)(backup
[i
] & ~BIT(3)));
4586 rtl8xxxu_write8(priv
, regs
[i
], (u8
)(backup
[i
] & ~BIT(5)));
4589 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4591 u32 reg_eac
, reg_e94
, reg_e9c
, reg_ea4
, val32
;
4594 /* path-A IQK setting */
4595 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x10008c1f);
4596 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x10008c1f);
4597 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82140102);
4599 val32
= (priv
->rf_paths
> 1) ? 0x28160202 :
4600 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
4602 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, val32
);
4604 /* path-B IQK setting */
4605 if (priv
->rf_paths
> 1) {
4606 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x10008c22);
4607 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x10008c22);
4608 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82140102);
4609 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28160202);
4612 /* LO calibration setting */
4613 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x001028d1);
4615 /* One shot, path A LOK & IQK */
4616 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4617 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4622 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4623 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4624 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4625 reg_ea4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_A_2
);
4627 if (!(reg_eac
& BIT(28)) &&
4628 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4629 ((reg_e9c
& 0x03ff0000) != 0x00420000))
4631 else /* If TX not OK, ignore RX */
4634 /* If TX is OK, check whether RX is OK */
4635 if (!(reg_eac
& BIT(27)) &&
4636 ((reg_ea4
& 0x03ff0000) != 0x01320000) &&
4637 ((reg_eac
& 0x03ff0000) != 0x00360000))
4640 dev_warn(&priv
->udev
->dev
, "%s: Path A RX IQK failed!\n",
4646 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv
*priv
)
4648 u32 reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
4651 /* One shot, path B LOK & IQK */
4652 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000002);
4653 rtl8xxxu_write32(priv
, REG_IQK_AGC_CONT
, 0x00000000);
4658 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4659 reg_eb4
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
4660 reg_ebc
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
4661 reg_ec4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
4662 reg_ecc
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
4664 if (!(reg_eac
& BIT(31)) &&
4665 ((reg_eb4
& 0x03ff0000) != 0x01420000) &&
4666 ((reg_ebc
& 0x03ff0000) != 0x00420000))
4671 if (!(reg_eac
& BIT(30)) &&
4672 (((reg_ec4
& 0x03ff0000) >> 16) != 0x132) &&
4673 (((reg_ecc
& 0x03ff0000) >> 16) != 0x36))
4676 dev_warn(&priv
->udev
->dev
, "%s: Path B RX IQK failed!\n",
4682 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4684 u32 reg_eac
, reg_e94
, reg_e9c
, path_sel
, val32
;
4687 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4692 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4693 val32
&= 0x000000ff;
4694 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4697 * Enable path A PA in TX IQK mode
4699 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4701 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4702 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x20000);
4703 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0003f);
4704 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xc7f87);
4709 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4710 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4712 /* path-A IQK setting */
4713 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
4714 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
4715 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4716 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4718 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x821403ea);
4719 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28110000);
4720 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4721 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4723 /* LO calibration setting */
4724 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x00462911);
4729 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4730 val32
&= 0x000000ff;
4731 val32
|= 0x80800000;
4732 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4735 * The vendor driver indicates the USB module is always using
4736 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4738 if (priv
->rf_paths
> 1)
4739 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4741 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4744 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4745 * No trace of this in the 8192eu or 8188eu vendor drivers.
4747 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4749 /* One shot, path A LOK & IQK */
4750 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4751 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4755 /* Restore Ant Path */
4756 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4759 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4765 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4766 val32
&= 0x000000ff;
4767 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4770 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4771 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4772 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4774 val32
= (reg_e9c
>> 16) & 0x3ff;
4776 val32
= 0x400 - val32
;
4778 if (!(reg_eac
& BIT(28)) &&
4779 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4780 ((reg_e9c
& 0x03ff0000) != 0x00420000) &&
4781 ((reg_e94
& 0x03ff0000) < 0x01100000) &&
4782 ((reg_e94
& 0x03ff0000) > 0x00f00000) &&
4785 else /* If TX not OK, ignore RX */
4792 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv
*priv
)
4794 u32 reg_ea4
, reg_eac
, reg_e94
, reg_e9c
, path_sel
, val32
;
4797 path_sel
= rtl8xxxu_read32(priv
, REG_S0S1_PATH_SWITCH
);
4802 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4803 val32
&= 0x000000ff;
4804 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4807 * Enable path A PA in TX IQK mode
4809 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4811 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4812 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4813 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4814 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7fb7);
4819 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
4820 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4822 /* path-A IQK setting */
4823 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
4824 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
4825 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4826 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4828 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82160ff0);
4829 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28110000);
4830 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4831 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4833 /* LO calibration setting */
4834 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a911);
4839 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4840 val32
&= 0x000000ff;
4841 val32
|= 0x80800000;
4842 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4845 * The vendor driver indicates the USB module is always using
4846 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4848 if (priv
->rf_paths
> 1)
4849 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4851 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4854 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4855 * No trace of this in the 8192eu or 8188eu vendor drivers.
4857 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4859 /* One shot, path A LOK & IQK */
4860 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4861 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4865 /* Restore Ant Path */
4866 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4869 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4875 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4876 val32
&= 0x000000ff;
4877 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4880 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4881 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
4882 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
4884 val32
= (reg_e9c
>> 16) & 0x3ff;
4886 val32
= 0x400 - val32
;
4888 if (!(reg_eac
& BIT(28)) &&
4889 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
4890 ((reg_e9c
& 0x03ff0000) != 0x00420000) &&
4891 ((reg_e94
& 0x03ff0000) < 0x01100000) &&
4892 ((reg_e94
& 0x03ff0000) > 0x00f00000) &&
4895 else /* If TX not OK, ignore RX */
4898 val32
= 0x80007c00 | (reg_e94
&0x3ff0000) |
4899 ((reg_e9c
& 0x3ff0000) >> 16);
4900 rtl8xxxu_write32(priv
, REG_TX_IQK
, val32
);
4903 * Modify RX IQK mode
4905 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4906 val32
&= 0x000000ff;
4907 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4908 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
4910 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
4911 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
4912 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
4913 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7d77);
4918 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0xf80);
4919 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_55
, 0x4021f);
4924 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
4926 /* path-A IQK setting */
4927 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x38008c1c);
4928 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x18008c1c);
4929 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
4930 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
4932 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82110000);
4933 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x2816001f);
4934 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82110000);
4935 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x28110000);
4937 /* LO calibration setting */
4938 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a8d1);
4943 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4944 val32
&= 0x000000ff;
4945 val32
|= 0x80800000;
4946 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4948 if (priv
->rf_paths
> 1)
4949 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000000);
4951 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00000280);
4956 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00000800);
4958 /* One shot, path A LOK & IQK */
4959 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
4960 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
4964 /* Restore Ant Path */
4965 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, path_sel
);
4968 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, 0x00001800);
4974 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
4975 val32
&= 0x000000ff;
4976 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
4979 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
4980 reg_ea4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_A_2
);
4982 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0x780);
4984 val32
= (reg_eac
>> 16) & 0x3ff;
4986 val32
= 0x400 - val32
;
4988 if (!(reg_eac
& BIT(27)) &&
4989 ((reg_ea4
& 0x03ff0000) != 0x01320000) &&
4990 ((reg_eac
& 0x03ff0000) != 0x00360000) &&
4991 ((reg_ea4
& 0x03ff0000) < 0x01100000) &&
4992 ((reg_ea4
& 0x03ff0000) > 0x00f00000) &&
4995 else /* If TX not OK, ignore RX */
5001 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv
*priv
)
5003 u32 reg_eac
, reg_e94
, reg_e9c
;
5008 * PA/PAD controlled by 0x0
5010 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5011 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0x00180);
5012 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5014 /* Path A IQK setting */
5015 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
5016 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
5017 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
5018 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
5020 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82140303);
5021 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x68160000);
5023 /* LO calibration setting */
5024 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x00462911);
5026 /* One shot, path A LOK & IQK */
5027 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf9000000);
5028 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
5033 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
5034 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
5035 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
5037 if (!(reg_eac
& BIT(28)) &&
5038 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
5039 ((reg_e9c
& 0x03ff0000) != 0x00420000))
5045 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv
*priv
)
5047 u32 reg_ea4
, reg_eac
, reg_e94
, reg_e9c
, val32
;
5050 /* Leave IQK mode */
5051 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00);
5053 /* Enable path A PA in TX IQK mode */
5054 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, 0x800a0);
5055 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
5056 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0000f);
5057 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf117b);
5059 /* PA/PAD control by 0x56, and set = 0x0 */
5060 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0x00980);
5061 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_56
, 0x51000);
5063 /* Enter IQK mode */
5064 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5066 /* TX IQK setting */
5067 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
5068 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
5070 /* path-A IQK setting */
5071 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x18008c1c);
5072 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
5073 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
5074 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
5076 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82160c1f);
5077 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x68160c1f);
5079 /* LO calibration setting */
5080 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a911);
5082 /* One shot, path A LOK & IQK */
5083 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xfa000000);
5084 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
5089 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
5090 reg_e94
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_A
);
5091 reg_e9c
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_A
);
5093 if (!(reg_eac
& BIT(28)) &&
5094 ((reg_e94
& 0x03ff0000) != 0x01420000) &&
5095 ((reg_e9c
& 0x03ff0000) != 0x00420000)) {
5098 /* PA/PAD controlled by 0x0 */
5099 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5100 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0x180);
5104 val32
= 0x80007c00 |
5105 (reg_e94
& 0x03ff0000) | ((reg_e9c
>> 16) & 0x03ff);
5106 rtl8xxxu_write32(priv
, REG_TX_IQK
, val32
);
5108 /* Modify RX IQK mode table */
5109 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5111 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, 0x800a0);
5112 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
5113 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0000f);
5114 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7ffa);
5116 /* PA/PAD control by 0x56, and set = 0x0 */
5117 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0x00980);
5118 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_56
, 0x51000);
5120 /* Enter IQK mode */
5121 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5124 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
5126 /* Path A IQK setting */
5127 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x38008c1c);
5128 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x18008c1c);
5129 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
5130 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
5132 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82160c1f);
5133 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28160c1f);
5135 /* LO calibration setting */
5136 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a891);
5138 /* One shot, path A LOK & IQK */
5139 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xfa000000);
5140 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
5144 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
5145 reg_ea4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_A_2
);
5147 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5148 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_DF
, 0x180);
5150 if (!(reg_eac
& BIT(27)) &&
5151 ((reg_ea4
& 0x03ff0000) != 0x01320000) &&
5152 ((reg_eac
& 0x03ff0000) != 0x00360000))
5155 dev_warn(&priv
->udev
->dev
, "%s: Path A RX IQK failed!\n",
5162 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv
*priv
)
5164 u32 reg_eac
, reg_eb4
, reg_ebc
;
5167 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5168 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_UNKNOWN_DF
, 0x00180);
5169 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5171 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5172 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5174 /* Path B IQK setting */
5175 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x38008c1c);
5176 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
5177 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x18008c1c);
5178 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
5180 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x821403e2);
5181 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x68160000);
5183 /* LO calibration setting */
5184 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x00492911);
5186 /* One shot, path A LOK & IQK */
5187 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xfa000000);
5188 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
5193 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
5194 reg_eb4
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
5195 reg_ebc
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
5197 if (!(reg_eac
& BIT(31)) &&
5198 ((reg_eb4
& 0x03ff0000) != 0x01420000) &&
5199 ((reg_ebc
& 0x03ff0000) != 0x00420000))
5202 dev_warn(&priv
->udev
->dev
, "%s: Path B IQK failed!\n",
5208 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv
*priv
)
5210 u32 reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
, val32
;
5213 /* Leave IQK mode */
5214 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5216 /* Enable path A PA in TX IQK mode */
5217 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_WE_LUT
, 0x800a0);
5218 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_RCK_OS
, 0x30000);
5219 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_TXPA_G1
, 0x0000f);
5220 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_TXPA_G2
, 0xf117b);
5222 /* PA/PAD control by 0x56, and set = 0x0 */
5223 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_UNKNOWN_DF
, 0x00980);
5224 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_UNKNOWN_56
, 0x51000);
5226 /* Enter IQK mode */
5227 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5229 /* TX IQK setting */
5230 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
5231 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
5233 /* path-A IQK setting */
5234 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x38008c1c);
5235 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
5236 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x18008c1c);
5237 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x38008c1c);
5239 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_B
, 0x82160c1f);
5240 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_B
, 0x68160c1f);
5242 /* LO calibration setting */
5243 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a911);
5245 /* One shot, path A LOK & IQK */
5246 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xfa000000);
5247 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
5252 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
5253 reg_eb4
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
5254 reg_ebc
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
5256 if (!(reg_eac
& BIT(31)) &&
5257 ((reg_eb4
& 0x03ff0000) != 0x01420000) &&
5258 ((reg_ebc
& 0x03ff0000) != 0x00420000)) {
5262 * PA/PAD controlled by 0x0
5263 * Vendor driver restores RF_A here which I believe is a bug
5265 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5266 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_UNKNOWN_DF
, 0x180);
5270 val32
= 0x80007c00 |
5271 (reg_eb4
& 0x03ff0000) | ((reg_ebc
>> 16) & 0x03ff);
5272 rtl8xxxu_write32(priv
, REG_TX_IQK
, val32
);
5274 /* Modify RX IQK mode table */
5275 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5277 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_WE_LUT
, 0x800a0);
5278 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_RCK_OS
, 0x30000);
5279 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_TXPA_G1
, 0x0000f);
5280 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_TXPA_G2
, 0xf7ffa);
5282 /* PA/PAD control by 0x56, and set = 0x0 */
5283 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_UNKNOWN_DF
, 0x00980);
5284 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_UNKNOWN_56
, 0x51000);
5286 /* Enter IQK mode */
5287 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5290 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
5292 /* Path A IQK setting */
5293 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x38008c1c);
5294 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x38008c1c);
5295 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_B
, 0x38008c1c);
5296 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_B
, 0x18008c1c);
5298 rtl8xxxu_write32(priv
, REG_TX_IQK_PI_A
, 0x82160c1f);
5299 rtl8xxxu_write32(priv
, REG_RX_IQK_PI_A
, 0x28160c1f);
5301 /* LO calibration setting */
5302 rtl8xxxu_write32(priv
, REG_IQK_AGC_RSP
, 0x0046a891);
5304 /* One shot, path A LOK & IQK */
5305 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xfa000000);
5306 rtl8xxxu_write32(priv
, REG_IQK_AGC_PTS
, 0xf8000000);
5310 reg_eac
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_A_2
);
5311 reg_ec4
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
5312 reg_ecc
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
5314 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5315 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_UNKNOWN_DF
, 0x180);
5317 if (!(reg_eac
& BIT(30)) &&
5318 ((reg_ec4
& 0x03ff0000) != 0x01320000) &&
5319 ((reg_ecc
& 0x03ff0000) != 0x00360000))
5322 dev_warn(&priv
->udev
->dev
, "%s: Path B RX IQK failed!\n",
5329 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv
*priv
,
5330 int result
[][8], int t
)
5332 struct device
*dev
= &priv
->udev
->dev
;
5334 int path_a_ok
, path_b_ok
;
5336 const u32 adda_regs
[RTL8XXXU_ADDA_REGS
] = {
5337 REG_FPGA0_XCD_SWITCH_CTRL
, REG_BLUETOOTH
,
5338 REG_RX_WAIT_CCA
, REG_TX_CCK_RFON
,
5339 REG_TX_CCK_BBON
, REG_TX_OFDM_RFON
,
5340 REG_TX_OFDM_BBON
, REG_TX_TO_RX
,
5341 REG_TX_TO_TX
, REG_RX_CCK
,
5342 REG_RX_OFDM
, REG_RX_WAIT_RIFS
,
5343 REG_RX_TO_RX
, REG_STANDBY
,
5344 REG_SLEEP
, REG_PMPD_ANAEN
5346 const u32 iqk_mac_regs
[RTL8XXXU_MAC_REGS
] = {
5347 REG_TXPAUSE
, REG_BEACON_CTRL
,
5348 REG_BEACON_CTRL_1
, REG_GPIO_MUXCFG
5350 const u32 iqk_bb_regs
[RTL8XXXU_BB_REGS
] = {
5351 REG_OFDM0_TRX_PATH_ENABLE
, REG_OFDM0_TR_MUX_PAR
,
5352 REG_FPGA0_XCD_RF_SW_CTRL
, REG_CONFIG_ANT_A
, REG_CONFIG_ANT_B
,
5353 REG_FPGA0_XAB_RF_SW_CTRL
, REG_FPGA0_XA_RF_INT_OE
,
5354 REG_FPGA0_XB_RF_INT_OE
, REG_FPGA0_RF_MODE
5358 * Note: IQ calibration must be performed after loading
5359 * PHY_REG.txt , and radio_a, radio_b.txt
5363 /* Save ADDA parameters, turn Path A ADDA on */
5364 rtl8xxxu_save_regs(priv
, adda_regs
, priv
->adda_backup
,
5365 RTL8XXXU_ADDA_REGS
);
5366 rtl8xxxu_save_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
5367 rtl8xxxu_save_regs(priv
, iqk_bb_regs
,
5368 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
5371 rtl8xxxu_path_adda_on(priv
, adda_regs
, true);
5374 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_HSSI_PARM1
);
5375 if (val32
& FPGA0_HSSI_PARM1_PI
)
5376 priv
->pi_enabled
= 1;
5379 if (!priv
->pi_enabled
) {
5380 /* Switch BB to PI mode to do IQ Calibration. */
5381 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM1
, 0x01000100);
5382 rtl8xxxu_write32(priv
, REG_FPGA0_XB_HSSI_PARM1
, 0x01000100);
5385 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
5386 val32
&= ~FPGA_RF_MODE_CCK
;
5387 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
5389 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, 0x03a05600);
5390 rtl8xxxu_write32(priv
, REG_OFDM0_TR_MUX_PAR
, 0x000800e4);
5391 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_SW_CTRL
, 0x22204000);
5393 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
);
5394 val32
|= (FPGA0_RF_PAPE
| (FPGA0_RF_PAPE
<< FPGA0_RF_BD_CTRL_SHIFT
));
5395 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
, val32
);
5397 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_RF_INT_OE
);
5399 rtl8xxxu_write32(priv
, REG_FPGA0_XA_RF_INT_OE
, val32
);
5400 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XB_RF_INT_OE
);
5402 rtl8xxxu_write32(priv
, REG_FPGA0_XB_RF_INT_OE
, val32
);
5404 if (priv
->tx_paths
> 1) {
5405 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00010000);
5406 rtl8xxxu_write32(priv
, REG_FPGA0_XB_LSSI_PARM
, 0x00010000);
5410 rtl8xxxu_mac_calibration(priv
, iqk_mac_regs
, priv
->mac_backup
);
5413 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_A
, 0x00080000);
5415 if (priv
->tx_paths
> 1)
5416 rtl8xxxu_write32(priv
, REG_CONFIG_ANT_B
, 0x00080000);
5418 /* IQ calibration setting */
5419 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5420 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
5421 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
5423 for (i
= 0; i
< retry
; i
++) {
5424 path_a_ok
= rtl8xxxu_iqk_path_a(priv
);
5425 if (path_a_ok
== 0x03) {
5426 val32
= rtl8xxxu_read32(priv
,
5427 REG_TX_POWER_BEFORE_IQK_A
);
5428 result
[t
][0] = (val32
>> 16) & 0x3ff;
5429 val32
= rtl8xxxu_read32(priv
,
5430 REG_TX_POWER_AFTER_IQK_A
);
5431 result
[t
][1] = (val32
>> 16) & 0x3ff;
5432 val32
= rtl8xxxu_read32(priv
,
5433 REG_RX_POWER_BEFORE_IQK_A_2
);
5434 result
[t
][2] = (val32
>> 16) & 0x3ff;
5435 val32
= rtl8xxxu_read32(priv
,
5436 REG_RX_POWER_AFTER_IQK_A_2
);
5437 result
[t
][3] = (val32
>> 16) & 0x3ff;
5439 } else if (i
== (retry
- 1) && path_a_ok
== 0x01) {
5441 dev_dbg(dev
, "%s: Path A IQK Only Tx Success!!\n",
5444 val32
= rtl8xxxu_read32(priv
,
5445 REG_TX_POWER_BEFORE_IQK_A
);
5446 result
[t
][0] = (val32
>> 16) & 0x3ff;
5447 val32
= rtl8xxxu_read32(priv
,
5448 REG_TX_POWER_AFTER_IQK_A
);
5449 result
[t
][1] = (val32
>> 16) & 0x3ff;
5454 dev_dbg(dev
, "%s: Path A IQK failed!\n", __func__
);
5456 if (priv
->tx_paths
> 1) {
5458 * Path A into standby
5460 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x0);
5461 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00010000);
5462 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5464 /* Turn Path B ADDA on */
5465 rtl8xxxu_path_adda_on(priv
, adda_regs
, false);
5467 for (i
= 0; i
< retry
; i
++) {
5468 path_b_ok
= rtl8xxxu_iqk_path_b(priv
);
5469 if (path_b_ok
== 0x03) {
5470 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
5471 result
[t
][4] = (val32
>> 16) & 0x3ff;
5472 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
5473 result
[t
][5] = (val32
>> 16) & 0x3ff;
5474 val32
= rtl8xxxu_read32(priv
, REG_RX_POWER_BEFORE_IQK_B_2
);
5475 result
[t
][6] = (val32
>> 16) & 0x3ff;
5476 val32
= rtl8xxxu_read32(priv
, REG_RX_POWER_AFTER_IQK_B_2
);
5477 result
[t
][7] = (val32
>> 16) & 0x3ff;
5479 } else if (i
== (retry
- 1) && path_b_ok
== 0x01) {
5481 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
5482 result
[t
][4] = (val32
>> 16) & 0x3ff;
5483 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
5484 result
[t
][5] = (val32
>> 16) & 0x3ff;
5489 dev_dbg(dev
, "%s: Path B IQK failed!\n", __func__
);
5492 /* Back to BB mode, load original value */
5493 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0);
5496 if (!priv
->pi_enabled
) {
5498 * Switch back BB to SI mode after finishing
5502 rtl8xxxu_write32(priv
, REG_FPGA0_XA_HSSI_PARM1
, val32
);
5503 rtl8xxxu_write32(priv
, REG_FPGA0_XB_HSSI_PARM1
, val32
);
5506 /* Reload ADDA power saving parameters */
5507 rtl8xxxu_restore_regs(priv
, adda_regs
, priv
->adda_backup
,
5508 RTL8XXXU_ADDA_REGS
);
5510 /* Reload MAC parameters */
5511 rtl8xxxu_restore_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
5513 /* Reload BB parameters */
5514 rtl8xxxu_restore_regs(priv
, iqk_bb_regs
,
5515 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
5517 /* Restore RX initial gain */
5518 rtl8xxxu_write32(priv
, REG_FPGA0_XA_LSSI_PARM
, 0x00032ed3);
5520 if (priv
->tx_paths
> 1) {
5521 rtl8xxxu_write32(priv
, REG_FPGA0_XB_LSSI_PARM
,
5525 /* Load 0xe30 IQC default value */
5526 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x01008c00);
5527 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x01008c00);
5531 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv
*priv
,
5532 int result
[][8], int t
)
5534 struct device
*dev
= &priv
->udev
->dev
;
5536 int path_a_ok
/*, path_b_ok */;
5538 const u32 adda_regs
[RTL8XXXU_ADDA_REGS
] = {
5539 REG_FPGA0_XCD_SWITCH_CTRL
, REG_BLUETOOTH
,
5540 REG_RX_WAIT_CCA
, REG_TX_CCK_RFON
,
5541 REG_TX_CCK_BBON
, REG_TX_OFDM_RFON
,
5542 REG_TX_OFDM_BBON
, REG_TX_TO_RX
,
5543 REG_TX_TO_TX
, REG_RX_CCK
,
5544 REG_RX_OFDM
, REG_RX_WAIT_RIFS
,
5545 REG_RX_TO_RX
, REG_STANDBY
,
5546 REG_SLEEP
, REG_PMPD_ANAEN
5548 const u32 iqk_mac_regs
[RTL8XXXU_MAC_REGS
] = {
5549 REG_TXPAUSE
, REG_BEACON_CTRL
,
5550 REG_BEACON_CTRL_1
, REG_GPIO_MUXCFG
5552 const u32 iqk_bb_regs
[RTL8XXXU_BB_REGS
] = {
5553 REG_OFDM0_TRX_PATH_ENABLE
, REG_OFDM0_TR_MUX_PAR
,
5554 REG_FPGA0_XCD_RF_SW_CTRL
, REG_CONFIG_ANT_A
, REG_CONFIG_ANT_B
,
5555 REG_FPGA0_XAB_RF_SW_CTRL
, REG_FPGA0_XA_RF_INT_OE
,
5556 REG_FPGA0_XB_RF_INT_OE
, REG_FPGA0_RF_MODE
5558 u8 xa_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
) & 0xff;
5559 u8 xb_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
) & 0xff;
5562 * Note: IQ calibration must be performed after loading
5563 * PHY_REG.txt , and radio_a, radio_b.txt
5567 /* Save ADDA parameters, turn Path A ADDA on */
5568 rtl8xxxu_save_regs(priv
, adda_regs
, priv
->adda_backup
,
5569 RTL8XXXU_ADDA_REGS
);
5570 rtl8xxxu_save_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
5571 rtl8xxxu_save_regs(priv
, iqk_bb_regs
,
5572 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
5575 rtl8xxxu_path_adda_on(priv
, adda_regs
, true);
5578 rtl8xxxu_mac_calibration(priv
, iqk_mac_regs
, priv
->mac_backup
);
5580 val32
= rtl8xxxu_read32(priv
, REG_CCK0_AFE_SETTING
);
5581 val32
|= 0x0f000000;
5582 rtl8xxxu_write32(priv
, REG_CCK0_AFE_SETTING
, val32
);
5584 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, 0x03a05600);
5585 rtl8xxxu_write32(priv
, REG_OFDM0_TR_MUX_PAR
, 0x000800e4);
5586 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_SW_CTRL
, 0x22204000);
5589 * RX IQ calibration setting for 8723B D cut large current issue
5592 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
5593 val32
&= 0x000000ff;
5594 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
5596 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
5598 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
5600 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x30000);
5601 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
5602 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xf7fb7);
5604 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
);
5606 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
, val32
);
5608 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_43
, 0x60fbd);
5610 for (i
= 0; i
< retry
; i
++) {
5611 path_a_ok
= rtl8723bu_iqk_path_a(priv
);
5612 if (path_a_ok
== 0x01) {
5613 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
5614 val32
&= 0x000000ff;
5615 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
5617 val32
= rtl8xxxu_read32(priv
,
5618 REG_TX_POWER_BEFORE_IQK_A
);
5619 result
[t
][0] = (val32
>> 16) & 0x3ff;
5620 val32
= rtl8xxxu_read32(priv
,
5621 REG_TX_POWER_AFTER_IQK_A
);
5622 result
[t
][1] = (val32
>> 16) & 0x3ff;
5629 dev_dbg(dev
, "%s: Path A TX IQK failed!\n", __func__
);
5631 for (i
= 0; i
< retry
; i
++) {
5632 path_a_ok
= rtl8723bu_rx_iqk_path_a(priv
);
5633 if (path_a_ok
== 0x03) {
5634 val32
= rtl8xxxu_read32(priv
,
5635 REG_RX_POWER_BEFORE_IQK_A_2
);
5636 result
[t
][2] = (val32
>> 16) & 0x3ff;
5637 val32
= rtl8xxxu_read32(priv
,
5638 REG_RX_POWER_AFTER_IQK_A_2
);
5639 result
[t
][3] = (val32
>> 16) & 0x3ff;
5646 dev_dbg(dev
, "%s: Path A RX IQK failed!\n", __func__
);
5648 if (priv
->tx_paths
> 1) {
5650 dev_warn(dev
, "%s: Path B not supported\n", __func__
);
5654 * Path A into standby
5656 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
5657 val32
&= 0x000000ff;
5658 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
5659 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0x10000);
5661 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
5662 val32
&= 0x000000ff;
5663 val32
|= 0x80800000;
5664 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
5666 /* Turn Path B ADDA on */
5667 rtl8xxxu_path_adda_on(priv
, adda_regs
, false);
5669 for (i
= 0; i
< retry
; i
++) {
5670 path_b_ok
= rtl8xxxu_iqk_path_b(priv
);
5671 if (path_b_ok
== 0x03) {
5672 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
5673 result
[t
][4] = (val32
>> 16) & 0x3ff;
5674 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
5675 result
[t
][5] = (val32
>> 16) & 0x3ff;
5681 dev_dbg(dev
, "%s: Path B IQK failed!\n", __func__
);
5683 for (i
= 0; i
< retry
; i
++) {
5684 path_b_ok
= rtl8723bu_rx_iqk_path_b(priv
);
5685 if (path_a_ok
== 0x03) {
5686 val32
= rtl8xxxu_read32(priv
,
5687 REG_RX_POWER_BEFORE_IQK_B_2
);
5688 result
[t
][6] = (val32
>> 16) & 0x3ff;
5689 val32
= rtl8xxxu_read32(priv
,
5690 REG_RX_POWER_AFTER_IQK_B_2
);
5691 result
[t
][7] = (val32
>> 16) & 0x3ff;
5697 dev_dbg(dev
, "%s: Path B RX IQK failed!\n", __func__
);
5701 /* Back to BB mode, load original value */
5702 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
5703 val32
&= 0x000000ff;
5704 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
5707 /* Reload ADDA power saving parameters */
5708 rtl8xxxu_restore_regs(priv
, adda_regs
, priv
->adda_backup
,
5709 RTL8XXXU_ADDA_REGS
);
5711 /* Reload MAC parameters */
5712 rtl8xxxu_restore_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
5714 /* Reload BB parameters */
5715 rtl8xxxu_restore_regs(priv
, iqk_bb_regs
,
5716 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
5718 /* Restore RX initial gain */
5719 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
);
5720 val32
&= 0xffffff00;
5721 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| 0x50);
5722 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| xa_agc
);
5724 if (priv
->tx_paths
> 1) {
5725 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
);
5726 val32
&= 0xffffff00;
5727 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
5729 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
5733 /* Load 0xe30 IQC default value */
5734 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x01008c00);
5735 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x01008c00);
5739 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv
*priv
,
5740 int result
[][8], int t
)
5742 struct device
*dev
= &priv
->udev
->dev
;
5744 int path_a_ok
, path_b_ok
;
5746 const u32 adda_regs
[RTL8XXXU_ADDA_REGS
] = {
5747 REG_FPGA0_XCD_SWITCH_CTRL
, REG_BLUETOOTH
,
5748 REG_RX_WAIT_CCA
, REG_TX_CCK_RFON
,
5749 REG_TX_CCK_BBON
, REG_TX_OFDM_RFON
,
5750 REG_TX_OFDM_BBON
, REG_TX_TO_RX
,
5751 REG_TX_TO_TX
, REG_RX_CCK
,
5752 REG_RX_OFDM
, REG_RX_WAIT_RIFS
,
5753 REG_RX_TO_RX
, REG_STANDBY
,
5754 REG_SLEEP
, REG_PMPD_ANAEN
5756 const u32 iqk_mac_regs
[RTL8XXXU_MAC_REGS
] = {
5757 REG_TXPAUSE
, REG_BEACON_CTRL
,
5758 REG_BEACON_CTRL_1
, REG_GPIO_MUXCFG
5760 const u32 iqk_bb_regs
[RTL8XXXU_BB_REGS
] = {
5761 REG_OFDM0_TRX_PATH_ENABLE
, REG_OFDM0_TR_MUX_PAR
,
5762 REG_FPGA0_XCD_RF_SW_CTRL
, REG_CONFIG_ANT_A
, REG_CONFIG_ANT_B
,
5763 REG_FPGA0_XAB_RF_SW_CTRL
, REG_FPGA0_XA_RF_INT_OE
,
5764 REG_FPGA0_XB_RF_INT_OE
, REG_CCK0_AFE_SETTING
5766 u8 xa_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
) & 0xff;
5767 u8 xb_agc
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
) & 0xff;
5770 * Note: IQ calibration must be performed after loading
5771 * PHY_REG.txt , and radio_a, radio_b.txt
5775 /* Save ADDA parameters, turn Path A ADDA on */
5776 rtl8xxxu_save_regs(priv
, adda_regs
, priv
->adda_backup
,
5777 RTL8XXXU_ADDA_REGS
);
5778 rtl8xxxu_save_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
5779 rtl8xxxu_save_regs(priv
, iqk_bb_regs
,
5780 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
5783 rtl8xxxu_path_adda_on(priv
, adda_regs
, true);
5786 rtl8xxxu_mac_calibration(priv
, iqk_mac_regs
, priv
->mac_backup
);
5788 val32
= rtl8xxxu_read32(priv
, REG_CCK0_AFE_SETTING
);
5789 val32
|= 0x0f000000;
5790 rtl8xxxu_write32(priv
, REG_CCK0_AFE_SETTING
, val32
);
5792 rtl8xxxu_write32(priv
, REG_OFDM0_TRX_PATH_ENABLE
, 0x03a05600);
5793 rtl8xxxu_write32(priv
, REG_OFDM0_TR_MUX_PAR
, 0x000800e4);
5794 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_SW_CTRL
, 0x22208200);
5796 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
);
5797 val32
|= (FPGA0_RF_PAPE
| (FPGA0_RF_PAPE
<< FPGA0_RF_BD_CTRL_SHIFT
));
5798 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
, val32
);
5800 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XA_RF_INT_OE
);
5802 rtl8xxxu_write32(priv
, REG_FPGA0_XA_RF_INT_OE
, val32
);
5803 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XB_RF_INT_OE
);
5805 rtl8xxxu_write32(priv
, REG_FPGA0_XB_RF_INT_OE
, val32
);
5807 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5808 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
5809 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
5811 for (i
= 0; i
< retry
; i
++) {
5812 path_a_ok
= rtl8192eu_iqk_path_a(priv
);
5813 if (path_a_ok
== 0x01) {
5814 val32
= rtl8xxxu_read32(priv
,
5815 REG_TX_POWER_BEFORE_IQK_A
);
5816 result
[t
][0] = (val32
>> 16) & 0x3ff;
5817 val32
= rtl8xxxu_read32(priv
,
5818 REG_TX_POWER_AFTER_IQK_A
);
5819 result
[t
][1] = (val32
>> 16) & 0x3ff;
5826 dev_dbg(dev
, "%s: Path A TX IQK failed!\n", __func__
);
5828 for (i
= 0; i
< retry
; i
++) {
5829 path_a_ok
= rtl8192eu_rx_iqk_path_a(priv
);
5830 if (path_a_ok
== 0x03) {
5831 val32
= rtl8xxxu_read32(priv
,
5832 REG_RX_POWER_BEFORE_IQK_A_2
);
5833 result
[t
][2] = (val32
>> 16) & 0x3ff;
5834 val32
= rtl8xxxu_read32(priv
,
5835 REG_RX_POWER_AFTER_IQK_A_2
);
5836 result
[t
][3] = (val32
>> 16) & 0x3ff;
5843 dev_dbg(dev
, "%s: Path A RX IQK failed!\n", __func__
);
5845 if (priv
->rf_paths
> 1) {
5846 /* Path A into standby */
5847 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5848 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, 0x10000);
5849 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5851 /* Turn Path B ADDA on */
5852 rtl8xxxu_path_adda_on(priv
, adda_regs
, false);
5854 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x80800000);
5855 rtl8xxxu_write32(priv
, REG_TX_IQK
, 0x01007c00);
5856 rtl8xxxu_write32(priv
, REG_RX_IQK
, 0x01004800);
5858 for (i
= 0; i
< retry
; i
++) {
5859 path_b_ok
= rtl8192eu_iqk_path_b(priv
);
5860 if (path_b_ok
== 0x01) {
5861 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_BEFORE_IQK_B
);
5862 result
[t
][4] = (val32
>> 16) & 0x3ff;
5863 val32
= rtl8xxxu_read32(priv
, REG_TX_POWER_AFTER_IQK_B
);
5864 result
[t
][5] = (val32
>> 16) & 0x3ff;
5870 dev_dbg(dev
, "%s: Path B IQK failed!\n", __func__
);
5872 for (i
= 0; i
< retry
; i
++) {
5873 path_b_ok
= rtl8192eu_rx_iqk_path_b(priv
);
5874 if (path_a_ok
== 0x03) {
5875 val32
= rtl8xxxu_read32(priv
,
5876 REG_RX_POWER_BEFORE_IQK_B_2
);
5877 result
[t
][6] = (val32
>> 16) & 0x3ff;
5878 val32
= rtl8xxxu_read32(priv
,
5879 REG_RX_POWER_AFTER_IQK_B_2
);
5880 result
[t
][7] = (val32
>> 16) & 0x3ff;
5886 dev_dbg(dev
, "%s: Path B RX IQK failed!\n", __func__
);
5889 /* Back to BB mode, load original value */
5890 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, 0x00000000);
5893 /* Reload ADDA power saving parameters */
5894 rtl8xxxu_restore_regs(priv
, adda_regs
, priv
->adda_backup
,
5895 RTL8XXXU_ADDA_REGS
);
5897 /* Reload MAC parameters */
5898 rtl8xxxu_restore_mac_regs(priv
, iqk_mac_regs
, priv
->mac_backup
);
5900 /* Reload BB parameters */
5901 rtl8xxxu_restore_regs(priv
, iqk_bb_regs
,
5902 priv
->bb_backup
, RTL8XXXU_BB_REGS
);
5904 /* Restore RX initial gain */
5905 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XA_AGC_CORE1
);
5906 val32
&= 0xffffff00;
5907 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| 0x50);
5908 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, val32
| xa_agc
);
5910 if (priv
->rf_paths
> 1) {
5911 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_XB_AGC_CORE1
);
5912 val32
&= 0xffffff00;
5913 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
5915 rtl8xxxu_write32(priv
, REG_OFDM0_XB_AGC_CORE1
,
5919 /* Load 0xe30 IQC default value */
5920 rtl8xxxu_write32(priv
, REG_TX_IQK_TONE_A
, 0x01008c00);
5921 rtl8xxxu_write32(priv
, REG_RX_IQK_TONE_A
, 0x01008c00);
5925 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv
*priv
, u8 start
)
5929 if (priv
->fops
->mbox_ext_width
< 4)
5932 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
5933 h2c
.bt_wlan_calibration
.cmd
= H2C_8723B_BT_WLAN_CALIBRATION
;
5934 h2c
.bt_wlan_calibration
.data
= start
;
5936 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_wlan_calibration
));
5939 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv
*priv
)
5941 struct device
*dev
= &priv
->udev
->dev
;
5942 int result
[4][8]; /* last is final result */
5944 bool path_a_ok
, path_b_ok
;
5945 u32 reg_e94
, reg_e9c
, reg_ea4
, reg_eac
;
5946 u32 reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
5950 rtl8xxxu_prepare_calibrate(priv
, 1);
5952 memset(result
, 0, sizeof(result
));
5958 rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
5960 for (i
= 0; i
< 3; i
++) {
5961 rtl8xxxu_phy_iqcalibrate(priv
, result
, i
);
5964 simu
= rtl8xxxu_simularity_compare(priv
, result
, 0, 1);
5972 simu
= rtl8xxxu_simularity_compare(priv
, result
, 0, 2);
5978 simu
= rtl8xxxu_simularity_compare(priv
, result
, 1, 2);
5982 for (i
= 0; i
< 8; i
++)
5983 reg_tmp
+= result
[3][i
];
5993 for (i
= 0; i
< 4; i
++) {
5994 reg_e94
= result
[i
][0];
5995 reg_e9c
= result
[i
][1];
5996 reg_ea4
= result
[i
][2];
5997 reg_eac
= result
[i
][3];
5998 reg_eb4
= result
[i
][4];
5999 reg_ebc
= result
[i
][5];
6000 reg_ec4
= result
[i
][6];
6001 reg_ecc
= result
[i
][7];
6004 if (candidate
>= 0) {
6005 reg_e94
= result
[candidate
][0];
6006 priv
->rege94
= reg_e94
;
6007 reg_e9c
= result
[candidate
][1];
6008 priv
->rege9c
= reg_e9c
;
6009 reg_ea4
= result
[candidate
][2];
6010 reg_eac
= result
[candidate
][3];
6011 reg_eb4
= result
[candidate
][4];
6012 priv
->regeb4
= reg_eb4
;
6013 reg_ebc
= result
[candidate
][5];
6014 priv
->regebc
= reg_ebc
;
6015 reg_ec4
= result
[candidate
][6];
6016 reg_ecc
= result
[candidate
][7];
6017 dev_dbg(dev
, "%s: candidate is %x\n", __func__
, candidate
);
6019 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
6020 "ecc=%x\n ", __func__
, reg_e94
, reg_e9c
,
6021 reg_ea4
, reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
);
6025 reg_e94
= reg_eb4
= priv
->rege94
= priv
->regeb4
= 0x100;
6026 reg_e9c
= reg_ebc
= priv
->rege9c
= priv
->regebc
= 0x0;
6029 if (reg_e94
&& candidate
>= 0)
6030 rtl8xxxu_fill_iqk_matrix_a(priv
, path_a_ok
, result
,
6031 candidate
, (reg_ea4
== 0));
6033 if (priv
->tx_paths
> 1 && reg_eb4
)
6034 rtl8xxxu_fill_iqk_matrix_b(priv
, path_b_ok
, result
,
6035 candidate
, (reg_ec4
== 0));
6037 rtl8xxxu_save_regs(priv
, rtl8723au_iqk_phy_iq_bb_reg
,
6038 priv
->bb_recovery_backup
, RTL8XXXU_BB_REGS
);
6040 rtl8xxxu_prepare_calibrate(priv
, 0);
6043 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv
*priv
)
6045 struct device
*dev
= &priv
->udev
->dev
;
6046 int result
[4][8]; /* last is final result */
6048 bool path_a_ok
, path_b_ok
;
6049 u32 reg_e94
, reg_e9c
, reg_ea4
, reg_eac
;
6050 u32 reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
6051 u32 val32
, bt_control
;
6055 rtl8xxxu_prepare_calibrate(priv
, 1);
6057 memset(result
, 0, sizeof(result
));
6063 bt_control
= rtl8xxxu_read32(priv
, REG_BT_CONTROL_8723BU
);
6065 for (i
= 0; i
< 3; i
++) {
6066 rtl8723bu_phy_iqcalibrate(priv
, result
, i
);
6069 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 1);
6077 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 2);
6083 simu
= rtl8723bu_simularity_compare(priv
, result
, 1, 2);
6087 for (i
= 0; i
< 8; i
++)
6088 reg_tmp
+= result
[3][i
];
6098 for (i
= 0; i
< 4; i
++) {
6099 reg_e94
= result
[i
][0];
6100 reg_e9c
= result
[i
][1];
6101 reg_ea4
= result
[i
][2];
6102 reg_eac
= result
[i
][3];
6103 reg_eb4
= result
[i
][4];
6104 reg_ebc
= result
[i
][5];
6105 reg_ec4
= result
[i
][6];
6106 reg_ecc
= result
[i
][7];
6109 if (candidate
>= 0) {
6110 reg_e94
= result
[candidate
][0];
6111 priv
->rege94
= reg_e94
;
6112 reg_e9c
= result
[candidate
][1];
6113 priv
->rege9c
= reg_e9c
;
6114 reg_ea4
= result
[candidate
][2];
6115 reg_eac
= result
[candidate
][3];
6116 reg_eb4
= result
[candidate
][4];
6117 priv
->regeb4
= reg_eb4
;
6118 reg_ebc
= result
[candidate
][5];
6119 priv
->regebc
= reg_ebc
;
6120 reg_ec4
= result
[candidate
][6];
6121 reg_ecc
= result
[candidate
][7];
6122 dev_dbg(dev
, "%s: candidate is %x\n", __func__
, candidate
);
6124 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
6125 "ecc=%x\n ", __func__
, reg_e94
, reg_e9c
,
6126 reg_ea4
, reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
);
6130 reg_e94
= reg_eb4
= priv
->rege94
= priv
->regeb4
= 0x100;
6131 reg_e9c
= reg_ebc
= priv
->rege9c
= priv
->regebc
= 0x0;
6134 if (reg_e94
&& candidate
>= 0)
6135 rtl8xxxu_fill_iqk_matrix_a(priv
, path_a_ok
, result
,
6136 candidate
, (reg_ea4
== 0));
6138 if (priv
->tx_paths
> 1 && reg_eb4
)
6139 rtl8xxxu_fill_iqk_matrix_b(priv
, path_b_ok
, result
,
6140 candidate
, (reg_ec4
== 0));
6142 rtl8xxxu_save_regs(priv
, rtl8723au_iqk_phy_iq_bb_reg
,
6143 priv
->bb_recovery_backup
, RTL8XXXU_BB_REGS
);
6145 rtl8xxxu_write32(priv
, REG_BT_CONTROL_8723BU
, bt_control
);
6147 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
);
6149 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_WE_LUT
, val32
);
6150 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_RCK_OS
, 0x18000);
6151 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G1
, 0x0001f);
6152 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_TXPA_G2
, 0xe6177);
6153 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
);
6155 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_UNKNOWN_ED
, val32
);
6156 rtl8xxxu_write_rfreg(priv
, RF_A
, 0x43, 0x300bd);
6158 if (priv
->rf_paths
> 1)
6159 dev_dbg(dev
, "%s: 8723BU 2T not supported\n", __func__
);
6161 rtl8xxxu_prepare_calibrate(priv
, 0);
6164 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv
*priv
)
6166 struct device
*dev
= &priv
->udev
->dev
;
6167 int result
[4][8]; /* last is final result */
6169 bool path_a_ok
, path_b_ok
;
6170 u32 reg_e94
, reg_e9c
, reg_ea4
, reg_eac
;
6171 u32 reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
;
6174 memset(result
, 0, sizeof(result
));
6180 for (i
= 0; i
< 3; i
++) {
6181 rtl8192eu_phy_iqcalibrate(priv
, result
, i
);
6184 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 1);
6192 simu
= rtl8723bu_simularity_compare(priv
, result
, 0, 2);
6198 simu
= rtl8723bu_simularity_compare(priv
, result
, 1, 2);
6206 for (i
= 0; i
< 4; i
++) {
6207 reg_e94
= result
[i
][0];
6208 reg_e9c
= result
[i
][1];
6209 reg_ea4
= result
[i
][2];
6210 reg_eac
= result
[i
][3];
6211 reg_eb4
= result
[i
][4];
6212 reg_ebc
= result
[i
][5];
6213 reg_ec4
= result
[i
][6];
6214 reg_ecc
= result
[i
][7];
6217 if (candidate
>= 0) {
6218 reg_e94
= result
[candidate
][0];
6219 priv
->rege94
= reg_e94
;
6220 reg_e9c
= result
[candidate
][1];
6221 priv
->rege9c
= reg_e9c
;
6222 reg_ea4
= result
[candidate
][2];
6223 reg_eac
= result
[candidate
][3];
6224 reg_eb4
= result
[candidate
][4];
6225 priv
->regeb4
= reg_eb4
;
6226 reg_ebc
= result
[candidate
][5];
6227 priv
->regebc
= reg_ebc
;
6228 reg_ec4
= result
[candidate
][6];
6229 reg_ecc
= result
[candidate
][7];
6230 dev_dbg(dev
, "%s: candidate is %x\n", __func__
, candidate
);
6232 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
6233 "ecc=%x\n ", __func__
, reg_e94
, reg_e9c
,
6234 reg_ea4
, reg_eac
, reg_eb4
, reg_ebc
, reg_ec4
, reg_ecc
);
6238 reg_e94
= reg_eb4
= priv
->rege94
= priv
->regeb4
= 0x100;
6239 reg_e9c
= reg_ebc
= priv
->rege9c
= priv
->regebc
= 0x0;
6242 if (reg_e94
&& candidate
>= 0)
6243 rtl8xxxu_fill_iqk_matrix_a(priv
, path_a_ok
, result
,
6244 candidate
, (reg_ea4
== 0));
6246 if (priv
->rf_paths
> 1)
6247 rtl8xxxu_fill_iqk_matrix_b(priv
, path_b_ok
, result
,
6248 candidate
, (reg_ec4
== 0));
6250 rtl8xxxu_save_regs(priv
, rtl8723au_iqk_phy_iq_bb_reg
,
6251 priv
->bb_recovery_backup
, RTL8XXXU_BB_REGS
);
6254 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv
*priv
)
6257 u32 rf_amode
, rf_bmode
= 0, lstf
;
6259 /* Check continuous TX and Packet TX */
6260 lstf
= rtl8xxxu_read32(priv
, REG_OFDM1_LSTF
);
6262 if (lstf
& OFDM_LSTF_MASK
) {
6263 /* Disable all continuous TX */
6264 val32
= lstf
& ~OFDM_LSTF_MASK
;
6265 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, val32
);
6267 /* Read original RF mode Path A */
6268 rf_amode
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_AC
);
6270 /* Set RF mode to standby Path A */
6271 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
,
6272 (rf_amode
& 0x8ffff) | 0x10000);
6275 if (priv
->tx_paths
> 1) {
6276 rf_bmode
= rtl8xxxu_read_rfreg(priv
, RF_B
,
6279 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
,
6280 (rf_bmode
& 0x8ffff) | 0x10000);
6283 /* Deal with Packet TX case */
6284 /* block all queues */
6285 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
6288 /* Start LC calibration */
6289 if (priv
->fops
->has_s0s1
)
6290 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_S0S1
, 0xdfbe0);
6291 val32
= rtl8xxxu_read_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
);
6293 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
, val32
);
6297 if (priv
->fops
->has_s0s1
)
6298 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_S0S1
, 0xdffe0);
6300 /* Restore original parameters */
6301 if (lstf
& OFDM_LSTF_MASK
) {
6303 rtl8xxxu_write32(priv
, REG_OFDM1_LSTF
, lstf
);
6304 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_AC
, rf_amode
);
6307 if (priv
->tx_paths
> 1)
6308 rtl8xxxu_write_rfreg(priv
, RF_B
, RF6052_REG_AC
,
6310 } else /* Deal with Packet TX case */
6311 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0x00);
6314 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv
*priv
)
6321 for (i
= 0; i
< ETH_ALEN
; i
++)
6322 rtl8xxxu_write8(priv
, reg
+ i
, priv
->mac_addr
[i
]);
6327 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv
*priv
, const u8
*bssid
)
6332 dev_dbg(&priv
->udev
->dev
, "%s: (%pM)\n", __func__
, bssid
);
6336 for (i
= 0; i
< ETH_ALEN
; i
++)
6337 rtl8xxxu_write8(priv
, reg
+ i
, bssid
[i
]);
6343 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv
*priv
, u8 ampdu_factor
)
6345 u8 vals
[4] = { 0x41, 0xa8, 0x72, 0xb9 };
6349 ampdu_factor
= 1 << (ampdu_factor
+ 2);
6350 if (ampdu_factor
> max_agg
)
6351 ampdu_factor
= max_agg
;
6353 for (i
= 0; i
< 4; i
++) {
6354 if ((vals
[i
] & 0xf0) > (ampdu_factor
<< 4))
6355 vals
[i
] = (vals
[i
] & 0x0f) | (ampdu_factor
<< 4);
6357 if ((vals
[i
] & 0x0f) > ampdu_factor
)
6358 vals
[i
] = (vals
[i
] & 0xf0) | ampdu_factor
;
6360 rtl8xxxu_write8(priv
, REG_AGGLEN_LMT
+ i
, vals
[i
]);
6364 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv
*priv
, u8 density
)
6368 val8
= rtl8xxxu_read8(priv
, REG_AMPDU_MIN_SPACE
);
6371 rtl8xxxu_write8(priv
, REG_AMPDU_MIN_SPACE
, val8
);
6374 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv
*priv
)
6379 /* Start of rtl8723AU_card_enable_flow */
6380 /* Act to Cardemu sequence*/
6382 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0);
6384 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
6385 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
6386 val8
&= ~LEDCFG2_DPDT_SELECT
;
6387 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
6389 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
6390 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6392 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6394 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
6395 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6396 if ((val8
& BIT(1)) == 0)
6402 dev_warn(&priv
->udev
->dev
, "%s: Disabling MAC timed out\n",
6408 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
6409 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
6410 val8
|= SYS_ISO_ANALOG_IPS
;
6411 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
6413 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
6414 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
6415 val8
&= ~LDOA15_ENABLE
;
6416 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
6422 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv
*priv
)
6430 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0);
6432 /* Enable rising edge triggering interrupt */
6433 val16
= rtl8xxxu_read16(priv
, REG_GPIO_INTM
);
6434 val16
&= ~GPIO_INTM_EDGE_TRIG_IRQ
;
6435 rtl8xxxu_write16(priv
, REG_GPIO_INTM
, val16
);
6437 /* Release WLON reset 0x04[16]= 1*/
6438 val32
= rtl8xxxu_read32(priv
, REG_GPIO_INTM
);
6439 val32
|= APS_FSMCO_WLON_RESET
;
6440 rtl8xxxu_write32(priv
, REG_GPIO_INTM
, val32
);
6442 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
6443 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6445 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6447 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
6448 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6449 if ((val8
& BIT(1)) == 0)
6455 dev_warn(&priv
->udev
->dev
, "%s: Disabling MAC timed out\n",
6461 /* Enable BT control XTAL setting */
6462 val8
= rtl8xxxu_read8(priv
, REG_AFE_MISC
);
6463 val8
&= ~AFE_MISC_WL_XTAL_CTRL
;
6464 rtl8xxxu_write8(priv
, REG_AFE_MISC
, val8
);
6466 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
6467 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
6468 val8
|= SYS_ISO_ANALOG_IPS
;
6469 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
6471 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
6472 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
6473 val8
&= ~LDOA15_ENABLE
;
6474 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
6480 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv
*priv
)
6486 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
6489 * Poll - wait for RX packet to complete
6491 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
6492 val32
= rtl8xxxu_read32(priv
, 0x5f8);
6499 dev_warn(&priv
->udev
->dev
,
6500 "%s: RX poll timed out (0x05f8)\n", __func__
);
6505 /* Disable CCK and OFDM, clock gated */
6506 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
);
6507 val8
&= ~SYS_FUNC_BBRSTB
;
6508 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, val8
);
6512 /* Reset baseband */
6513 val8
= rtl8xxxu_read8(priv
, REG_SYS_FUNC
);
6514 val8
&= ~SYS_FUNC_BB_GLB_RSTN
;
6515 rtl8xxxu_write8(priv
, REG_SYS_FUNC
, val8
);
6518 val8
= rtl8xxxu_read8(priv
, REG_CR
);
6519 val8
= CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
;
6520 rtl8xxxu_write8(priv
, REG_CR
, val8
);
6523 val8
= rtl8xxxu_read8(priv
, REG_CR
+ 1);
6524 val8
&= ~BIT(1); /* CR_SECURITY_ENABLE */
6525 rtl8xxxu_write8(priv
, REG_CR
+ 1, val8
);
6527 /* Respond TX OK to scheduler */
6528 val8
= rtl8xxxu_read8(priv
, REG_DUAL_TSF_RST
);
6529 val8
|= DUAL_TSF_TX_OK
;
6530 rtl8xxxu_write8(priv
, REG_DUAL_TSF_RST
, val8
);
6536 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv
*priv
)
6540 /* Clear suspend enable and power down enable*/
6541 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6542 val8
&= ~(BIT(3) | BIT(7));
6543 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6545 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
6546 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 2);
6548 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 2, val8
);
6550 /* 0x04[12:11] = 11 enable WL suspend*/
6551 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6552 val8
&= ~(BIT(3) | BIT(4));
6553 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6556 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv
*priv
)
6560 /* Clear suspend enable and power down enable*/
6561 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6562 val8
&= ~(BIT(3) | BIT(4));
6563 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6566 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv
*priv
)
6572 /* disable HWPDN 0x04[15]=0*/
6573 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6575 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6577 /* disable SW LPS 0x04[10]= 0 */
6578 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6580 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6582 /* disable WL suspend*/
6583 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6584 val8
&= ~(BIT(3) | BIT(4));
6585 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6587 /* wait till 0x04[17] = 1 power ready*/
6588 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
6589 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6590 if (val32
& BIT(17))
6601 /* We should be able to optimize the following three entries into one */
6603 /* release WLON reset 0x04[16]= 1*/
6604 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
6606 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
6608 /* set, then poll until 0 */
6609 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6610 val32
|= APS_FSMCO_MAC_ENABLE
;
6611 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
6613 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
6614 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6615 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
6631 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv
*priv
)
6637 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
6638 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
6639 val8
|= LDOA15_ENABLE
;
6640 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
6642 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
6643 val8
= rtl8xxxu_read8(priv
, 0x0067);
6645 rtl8xxxu_write8(priv
, 0x0067, val8
);
6649 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
6650 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
6651 val8
&= ~SYS_ISO_ANALOG_IPS
;
6652 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
6654 /* disable SW LPS 0x04[10]= 0 */
6655 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6657 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6659 /* wait till 0x04[17] = 1 power ready*/
6660 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
6661 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6662 if (val32
& BIT(17))
6673 /* We should be able to optimize the following three entries into one */
6675 /* release WLON reset 0x04[16]= 1*/
6676 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
6678 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
6680 /* disable HWPDN 0x04[15]= 0*/
6681 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6683 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6685 /* disable WL suspend*/
6686 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6687 val8
&= ~(BIT(3) | BIT(4));
6688 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6690 /* set, then poll until 0 */
6691 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6692 val32
|= APS_FSMCO_MAC_ENABLE
;
6693 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
6695 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
6696 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6697 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
6709 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
6711 * Note: Vendor driver actually clears this bit, despite the
6712 * documentation claims it's being set!
6714 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
6715 val8
|= LEDCFG2_DPDT_SELECT
;
6716 val8
&= ~LEDCFG2_DPDT_SELECT
;
6717 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
6723 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv
*priv
)
6729 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
6730 val8
= rtl8xxxu_read8(priv
, REG_LDOA15_CTRL
);
6731 val8
|= LDOA15_ENABLE
;
6732 rtl8xxxu_write8(priv
, REG_LDOA15_CTRL
, val8
);
6734 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
6735 val8
= rtl8xxxu_read8(priv
, 0x0067);
6737 rtl8xxxu_write8(priv
, 0x0067, val8
);
6741 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
6742 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
6743 val8
&= ~SYS_ISO_ANALOG_IPS
;
6744 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
6746 /* Disable SW LPS 0x04[10]= 0 */
6747 val32
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
);
6748 val32
&= ~APS_FSMCO_SW_LPS
;
6749 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
6751 /* Wait until 0x04[17] = 1 power ready */
6752 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
6753 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6754 if (val32
& BIT(17))
6765 /* We should be able to optimize the following three entries into one */
6767 /* Release WLON reset 0x04[16]= 1*/
6768 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6769 val32
|= APS_FSMCO_WLON_RESET
;
6770 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
6772 /* Disable HWPDN 0x04[15]= 0*/
6773 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6774 val32
&= ~APS_FSMCO_HW_POWERDOWN
;
6775 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
6777 /* Disable WL suspend*/
6778 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6779 val32
&= ~(APS_FSMCO_HW_SUSPEND
| APS_FSMCO_PCIE
);
6780 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
6782 /* Set, then poll until 0 */
6783 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6784 val32
|= APS_FSMCO_MAC_ENABLE
;
6785 rtl8xxxu_write32(priv
, REG_APS_FSMCO
, val32
);
6787 for (count
= RTL8XXXU_MAX_REG_POLL
; count
; count
--) {
6788 val32
= rtl8xxxu_read32(priv
, REG_APS_FSMCO
);
6789 if ((val32
& APS_FSMCO_MAC_ENABLE
) == 0) {
6801 /* Enable WL control XTAL setting */
6802 val8
= rtl8xxxu_read8(priv
, REG_AFE_MISC
);
6803 val8
|= AFE_MISC_WL_XTAL_CTRL
;
6804 rtl8xxxu_write8(priv
, REG_AFE_MISC
, val8
);
6806 /* Enable falling edge triggering interrupt */
6807 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 1);
6809 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 1, val8
);
6811 /* Enable GPIO9 interrupt mode */
6812 val8
= rtl8xxxu_read8(priv
, REG_GPIO_IO_SEL_2
+ 1);
6814 rtl8xxxu_write8(priv
, REG_GPIO_IO_SEL_2
+ 1, val8
);
6816 /* Enable GPIO9 input mode */
6817 val8
= rtl8xxxu_read8(priv
, REG_GPIO_IO_SEL_2
);
6819 rtl8xxxu_write8(priv
, REG_GPIO_IO_SEL_2
, val8
);
6821 /* Enable HSISR GPIO[C:0] interrupt */
6822 val8
= rtl8xxxu_read8(priv
, REG_HSIMR
);
6824 rtl8xxxu_write8(priv
, REG_HSIMR
, val8
);
6826 /* Enable HSISR GPIO9 interrupt */
6827 val8
= rtl8xxxu_read8(priv
, REG_HSIMR
+ 2);
6829 rtl8xxxu_write8(priv
, REG_HSIMR
+ 2, val8
);
6831 val8
= rtl8xxxu_read8(priv
, REG_MULTI_FUNC_CTRL
);
6832 val8
|= MULTI_WIFI_HW_ROF_EN
;
6833 rtl8xxxu_write8(priv
, REG_MULTI_FUNC_CTRL
, val8
);
6835 /* For GPIO9 internal pull high setting BIT(14) */
6836 val8
= rtl8xxxu_read8(priv
, REG_MULTI_FUNC_CTRL
+ 1);
6838 rtl8xxxu_write8(priv
, REG_MULTI_FUNC_CTRL
+ 1, val8
);
6844 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv
*priv
)
6848 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
6849 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 3, 0x20);
6851 /* 0x04[12:11] = 01 enable WL suspend */
6852 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6855 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6857 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 1);
6859 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 1, val8
);
6861 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
6862 val8
= rtl8xxxu_read8(priv
, REG_GPIO_INTM
+ 2);
6864 rtl8xxxu_write8(priv
, REG_GPIO_INTM
+ 2, val8
);
6869 static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv
*priv
)
6871 struct device
*dev
= &priv
->udev
->dev
;
6875 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
6877 val32
= rtl8xxxu_read32(priv
, REG_RXPKT_NUM
);
6878 val32
|= RXPKT_NUM_RW_RELEASE_EN
;
6879 rtl8xxxu_write32(priv
, REG_RXPKT_NUM
, val32
);
6885 val32
= rtl8xxxu_read32(priv
, REG_RXPKT_NUM
);
6886 if (val32
& RXPKT_NUM_RXDMA_IDLE
) {
6892 rtl8xxxu_write16(priv
, REG_RQPN_NPQ
, 0);
6893 rtl8xxxu_write32(priv
, REG_RQPN
, 0x80000000);
6897 dev_warn(dev
, "Failed to flush FIFO\n");
6902 static void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv
*priv
)
6904 /* Fix USB interface interference issue */
6905 rtl8xxxu_write8(priv
, 0xfe40, 0xe0);
6906 rtl8xxxu_write8(priv
, 0xfe41, 0x8d);
6907 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6909 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
6910 * 8 and 5, for which I have found no documentation.
6912 rtl8xxxu_write32(priv
, REG_TXDMA_OFFSET_CHK
, 0xfd0320);
6915 * Solve too many protocol error on USB bus.
6916 * Can't do this for 8188/8192 UMC A cut parts
6918 if (!(!priv
->chip_cut
&& priv
->vendor_umc
)) {
6919 rtl8xxxu_write8(priv
, 0xfe40, 0xe6);
6920 rtl8xxxu_write8(priv
, 0xfe41, 0x94);
6921 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6923 rtl8xxxu_write8(priv
, 0xfe40, 0xe0);
6924 rtl8xxxu_write8(priv
, 0xfe41, 0x19);
6925 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6927 rtl8xxxu_write8(priv
, 0xfe40, 0xe5);
6928 rtl8xxxu_write8(priv
, 0xfe41, 0x91);
6929 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6931 rtl8xxxu_write8(priv
, 0xfe40, 0xe2);
6932 rtl8xxxu_write8(priv
, 0xfe41, 0x81);
6933 rtl8xxxu_write8(priv
, 0xfe42, 0x80);
6937 static void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv
*priv
)
6941 val32
= rtl8xxxu_read32(priv
, REG_TXDMA_OFFSET_CHK
);
6942 val32
|= TXDMA_OFFSET_DROP_DATA_EN
;
6943 rtl8xxxu_write32(priv
, REG_TXDMA_OFFSET_CHK
, val32
);
6946 static int rtl8723au_power_on(struct rtl8xxxu_priv
*priv
)
6954 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
6956 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0);
6958 rtl8723a_disabled_to_emu(priv
);
6960 ret
= rtl8723a_emu_to_active(priv
);
6965 * 0x0004[19] = 1, reset 8051
6967 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
+ 2);
6969 rtl8xxxu_write8(priv
, REG_APS_FSMCO
+ 2, val8
);
6972 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
6973 * Set CR bit10 to enable 32k calibration.
6975 val16
= rtl8xxxu_read16(priv
, REG_CR
);
6976 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
6977 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
6978 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
6979 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
6980 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
6981 rtl8xxxu_write16(priv
, REG_CR
, val16
);
6984 val32
= rtl8xxxu_read32(priv
, REG_EFUSE_CTRL
);
6985 val32
&= ~(BIT(28) | BIT(29) | BIT(30));
6986 val32
|= (0x06 << 28);
6987 rtl8xxxu_write32(priv
, REG_EFUSE_CTRL
, val32
);
6992 static int rtl8723bu_power_on(struct rtl8xxxu_priv
*priv
)
6999 rtl8723a_disabled_to_emu(priv
);
7001 ret
= rtl8723b_emu_to_active(priv
);
7006 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7007 * Set CR bit10 to enable 32k calibration.
7009 val16
= rtl8xxxu_read16(priv
, REG_CR
);
7010 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
7011 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
7012 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
7013 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
7014 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
7015 rtl8xxxu_write16(priv
, REG_CR
, val16
);
7018 * BT coexist power on settings. This is identical for 1 and 2
7021 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
+ 3, 0x20);
7023 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
7024 val16
|= SYS_FUNC_BBRSTB
| SYS_FUNC_BB_GLB_RSTN
;
7025 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
7027 rtl8xxxu_write8(priv
, REG_BT_CONTROL_8723BU
+ 1, 0x18);
7028 rtl8xxxu_write8(priv
, REG_WLAN_ACT_CONTROL_8723B
, 0x04);
7029 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
7030 /* Antenna inverse */
7031 rtl8xxxu_write8(priv
, 0xfe08, 0x01);
7033 val16
= rtl8xxxu_read16(priv
, REG_PWR_DATA
);
7034 val16
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
7035 rtl8xxxu_write16(priv
, REG_PWR_DATA
, val16
);
7037 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
7038 val32
|= LEDCFG0_DPDT_SELECT
;
7039 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
7041 val8
= rtl8xxxu_read8(priv
, REG_PAD_CTRL1
);
7042 val8
&= ~PAD_CTRL1_SW_DPDT_SEL_DATA
;
7043 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
, val8
);
7048 #ifdef CONFIG_RTL8XXXU_UNTESTED
7050 static int rtl8192cu_power_on(struct rtl8xxxu_priv
*priv
)
7057 for (i
= 100; i
; i
--) {
7058 val8
= rtl8xxxu_read8(priv
, REG_APS_FSMCO
);
7059 if (val8
& APS_FSMCO_PFM_ALDN
)
7064 pr_info("%s: Poll failed\n", __func__
);
7069 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
7071 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0);
7072 rtl8xxxu_write8(priv
, REG_SPS0_CTRL
, 0x2b);
7075 val8
= rtl8xxxu_read8(priv
, REG_LDOV12D_CTRL
);
7076 if (!(val8
& LDOV12D_ENABLE
)) {
7077 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__
, val8
);
7078 val8
|= LDOV12D_ENABLE
;
7079 rtl8xxxu_write8(priv
, REG_LDOV12D_CTRL
, val8
);
7083 val8
= rtl8xxxu_read8(priv
, REG_SYS_ISO_CTRL
);
7084 val8
&= ~SYS_ISO_MD2PP
;
7085 rtl8xxxu_write8(priv
, REG_SYS_ISO_CTRL
, val8
);
7091 val16
= rtl8xxxu_read16(priv
, REG_APS_FSMCO
);
7092 val16
|= APS_FSMCO_MAC_ENABLE
;
7093 rtl8xxxu_write16(priv
, REG_APS_FSMCO
, val16
);
7095 for (i
= 1000; i
; i
--) {
7096 val16
= rtl8xxxu_read16(priv
, REG_APS_FSMCO
);
7097 if (!(val16
& APS_FSMCO_MAC_ENABLE
))
7101 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__
);
7106 * Enable radio, GPIO, LED
7108 val16
= APS_FSMCO_HW_SUSPEND
| APS_FSMCO_ENABLE_POWERDOWN
|
7110 rtl8xxxu_write16(priv
, REG_APS_FSMCO
, val16
);
7113 * Release RF digital isolation
7115 val16
= rtl8xxxu_read16(priv
, REG_SYS_ISO_CTRL
);
7116 val16
&= ~SYS_ISO_DIOR
;
7117 rtl8xxxu_write16(priv
, REG_SYS_ISO_CTRL
, val16
);
7119 val8
= rtl8xxxu_read8(priv
, REG_APSD_CTRL
);
7120 val8
&= ~APSD_CTRL_OFF
;
7121 rtl8xxxu_write8(priv
, REG_APSD_CTRL
, val8
);
7122 for (i
= 200; i
; i
--) {
7123 val8
= rtl8xxxu_read8(priv
, REG_APSD_CTRL
);
7124 if (!(val8
& APSD_CTRL_OFF_STATUS
))
7129 pr_info("%s: APSD_CTRL poll failed\n", __func__
);
7134 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7136 val16
= rtl8xxxu_read16(priv
, REG_CR
);
7137 val16
|= CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
7138 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
| CR_PROTOCOL_ENABLE
|
7139 CR_SCHEDULE_ENABLE
| CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
;
7140 rtl8xxxu_write16(priv
, REG_CR
, val16
);
7143 * Workaround for 8188RU LNA power leakage problem.
7145 if (priv
->rtl_chip
== RTL8188C
&& priv
->hi_pa
) {
7146 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XCD_RF_PARM
);
7148 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_PARM
, val32
);
7156 * This is needed for 8723bu as well, presumable
7158 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv
*priv
)
7164 * 40Mhz crystal source, MAC 0x28[2]=0
7166 val8
= rtl8xxxu_read8(priv
, REG_AFE_PLL_CTRL
);
7168 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
, val8
);
7170 val32
= rtl8xxxu_read32(priv
, REG_AFE_CTRL4
);
7171 val32
&= 0xfffffc7f;
7172 rtl8xxxu_write32(priv
, REG_AFE_CTRL4
, val32
);
7176 * AFE PLL KVCO selection, MAC 0x28[6]=1
7178 val8
= rtl8xxxu_read8(priv
, REG_AFE_PLL_CTRL
);
7180 rtl8xxxu_write8(priv
, REG_AFE_PLL_CTRL
, val8
);
7183 * AFE PLL KVCO selection, MAC 0x78[21]=0
7185 val32
= rtl8xxxu_read32(priv
, REG_AFE_CTRL4
);
7186 val32
&= 0xffdfffff;
7187 rtl8xxxu_write32(priv
, REG_AFE_CTRL4
, val32
);
7190 static int rtl8192eu_power_on(struct rtl8xxxu_priv
*priv
)
7198 val32
= rtl8xxxu_read32(priv
, REG_SYS_CFG
);
7199 if (val32
& SYS_CFG_SPS_LDO_SEL
) {
7200 rtl8xxxu_write8(priv
, REG_LDO_SW_CTRL
, 0xc3);
7203 * Raise 1.2V voltage
7205 val32
= rtl8xxxu_read32(priv
, REG_8192E_LDOV12_CTRL
);
7206 val32
&= 0xff0fffff;
7207 val32
|= 0x00500000;
7208 rtl8xxxu_write32(priv
, REG_8192E_LDOV12_CTRL
, val32
);
7209 rtl8xxxu_write8(priv
, REG_LDO_SW_CTRL
, 0x83);
7213 * Adjust AFE before enabling PLL
7215 rtl8192e_crystal_afe_adjust(priv
);
7216 rtl8192e_disabled_to_emu(priv
);
7218 ret
= rtl8192e_emu_to_active(priv
);
7222 rtl8xxxu_write16(priv
, REG_CR
, 0x0000);
7225 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7226 * Set CR bit10 to enable 32k calibration.
7228 val16
= rtl8xxxu_read16(priv
, REG_CR
);
7229 val16
|= (CR_HCI_TXDMA_ENABLE
| CR_HCI_RXDMA_ENABLE
|
7230 CR_TXDMA_ENABLE
| CR_RXDMA_ENABLE
|
7231 CR_PROTOCOL_ENABLE
| CR_SCHEDULE_ENABLE
|
7232 CR_MAC_TX_ENABLE
| CR_MAC_RX_ENABLE
|
7233 CR_SECURITY_ENABLE
| CR_CALTIMER_ENABLE
);
7234 rtl8xxxu_write16(priv
, REG_CR
, val16
);
7240 static void rtl8xxxu_power_off(struct rtl8xxxu_priv
*priv
)
7247 * Workaround for 8188RU LNA power leakage problem.
7249 if (priv
->rtl_chip
== RTL8188C
&& priv
->hi_pa
) {
7250 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_XCD_RF_PARM
);
7252 rtl8xxxu_write32(priv
, REG_FPGA0_XCD_RF_PARM
, val32
);
7255 rtl8xxxu_flush_fifo(priv
);
7257 rtl8xxxu_active_to_lps(priv
);
7260 rtl8xxxu_write8(priv
, REG_RF_CTRL
, 0x00);
7262 /* Reset Firmware if running in RAM */
7263 if (rtl8xxxu_read8(priv
, REG_MCU_FW_DL
) & MCU_FW_RAM_SEL
)
7264 rtl8xxxu_firmware_self_reset(priv
);
7267 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
7268 val16
&= ~SYS_FUNC_CPU_ENABLE
;
7269 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
7271 /* Reset MCU ready status */
7272 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
7274 rtl8xxxu_active_to_emu(priv
);
7275 rtl8xxxu_emu_to_disabled(priv
);
7277 /* Reset MCU IO Wrapper */
7278 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
7280 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
7282 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
+ 1);
7284 rtl8xxxu_write8(priv
, REG_RSV_CTRL
+ 1, val8
);
7286 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
7287 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, 0x0e);
7290 static void rtl8723bu_power_off(struct rtl8xxxu_priv
*priv
)
7295 rtl8xxxu_flush_fifo(priv
);
7298 * Disable TX report timer
7300 val8
= rtl8xxxu_read8(priv
, REG_TX_REPORT_CTRL
);
7301 val8
&= ~TX_REPORT_CTRL_TIMER_ENABLE
;
7302 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
, val8
);
7304 rtl8xxxu_write16(priv
, REG_CR
, 0x0000);
7306 rtl8xxxu_active_to_lps(priv
);
7308 /* Reset Firmware if running in RAM */
7309 if (rtl8xxxu_read8(priv
, REG_MCU_FW_DL
) & MCU_FW_RAM_SEL
)
7310 rtl8xxxu_firmware_self_reset(priv
);
7313 val16
= rtl8xxxu_read16(priv
, REG_SYS_FUNC
);
7314 val16
&= ~SYS_FUNC_CPU_ENABLE
;
7315 rtl8xxxu_write16(priv
, REG_SYS_FUNC
, val16
);
7317 /* Reset MCU ready status */
7318 rtl8xxxu_write8(priv
, REG_MCU_FW_DL
, 0x00);
7320 rtl8723bu_active_to_emu(priv
);
7321 rtl8xxxu_emu_to_disabled(priv
);
7325 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv
*priv
,
7326 u8 arg1
, u8 arg2
, u8 arg3
, u8 arg4
, u8 arg5
)
7330 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
7331 h2c
.b_type_dma
.cmd
= H2C_8723B_B_TYPE_TDMA
;
7332 h2c
.b_type_dma
.data1
= arg1
;
7333 h2c
.b_type_dma
.data2
= arg2
;
7334 h2c
.b_type_dma
.data3
= arg3
;
7335 h2c
.b_type_dma
.data4
= arg4
;
7336 h2c
.b_type_dma
.data5
= arg5
;
7337 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.b_type_dma
));
7341 static void rtl8723b_enable_rf(struct rtl8xxxu_priv
*priv
)
7348 * No indication anywhere as to what 0x0790 does. The 2 antenna
7349 * vendor code preserves bits 6-7 here.
7351 rtl8xxxu_write8(priv
, 0x0790, 0x05);
7353 * 0x0778 seems to be related to enabling the number of antennas
7354 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
7355 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
7357 rtl8xxxu_write8(priv
, 0x0778, 0x01);
7359 val8
= rtl8xxxu_read8(priv
, REG_GPIO_MUXCFG
);
7361 rtl8xxxu_write8(priv
, REG_GPIO_MUXCFG
, val8
);
7363 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_IQADJ_G1
, 0x780);
7365 rtl8723bu_write_btreg(priv
, 0x3c, 0x15); /* BT TRx Mask on */
7368 * Set BT grant to low
7370 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
7371 h2c
.bt_grant
.cmd
= H2C_8723B_BT_GRANT
;
7372 h2c
.bt_grant
.data
= 0;
7373 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_grant
));
7376 * WLAN action by PTA
7378 rtl8xxxu_write8(priv
, REG_WLAN_ACT_CONTROL_8723B
, 0x04);
7381 * BT select S0/S1 controlled by WiFi
7383 val8
= rtl8xxxu_read8(priv
, 0x0067);
7385 rtl8xxxu_write8(priv
, 0x0067, val8
);
7387 val32
= rtl8xxxu_read32(priv
, REG_PWR_DATA
);
7388 val32
|= PWR_DATA_EEPRPAD_RFE_CTRL_EN
;
7389 rtl8xxxu_write32(priv
, REG_PWR_DATA
, val32
);
7392 * Bits 6/7 are marked in/out ... but for what?
7394 rtl8xxxu_write8(priv
, 0x0974, 0xff);
7396 val32
= rtl8xxxu_read32(priv
, REG_RFE_BUFFER
);
7397 val32
|= (BIT(0) | BIT(1));
7398 rtl8xxxu_write32(priv
, REG_RFE_BUFFER
, val32
);
7400 rtl8xxxu_write8(priv
, REG_RFE_CTRL_ANTA_SRC
, 0x77);
7402 val32
= rtl8xxxu_read32(priv
, REG_LEDCFG0
);
7405 rtl8xxxu_write32(priv
, REG_LEDCFG0
, val32
);
7408 * Fix external switch Main->S1, Aux->S0
7410 val8
= rtl8xxxu_read8(priv
, REG_PAD_CTRL1
);
7412 rtl8xxxu_write8(priv
, REG_PAD_CTRL1
, val8
);
7414 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
7415 h2c
.ant_sel_rsv
.cmd
= H2C_8723B_ANT_SEL_RSV
;
7416 h2c
.ant_sel_rsv
.ant_inverse
= 1;
7417 h2c
.ant_sel_rsv
.int_switch_type
= 0;
7418 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ant_sel_rsv
));
7421 * 0x280, 0x00, 0x200, 0x80 - not clear
7423 rtl8xxxu_write32(priv
, REG_S0S1_PATH_SWITCH
, 0x00);
7426 * Software control, antenna at WiFi side
7429 rtl8723bu_set_ps_tdma(priv
, 0x08, 0x00, 0x00, 0x00, 0x00);
7432 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE1
, 0x55555555);
7433 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE2
, 0x55555555);
7434 rtl8xxxu_write32(priv
, REG_BT_COEX_TABLE3
, 0x00ffffff);
7435 rtl8xxxu_write8(priv
, REG_BT_COEX_TABLE4
, 0x03);
7437 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
7438 h2c
.bt_info
.cmd
= H2C_8723B_BT_INFO
;
7439 h2c
.bt_info
.data
= BIT(0);
7440 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.bt_info
));
7442 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
7443 h2c
.ignore_wlan
.cmd
= H2C_8723B_BT_IGNORE_WLANACT
;
7444 h2c
.ignore_wlan
.data
= 0;
7445 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ignore_wlan
));
7448 static void rtl8723b_disable_rf(struct rtl8xxxu_priv
*priv
)
7452 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
7454 val32
= rtl8xxxu_read32(priv
, REG_RX_WAIT_CCA
);
7455 val32
&= ~(BIT(22) | BIT(23));
7456 rtl8xxxu_write32(priv
, REG_RX_WAIT_CCA
, val32
);
7459 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv
*priv
)
7465 * For now simply disable RX aggregation
7467 agg_ctrl
= rtl8xxxu_read8(priv
, REG_TRXDMA_CTRL
);
7468 agg_ctrl
&= ~TRXDMA_CTRL_RXDMA_AGG_EN
;
7470 agg_rx
= rtl8xxxu_read32(priv
, REG_RXDMA_AGG_PG_TH
);
7471 agg_rx
&= ~RXDMA_USB_AGG_ENABLE
;
7474 rtl8xxxu_write8(priv
, REG_TRXDMA_CTRL
, agg_ctrl
);
7475 rtl8xxxu_write32(priv
, REG_RXDMA_AGG_PG_TH
, agg_rx
);
7478 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv
*priv
)
7482 /* Time duration for NHM unit: 4us, 0x2710=40ms */
7483 rtl8xxxu_write16(priv
, REG_NHM_TIMER_8723B
+ 2, 0x2710);
7484 rtl8xxxu_write16(priv
, REG_NHM_TH9_TH10_8723B
+ 2, 0xffff);
7485 rtl8xxxu_write32(priv
, REG_NHM_TH3_TO_TH0_8723B
, 0xffffff52);
7486 rtl8xxxu_write32(priv
, REG_NHM_TH7_TO_TH4_8723B
, 0xffffffff);
7488 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_IQK
);
7490 rtl8xxxu_write32(priv
, REG_FPGA0_IQK
, val32
);
7492 val32
= rtl8xxxu_read32(priv
, REG_NHM_TH9_TH10_8723B
);
7493 val32
|= BIT(8) | BIT(9) | BIT(10);
7494 rtl8xxxu_write32(priv
, REG_NHM_TH9_TH10_8723B
, val32
);
7495 /* Max power amongst all RX antennas */
7496 val32
= rtl8xxxu_read32(priv
, REG_OFDM0_FA_RSTC
);
7498 rtl8xxxu_write32(priv
, REG_OFDM0_FA_RSTC
, val32
);
7501 static void rtl8xxxu_old_init_queue_reserved_page(struct rtl8xxxu_priv
*priv
)
7506 if (priv
->ep_tx_normal_queue
)
7507 val8
= TX_PAGE_NUM_NORM_PQ
;
7511 rtl8xxxu_write8(priv
, REG_RQPN_NPQ
, val8
);
7513 val32
= (TX_PAGE_NUM_PUBQ
<< RQPN_PUB_PQ_SHIFT
) | RQPN_LOAD
;
7515 if (priv
->ep_tx_high_queue
)
7516 val32
|= (TX_PAGE_NUM_HI_PQ
<< RQPN_HI_PQ_SHIFT
);
7517 if (priv
->ep_tx_low_queue
)
7518 val32
|= (TX_PAGE_NUM_LO_PQ
<< RQPN_LO_PQ_SHIFT
);
7520 rtl8xxxu_write32(priv
, REG_RQPN
, val32
);
7523 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv
*priv
)
7525 struct rtl8xxxu_fileops
*fops
= priv
->fops
;
7526 u32 hq
, lq
, nq
, eq
, pubq
;
7535 if (priv
->ep_tx_high_queue
)
7536 hq
= fops
->page_num_hi
;
7537 if (priv
->ep_tx_low_queue
)
7538 lq
= fops
->page_num_lo
;
7539 if (priv
->ep_tx_normal_queue
)
7540 nq
= fops
->page_num_norm
;
7542 val32
= (nq
<< RQPN_NPQ_SHIFT
) | (eq
<< RQPN_EPQ_SHIFT
);
7543 rtl8xxxu_write32(priv
, REG_RQPN_NPQ
, val32
);
7545 pubq
= fops
->total_page_num
- hq
- lq
- nq
;
7548 val32
|= (hq
<< RQPN_HI_PQ_SHIFT
);
7549 val32
|= (lq
<< RQPN_LO_PQ_SHIFT
);
7550 val32
|= (pubq
<< RQPN_PUB_PQ_SHIFT
);
7552 rtl8xxxu_write32(priv
, REG_RQPN
, val32
);
7555 static int rtl8xxxu_init_device(struct ieee80211_hw
*hw
)
7557 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7558 struct device
*dev
= &priv
->udev
->dev
;
7559 struct rtl8xxxu_rfregval
*rftable
;
7566 /* Check if MAC is already powered on */
7567 val8
= rtl8xxxu_read8(priv
, REG_CR
);
7570 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
7571 * initialized. First MAC returns 0xea, second MAC returns 0x00
7578 ret
= priv
->fops
->power_on(priv
);
7580 dev_warn(dev
, "%s: Failed power on\n", __func__
);
7585 if (priv
->fops
->total_page_num
)
7586 rtl8xxxu_init_queue_reserved_page(priv
);
7588 rtl8xxxu_old_init_queue_reserved_page(priv
);
7591 ret
= rtl8xxxu_init_queue_priority(priv
);
7592 dev_dbg(dev
, "%s: init_queue_priority %i\n", __func__
, ret
);
7597 * Set RX page boundary
7599 rtl8xxxu_write16(priv
, REG_TRXFF_BNDY
+ 2, priv
->fops
->trxff_boundary
);
7601 ret
= rtl8xxxu_download_firmware(priv
);
7602 dev_dbg(dev
, "%s: download_fiwmare %i\n", __func__
, ret
);
7605 ret
= rtl8xxxu_start_firmware(priv
);
7606 dev_dbg(dev
, "%s: start_fiwmare %i\n", __func__
, ret
);
7610 if (priv
->fops
->phy_init_antenna_selection
)
7611 priv
->fops
->phy_init_antenna_selection(priv
);
7613 ret
= rtl8xxxu_init_mac(priv
);
7615 dev_dbg(dev
, "%s: init_mac %i\n", __func__
, ret
);
7619 ret
= rtl8xxxu_init_phy_bb(priv
);
7620 dev_dbg(dev
, "%s: init_phy_bb %i\n", __func__
, ret
);
7624 switch(priv
->rtl_chip
) {
7626 rftable
= rtl8723au_radioa_1t_init_table
;
7627 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
7629 /* Reduce 80M spur */
7630 rtl8xxxu_write32(priv
, REG_AFE_XTAL_CTRL
, 0x0381808d);
7631 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff83);
7632 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff82);
7633 rtl8xxxu_write32(priv
, REG_AFE_PLL_CTRL
, 0xf0ffff83);
7636 rftable
= rtl8723bu_radioa_1t_init_table
;
7637 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
7641 rtl8xxxu_write_rfreg(priv
, RF_A
, 0xb0, 0xdfbe0);
7642 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_MODE_AG
, 0x8c01);
7644 rtl8xxxu_write_rfreg(priv
, RF_A
, 0xb0, 0xdffe0);
7648 rftable
= rtl8188ru_radioa_1t_highpa_table
;
7650 rftable
= rtl8192cu_radioa_1t_init_table
;
7651 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
7654 rftable
= rtl8192cu_radioa_1t_init_table
;
7655 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
7658 rftable
= rtl8192cu_radioa_2t_init_table
;
7659 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
7662 rftable
= rtl8192cu_radiob_2t_init_table
;
7663 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_B
);
7666 rftable
= rtl8192eu_radioa_init_table
;
7667 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_A
);
7670 rftable
= rtl8192eu_radiob_init_table
;
7671 ret
= rtl8xxxu_init_phy_rf(priv
, rftable
, RF_B
);
7680 /* RFSW Control - clear bit 14 ?? */
7681 if (priv
->rtl_chip
!= RTL8723B
&& priv
->rtl_chip
!= RTL8192E
)
7682 rtl8xxxu_write32(priv
, REG_FPGA0_TX_INFO
, 0x00000003);
7684 val32
= FPGA0_RF_TRSW
| FPGA0_RF_TRSWB
| FPGA0_RF_ANTSW
|
7685 FPGA0_RF_ANTSWB
| FPGA0_RF_PAPE
|
7686 ((FPGA0_RF_ANTSW
| FPGA0_RF_ANTSWB
| FPGA0_RF_PAPE
) <<
7687 FPGA0_RF_BD_CTRL_SHIFT
);
7689 rtl8xxxu_write32(priv
, REG_FPGA0_XAB_RF_SW_CTRL
, val32
);
7690 /* 0x860[6:5]= 00 - why? - this sets antenna B */
7691 if (priv
->rtl_chip
!= RTL8192E
)
7692 rtl8xxxu_write32(priv
, REG_FPGA0_XA_RF_INT_OE
, 0x66f60210);
7696 * Set TX buffer boundary
7698 if (priv
->rtl_chip
== RTL8192E
)
7699 val8
= TX_TOTAL_PAGE_NUM_8192E
+ 1;
7701 val8
= TX_TOTAL_PAGE_NUM
+ 1;
7703 if (priv
->rtl_chip
== RTL8723B
)
7706 rtl8xxxu_write8(priv
, REG_TXPKTBUF_BCNQ_BDNY
, val8
);
7707 rtl8xxxu_write8(priv
, REG_TXPKTBUF_MGQ_BDNY
, val8
);
7708 rtl8xxxu_write8(priv
, REG_TXPKTBUF_WMAC_LBK_BF_HD
, val8
);
7709 rtl8xxxu_write8(priv
, REG_TRXFF_BNDY
, val8
);
7710 rtl8xxxu_write8(priv
, REG_TDECTRL
+ 1, val8
);
7714 * The vendor drivers set PBP for all devices, except 8192e.
7715 * There is no explanation for this in any of the sources.
7717 val8
= (priv
->fops
->pbp_rx
<< PBP_PAGE_SIZE_RX_SHIFT
) |
7718 (priv
->fops
->pbp_tx
<< PBP_PAGE_SIZE_TX_SHIFT
);
7719 if (priv
->rtl_chip
!= RTL8192E
)
7720 rtl8xxxu_write8(priv
, REG_PBP
, val8
);
7722 dev_dbg(dev
, "%s: macpower %i\n", __func__
, macpower
);
7724 ret
= priv
->fops
->llt_init(priv
, TX_TOTAL_PAGE_NUM
);
7726 dev_warn(dev
, "%s: LLT table init failed\n", __func__
);
7731 * Chip specific quirks
7733 priv
->fops
->usb_quirks(priv
);
7736 * Presumably this is for 8188EU as well
7737 * Enable TX report and TX report timer
7739 if (priv
->rtl_chip
== RTL8723B
) {
7740 val8
= rtl8xxxu_read8(priv
, REG_TX_REPORT_CTRL
);
7741 val8
|= TX_REPORT_CTRL_TIMER_ENABLE
;
7742 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
, val8
);
7743 /* Set MAX RPT MACID */
7744 rtl8xxxu_write8(priv
, REG_TX_REPORT_CTRL
+ 1, 0x02);
7745 /* TX report Timer. Unit: 32us */
7746 rtl8xxxu_write16(priv
, REG_TX_REPORT_TIME
, 0xcdf0);
7749 val8
= rtl8xxxu_read8(priv
, 0xa3);
7751 rtl8xxxu_write8(priv
, 0xa3, val8
);
7756 * Unit in 8 bytes, not obvious what it is used for
7758 rtl8xxxu_write8(priv
, REG_RX_DRVINFO_SZ
, 4);
7760 if (priv
->rtl_chip
== RTL8192E
) {
7761 rtl8xxxu_write32(priv
, REG_HIMR0
, 0x00);
7762 rtl8xxxu_write32(priv
, REG_HIMR1
, 0x00);
7765 * Enable all interrupts - not obvious USB needs to do this
7767 rtl8xxxu_write32(priv
, REG_HISR
, 0xffffffff);
7768 rtl8xxxu_write32(priv
, REG_HIMR
, 0xffffffff);
7771 rtl8xxxu_set_mac(priv
);
7772 rtl8xxxu_set_linktype(priv
, NL80211_IFTYPE_STATION
);
7775 * Configure initial WMAC settings
7777 val32
= RCR_ACCEPT_PHYS_MATCH
| RCR_ACCEPT_MCAST
| RCR_ACCEPT_BCAST
|
7778 RCR_ACCEPT_MGMT_FRAME
| RCR_HTC_LOC_CTRL
|
7779 RCR_APPEND_PHYSTAT
| RCR_APPEND_ICV
| RCR_APPEND_MIC
;
7780 rtl8xxxu_write32(priv
, REG_RCR
, val32
);
7783 * Accept all multicast
7785 rtl8xxxu_write32(priv
, REG_MAR
, 0xffffffff);
7786 rtl8xxxu_write32(priv
, REG_MAR
+ 4, 0xffffffff);
7789 * Init adaptive controls
7791 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
7792 val32
&= ~RESPONSE_RATE_BITMAP_ALL
;
7793 val32
|= RESPONSE_RATE_RRSR_CCK_ONLY_1M
;
7794 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
7796 /* CCK = 0x0a, OFDM = 0x10 */
7797 rtl8xxxu_set_spec_sifs(priv
, 0x10, 0x10);
7798 rtl8xxxu_set_retry(priv
, 0x30, 0x30);
7799 rtl8xxxu_set_spec_sifs(priv
, 0x0a, 0x10);
7804 rtl8xxxu_write16(priv
, REG_MAC_SPEC_SIFS
, 0x100a);
7807 rtl8xxxu_write16(priv
, REG_SIFS_CCK
, 0x100a);
7810 rtl8xxxu_write16(priv
, REG_SIFS_OFDM
, 0x100a);
7813 rtl8xxxu_write32(priv
, REG_EDCA_BE_PARAM
, 0x005ea42b);
7814 rtl8xxxu_write32(priv
, REG_EDCA_BK_PARAM
, 0x0000a44f);
7815 rtl8xxxu_write32(priv
, REG_EDCA_VI_PARAM
, 0x005ea324);
7816 rtl8xxxu_write32(priv
, REG_EDCA_VO_PARAM
, 0x002fa226);
7818 /* Set data auto rate fallback retry count */
7819 rtl8xxxu_write32(priv
, REG_DARFRC
, 0x00000000);
7820 rtl8xxxu_write32(priv
, REG_DARFRC
+ 4, 0x10080404);
7821 rtl8xxxu_write32(priv
, REG_RARFRC
, 0x04030201);
7822 rtl8xxxu_write32(priv
, REG_RARFRC
+ 4, 0x08070605);
7824 val8
= rtl8xxxu_read8(priv
, REG_FWHW_TXQ_CTRL
);
7825 val8
|= FWHW_TXQ_CTRL_AMPDU_RETRY
;
7826 rtl8xxxu_write8(priv
, REG_FWHW_TXQ_CTRL
, val8
);
7828 /* Set ACK timeout */
7829 rtl8xxxu_write8(priv
, REG_ACKTO
, 0x40);
7832 * Initialize beacon parameters
7834 val16
= BEACON_DISABLE_TSF_UPDATE
| (BEACON_DISABLE_TSF_UPDATE
<< 8);
7835 rtl8xxxu_write16(priv
, REG_BEACON_CTRL
, val16
);
7836 rtl8xxxu_write16(priv
, REG_TBTT_PROHIBIT
, 0x6404);
7837 rtl8xxxu_write8(priv
, REG_DRIVER_EARLY_INT
, DRIVER_EARLY_INT_TIME
);
7838 rtl8xxxu_write8(priv
, REG_BEACON_DMA_TIME
, BEACON_DMA_ATIME_INT_TIME
);
7839 rtl8xxxu_write16(priv
, REG_BEACON_TCFG
, 0x660F);
7842 * Initialize burst parameters
7844 if (priv
->rtl_chip
== RTL8723B
) {
7846 * For USB high speed set 512B packets
7848 val8
= rtl8xxxu_read8(priv
, REG_RXDMA_PRO_8723B
);
7849 val8
&= ~(BIT(4) | BIT(5));
7851 val8
|= BIT(1) | BIT(2) | BIT(3);
7852 rtl8xxxu_write8(priv
, REG_RXDMA_PRO_8723B
, val8
);
7855 * For USB high speed set 512B packets
7857 val8
= rtl8xxxu_read8(priv
, REG_HT_SINGLE_AMPDU_8723B
);
7859 rtl8xxxu_write8(priv
, REG_HT_SINGLE_AMPDU_8723B
, val8
);
7861 rtl8xxxu_write16(priv
, REG_MAX_AGGR_NUM
, 0x0c14);
7862 rtl8xxxu_write8(priv
, REG_AMPDU_MAX_TIME_8723B
, 0x5e);
7863 rtl8xxxu_write32(priv
, REG_AGGLEN_LMT
, 0xffffffff);
7864 rtl8xxxu_write8(priv
, REG_RX_PKT_LIMIT
, 0x18);
7865 rtl8xxxu_write8(priv
, REG_PIFS
, 0x00);
7866 rtl8xxxu_write8(priv
, REG_USTIME_TSF_8723B
, 0x50);
7867 rtl8xxxu_write8(priv
, REG_USTIME_EDCA
, 0x50);
7869 val8
= rtl8xxxu_read8(priv
, REG_RSV_CTRL
);
7870 val8
|= BIT(5) | BIT(6);
7871 rtl8xxxu_write8(priv
, REG_RSV_CTRL
, val8
);
7874 if (priv
->fops
->init_aggregation
)
7875 priv
->fops
->init_aggregation(priv
);
7878 * Enable CCK and OFDM block
7880 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
7881 val32
|= (FPGA_RF_MODE_CCK
| FPGA_RF_MODE_OFDM
);
7882 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
7885 * Invalidate all CAM entries - bit 30 is undocumented
7887 rtl8xxxu_write32(priv
, REG_CAM_CMD
, CAM_CMD_POLLING
| BIT(30));
7890 * Start out with default power levels for channel 6, 20MHz
7892 priv
->fops
->set_tx_power(priv
, 1, false);
7894 /* Let the 8051 take control of antenna setting */
7895 if (priv
->rtl_chip
!= RTL8192E
) {
7896 val8
= rtl8xxxu_read8(priv
, REG_LEDCFG2
);
7897 val8
|= LEDCFG2_DPDT_SELECT
;
7898 rtl8xxxu_write8(priv
, REG_LEDCFG2
, val8
);
7901 rtl8xxxu_write8(priv
, REG_HWSEQ_CTRL
, 0xff);
7903 /* Disable BAR - not sure if this has any effect on USB */
7904 rtl8xxxu_write32(priv
, REG_BAR_MODE_CTRL
, 0x0201ffff);
7906 rtl8xxxu_write16(priv
, REG_FAST_EDCA_CTRL
, 0);
7908 if (priv
->fops
->init_statistics
)
7909 priv
->fops
->init_statistics(priv
);
7911 if (priv
->rtl_chip
== RTL8192E
) {
7913 * 0x4c6[3] 1: RTS BW = Data BW
7914 * 0: RTS BW depends on CCA / secondary CCA result.
7916 val8
= rtl8xxxu_read8(priv
, REG_QUEUE_CTRL
);
7918 rtl8xxxu_write8(priv
, REG_QUEUE_CTRL
, val8
);
7920 * Reset USB mode switch setting
7922 rtl8xxxu_write8(priv
, REG_ACLK_MON
, 0x00);
7925 rtl8723a_phy_lc_calibrate(priv
);
7927 priv
->fops
->phy_iq_calibrate(priv
);
7930 * This should enable thermal meter
7932 if (priv
->fops
->tx_desc_size
== sizeof(struct rtl8xxxu_txdesc40
))
7933 rtl8xxxu_write_rfreg(priv
,
7934 RF_A
, RF6052_REG_T_METER_8723B
, 0x37cf8);
7936 rtl8xxxu_write_rfreg(priv
, RF_A
, RF6052_REG_T_METER
, 0x60);
7938 /* Set NAV_UPPER to 30000us */
7939 val8
= ((30000 + NAV_UPPER_UNIT
- 1) / NAV_UPPER_UNIT
);
7940 rtl8xxxu_write8(priv
, REG_NAV_UPPER
, val8
);
7942 if (priv
->rtl_chip
== RTL8723A
) {
7944 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
7945 * but we need to find root cause.
7946 * This is 8723au only.
7948 val32
= rtl8xxxu_read32(priv
, REG_FPGA0_RF_MODE
);
7949 if ((val32
& 0xff000000) != 0x83000000) {
7950 val32
|= FPGA_RF_MODE_CCK
;
7951 rtl8xxxu_write32(priv
, REG_FPGA0_RF_MODE
, val32
);
7953 } else if (priv
->rtl_chip
== RTL8192E
) {
7954 rtl8xxxu_write8(priv
, REG_USB_HRPWM
, 0x00);
7957 val32
= rtl8xxxu_read32(priv
, REG_FWHW_TXQ_CTRL
);
7958 val32
|= FWHW_TXQ_CTRL_XMIT_MGMT_ACK
;
7959 /* ack for xmit mgmt frames. */
7960 rtl8xxxu_write32(priv
, REG_FWHW_TXQ_CTRL
, val32
);
7962 if (priv
->rtl_chip
== RTL8192E
) {
7964 * Fix LDPC rx hang issue.
7966 val32
= rtl8xxxu_read32(priv
, REG_AFE_MISC
);
7967 rtl8xxxu_write8(priv
, REG_8192E_LDOV12_CTRL
, 0x75);
7968 val32
&= 0xfff00fff;
7969 val32
|= 0x0007e000;
7970 rtl8xxxu_write32(priv
, REG_8192E_LDOV12_CTRL
, val32
);
7976 static void rtl8xxxu_disable_device(struct ieee80211_hw
*hw
)
7978 struct rtl8xxxu_priv
*priv
= hw
->priv
;
7980 priv
->fops
->power_off(priv
);
7983 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv
*priv
,
7984 struct ieee80211_key_conf
*key
, const u8
*mac
)
7986 u32 cmd
, val32
, addr
, ctrl
;
7987 int j
, i
, tmp_debug
;
7989 tmp_debug
= rtl8xxxu_debug
;
7990 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_KEY
)
7991 rtl8xxxu_debug
|= RTL8XXXU_DEBUG_REG_WRITE
;
7994 * This is a bit of a hack - the lower bits of the cipher
7995 * suite selector happens to match the cipher index in the CAM
7997 addr
= key
->keyidx
<< CAM_CMD_KEY_SHIFT
;
7998 ctrl
= (key
->cipher
& 0x0f) << 2 | key
->keyidx
| CAM_WRITE_VALID
;
8000 for (j
= 5; j
>= 0; j
--) {
8003 val32
= ctrl
| (mac
[0] << 16) | (mac
[1] << 24);
8006 val32
= mac
[2] | (mac
[3] << 8) |
8007 (mac
[4] << 16) | (mac
[5] << 24);
8011 val32
= key
->key
[i
] | (key
->key
[i
+ 1] << 8) |
8012 key
->key
[i
+ 2] << 16 | key
->key
[i
+ 3] << 24;
8016 rtl8xxxu_write32(priv
, REG_CAM_WRITE
, val32
);
8017 cmd
= CAM_CMD_POLLING
| CAM_CMD_WRITE
| (addr
+ j
);
8018 rtl8xxxu_write32(priv
, REG_CAM_CMD
, cmd
);
8022 rtl8xxxu_debug
= tmp_debug
;
8025 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw
*hw
,
8026 struct ieee80211_vif
*vif
, const u8
*mac
)
8028 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8031 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
8032 val8
|= BEACON_DISABLE_TSF_UPDATE
;
8033 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
8036 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw
*hw
,
8037 struct ieee80211_vif
*vif
)
8039 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8042 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
8043 val8
&= ~BEACON_DISABLE_TSF_UPDATE
;
8044 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
8047 static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv
*priv
,
8048 u32 ramask
, int sgi
)
8052 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
8054 h2c
.ramask
.cmd
= H2C_SET_RATE_MASK
;
8055 h2c
.ramask
.mask_lo
= cpu_to_le16(ramask
& 0xffff);
8056 h2c
.ramask
.mask_hi
= cpu_to_le16(ramask
>> 16);
8058 h2c
.ramask
.arg
= 0x80;
8060 h2c
.ramask
.arg
|= 0x20;
8062 dev_dbg(&priv
->udev
->dev
, "%s: rate mask %08x, arg %02x, size %zi\n",
8063 __func__
, ramask
, h2c
.ramask
.arg
, sizeof(h2c
.ramask
));
8064 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.ramask
));
8067 static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv
*priv
,
8068 u32 ramask
, int sgi
)
8073 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
8075 h2c
.b_macid_cfg
.cmd
= H2C_8723B_MACID_CFG_RAID
;
8076 h2c
.b_macid_cfg
.ramask0
= ramask
& 0xff;
8077 h2c
.b_macid_cfg
.ramask1
= (ramask
>> 8) & 0xff;
8078 h2c
.b_macid_cfg
.ramask2
= (ramask
>> 16) & 0xff;
8079 h2c
.b_macid_cfg
.ramask3
= (ramask
>> 24) & 0xff;
8081 h2c
.ramask
.arg
= 0x80;
8082 h2c
.b_macid_cfg
.data1
= 0;
8084 h2c
.b_macid_cfg
.data1
|= BIT(7);
8086 h2c
.b_macid_cfg
.data2
= bw
;
8088 dev_dbg(&priv
->udev
->dev
, "%s: rate mask %08x, arg %02x, size %zi\n",
8089 __func__
, ramask
, h2c
.ramask
.arg
, sizeof(h2c
.b_macid_cfg
));
8090 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.b_macid_cfg
));
8093 static void rtl8723au_report_connect(struct rtl8xxxu_priv
*priv
,
8094 u8 macid
, bool connect
)
8098 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
8100 h2c
.joinbss
.cmd
= H2C_JOIN_BSS_REPORT
;
8103 h2c
.joinbss
.data
= H2C_JOIN_BSS_CONNECT
;
8105 h2c
.joinbss
.data
= H2C_JOIN_BSS_DISCONNECT
;
8107 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.joinbss
));
8110 static void rtl8723bu_report_connect(struct rtl8xxxu_priv
*priv
,
8111 u8 macid
, bool connect
)
8115 memset(&h2c
, 0, sizeof(struct h2c_cmd
));
8117 h2c
.media_status_rpt
.cmd
= H2C_8723B_MEDIA_STATUS_RPT
;
8119 h2c
.media_status_rpt
.parm
|= BIT(0);
8121 h2c
.media_status_rpt
.parm
&= ~BIT(0);
8123 rtl8723a_h2c_cmd(priv
, &h2c
, sizeof(h2c
.media_status_rpt
));
8126 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv
*priv
, u32 rate_cfg
)
8131 rate_cfg
&= RESPONSE_RATE_BITMAP_ALL
;
8133 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
8134 val32
&= ~RESPONSE_RATE_BITMAP_ALL
;
8136 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
8138 dev_dbg(&priv
->udev
->dev
, "%s: rates %08x\n", __func__
, rate_cfg
);
8141 rate_cfg
= (rate_cfg
>> 1);
8144 rtl8xxxu_write8(priv
, REG_INIRTS_RATE_SEL
, rate_idx
);
8148 rtl8xxxu_bss_info_changed(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
8149 struct ieee80211_bss_conf
*bss_conf
, u32 changed
)
8151 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8152 struct device
*dev
= &priv
->udev
->dev
;
8153 struct ieee80211_sta
*sta
;
8157 if (changed
& BSS_CHANGED_ASSOC
) {
8158 dev_dbg(dev
, "Changed ASSOC: %i!\n", bss_conf
->assoc
);
8160 rtl8xxxu_set_linktype(priv
, vif
->type
);
8162 if (bss_conf
->assoc
) {
8167 sta
= ieee80211_find_sta(vif
, bss_conf
->bssid
);
8169 dev_info(dev
, "%s: ASSOC no sta found\n",
8175 if (sta
->ht_cap
.ht_supported
)
8176 dev_info(dev
, "%s: HT supported\n", __func__
);
8177 if (sta
->vht_cap
.vht_supported
)
8178 dev_info(dev
, "%s: VHT supported\n", __func__
);
8180 /* TODO: Set bits 28-31 for rate adaptive id */
8181 ramask
= (sta
->supp_rates
[0] & 0xfff) |
8182 sta
->ht_cap
.mcs
.rx_mask
[0] << 12 |
8183 sta
->ht_cap
.mcs
.rx_mask
[1] << 20;
8184 if (sta
->ht_cap
.cap
&
8185 (IEEE80211_HT_CAP_SGI_40
| IEEE80211_HT_CAP_SGI_20
))
8189 priv
->fops
->update_rate_mask(priv
, ramask
, sgi
);
8191 rtl8xxxu_write8(priv
, REG_BCN_MAX_ERR
, 0xff);
8193 rtl8723a_stop_tx_beacon(priv
);
8195 /* joinbss sequence */
8196 rtl8xxxu_write16(priv
, REG_BCN_PSR_RPT
,
8197 0xc000 | bss_conf
->aid
);
8199 priv
->fops
->report_connect(priv
, 0, true);
8201 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
8202 val8
|= BEACON_DISABLE_TSF_UPDATE
;
8203 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
8205 priv
->fops
->report_connect(priv
, 0, false);
8209 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
8210 dev_dbg(dev
, "Changed ERP_PREAMBLE: Use short preamble %i\n",
8211 bss_conf
->use_short_preamble
);
8212 val32
= rtl8xxxu_read32(priv
, REG_RESPONSE_RATE_SET
);
8213 if (bss_conf
->use_short_preamble
)
8214 val32
|= RSR_ACK_SHORT_PREAMBLE
;
8216 val32
&= ~RSR_ACK_SHORT_PREAMBLE
;
8217 rtl8xxxu_write32(priv
, REG_RESPONSE_RATE_SET
, val32
);
8220 if (changed
& BSS_CHANGED_ERP_SLOT
) {
8221 dev_dbg(dev
, "Changed ERP_SLOT: short_slot_time %i\n",
8222 bss_conf
->use_short_slot
);
8224 if (bss_conf
->use_short_slot
)
8228 rtl8xxxu_write8(priv
, REG_SLOT
, val8
);
8231 if (changed
& BSS_CHANGED_BSSID
) {
8232 dev_dbg(dev
, "Changed BSSID!\n");
8233 rtl8xxxu_set_bssid(priv
, bss_conf
->bssid
);
8236 if (changed
& BSS_CHANGED_BASIC_RATES
) {
8237 dev_dbg(dev
, "Changed BASIC_RATES!\n");
8238 rtl8xxxu_set_basic_rates(priv
, bss_conf
->basic_rates
);
8244 static u32
rtl8xxxu_80211_to_rtl_queue(u32 queue
)
8249 case IEEE80211_AC_VO
:
8250 rtlqueue
= TXDESC_QUEUE_VO
;
8252 case IEEE80211_AC_VI
:
8253 rtlqueue
= TXDESC_QUEUE_VI
;
8255 case IEEE80211_AC_BE
:
8256 rtlqueue
= TXDESC_QUEUE_BE
;
8258 case IEEE80211_AC_BK
:
8259 rtlqueue
= TXDESC_QUEUE_BK
;
8262 rtlqueue
= TXDESC_QUEUE_BE
;
8268 static u32
rtl8xxxu_queue_select(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
8270 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
8273 if (ieee80211_is_mgmt(hdr
->frame_control
))
8274 queue
= TXDESC_QUEUE_MGNT
;
8276 queue
= rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb
));
8282 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
8283 * format. The descriptor checksum is still only calculated over the
8284 * initial 32 bytes of the descriptor!
8286 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32
*tx_desc
)
8288 __le16
*ptr
= (__le16
*)tx_desc
;
8293 * Clear csum field before calculation, as the csum field is
8294 * in the middle of the struct.
8296 tx_desc
->csum
= cpu_to_le16(0);
8298 for (i
= 0; i
< (sizeof(struct rtl8xxxu_txdesc32
) / sizeof(u16
)); i
++)
8299 csum
= csum
^ le16_to_cpu(ptr
[i
]);
8301 tx_desc
->csum
|= cpu_to_le16(csum
);
8304 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv
*priv
)
8306 struct rtl8xxxu_tx_urb
*tx_urb
, *tmp
;
8307 unsigned long flags
;
8309 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
8310 list_for_each_entry_safe(tx_urb
, tmp
, &priv
->tx_urb_free_list
, list
) {
8311 list_del(&tx_urb
->list
);
8312 priv
->tx_urb_free_count
--;
8313 usb_free_urb(&tx_urb
->urb
);
8315 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
8318 static struct rtl8xxxu_tx_urb
*
8319 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv
*priv
)
8321 struct rtl8xxxu_tx_urb
*tx_urb
;
8322 unsigned long flags
;
8324 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
8325 tx_urb
= list_first_entry_or_null(&priv
->tx_urb_free_list
,
8326 struct rtl8xxxu_tx_urb
, list
);
8328 list_del(&tx_urb
->list
);
8329 priv
->tx_urb_free_count
--;
8330 if (priv
->tx_urb_free_count
< RTL8XXXU_TX_URB_LOW_WATER
&&
8331 !priv
->tx_stopped
) {
8332 priv
->tx_stopped
= true;
8333 ieee80211_stop_queues(priv
->hw
);
8337 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
8342 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv
*priv
,
8343 struct rtl8xxxu_tx_urb
*tx_urb
)
8345 unsigned long flags
;
8347 INIT_LIST_HEAD(&tx_urb
->list
);
8349 spin_lock_irqsave(&priv
->tx_urb_lock
, flags
);
8351 list_add(&tx_urb
->list
, &priv
->tx_urb_free_list
);
8352 priv
->tx_urb_free_count
++;
8353 if (priv
->tx_urb_free_count
> RTL8XXXU_TX_URB_HIGH_WATER
&&
8355 priv
->tx_stopped
= false;
8356 ieee80211_wake_queues(priv
->hw
);
8359 spin_unlock_irqrestore(&priv
->tx_urb_lock
, flags
);
8362 static void rtl8xxxu_tx_complete(struct urb
*urb
)
8364 struct sk_buff
*skb
= (struct sk_buff
*)urb
->context
;
8365 struct ieee80211_tx_info
*tx_info
;
8366 struct ieee80211_hw
*hw
;
8367 struct rtl8xxxu_priv
*priv
;
8368 struct rtl8xxxu_tx_urb
*tx_urb
=
8369 container_of(urb
, struct rtl8xxxu_tx_urb
, urb
);
8371 tx_info
= IEEE80211_SKB_CB(skb
);
8372 hw
= tx_info
->rate_driver_data
[0];
8375 skb_pull(skb
, priv
->fops
->tx_desc_size
);
8377 ieee80211_tx_info_clear_status(tx_info
);
8378 tx_info
->status
.rates
[0].idx
= -1;
8379 tx_info
->status
.rates
[0].count
= 0;
8382 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
8384 ieee80211_tx_status_irqsafe(hw
, skb
);
8386 rtl8xxxu_free_tx_urb(priv
, tx_urb
);
8389 static void rtl8xxxu_dump_action(struct device
*dev
,
8390 struct ieee80211_hdr
*hdr
)
8392 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)hdr
;
8395 if (!(rtl8xxxu_debug
& RTL8XXXU_DEBUG_ACTION
))
8398 switch (mgmt
->u
.action
.u
.addba_resp
.action_code
) {
8399 case WLAN_ACTION_ADDBA_RESP
:
8400 cap
= le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.capab
);
8401 timeout
= le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.timeout
);
8402 dev_info(dev
, "WLAN_ACTION_ADDBA_RESP: "
8403 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
8406 (cap
& IEEE80211_ADDBA_PARAM_TID_MASK
) >> 2,
8407 (cap
& IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
) >> 6,
8409 le16_to_cpu(mgmt
->u
.action
.u
.addba_resp
.status
));
8411 case WLAN_ACTION_ADDBA_REQ
:
8412 cap
= le16_to_cpu(mgmt
->u
.action
.u
.addba_req
.capab
);
8413 timeout
= le16_to_cpu(mgmt
->u
.action
.u
.addba_req
.timeout
);
8414 dev_info(dev
, "WLAN_ACTION_ADDBA_REQ: "
8415 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
8417 (cap
& IEEE80211_ADDBA_PARAM_TID_MASK
) >> 2,
8418 (cap
& IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
) >> 6,
8422 dev_info(dev
, "action frame %02x\n",
8423 mgmt
->u
.action
.u
.addba_resp
.action_code
);
8428 static void rtl8xxxu_tx(struct ieee80211_hw
*hw
,
8429 struct ieee80211_tx_control
*control
,
8430 struct sk_buff
*skb
)
8432 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
8433 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
8434 struct ieee80211_rate
*tx_rate
= ieee80211_get_tx_rate(hw
, tx_info
);
8435 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8436 struct rtl8xxxu_txdesc32
*tx_desc
;
8437 struct rtl8xxxu_txdesc40
*tx_desc40
;
8438 struct rtl8xxxu_tx_urb
*tx_urb
;
8439 struct ieee80211_sta
*sta
= NULL
;
8440 struct ieee80211_vif
*vif
= tx_info
->control
.vif
;
8441 struct device
*dev
= &priv
->udev
->dev
;
8443 u16 pktlen
= skb
->len
;
8445 u16 rate_flag
= tx_info
->control
.rates
[0].flags
;
8446 int tx_desc_size
= priv
->fops
->tx_desc_size
;
8448 bool usedesc40
, ampdu_enable
;
8450 if (skb_headroom(skb
) < tx_desc_size
) {
8452 "%s: Not enough headroom (%i) for tx descriptor\n",
8453 __func__
, skb_headroom(skb
));
8457 if (unlikely(skb
->len
> (65535 - tx_desc_size
))) {
8458 dev_warn(dev
, "%s: Trying to send over-sized skb (%i)\n",
8459 __func__
, skb
->len
);
8463 tx_urb
= rtl8xxxu_alloc_tx_urb(priv
);
8465 dev_warn(dev
, "%s: Unable to allocate tx urb\n", __func__
);
8469 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_TX
)
8470 dev_info(dev
, "%s: TX rate: %d (%d), pkt size %d\n",
8471 __func__
, tx_rate
->bitrate
, tx_rate
->hw_value
, pktlen
);
8473 if (ieee80211_is_action(hdr
->frame_control
))
8474 rtl8xxxu_dump_action(dev
, hdr
);
8476 usedesc40
= (tx_desc_size
== 40);
8477 tx_info
->rate_driver_data
[0] = hw
;
8479 if (control
&& control
->sta
)
8482 tx_desc
= (struct rtl8xxxu_txdesc32
*)skb_push(skb
, tx_desc_size
);
8484 memset(tx_desc
, 0, tx_desc_size
);
8485 tx_desc
->pkt_size
= cpu_to_le16(pktlen
);
8486 tx_desc
->pkt_offset
= tx_desc_size
;
8489 TXDESC_OWN
| TXDESC_FIRST_SEGMENT
| TXDESC_LAST_SEGMENT
;
8490 if (is_multicast_ether_addr(ieee80211_get_DA(hdr
)) ||
8491 is_broadcast_ether_addr(ieee80211_get_DA(hdr
)))
8492 tx_desc
->txdw0
|= TXDESC_BROADMULTICAST
;
8494 queue
= rtl8xxxu_queue_select(hw
, skb
);
8495 tx_desc
->txdw1
= cpu_to_le32(queue
<< TXDESC_QUEUE_SHIFT
);
8497 if (tx_info
->control
.hw_key
) {
8498 switch (tx_info
->control
.hw_key
->cipher
) {
8499 case WLAN_CIPHER_SUITE_WEP40
:
8500 case WLAN_CIPHER_SUITE_WEP104
:
8501 case WLAN_CIPHER_SUITE_TKIP
:
8502 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_SEC_RC4
);
8504 case WLAN_CIPHER_SUITE_CCMP
:
8505 tx_desc
->txdw1
|= cpu_to_le32(TXDESC_SEC_AES
);
8512 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
8513 ampdu_enable
= false;
8514 if (ieee80211_is_data_qos(hdr
->frame_control
) && sta
) {
8515 if (sta
->ht_cap
.ht_supported
) {
8518 ampdu
= (u32
)sta
->ht_cap
.ampdu_density
;
8519 val32
= ampdu
<< TXDESC_AMPDU_DENSITY_SHIFT
;
8520 tx_desc
->txdw2
|= cpu_to_le32(val32
);
8522 ampdu_enable
= true;
8526 if (rate_flag
& IEEE80211_TX_RC_MCS
)
8527 rate
= tx_info
->control
.rates
[0].idx
+ DESC_RATE_MCS0
;
8529 rate
= tx_rate
->hw_value
;
8531 seq_number
= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
8533 tx_desc
->txdw5
= cpu_to_le32(rate
);
8535 if (ieee80211_is_data(hdr
->frame_control
))
8536 tx_desc
->txdw5
|= cpu_to_le32(0x0001ff00);
8539 cpu_to_le32((u32
)seq_number
<< TXDESC32_SEQ_SHIFT
);
8542 tx_desc
->txdw1
|= cpu_to_le32(TXDESC32_AGG_ENABLE
);
8544 tx_desc
->txdw1
|= cpu_to_le32(TXDESC32_AGG_BREAK
);
8546 if (ieee80211_is_mgmt(hdr
->frame_control
)) {
8547 tx_desc
->txdw5
= cpu_to_le32(tx_rate
->hw_value
);
8549 cpu_to_le32(TXDESC32_USE_DRIVER_RATE
);
8551 cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT
);
8553 cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE
);
8556 if (ieee80211_is_data_qos(hdr
->frame_control
))
8557 tx_desc
->txdw4
|= cpu_to_le32(TXDESC32_QOS
);
8559 if (rate_flag
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
||
8560 (sta
&& vif
&& vif
->bss_conf
.use_short_preamble
))
8561 tx_desc
->txdw4
|= cpu_to_le32(TXDESC32_SHORT_PREAMBLE
);
8563 if (rate_flag
& IEEE80211_TX_RC_SHORT_GI
||
8564 (ieee80211_is_data_qos(hdr
->frame_control
) &&
8565 sta
&& sta
->ht_cap
.cap
&
8566 (IEEE80211_HT_CAP_SGI_40
| IEEE80211_HT_CAP_SGI_20
))) {
8567 tx_desc
->txdw5
|= cpu_to_le32(TXDESC32_SHORT_GI
);
8570 if (rate_flag
& IEEE80211_TX_RC_USE_RTS_CTS
) {
8572 * Use RTS rate 24M - does the mac80211 tell
8576 cpu_to_le32(DESC_RATE_24M
<<
8577 TXDESC32_RTS_RATE_SHIFT
);
8579 cpu_to_le32(TXDESC32_RTS_CTS_ENABLE
);
8580 tx_desc
->txdw4
|= cpu_to_le32(TXDESC32_HW_RTS_ENABLE
);
8583 tx_desc40
= (struct rtl8xxxu_txdesc40
*)tx_desc
;
8585 tx_desc40
->txdw4
= cpu_to_le32(rate
);
8586 if (ieee80211_is_data(hdr
->frame_control
)) {
8589 TXDESC40_DATA_RATE_FB_SHIFT
);
8593 cpu_to_le32((u32
)seq_number
<< TXDESC40_SEQ_SHIFT
);
8596 tx_desc40
->txdw2
|= cpu_to_le32(TXDESC40_AGG_ENABLE
);
8598 tx_desc40
->txdw2
|= cpu_to_le32(TXDESC40_AGG_BREAK
);
8600 if (ieee80211_is_mgmt(hdr
->frame_control
)) {
8601 tx_desc40
->txdw4
= cpu_to_le32(tx_rate
->hw_value
);
8603 cpu_to_le32(TXDESC40_USE_DRIVER_RATE
);
8605 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT
);
8607 cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE
);
8610 if (rate_flag
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
||
8611 (sta
&& vif
&& vif
->bss_conf
.use_short_preamble
))
8613 cpu_to_le32(TXDESC40_SHORT_PREAMBLE
);
8615 if (rate_flag
& IEEE80211_TX_RC_USE_RTS_CTS
) {
8617 * Use RTS rate 24M - does the mac80211 tell
8621 cpu_to_le32(DESC_RATE_24M
<<
8622 TXDESC40_RTS_RATE_SHIFT
);
8623 tx_desc
->txdw3
|= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE
);
8624 tx_desc
->txdw3
|= cpu_to_le32(TXDESC40_HW_RTS_ENABLE
);
8628 rtl8xxxu_calc_tx_desc_csum(tx_desc
);
8630 usb_fill_bulk_urb(&tx_urb
->urb
, priv
->udev
, priv
->pipe_out
[queue
],
8631 skb
->data
, skb
->len
, rtl8xxxu_tx_complete
, skb
);
8633 usb_anchor_urb(&tx_urb
->urb
, &priv
->tx_anchor
);
8634 ret
= usb_submit_urb(&tx_urb
->urb
, GFP_ATOMIC
);
8636 usb_unanchor_urb(&tx_urb
->urb
);
8637 rtl8xxxu_free_tx_urb(priv
, tx_urb
);
8645 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv
*priv
,
8646 struct ieee80211_rx_status
*rx_status
,
8647 struct rtl8723au_phy_stats
*phy_stats
,
8650 if (phy_stats
->sgi_en
)
8651 rx_status
->flag
|= RX_FLAG_SHORT_GI
;
8653 if (rxmcs
< DESC_RATE_6M
) {
8655 * Handle PHY stats for CCK rates
8657 u8 cck_agc_rpt
= phy_stats
->cck_agc_rpt_ofdm_cfosho_a
;
8659 switch (cck_agc_rpt
& 0xc0) {
8661 rx_status
->signal
= -46 - (cck_agc_rpt
& 0x3e);
8664 rx_status
->signal
= -26 - (cck_agc_rpt
& 0x3e);
8667 rx_status
->signal
= -12 - (cck_agc_rpt
& 0x3e);
8670 rx_status
->signal
= 16 - (cck_agc_rpt
& 0x3e);
8675 (phy_stats
->cck_sig_qual_ofdm_pwdb_all
>> 1) - 110;
8679 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv
*priv
)
8681 struct rtl8xxxu_rx_urb
*rx_urb
, *tmp
;
8682 unsigned long flags
;
8684 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
8686 list_for_each_entry_safe(rx_urb
, tmp
,
8687 &priv
->rx_urb_pending_list
, list
) {
8688 list_del(&rx_urb
->list
);
8689 priv
->rx_urb_pending_count
--;
8690 usb_free_urb(&rx_urb
->urb
);
8693 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
8696 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv
*priv
,
8697 struct rtl8xxxu_rx_urb
*rx_urb
)
8699 struct sk_buff
*skb
;
8700 unsigned long flags
;
8703 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
8705 if (!priv
->shutdown
) {
8706 list_add_tail(&rx_urb
->list
, &priv
->rx_urb_pending_list
);
8707 priv
->rx_urb_pending_count
++;
8708 pending
= priv
->rx_urb_pending_count
;
8710 skb
= (struct sk_buff
*)rx_urb
->urb
.context
;
8712 usb_free_urb(&rx_urb
->urb
);
8715 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
8717 if (pending
> RTL8XXXU_RX_URB_PENDING_WATER
)
8718 schedule_work(&priv
->rx_urb_wq
);
8721 static void rtl8xxxu_rx_urb_work(struct work_struct
*work
)
8723 struct rtl8xxxu_priv
*priv
;
8724 struct rtl8xxxu_rx_urb
*rx_urb
, *tmp
;
8725 struct list_head local
;
8726 struct sk_buff
*skb
;
8727 unsigned long flags
;
8730 priv
= container_of(work
, struct rtl8xxxu_priv
, rx_urb_wq
);
8731 INIT_LIST_HEAD(&local
);
8733 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
8735 list_splice_init(&priv
->rx_urb_pending_list
, &local
);
8736 priv
->rx_urb_pending_count
= 0;
8738 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
8740 list_for_each_entry_safe(rx_urb
, tmp
, &local
, list
) {
8741 list_del_init(&rx_urb
->list
);
8742 ret
= rtl8xxxu_submit_rx_urb(priv
, rx_urb
);
8744 * If out of memory or temporary error, put it back on the
8745 * queue and try again. Otherwise the device is dead/gone
8746 * and we should drop it.
8753 rtl8xxxu_queue_rx_urb(priv
, rx_urb
);
8756 pr_info("failed to requeue urb %i\n", ret
);
8757 skb
= (struct sk_buff
*)rx_urb
->urb
.context
;
8759 usb_free_urb(&rx_urb
->urb
);
8764 static int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv
*priv
,
8765 struct sk_buff
*skb
,
8766 struct ieee80211_rx_status
*rx_status
)
8768 struct rtl8xxxu_rxdesc16
*rx_desc
=
8769 (struct rtl8xxxu_rxdesc16
*)skb
->data
;
8770 struct rtl8723au_phy_stats
*phy_stats
;
8771 __le32
*_rx_desc_le
= (__le32
*)skb
->data
;
8772 u32
*_rx_desc
= (u32
*)skb
->data
;
8773 int drvinfo_sz
, desc_shift
;
8776 for (i
= 0; i
< (sizeof(struct rtl8xxxu_rxdesc16
) / sizeof(u32
)); i
++)
8777 _rx_desc
[i
] = le32_to_cpu(_rx_desc_le
[i
]);
8779 skb_pull(skb
, sizeof(struct rtl8xxxu_rxdesc16
));
8781 phy_stats
= (struct rtl8723au_phy_stats
*)skb
->data
;
8783 drvinfo_sz
= rx_desc
->drvinfo_sz
* 8;
8784 desc_shift
= rx_desc
->shift
;
8785 skb_pull(skb
, drvinfo_sz
+ desc_shift
);
8787 if (rx_desc
->phy_stats
)
8788 rtl8xxxu_rx_parse_phystats(priv
, rx_status
, phy_stats
,
8791 rx_status
->mactime
= le32_to_cpu(rx_desc
->tsfl
);
8792 rx_status
->flag
|= RX_FLAG_MACTIME_START
;
8794 if (!rx_desc
->swdec
)
8795 rx_status
->flag
|= RX_FLAG_DECRYPTED
;
8797 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
8799 rx_status
->flag
|= RX_FLAG_40MHZ
;
8801 if (rx_desc
->rxht
) {
8802 rx_status
->flag
|= RX_FLAG_HT
;
8803 rx_status
->rate_idx
= rx_desc
->rxmcs
- DESC_RATE_MCS0
;
8805 rx_status
->rate_idx
= rx_desc
->rxmcs
;
8808 return RX_TYPE_DATA_PKT
;
8811 static int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv
*priv
,
8812 struct sk_buff
*skb
,
8813 struct ieee80211_rx_status
*rx_status
)
8815 struct rtl8xxxu_rxdesc24
*rx_desc
=
8816 (struct rtl8xxxu_rxdesc24
*)skb
->data
;
8817 struct rtl8723au_phy_stats
*phy_stats
;
8818 __le32
*_rx_desc_le
= (__le32
*)skb
->data
;
8819 u32
*_rx_desc
= (u32
*)skb
->data
;
8820 int drvinfo_sz
, desc_shift
;
8823 for (i
= 0; i
< (sizeof(struct rtl8xxxu_rxdesc24
) / sizeof(u32
)); i
++)
8824 _rx_desc
[i
] = le32_to_cpu(_rx_desc_le
[i
]);
8826 skb_pull(skb
, sizeof(struct rtl8xxxu_rxdesc24
));
8828 phy_stats
= (struct rtl8723au_phy_stats
*)skb
->data
;
8830 drvinfo_sz
= rx_desc
->drvinfo_sz
* 8;
8831 desc_shift
= rx_desc
->shift
;
8832 skb_pull(skb
, drvinfo_sz
+ desc_shift
);
8834 if (rx_desc
->rpt_sel
) {
8835 struct device
*dev
= &priv
->udev
->dev
;
8836 dev_dbg(dev
, "%s: C2H packet\n", __func__
);
8840 if (rx_desc
->phy_stats
)
8841 rtl8xxxu_rx_parse_phystats(priv
, rx_status
, phy_stats
,
8844 rx_status
->mactime
= le32_to_cpu(rx_desc
->tsfl
);
8845 rx_status
->flag
|= RX_FLAG_MACTIME_START
;
8847 if (!rx_desc
->swdec
)
8848 rx_status
->flag
|= RX_FLAG_DECRYPTED
;
8850 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
8852 rx_status
->flag
|= RX_FLAG_40MHZ
;
8854 if (rx_desc
->rxmcs
>= DESC_RATE_MCS0
) {
8855 rx_status
->flag
|= RX_FLAG_HT
;
8856 rx_status
->rate_idx
= rx_desc
->rxmcs
- DESC_RATE_MCS0
;
8858 rx_status
->rate_idx
= rx_desc
->rxmcs
;
8861 return RX_TYPE_DATA_PKT
;
8864 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv
*priv
,
8865 struct sk_buff
*skb
)
8867 struct rtl8723bu_c2h
*c2h
= (struct rtl8723bu_c2h
*)skb
->data
;
8868 struct device
*dev
= &priv
->udev
->dev
;
8873 dev_dbg(dev
, "C2H ID %02x seq %02x, len %02x source %02x\n",
8874 c2h
->id
, c2h
->seq
, len
, c2h
->bt_info
.response_source
);
8877 case C2H_8723B_BT_INFO
:
8878 if (c2h
->bt_info
.response_source
>
8879 BT_INFO_SRC_8723B_BT_ACTIVE_SEND
)
8880 dev_dbg(dev
, "C2H_BT_INFO WiFi only firmware\n");
8882 dev_dbg(dev
, "C2H_BT_INFO BT/WiFi coexist firmware\n");
8884 if (c2h
->bt_info
.bt_has_reset
)
8885 dev_dbg(dev
, "BT has been reset\n");
8886 if (c2h
->bt_info
.tx_rx_mask
)
8887 dev_dbg(dev
, "BT TRx mask\n");
8890 case C2H_8723B_BT_MP_INFO
:
8891 dev_dbg(dev
, "C2H_MP_INFO ext ID %02x, status %02x\n",
8892 c2h
->bt_mp_info
.ext_id
, c2h
->bt_mp_info
.status
);
8894 case C2H_8723B_RA_REPORT
:
8896 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
8897 c2h
->ra_report
.rate
, c2h
->ra_report
.dummy0_0
,
8898 c2h
->ra_report
.macid
, c2h
->ra_report
.noisy_state
);
8901 dev_info(dev
, "Unhandled C2H event %02x seq %02x\n",
8903 print_hex_dump(KERN_INFO
, "C2H content: ", DUMP_PREFIX_NONE
,
8904 16, 1, c2h
->raw
.payload
, len
, false);
8909 static void rtl8xxxu_rx_complete(struct urb
*urb
)
8911 struct rtl8xxxu_rx_urb
*rx_urb
=
8912 container_of(urb
, struct rtl8xxxu_rx_urb
, urb
);
8913 struct ieee80211_hw
*hw
= rx_urb
->hw
;
8914 struct rtl8xxxu_priv
*priv
= hw
->priv
;
8915 struct sk_buff
*skb
= (struct sk_buff
*)urb
->context
;
8916 struct ieee80211_rx_status
*rx_status
= IEEE80211_SKB_RXCB(skb
);
8917 struct device
*dev
= &priv
->udev
->dev
;
8920 skb_put(skb
, urb
->actual_length
);
8922 if (urb
->status
== 0) {
8923 memset(rx_status
, 0, sizeof(struct ieee80211_rx_status
));
8925 rx_type
= priv
->fops
->parse_rx_desc(priv
, skb
, rx_status
);
8927 rx_status
->freq
= hw
->conf
.chandef
.chan
->center_freq
;
8928 rx_status
->band
= hw
->conf
.chandef
.chan
->band
;
8930 if (rx_type
== RX_TYPE_DATA_PKT
)
8931 ieee80211_rx_irqsafe(hw
, skb
);
8933 rtl8723bu_handle_c2h(priv
, skb
);
8938 rx_urb
->urb
.context
= NULL
;
8939 rtl8xxxu_queue_rx_urb(priv
, rx_urb
);
8941 dev_dbg(dev
, "%s: status %i\n", __func__
, urb
->status
);
8952 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv
*priv
,
8953 struct rtl8xxxu_rx_urb
*rx_urb
)
8955 struct sk_buff
*skb
;
8957 int ret
, rx_desc_sz
;
8959 rx_desc_sz
= priv
->fops
->rx_desc_size
;
8960 skb_size
= rx_desc_sz
+ RTL_RX_BUFFER_SIZE
;
8961 skb
= __netdev_alloc_skb(NULL
, skb_size
, GFP_KERNEL
);
8965 memset(skb
->data
, 0, rx_desc_sz
);
8966 usb_fill_bulk_urb(&rx_urb
->urb
, priv
->udev
, priv
->pipe_in
, skb
->data
,
8967 skb_size
, rtl8xxxu_rx_complete
, skb
);
8968 usb_anchor_urb(&rx_urb
->urb
, &priv
->rx_anchor
);
8969 ret
= usb_submit_urb(&rx_urb
->urb
, GFP_ATOMIC
);
8971 usb_unanchor_urb(&rx_urb
->urb
);
8975 static void rtl8xxxu_int_complete(struct urb
*urb
)
8977 struct rtl8xxxu_priv
*priv
= (struct rtl8xxxu_priv
*)urb
->context
;
8978 struct device
*dev
= &priv
->udev
->dev
;
8981 dev_dbg(dev
, "%s: status %i\n", __func__
, urb
->status
);
8982 if (urb
->status
== 0) {
8983 usb_anchor_urb(urb
, &priv
->int_anchor
);
8984 ret
= usb_submit_urb(urb
, GFP_ATOMIC
);
8986 usb_unanchor_urb(urb
);
8988 dev_info(dev
, "%s: Error %i\n", __func__
, urb
->status
);
8993 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw
*hw
)
8995 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9000 urb
= usb_alloc_urb(0, GFP_KERNEL
);
9004 usb_fill_int_urb(urb
, priv
->udev
, priv
->pipe_interrupt
,
9005 priv
->int_buf
, USB_INTR_CONTENT_LENGTH
,
9006 rtl8xxxu_int_complete
, priv
, 1);
9007 usb_anchor_urb(urb
, &priv
->int_anchor
);
9008 ret
= usb_submit_urb(urb
, GFP_KERNEL
);
9010 usb_unanchor_urb(urb
);
9014 val32
= rtl8xxxu_read32(priv
, REG_USB_HIMR
);
9015 val32
|= USB_HIMR_CPWM
;
9016 rtl8xxxu_write32(priv
, REG_USB_HIMR
, val32
);
9022 static int rtl8xxxu_add_interface(struct ieee80211_hw
*hw
,
9023 struct ieee80211_vif
*vif
)
9025 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9029 switch (vif
->type
) {
9030 case NL80211_IFTYPE_STATION
:
9031 rtl8723a_stop_tx_beacon(priv
);
9033 val8
= rtl8xxxu_read8(priv
, REG_BEACON_CTRL
);
9034 val8
|= BEACON_ATIM
| BEACON_FUNCTION_ENABLE
|
9035 BEACON_DISABLE_TSF_UPDATE
;
9036 rtl8xxxu_write8(priv
, REG_BEACON_CTRL
, val8
);
9043 rtl8xxxu_set_linktype(priv
, vif
->type
);
9048 static void rtl8xxxu_remove_interface(struct ieee80211_hw
*hw
,
9049 struct ieee80211_vif
*vif
)
9051 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9053 dev_dbg(&priv
->udev
->dev
, "%s\n", __func__
);
9056 static int rtl8xxxu_config(struct ieee80211_hw
*hw
, u32 changed
)
9058 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9059 struct device
*dev
= &priv
->udev
->dev
;
9061 int ret
= 0, channel
;
9064 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_CHANNEL
)
9066 "%s: channel: %i (changed %08x chandef.width %02x)\n",
9067 __func__
, hw
->conf
.chandef
.chan
->hw_value
,
9068 changed
, hw
->conf
.chandef
.width
);
9070 if (changed
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
) {
9071 val16
= ((hw
->conf
.long_frame_max_tx_count
<<
9072 RETRY_LIMIT_LONG_SHIFT
) & RETRY_LIMIT_LONG_MASK
) |
9073 ((hw
->conf
.short_frame_max_tx_count
<<
9074 RETRY_LIMIT_SHORT_SHIFT
) & RETRY_LIMIT_SHORT_MASK
);
9075 rtl8xxxu_write16(priv
, REG_RETRY_LIMIT
, val16
);
9078 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
9079 switch (hw
->conf
.chandef
.width
) {
9080 case NL80211_CHAN_WIDTH_20_NOHT
:
9081 case NL80211_CHAN_WIDTH_20
:
9084 case NL80211_CHAN_WIDTH_40
:
9092 channel
= hw
->conf
.chandef
.chan
->hw_value
;
9094 priv
->fops
->set_tx_power(priv
, channel
, ht40
);
9096 priv
->fops
->config_channel(hw
);
9103 static int rtl8xxxu_conf_tx(struct ieee80211_hw
*hw
,
9104 struct ieee80211_vif
*vif
, u16 queue
,
9105 const struct ieee80211_tx_queue_params
*param
)
9107 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9108 struct device
*dev
= &priv
->udev
->dev
;
9110 u8 aifs
, acm_ctrl
, acm_bit
;
9115 fls(param
->cw_min
) << EDCA_PARAM_ECW_MIN_SHIFT
|
9116 fls(param
->cw_max
) << EDCA_PARAM_ECW_MAX_SHIFT
|
9117 (u32
)param
->txop
<< EDCA_PARAM_TXOP_SHIFT
;
9119 acm_ctrl
= rtl8xxxu_read8(priv
, REG_ACM_HW_CTRL
);
9121 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
9122 __func__
, queue
, val32
, param
->acm
, acm_ctrl
);
9125 case IEEE80211_AC_VO
:
9126 acm_bit
= ACM_HW_CTRL_VO
;
9127 rtl8xxxu_write32(priv
, REG_EDCA_VO_PARAM
, val32
);
9129 case IEEE80211_AC_VI
:
9130 acm_bit
= ACM_HW_CTRL_VI
;
9131 rtl8xxxu_write32(priv
, REG_EDCA_VI_PARAM
, val32
);
9133 case IEEE80211_AC_BE
:
9134 acm_bit
= ACM_HW_CTRL_BE
;
9135 rtl8xxxu_write32(priv
, REG_EDCA_BE_PARAM
, val32
);
9137 case IEEE80211_AC_BK
:
9138 acm_bit
= ACM_HW_CTRL_BK
;
9139 rtl8xxxu_write32(priv
, REG_EDCA_BK_PARAM
, val32
);
9147 acm_ctrl
|= acm_bit
;
9149 acm_ctrl
&= ~acm_bit
;
9150 rtl8xxxu_write8(priv
, REG_ACM_HW_CTRL
, acm_ctrl
);
9155 static void rtl8xxxu_configure_filter(struct ieee80211_hw
*hw
,
9156 unsigned int changed_flags
,
9157 unsigned int *total_flags
, u64 multicast
)
9159 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9160 u32 rcr
= rtl8xxxu_read32(priv
, REG_RCR
);
9162 dev_dbg(&priv
->udev
->dev
, "%s: changed_flags %08x, total_flags %08x\n",
9163 __func__
, changed_flags
, *total_flags
);
9166 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
9169 if (*total_flags
& FIF_FCSFAIL
)
9170 rcr
|= RCR_ACCEPT_CRC32
;
9172 rcr
&= ~RCR_ACCEPT_CRC32
;
9175 * FIF_PLCPFAIL not supported?
9178 if (*total_flags
& FIF_BCN_PRBRESP_PROMISC
)
9179 rcr
&= ~RCR_CHECK_BSSID_BEACON
;
9181 rcr
|= RCR_CHECK_BSSID_BEACON
;
9183 if (*total_flags
& FIF_CONTROL
)
9184 rcr
|= RCR_ACCEPT_CTRL_FRAME
;
9186 rcr
&= ~RCR_ACCEPT_CTRL_FRAME
;
9188 if (*total_flags
& FIF_OTHER_BSS
) {
9189 rcr
|= RCR_ACCEPT_AP
;
9190 rcr
&= ~RCR_CHECK_BSSID_MATCH
;
9192 rcr
&= ~RCR_ACCEPT_AP
;
9193 rcr
|= RCR_CHECK_BSSID_MATCH
;
9196 if (*total_flags
& FIF_PSPOLL
)
9197 rcr
|= RCR_ACCEPT_PM
;
9199 rcr
&= ~RCR_ACCEPT_PM
;
9202 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
9205 rtl8xxxu_write32(priv
, REG_RCR
, rcr
);
9207 *total_flags
&= (FIF_ALLMULTI
| FIF_FCSFAIL
| FIF_BCN_PRBRESP_PROMISC
|
9208 FIF_CONTROL
| FIF_OTHER_BSS
| FIF_PSPOLL
|
9212 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw
*hw
, u32 rts
)
9220 static int rtl8xxxu_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
9221 struct ieee80211_vif
*vif
,
9222 struct ieee80211_sta
*sta
,
9223 struct ieee80211_key_conf
*key
)
9225 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9226 struct device
*dev
= &priv
->udev
->dev
;
9227 u8 mac_addr
[ETH_ALEN
];
9231 int retval
= -EOPNOTSUPP
;
9233 dev_dbg(dev
, "%s: cmd %02x, cipher %08x, index %i\n",
9234 __func__
, cmd
, key
->cipher
, key
->keyidx
);
9236 if (vif
->type
!= NL80211_IFTYPE_STATION
)
9239 if (key
->keyidx
> 3)
9242 switch (key
->cipher
) {
9243 case WLAN_CIPHER_SUITE_WEP40
:
9244 case WLAN_CIPHER_SUITE_WEP104
:
9247 case WLAN_CIPHER_SUITE_CCMP
:
9248 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT_TX
;
9250 case WLAN_CIPHER_SUITE_TKIP
:
9251 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
9256 if (key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) {
9257 dev_dbg(dev
, "%s: pairwise key\n", __func__
);
9258 ether_addr_copy(mac_addr
, sta
->addr
);
9260 dev_dbg(dev
, "%s: group key\n", __func__
);
9261 eth_broadcast_addr(mac_addr
);
9264 val16
= rtl8xxxu_read16(priv
, REG_CR
);
9265 val16
|= CR_SECURITY_ENABLE
;
9266 rtl8xxxu_write16(priv
, REG_CR
, val16
);
9268 val8
= SEC_CFG_TX_SEC_ENABLE
| SEC_CFG_TXBC_USE_DEFKEY
|
9269 SEC_CFG_RX_SEC_ENABLE
| SEC_CFG_RXBC_USE_DEFKEY
;
9270 val8
|= SEC_CFG_TX_USE_DEFKEY
| SEC_CFG_RX_USE_DEFKEY
;
9271 rtl8xxxu_write8(priv
, REG_SECURITY_CFG
, val8
);
9275 key
->hw_key_idx
= key
->keyidx
;
9276 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
9277 rtl8xxxu_cam_write(priv
, key
, mac_addr
);
9281 rtl8xxxu_write32(priv
, REG_CAM_WRITE
, 0x00000000);
9282 val32
= CAM_CMD_POLLING
| CAM_CMD_WRITE
|
9283 key
->keyidx
<< CAM_CMD_KEY_SHIFT
;
9284 rtl8xxxu_write32(priv
, REG_CAM_CMD
, val32
);
9288 dev_warn(dev
, "%s: Unsupported command %02x\n", __func__
, cmd
);
9295 rtl8xxxu_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
9296 struct ieee80211_ampdu_params
*params
)
9298 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9299 struct device
*dev
= &priv
->udev
->dev
;
9300 u8 ampdu_factor
, ampdu_density
;
9301 struct ieee80211_sta
*sta
= params
->sta
;
9302 enum ieee80211_ampdu_mlme_action action
= params
->action
;
9305 case IEEE80211_AMPDU_TX_START
:
9306 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_START\n", __func__
);
9307 ampdu_factor
= sta
->ht_cap
.ampdu_factor
;
9308 ampdu_density
= sta
->ht_cap
.ampdu_density
;
9309 rtl8xxxu_set_ampdu_factor(priv
, ampdu_factor
);
9310 rtl8xxxu_set_ampdu_min_space(priv
, ampdu_density
);
9312 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
9313 ampdu_factor
, ampdu_density
);
9315 case IEEE80211_AMPDU_TX_STOP_FLUSH
:
9316 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__
);
9317 rtl8xxxu_set_ampdu_factor(priv
, 0);
9318 rtl8xxxu_set_ampdu_min_space(priv
, 0);
9320 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
:
9321 dev_info(dev
, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
9323 rtl8xxxu_set_ampdu_factor(priv
, 0);
9324 rtl8xxxu_set_ampdu_min_space(priv
, 0);
9326 case IEEE80211_AMPDU_RX_START
:
9327 dev_info(dev
, "%s: IEEE80211_AMPDU_RX_START\n", __func__
);
9329 case IEEE80211_AMPDU_RX_STOP
:
9330 dev_info(dev
, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__
);
9338 static int rtl8xxxu_start(struct ieee80211_hw
*hw
)
9340 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9341 struct rtl8xxxu_rx_urb
*rx_urb
;
9342 struct rtl8xxxu_tx_urb
*tx_urb
;
9343 unsigned long flags
;
9348 init_usb_anchor(&priv
->rx_anchor
);
9349 init_usb_anchor(&priv
->tx_anchor
);
9350 init_usb_anchor(&priv
->int_anchor
);
9352 priv
->fops
->enable_rf(priv
);
9353 if (priv
->usb_interrupts
) {
9354 ret
= rtl8xxxu_submit_int_urb(hw
);
9359 for (i
= 0; i
< RTL8XXXU_TX_URBS
; i
++) {
9360 tx_urb
= kmalloc(sizeof(struct rtl8xxxu_tx_urb
), GFP_KERNEL
);
9367 usb_init_urb(&tx_urb
->urb
);
9368 INIT_LIST_HEAD(&tx_urb
->list
);
9370 list_add(&tx_urb
->list
, &priv
->tx_urb_free_list
);
9371 priv
->tx_urb_free_count
++;
9374 priv
->tx_stopped
= false;
9376 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
9377 priv
->shutdown
= false;
9378 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
9380 for (i
= 0; i
< RTL8XXXU_RX_URBS
; i
++) {
9381 rx_urb
= kmalloc(sizeof(struct rtl8xxxu_rx_urb
), GFP_KERNEL
);
9388 usb_init_urb(&rx_urb
->urb
);
9389 INIT_LIST_HEAD(&rx_urb
->list
);
9392 ret
= rtl8xxxu_submit_rx_urb(priv
, rx_urb
);
9396 * Accept all data and mgmt frames
9398 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0xffff);
9399 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0xffff);
9401 rtl8xxxu_write32(priv
, REG_OFDM0_XA_AGC_CORE1
, 0x6954341e);
9406 rtl8xxxu_free_tx_resources(priv
);
9408 * Disable all data and mgmt frames
9410 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0x0000);
9411 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0x0000);
9416 static void rtl8xxxu_stop(struct ieee80211_hw
*hw
)
9418 struct rtl8xxxu_priv
*priv
= hw
->priv
;
9419 unsigned long flags
;
9421 rtl8xxxu_write8(priv
, REG_TXPAUSE
, 0xff);
9423 rtl8xxxu_write16(priv
, REG_RXFLTMAP0
, 0x0000);
9424 rtl8xxxu_write16(priv
, REG_RXFLTMAP2
, 0x0000);
9426 spin_lock_irqsave(&priv
->rx_urb_lock
, flags
);
9427 priv
->shutdown
= true;
9428 spin_unlock_irqrestore(&priv
->rx_urb_lock
, flags
);
9430 usb_kill_anchored_urbs(&priv
->rx_anchor
);
9431 usb_kill_anchored_urbs(&priv
->tx_anchor
);
9432 if (priv
->usb_interrupts
)
9433 usb_kill_anchored_urbs(&priv
->int_anchor
);
9435 priv
->fops
->disable_rf(priv
);
9438 * Disable interrupts
9440 if (priv
->usb_interrupts
)
9441 rtl8xxxu_write32(priv
, REG_USB_HIMR
, 0);
9443 rtl8xxxu_free_rx_resources(priv
);
9444 rtl8xxxu_free_tx_resources(priv
);
9447 static const struct ieee80211_ops rtl8xxxu_ops
= {
9449 .add_interface
= rtl8xxxu_add_interface
,
9450 .remove_interface
= rtl8xxxu_remove_interface
,
9451 .config
= rtl8xxxu_config
,
9452 .conf_tx
= rtl8xxxu_conf_tx
,
9453 .bss_info_changed
= rtl8xxxu_bss_info_changed
,
9454 .configure_filter
= rtl8xxxu_configure_filter
,
9455 .set_rts_threshold
= rtl8xxxu_set_rts_threshold
,
9456 .start
= rtl8xxxu_start
,
9457 .stop
= rtl8xxxu_stop
,
9458 .sw_scan_start
= rtl8xxxu_sw_scan_start
,
9459 .sw_scan_complete
= rtl8xxxu_sw_scan_complete
,
9460 .set_key
= rtl8xxxu_set_key
,
9461 .ampdu_action
= rtl8xxxu_ampdu_action
,
9464 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv
*priv
,
9465 struct usb_interface
*interface
)
9467 struct usb_interface_descriptor
*interface_desc
;
9468 struct usb_host_interface
*host_interface
;
9469 struct usb_endpoint_descriptor
*endpoint
;
9470 struct device
*dev
= &priv
->udev
->dev
;
9471 int i
, j
= 0, endpoints
;
9475 host_interface
= &interface
->altsetting
[0];
9476 interface_desc
= &host_interface
->desc
;
9477 endpoints
= interface_desc
->bNumEndpoints
;
9479 for (i
= 0; i
< endpoints
; i
++) {
9480 endpoint
= &host_interface
->endpoint
[i
].desc
;
9482 dir
= endpoint
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
;
9483 num
= usb_endpoint_num(endpoint
);
9484 xtype
= usb_endpoint_type(endpoint
);
9485 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
9487 "%s: endpoint: dir %02x, # %02x, type %02x\n",
9488 __func__
, dir
, num
, xtype
);
9489 if (usb_endpoint_dir_in(endpoint
) &&
9490 usb_endpoint_xfer_bulk(endpoint
)) {
9491 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
9492 dev_dbg(dev
, "%s: in endpoint num %i\n",
9495 if (priv
->pipe_in
) {
9497 "%s: Too many IN pipes\n", __func__
);
9502 priv
->pipe_in
= usb_rcvbulkpipe(priv
->udev
, num
);
9505 if (usb_endpoint_dir_in(endpoint
) &&
9506 usb_endpoint_xfer_int(endpoint
)) {
9507 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
9508 dev_dbg(dev
, "%s: interrupt endpoint num %i\n",
9511 if (priv
->pipe_interrupt
) {
9512 dev_warn(dev
, "%s: Too many INTERRUPT pipes\n",
9518 priv
->pipe_interrupt
= usb_rcvintpipe(priv
->udev
, num
);
9521 if (usb_endpoint_dir_out(endpoint
) &&
9522 usb_endpoint_xfer_bulk(endpoint
)) {
9523 if (rtl8xxxu_debug
& RTL8XXXU_DEBUG_USB
)
9524 dev_dbg(dev
, "%s: out endpoint num %i\n",
9526 if (j
>= RTL8XXXU_OUT_ENDPOINTS
) {
9528 "%s: Too many OUT pipes\n", __func__
);
9532 priv
->out_ep
[j
++] = num
;
9536 priv
->nr_out_eps
= j
;
9540 static int rtl8xxxu_probe(struct usb_interface
*interface
,
9541 const struct usb_device_id
*id
)
9543 struct rtl8xxxu_priv
*priv
;
9544 struct ieee80211_hw
*hw
;
9545 struct usb_device
*udev
;
9546 struct ieee80211_supported_band
*sband
;
9550 udev
= usb_get_dev(interface_to_usbdev(interface
));
9552 switch (id
->idVendor
) {
9553 case USB_VENDOR_ID_REALTEK
:
9554 switch(id
->idProduct
) {
9564 if (id
->idProduct
== 0x7811)
9572 rtl8xxxu_debug
|= RTL8XXXU_DEBUG_EFUSE
;
9573 dev_info(&udev
->dev
,
9574 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
9575 id
->idVendor
, id
->idProduct
);
9576 dev_info(&udev
->dev
,
9577 "Please report results to Jes.Sorensen@gmail.com\n");
9580 hw
= ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv
), &rtl8xxxu_ops
);
9589 priv
->fops
= (struct rtl8xxxu_fileops
*)id
->driver_info
;
9590 mutex_init(&priv
->usb_buf_mutex
);
9591 mutex_init(&priv
->h2c_mutex
);
9592 INIT_LIST_HEAD(&priv
->tx_urb_free_list
);
9593 spin_lock_init(&priv
->tx_urb_lock
);
9594 INIT_LIST_HEAD(&priv
->rx_urb_pending_list
);
9595 spin_lock_init(&priv
->rx_urb_lock
);
9596 INIT_WORK(&priv
->rx_urb_wq
, rtl8xxxu_rx_urb_work
);
9598 usb_set_intfdata(interface
, hw
);
9600 ret
= rtl8xxxu_parse_usb(priv
, interface
);
9604 ret
= rtl8xxxu_identify_chip(priv
);
9606 dev_err(&udev
->dev
, "Fatal - failed to identify chip\n");
9610 ret
= rtl8xxxu_read_efuse(priv
);
9612 dev_err(&udev
->dev
, "Fatal - failed to read EFuse\n");
9616 ret
= priv
->fops
->parse_efuse(priv
);
9618 dev_err(&udev
->dev
, "Fatal - failed to parse EFuse\n");
9622 rtl8xxxu_print_chipinfo(priv
);
9624 ret
= priv
->fops
->load_firmware(priv
);
9626 dev_err(&udev
->dev
, "Fatal - failed to load firmware\n");
9630 ret
= rtl8xxxu_init_device(hw
);
9632 hw
->wiphy
->max_scan_ssids
= 1;
9633 hw
->wiphy
->max_scan_ie_len
= IEEE80211_MAX_DATA_LEN
;
9634 hw
->wiphy
->interface_modes
= BIT(NL80211_IFTYPE_STATION
);
9637 sband
= &rtl8xxxu_supported_band
;
9638 sband
->ht_cap
.ht_supported
= true;
9639 sband
->ht_cap
.ampdu_factor
= IEEE80211_HT_MAX_AMPDU_64K
;
9640 sband
->ht_cap
.ampdu_density
= IEEE80211_HT_MPDU_DENSITY_16
;
9641 sband
->ht_cap
.cap
= IEEE80211_HT_CAP_SGI_20
| IEEE80211_HT_CAP_SGI_40
;
9642 memset(&sband
->ht_cap
.mcs
, 0, sizeof(sband
->ht_cap
.mcs
));
9643 sband
->ht_cap
.mcs
.rx_mask
[0] = 0xff;
9644 sband
->ht_cap
.mcs
.rx_mask
[4] = 0x01;
9645 if (priv
->rf_paths
> 1) {
9646 sband
->ht_cap
.mcs
.rx_mask
[1] = 0xff;
9647 sband
->ht_cap
.cap
|= IEEE80211_HT_CAP_SGI_40
;
9649 sband
->ht_cap
.mcs
.tx_params
= IEEE80211_HT_MCS_TX_DEFINED
;
9651 * Some APs will negotiate HT20_40 in a noisy environment leading
9652 * to miserable performance. Rather than defaulting to this, only
9653 * enable it if explicitly requested at module load time.
9655 if (rtl8xxxu_ht40_2g
) {
9656 dev_info(&udev
->dev
, "Enabling HT_20_40 on the 2.4GHz band\n");
9657 sband
->ht_cap
.cap
|= IEEE80211_HT_CAP_SUP_WIDTH_20_40
;
9659 hw
->wiphy
->bands
[NL80211_BAND_2GHZ
] = sband
;
9661 hw
->wiphy
->rts_threshold
= 2347;
9663 SET_IEEE80211_DEV(priv
->hw
, &interface
->dev
);
9664 SET_IEEE80211_PERM_ADDR(hw
, priv
->mac_addr
);
9666 hw
->extra_tx_headroom
= priv
->fops
->tx_desc_size
;
9667 ieee80211_hw_set(hw
, SIGNAL_DBM
);
9669 * The firmware handles rate control
9671 ieee80211_hw_set(hw
, HAS_RATE_CONTROL
);
9672 ieee80211_hw_set(hw
, AMPDU_AGGREGATION
);
9674 ret
= ieee80211_register_hw(priv
->hw
);
9676 dev_err(&udev
->dev
, "%s: Failed to register: %i\n",
9687 static void rtl8xxxu_disconnect(struct usb_interface
*interface
)
9689 struct rtl8xxxu_priv
*priv
;
9690 struct ieee80211_hw
*hw
;
9692 hw
= usb_get_intfdata(interface
);
9695 rtl8xxxu_disable_device(hw
);
9696 usb_set_intfdata(interface
, NULL
);
9698 dev_info(&priv
->udev
->dev
, "disconnecting\n");
9700 ieee80211_unregister_hw(hw
);
9702 kfree(priv
->fw_data
);
9703 mutex_destroy(&priv
->usb_buf_mutex
);
9704 mutex_destroy(&priv
->h2c_mutex
);
9706 usb_put_dev(priv
->udev
);
9707 ieee80211_free_hw(hw
);
9710 static struct rtl8xxxu_fileops rtl8723au_fops
= {
9711 .parse_efuse
= rtl8723au_parse_efuse
,
9712 .load_firmware
= rtl8723au_load_firmware
,
9713 .power_on
= rtl8723au_power_on
,
9714 .power_off
= rtl8xxxu_power_off
,
9715 .reset_8051
= rtl8xxxu_reset_8051
,
9716 .llt_init
= rtl8xxxu_init_llt_table
,
9717 .init_phy_bb
= rtl8723au_init_phy_bb
,
9718 .phy_iq_calibrate
= rtl8723au_phy_iq_calibrate
,
9719 .config_channel
= rtl8723au_config_channel
,
9720 .parse_rx_desc
= rtl8xxxu_parse_rxdesc16
,
9721 .enable_rf
= rtl8723a_enable_rf
,
9722 .disable_rf
= rtl8723a_disable_rf
,
9723 .usb_quirks
= rtl8xxxu_gen1_usb_quirks
,
9724 .set_tx_power
= rtl8723a_set_tx_power
,
9725 .update_rate_mask
= rtl8723au_update_rate_mask
,
9726 .report_connect
= rtl8723au_report_connect
,
9727 .writeN_block_size
= 1024,
9728 .mbox_ext_reg
= REG_HMBOX_EXT_0
,
9729 .mbox_ext_width
= 2,
9730 .tx_desc_size
= sizeof(struct rtl8xxxu_txdesc32
),
9731 .rx_desc_size
= sizeof(struct rtl8xxxu_rxdesc16
),
9732 .adda_1t_init
= 0x0b1b25a0,
9733 .adda_1t_path_on
= 0x0bdb25a0,
9734 .adda_2t_path_on_a
= 0x04db25a4,
9735 .adda_2t_path_on_b
= 0x0b1b25a4,
9736 .trxff_boundary
= 0x27ff,
9737 .pbp_rx
= PBP_PAGE_SIZE_128
,
9738 .pbp_tx
= PBP_PAGE_SIZE_128
,
9739 .mactable
= rtl8723a_mac_init_table
,
9742 static struct rtl8xxxu_fileops rtl8723bu_fops
= {
9743 .parse_efuse
= rtl8723bu_parse_efuse
,
9744 .load_firmware
= rtl8723bu_load_firmware
,
9745 .power_on
= rtl8723bu_power_on
,
9746 .power_off
= rtl8723bu_power_off
,
9747 .reset_8051
= rtl8723bu_reset_8051
,
9748 .llt_init
= rtl8xxxu_auto_llt_table
,
9749 .init_phy_bb
= rtl8723bu_init_phy_bb
,
9750 .phy_init_antenna_selection
= rtl8723bu_phy_init_antenna_selection
,
9751 .phy_iq_calibrate
= rtl8723bu_phy_iq_calibrate
,
9752 .config_channel
= rtl8723bu_config_channel
,
9753 .parse_rx_desc
= rtl8xxxu_parse_rxdesc24
,
9754 .init_aggregation
= rtl8723bu_init_aggregation
,
9755 .init_statistics
= rtl8723bu_init_statistics
,
9756 .enable_rf
= rtl8723b_enable_rf
,
9757 .disable_rf
= rtl8723b_disable_rf
,
9758 .usb_quirks
= rtl8xxxu_gen2_usb_quirks
,
9759 .set_tx_power
= rtl8723b_set_tx_power
,
9760 .update_rate_mask
= rtl8723bu_update_rate_mask
,
9761 .report_connect
= rtl8723bu_report_connect
,
9762 .writeN_block_size
= 1024,
9763 .mbox_ext_reg
= REG_HMBOX_EXT0_8723B
,
9764 .mbox_ext_width
= 4,
9765 .tx_desc_size
= sizeof(struct rtl8xxxu_txdesc40
),
9766 .rx_desc_size
= sizeof(struct rtl8xxxu_rxdesc24
),
9768 .adda_1t_init
= 0x01c00014,
9769 .adda_1t_path_on
= 0x01c00014,
9770 .adda_2t_path_on_a
= 0x01c00014,
9771 .adda_2t_path_on_b
= 0x01c00014,
9772 .trxff_boundary
= 0x3f7f,
9773 .pbp_rx
= PBP_PAGE_SIZE_256
,
9774 .pbp_tx
= PBP_PAGE_SIZE_256
,
9775 .mactable
= rtl8723b_mac_init_table
,
9778 #ifdef CONFIG_RTL8XXXU_UNTESTED
9780 static struct rtl8xxxu_fileops rtl8192cu_fops
= {
9781 .parse_efuse
= rtl8192cu_parse_efuse
,
9782 .load_firmware
= rtl8192cu_load_firmware
,
9783 .power_on
= rtl8192cu_power_on
,
9784 .power_off
= rtl8xxxu_power_off
,
9785 .reset_8051
= rtl8xxxu_reset_8051
,
9786 .llt_init
= rtl8xxxu_init_llt_table
,
9787 .init_phy_bb
= rtl8723au_init_phy_bb
,
9788 .phy_iq_calibrate
= rtl8723au_phy_iq_calibrate
,
9789 .config_channel
= rtl8723au_config_channel
,
9790 .parse_rx_desc
= rtl8xxxu_parse_rxdesc16
,
9791 .enable_rf
= rtl8723a_enable_rf
,
9792 .disable_rf
= rtl8723a_disable_rf
,
9793 .usb_quirks
= rtl8xxxu_gen1_usb_quirks
,
9794 .set_tx_power
= rtl8723a_set_tx_power
,
9795 .update_rate_mask
= rtl8723au_update_rate_mask
,
9796 .report_connect
= rtl8723au_report_connect
,
9797 .writeN_block_size
= 128,
9798 .mbox_ext_reg
= REG_HMBOX_EXT_0
,
9799 .mbox_ext_width
= 2,
9800 .tx_desc_size
= sizeof(struct rtl8xxxu_txdesc32
),
9801 .rx_desc_size
= sizeof(struct rtl8xxxu_rxdesc16
),
9802 .adda_1t_init
= 0x0b1b25a0,
9803 .adda_1t_path_on
= 0x0bdb25a0,
9804 .adda_2t_path_on_a
= 0x04db25a4,
9805 .adda_2t_path_on_b
= 0x0b1b25a4,
9806 .trxff_boundary
= 0x27ff,
9807 .pbp_rx
= PBP_PAGE_SIZE_128
,
9808 .pbp_tx
= PBP_PAGE_SIZE_128
,
9809 .mactable
= rtl8723a_mac_init_table
,
9814 static struct rtl8xxxu_fileops rtl8192eu_fops
= {
9815 .parse_efuse
= rtl8192eu_parse_efuse
,
9816 .load_firmware
= rtl8192eu_load_firmware
,
9817 .power_on
= rtl8192eu_power_on
,
9818 .power_off
= rtl8xxxu_power_off
,
9819 .reset_8051
= rtl8xxxu_reset_8051
,
9820 .llt_init
= rtl8xxxu_auto_llt_table
,
9821 .init_phy_bb
= rtl8192eu_init_phy_bb
,
9822 .phy_iq_calibrate
= rtl8192eu_phy_iq_calibrate
,
9823 .config_channel
= rtl8723bu_config_channel
,
9824 .parse_rx_desc
= rtl8xxxu_parse_rxdesc24
,
9825 .enable_rf
= rtl8723b_enable_rf
,
9826 .disable_rf
= rtl8723b_disable_rf
,
9827 .usb_quirks
= rtl8xxxu_gen2_usb_quirks
,
9828 .set_tx_power
= rtl8192e_set_tx_power
,
9829 .update_rate_mask
= rtl8723bu_update_rate_mask
,
9830 .report_connect
= rtl8723bu_report_connect
,
9831 .writeN_block_size
= 128,
9832 .mbox_ext_reg
= REG_HMBOX_EXT0_8723B
,
9833 .mbox_ext_width
= 4,
9834 .tx_desc_size
= sizeof(struct rtl8xxxu_txdesc40
),
9835 .rx_desc_size
= sizeof(struct rtl8xxxu_rxdesc24
),
9837 .adda_1t_init
= 0x0fc01616,
9838 .adda_1t_path_on
= 0x0fc01616,
9839 .adda_2t_path_on_a
= 0x0fc01616,
9840 .adda_2t_path_on_b
= 0x0fc01616,
9841 .trxff_boundary
= 0x3cff,
9842 .mactable
= rtl8192e_mac_init_table
,
9843 .total_page_num
= TX_TOTAL_PAGE_NUM_8192E
,
9844 .page_num_hi
= TX_PAGE_NUM_HI_PQ_8192E
,
9845 .page_num_lo
= TX_PAGE_NUM_LO_PQ_8192E
,
9846 .page_num_norm
= TX_PAGE_NUM_NORM_PQ_8192E
,
9849 static struct usb_device_id dev_table
[] = {
9850 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8724, 0xff, 0xff, 0xff),
9851 .driver_info
= (unsigned long)&rtl8723au_fops
},
9852 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x1724, 0xff, 0xff, 0xff),
9853 .driver_info
= (unsigned long)&rtl8723au_fops
},
9854 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x0724, 0xff, 0xff, 0xff),
9855 .driver_info
= (unsigned long)&rtl8723au_fops
},
9856 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x818b, 0xff, 0xff, 0xff),
9857 .driver_info
= (unsigned long)&rtl8192eu_fops
},
9858 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0xb720, 0xff, 0xff, 0xff),
9859 .driver_info
= (unsigned long)&rtl8723bu_fops
},
9860 #ifdef CONFIG_RTL8XXXU_UNTESTED
9861 /* Still supported by rtlwifi */
9862 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8176, 0xff, 0xff, 0xff),
9863 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9864 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8178, 0xff, 0xff, 0xff),
9865 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9866 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817f, 0xff, 0xff, 0xff),
9867 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9868 /* Tested by Larry Finger */
9869 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
9870 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9871 /* Currently untested 8188 series devices */
9872 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8191, 0xff, 0xff, 0xff),
9873 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9874 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8170, 0xff, 0xff, 0xff),
9875 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9876 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x8177, 0xff, 0xff, 0xff),
9877 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9878 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817a, 0xff, 0xff, 0xff),
9879 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9880 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817b, 0xff, 0xff, 0xff),
9881 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9882 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817d, 0xff, 0xff, 0xff),
9883 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9884 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x817e, 0xff, 0xff, 0xff),
9885 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9886 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x818a, 0xff, 0xff, 0xff),
9887 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9888 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x317f, 0xff, 0xff, 0xff),
9889 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9890 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
9891 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9892 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
9893 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9894 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
9895 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9896 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
9897 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9898 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
9899 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9900 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
9901 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9902 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
9903 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9904 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x1e1e, 0xff, 0xff, 0xff),
9905 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9906 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x5088, 0xff, 0xff, 0xff),
9907 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9908 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
9909 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9910 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
9911 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9912 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
9913 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9914 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
9915 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9916 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
9917 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9918 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
9919 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9920 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
9921 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9922 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
9923 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9924 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
9925 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9926 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
9927 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9928 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
9929 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9930 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
9931 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9932 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
9933 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9934 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
9935 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9936 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
9937 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9938 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
9939 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9940 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
9941 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9942 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
9943 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9944 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
9945 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9946 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
9947 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9948 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
9949 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9950 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
9951 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9952 /* Currently untested 8192 series devices */
9953 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
9954 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9955 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
9956 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9957 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
9958 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9959 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
9960 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9961 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
9962 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9963 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
9964 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9965 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
9966 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9967 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
9968 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9969 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
9970 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9971 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
9972 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9973 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
9974 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9975 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
9976 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9977 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
9978 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9979 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
9980 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9981 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK
, 0x2e2e, 0xff, 0xff, 0xff),
9982 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9983 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
9984 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9985 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
9986 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9987 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
9988 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9989 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
9990 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9991 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
9992 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9993 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
9994 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9995 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
9996 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9997 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
9998 .driver_info
= (unsigned long)&rtl8192cu_fops
},
9999 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
10000 .driver_info
= (unsigned long)&rtl8192cu_fops
},
10001 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
10002 .driver_info
= (unsigned long)&rtl8192cu_fops
},
10007 static struct usb_driver rtl8xxxu_driver
= {
10008 .name
= DRIVER_NAME
,
10009 .probe
= rtl8xxxu_probe
,
10010 .disconnect
= rtl8xxxu_disconnect
,
10011 .id_table
= dev_table
,
10012 .disable_hub_initiated_lpm
= 1,
10015 static int __init
rtl8xxxu_module_init(void)
10019 res
= usb_register(&rtl8xxxu_driver
);
10021 pr_err(DRIVER_NAME
": usb_register() failed (%i)\n", res
);
10026 static void __exit
rtl8xxxu_module_exit(void)
10028 usb_deregister(&rtl8xxxu_driver
);
10032 MODULE_DEVICE_TABLE(usb
, dev_table
);
10034 module_init(rtl8xxxu_module_init
);
10035 module_exit(rtl8xxxu_module_exit
);