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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.c
1 /*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 /*
20 Module: rt61pci
21 Abstract: rt61pci device specific routines.
22 Supported chipsets: RT2561, RT2561s, RT2661.
23 */
24
25 #include <linux/crc-itu-t.h>
26 #include <linux/delay.h>
27 #include <linux/etherdevice.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/eeprom_93cx6.h>
33
34 #include "rt2x00.h"
35 #include "rt2x00mmio.h"
36 #include "rt2x00pci.h"
37 #include "rt61pci.h"
38
39 /*
40 * Allow hardware encryption to be disabled.
41 */
42 static bool modparam_nohwcrypt = false;
43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46 /*
47 * Register access.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attempt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 */
57 #define WAIT_FOR_BBP(__dev, __reg) \
58 rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
59 #define WAIT_FOR_RF(__dev, __reg) \
60 rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
61 #define WAIT_FOR_MCU(__dev, __reg) \
62 rt2x00mmio_regbusy_read((__dev), H2M_MAILBOX_CSR, \
63 H2M_MAILBOX_CSR_OWNER, (__reg))
64
65 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
66 const unsigned int word, const u8 value)
67 {
68 u32 reg;
69
70 mutex_lock(&rt2x00dev->csr_mutex);
71
72 /*
73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
75 */
76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77 reg = 0;
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
84 }
85
86 mutex_unlock(&rt2x00dev->csr_mutex);
87 }
88
89 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
90 const unsigned int word, u8 *value)
91 {
92 u32 reg;
93
94 mutex_lock(&rt2x00dev->csr_mutex);
95
96 /*
97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
103 */
104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105 reg = 0;
106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
109
110 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
111
112 WAIT_FOR_BBP(rt2x00dev, &reg);
113 }
114
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
116
117 mutex_unlock(&rt2x00dev->csr_mutex);
118 }
119
120 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
121 const unsigned int word, const u32 value)
122 {
123 u32 reg;
124
125 mutex_lock(&rt2x00dev->csr_mutex);
126
127 /*
128 * Wait until the RF becomes available, afterwards we
129 * can safely write the new data into the register.
130 */
131 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
132 reg = 0;
133 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
134 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
135 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
136 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
137
138 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg);
139 rt2x00_rf_write(rt2x00dev, word, value);
140 }
141
142 mutex_unlock(&rt2x00dev->csr_mutex);
143 }
144
145 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
146 const u8 command, const u8 token,
147 const u8 arg0, const u8 arg1)
148 {
149 u32 reg;
150
151 mutex_lock(&rt2x00dev->csr_mutex);
152
153 /*
154 * Wait until the MCU becomes available, afterwards we
155 * can safely write the new data into the register.
156 */
157 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
158 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
159 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
162 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
163
164 rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
165 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
166 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
167 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg);
168 }
169
170 mutex_unlock(&rt2x00dev->csr_mutex);
171
172 }
173
174 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
175 {
176 struct rt2x00_dev *rt2x00dev = eeprom->data;
177 u32 reg;
178
179 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
180
181 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
182 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
183 eeprom->reg_data_clock =
184 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
185 eeprom->reg_chip_select =
186 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
187 }
188
189 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
190 {
191 struct rt2x00_dev *rt2x00dev = eeprom->data;
192 u32 reg = 0;
193
194 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
195 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
197 !!eeprom->reg_data_clock);
198 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
199 !!eeprom->reg_chip_select);
200
201 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
202 }
203
204 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
205 static const struct rt2x00debug rt61pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2x00mmio_register_read,
209 .write = rt2x00mmio_register_write,
210 .flags = RT2X00DEBUGFS_OFFSET,
211 .word_base = CSR_REG_BASE,
212 .word_size = sizeof(u32),
213 .word_count = CSR_REG_SIZE / sizeof(u32),
214 },
215 .eeprom = {
216 .read = rt2x00_eeprom_read,
217 .write = rt2x00_eeprom_write,
218 .word_base = EEPROM_BASE,
219 .word_size = sizeof(u16),
220 .word_count = EEPROM_SIZE / sizeof(u16),
221 },
222 .bbp = {
223 .read = rt61pci_bbp_read,
224 .write = rt61pci_bbp_write,
225 .word_base = BBP_BASE,
226 .word_size = sizeof(u8),
227 .word_count = BBP_SIZE / sizeof(u8),
228 },
229 .rf = {
230 .read = rt2x00_rf_read,
231 .write = rt61pci_rf_write,
232 .word_base = RF_BASE,
233 .word_size = sizeof(u32),
234 .word_count = RF_SIZE / sizeof(u32),
235 },
236 };
237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238
239 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
240 {
241 u32 reg;
242
243 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
244 return rt2x00_get_field32(reg, MAC_CSR13_VAL5);
245 }
246
247 #ifdef CONFIG_RT2X00_LIB_LEDS
248 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
249 enum led_brightness brightness)
250 {
251 struct rt2x00_led *led =
252 container_of(led_cdev, struct rt2x00_led, led_dev);
253 unsigned int enabled = brightness != LED_OFF;
254 unsigned int a_mode =
255 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
256 unsigned int bg_mode =
257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
258
259 if (led->type == LED_TYPE_RADIO) {
260 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
261 MCU_LEDCS_RADIO_STATUS, enabled);
262
263 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
264 (led->rt2x00dev->led_mcu_reg & 0xff),
265 ((led->rt2x00dev->led_mcu_reg >> 8)));
266 } else if (led->type == LED_TYPE_ASSOC) {
267 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
268 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
270 MCU_LEDCS_LINK_A_STATUS, a_mode);
271
272 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
273 (led->rt2x00dev->led_mcu_reg & 0xff),
274 ((led->rt2x00dev->led_mcu_reg >> 8)));
275 } else if (led->type == LED_TYPE_QUALITY) {
276 /*
277 * The brightness is divided into 6 levels (0 - 5),
278 * this means we need to convert the brightness
279 * argument into the matching level within that range.
280 */
281 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
282 brightness / (LED_FULL / 6), 0);
283 }
284 }
285
286 static int rt61pci_blink_set(struct led_classdev *led_cdev,
287 unsigned long *delay_on,
288 unsigned long *delay_off)
289 {
290 struct rt2x00_led *led =
291 container_of(led_cdev, struct rt2x00_led, led_dev);
292 u32 reg;
293
294 rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, &reg);
295 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
296 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
297 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg);
298
299 return 0;
300 }
301
302 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
303 struct rt2x00_led *led,
304 enum led_type type)
305 {
306 led->rt2x00dev = rt2x00dev;
307 led->type = type;
308 led->led_dev.brightness_set = rt61pci_brightness_set;
309 led->led_dev.blink_set = rt61pci_blink_set;
310 led->flags = LED_INITIALIZED;
311 }
312 #endif /* CONFIG_RT2X00_LIB_LEDS */
313
314 /*
315 * Configuration handlers.
316 */
317 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
318 struct rt2x00lib_crypto *crypto,
319 struct ieee80211_key_conf *key)
320 {
321 struct hw_key_entry key_entry;
322 struct rt2x00_field32 field;
323 u32 mask;
324 u32 reg;
325
326 if (crypto->cmd == SET_KEY) {
327 /*
328 * rt2x00lib can't determine the correct free
329 * key_idx for shared keys. We have 1 register
330 * with key valid bits. The goal is simple, read
331 * the register, if that is full we have no slots
332 * left.
333 * Note that each BSS is allowed to have up to 4
334 * shared keys, so put a mask over the allowed
335 * entries.
336 */
337 mask = (0xf << crypto->bssidx);
338
339 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
340 reg &= mask;
341
342 if (reg && reg == mask)
343 return -ENOSPC;
344
345 key->hw_key_idx += reg ? ffz(reg) : 0;
346
347 /*
348 * Upload key to hardware
349 */
350 memcpy(key_entry.key, crypto->key,
351 sizeof(key_entry.key));
352 memcpy(key_entry.tx_mic, crypto->tx_mic,
353 sizeof(key_entry.tx_mic));
354 memcpy(key_entry.rx_mic, crypto->rx_mic,
355 sizeof(key_entry.rx_mic));
356
357 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
358 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
359 &key_entry, sizeof(key_entry));
360
361 /*
362 * The cipher types are stored over 2 registers.
363 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
364 * bssidx 1 and 2 keys are stored in SEC_CSR5.
365 * Using the correct defines correctly will cause overhead,
366 * so just calculate the correct offset.
367 */
368 if (key->hw_key_idx < 8) {
369 field.bit_offset = (3 * key->hw_key_idx);
370 field.bit_mask = 0x7 << field.bit_offset;
371
372 rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, &reg);
373 rt2x00_set_field32(&reg, field, crypto->cipher);
374 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg);
375 } else {
376 field.bit_offset = (3 * (key->hw_key_idx - 8));
377 field.bit_mask = 0x7 << field.bit_offset;
378
379 rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, &reg);
380 rt2x00_set_field32(&reg, field, crypto->cipher);
381 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg);
382 }
383
384 /*
385 * The driver does not support the IV/EIV generation
386 * in hardware. However it doesn't support the IV/EIV
387 * inside the ieee80211 frame either, but requires it
388 * to be provided separately for the descriptor.
389 * rt2x00lib will cut the IV/EIV data out of all frames
390 * given to us by mac80211, but we must tell mac80211
391 * to generate the IV/EIV data.
392 */
393 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
394 }
395
396 /*
397 * SEC_CSR0 contains only single-bit fields to indicate
398 * a particular key is valid. Because using the FIELD32()
399 * defines directly will cause a lot of overhead, we use
400 * a calculation to determine the correct bit directly.
401 */
402 mask = 1 << key->hw_key_idx;
403
404 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
405 if (crypto->cmd == SET_KEY)
406 reg |= mask;
407 else if (crypto->cmd == DISABLE_KEY)
408 reg &= ~mask;
409 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg);
410
411 return 0;
412 }
413
414 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
415 struct rt2x00lib_crypto *crypto,
416 struct ieee80211_key_conf *key)
417 {
418 struct hw_pairwise_ta_entry addr_entry;
419 struct hw_key_entry key_entry;
420 u32 mask;
421 u32 reg;
422
423 if (crypto->cmd == SET_KEY) {
424 /*
425 * rt2x00lib can't determine the correct free
426 * key_idx for pairwise keys. We have 2 registers
427 * with key valid bits. The goal is simple: read
428 * the first register. If that is full, move to
429 * the next register.
430 * When both registers are full, we drop the key.
431 * Otherwise, we use the first invalid entry.
432 */
433 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
434 if (reg && reg == ~0) {
435 key->hw_key_idx = 32;
436 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
437 if (reg && reg == ~0)
438 return -ENOSPC;
439 }
440
441 key->hw_key_idx += reg ? ffz(reg) : 0;
442
443 /*
444 * Upload key to hardware
445 */
446 memcpy(key_entry.key, crypto->key,
447 sizeof(key_entry.key));
448 memcpy(key_entry.tx_mic, crypto->tx_mic,
449 sizeof(key_entry.tx_mic));
450 memcpy(key_entry.rx_mic, crypto->rx_mic,
451 sizeof(key_entry.rx_mic));
452
453 memset(&addr_entry, 0, sizeof(addr_entry));
454 memcpy(&addr_entry, crypto->address, ETH_ALEN);
455 addr_entry.cipher = crypto->cipher;
456
457 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
458 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
459 &key_entry, sizeof(key_entry));
460
461 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
462 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
463 &addr_entry, sizeof(addr_entry));
464
465 /*
466 * Enable pairwise lookup table for given BSS idx.
467 * Without this, received frames will not be decrypted
468 * by the hardware.
469 */
470 rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, &reg);
471 reg |= (1 << crypto->bssidx);
472 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg);
473
474 /*
475 * The driver does not support the IV/EIV generation
476 * in hardware. However it doesn't support the IV/EIV
477 * inside the ieee80211 frame either, but requires it
478 * to be provided separately for the descriptor.
479 * rt2x00lib will cut the IV/EIV data out of all frames
480 * given to us by mac80211, but we must tell mac80211
481 * to generate the IV/EIV data.
482 */
483 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
484 }
485
486 /*
487 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
488 * a particular key is valid. Because using the FIELD32()
489 * defines directly will cause a lot of overhead, we use
490 * a calculation to determine the correct bit directly.
491 */
492 if (key->hw_key_idx < 32) {
493 mask = 1 << key->hw_key_idx;
494
495 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
496 if (crypto->cmd == SET_KEY)
497 reg |= mask;
498 else if (crypto->cmd == DISABLE_KEY)
499 reg &= ~mask;
500 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg);
501 } else {
502 mask = 1 << (key->hw_key_idx - 32);
503
504 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
505 if (crypto->cmd == SET_KEY)
506 reg |= mask;
507 else if (crypto->cmd == DISABLE_KEY)
508 reg &= ~mask;
509 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg);
510 }
511
512 return 0;
513 }
514
515 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
516 const unsigned int filter_flags)
517 {
518 u32 reg;
519
520 /*
521 * Start configuration steps.
522 * Note that the version error will always be dropped
523 * and broadcast frames will always be accepted since
524 * there is no filter for it at this time.
525 */
526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
527 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
528 !(filter_flags & FIF_FCSFAIL));
529 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
530 !(filter_flags & FIF_PLCPFAIL));
531 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
532 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
533 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME, 1);
534 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
535 !rt2x00dev->intf_ap_count);
536 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
537 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
538 !(filter_flags & FIF_ALLMULTI));
539 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
540 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
541 !(filter_flags & FIF_CONTROL));
542 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
543 }
544
545 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
546 struct rt2x00_intf *intf,
547 struct rt2x00intf_conf *conf,
548 const unsigned int flags)
549 {
550 u32 reg;
551
552 if (flags & CONFIG_UPDATE_TYPE) {
553 /*
554 * Enable synchronisation.
555 */
556 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
557 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
558 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
559 }
560
561 if (flags & CONFIG_UPDATE_MAC) {
562 reg = le32_to_cpu(conf->mac[1]);
563 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
564 conf->mac[1] = cpu_to_le32(reg);
565
566 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2,
567 conf->mac, sizeof(conf->mac));
568 }
569
570 if (flags & CONFIG_UPDATE_BSSID) {
571 reg = le32_to_cpu(conf->bssid[1]);
572 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
573 conf->bssid[1] = cpu_to_le32(reg);
574
575 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4,
576 conf->bssid,
577 sizeof(conf->bssid));
578 }
579 }
580
581 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
582 struct rt2x00lib_erp *erp,
583 u32 changed)
584 {
585 u32 reg;
586
587 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
588 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
589 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
590 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
591
592 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
593 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
594 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
595 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
596 !!erp->short_preamble);
597 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
598 }
599
600 if (changed & BSS_CHANGED_BASIC_RATES)
601 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5,
602 erp->basic_rates);
603
604 if (changed & BSS_CHANGED_BEACON_INT) {
605 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
606 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
607 erp->beacon_int * 16);
608 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
609 }
610
611 if (changed & BSS_CHANGED_ERP_SLOT) {
612 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
613 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
614 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
615
616 rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, &reg);
617 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
618 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
619 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
620 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg);
621 }
622 }
623
624 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
625 struct antenna_setup *ant)
626 {
627 u8 r3;
628 u8 r4;
629 u8 r77;
630
631 rt61pci_bbp_read(rt2x00dev, 3, &r3);
632 rt61pci_bbp_read(rt2x00dev, 4, &r4);
633 rt61pci_bbp_read(rt2x00dev, 77, &r77);
634
635 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
636
637 /*
638 * Configure the RX antenna.
639 */
640 switch (ant->rx) {
641 case ANTENNA_HW_DIVERSITY:
642 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
643 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
644 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
645 break;
646 case ANTENNA_A:
647 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
648 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
649 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
650 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
651 else
652 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
653 break;
654 case ANTENNA_B:
655 default:
656 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
657 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
658 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
659 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
660 else
661 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
662 break;
663 }
664
665 rt61pci_bbp_write(rt2x00dev, 77, r77);
666 rt61pci_bbp_write(rt2x00dev, 3, r3);
667 rt61pci_bbp_write(rt2x00dev, 4, r4);
668 }
669
670 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
671 struct antenna_setup *ant)
672 {
673 u8 r3;
674 u8 r4;
675 u8 r77;
676
677 rt61pci_bbp_read(rt2x00dev, 3, &r3);
678 rt61pci_bbp_read(rt2x00dev, 4, &r4);
679 rt61pci_bbp_read(rt2x00dev, 77, &r77);
680
681 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
682 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
683 !rt2x00_has_cap_frame_type(rt2x00dev));
684
685 /*
686 * Configure the RX antenna.
687 */
688 switch (ant->rx) {
689 case ANTENNA_HW_DIVERSITY:
690 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
691 break;
692 case ANTENNA_A:
693 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
694 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
695 break;
696 case ANTENNA_B:
697 default:
698 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
699 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
700 break;
701 }
702
703 rt61pci_bbp_write(rt2x00dev, 77, r77);
704 rt61pci_bbp_write(rt2x00dev, 3, r3);
705 rt61pci_bbp_write(rt2x00dev, 4, r4);
706 }
707
708 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
709 const int p1, const int p2)
710 {
711 u32 reg;
712
713 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
714
715 rt2x00_set_field32(&reg, MAC_CSR13_DIR4, 0);
716 rt2x00_set_field32(&reg, MAC_CSR13_VAL4, p1);
717
718 rt2x00_set_field32(&reg, MAC_CSR13_DIR3, 0);
719 rt2x00_set_field32(&reg, MAC_CSR13_VAL3, !p2);
720
721 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
722 }
723
724 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
725 struct antenna_setup *ant)
726 {
727 u8 r3;
728 u8 r4;
729 u8 r77;
730
731 rt61pci_bbp_read(rt2x00dev, 3, &r3);
732 rt61pci_bbp_read(rt2x00dev, 4, &r4);
733 rt61pci_bbp_read(rt2x00dev, 77, &r77);
734
735 /*
736 * Configure the RX antenna.
737 */
738 switch (ant->rx) {
739 case ANTENNA_A:
740 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
741 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
742 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
743 break;
744 case ANTENNA_HW_DIVERSITY:
745 /*
746 * FIXME: Antenna selection for the rf 2529 is very confusing
747 * in the legacy driver. Just default to antenna B until the
748 * legacy code can be properly translated into rt2x00 code.
749 */
750 case ANTENNA_B:
751 default:
752 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
753 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
754 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
755 break;
756 }
757
758 rt61pci_bbp_write(rt2x00dev, 77, r77);
759 rt61pci_bbp_write(rt2x00dev, 3, r3);
760 rt61pci_bbp_write(rt2x00dev, 4, r4);
761 }
762
763 struct antenna_sel {
764 u8 word;
765 /*
766 * value[0] -> non-LNA
767 * value[1] -> LNA
768 */
769 u8 value[2];
770 };
771
772 static const struct antenna_sel antenna_sel_a[] = {
773 { 96, { 0x58, 0x78 } },
774 { 104, { 0x38, 0x48 } },
775 { 75, { 0xfe, 0x80 } },
776 { 86, { 0xfe, 0x80 } },
777 { 88, { 0xfe, 0x80 } },
778 { 35, { 0x60, 0x60 } },
779 { 97, { 0x58, 0x58 } },
780 { 98, { 0x58, 0x58 } },
781 };
782
783 static const struct antenna_sel antenna_sel_bg[] = {
784 { 96, { 0x48, 0x68 } },
785 { 104, { 0x2c, 0x3c } },
786 { 75, { 0xfe, 0x80 } },
787 { 86, { 0xfe, 0x80 } },
788 { 88, { 0xfe, 0x80 } },
789 { 35, { 0x50, 0x50 } },
790 { 97, { 0x48, 0x48 } },
791 { 98, { 0x48, 0x48 } },
792 };
793
794 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
795 struct antenna_setup *ant)
796 {
797 const struct antenna_sel *sel;
798 unsigned int lna;
799 unsigned int i;
800 u32 reg;
801
802 /*
803 * We should never come here because rt2x00lib is supposed
804 * to catch this and send us the correct antenna explicitely.
805 */
806 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
807 ant->tx == ANTENNA_SW_DIVERSITY);
808
809 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
810 sel = antenna_sel_a;
811 lna = rt2x00_has_cap_external_lna_a(rt2x00dev);
812 } else {
813 sel = antenna_sel_bg;
814 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev);
815 }
816
817 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
818 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
819
820 rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, &reg);
821
822 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
823 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
824 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
825 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
826
827 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg);
828
829 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
830 rt61pci_config_antenna_5x(rt2x00dev, ant);
831 else if (rt2x00_rf(rt2x00dev, RF2527))
832 rt61pci_config_antenna_2x(rt2x00dev, ant);
833 else if (rt2x00_rf(rt2x00dev, RF2529)) {
834 if (rt2x00_has_cap_double_antenna(rt2x00dev))
835 rt61pci_config_antenna_2x(rt2x00dev, ant);
836 else
837 rt61pci_config_antenna_2529(rt2x00dev, ant);
838 }
839 }
840
841 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
842 struct rt2x00lib_conf *libconf)
843 {
844 u16 eeprom;
845 short lna_gain = 0;
846
847 if (libconf->conf->chandef.chan->band == IEEE80211_BAND_2GHZ) {
848 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
849 lna_gain += 14;
850
851 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
852 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
853 } else {
854 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
855 lna_gain += 14;
856
857 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
858 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
859 }
860
861 rt2x00dev->lna_gain = lna_gain;
862 }
863
864 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
865 struct rf_channel *rf, const int txpower)
866 {
867 u8 r3;
868 u8 r94;
869 u8 smart;
870
871 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
872 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
873
874 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
875
876 rt61pci_bbp_read(rt2x00dev, 3, &r3);
877 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
878 rt61pci_bbp_write(rt2x00dev, 3, r3);
879
880 r94 = 6;
881 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
882 r94 += txpower - MAX_TXPOWER;
883 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
884 r94 += txpower;
885 rt61pci_bbp_write(rt2x00dev, 94, r94);
886
887 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
888 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
889 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
890 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
891
892 udelay(200);
893
894 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
895 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
896 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
897 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
898
899 udelay(200);
900
901 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
902 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
903 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
904 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
905
906 msleep(1);
907 }
908
909 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
910 const int txpower)
911 {
912 struct rf_channel rf;
913
914 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
915 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
916 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
917 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
918
919 rt61pci_config_channel(rt2x00dev, &rf, txpower);
920 }
921
922 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
923 struct rt2x00lib_conf *libconf)
924 {
925 u32 reg;
926
927 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
928 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
929 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
930 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
931 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
932 libconf->conf->long_frame_max_tx_count);
933 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
934 libconf->conf->short_frame_max_tx_count);
935 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
936 }
937
938 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
939 struct rt2x00lib_conf *libconf)
940 {
941 enum dev_state state =
942 (libconf->conf->flags & IEEE80211_CONF_PS) ?
943 STATE_SLEEP : STATE_AWAKE;
944 u32 reg;
945
946 if (state == STATE_SLEEP) {
947 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
948 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
949 rt2x00dev->beacon_int - 10);
950 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
951 libconf->conf->listen_interval - 1);
952 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
953
954 /* We must first disable autowake before it can be enabled */
955 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
956 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
957
958 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
959 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
960
961 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
962 0x00000005);
963 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
964 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
965
966 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
967 } else {
968 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
969 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
970 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
971 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
972 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
973 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
974
975 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
976 0x00000007);
977 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
978 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
979
980 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
981 }
982 }
983
984 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
985 struct rt2x00lib_conf *libconf,
986 const unsigned int flags)
987 {
988 /* Always recalculate LNA gain before changing configuration */
989 rt61pci_config_lna_gain(rt2x00dev, libconf);
990
991 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
992 rt61pci_config_channel(rt2x00dev, &libconf->rf,
993 libconf->conf->power_level);
994 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
995 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
996 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
997 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
998 rt61pci_config_retry_limit(rt2x00dev, libconf);
999 if (flags & IEEE80211_CONF_CHANGE_PS)
1000 rt61pci_config_ps(rt2x00dev, libconf);
1001 }
1002
1003 /*
1004 * Link tuning
1005 */
1006 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1007 struct link_qual *qual)
1008 {
1009 u32 reg;
1010
1011 /*
1012 * Update FCS error count from register.
1013 */
1014 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
1015 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1016
1017 /*
1018 * Update False CCA count from register.
1019 */
1020 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
1021 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1022 }
1023
1024 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1025 struct link_qual *qual, u8 vgc_level)
1026 {
1027 if (qual->vgc_level != vgc_level) {
1028 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1029 qual->vgc_level = vgc_level;
1030 qual->vgc_level_reg = vgc_level;
1031 }
1032 }
1033
1034 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1035 struct link_qual *qual)
1036 {
1037 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1038 }
1039
1040 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1041 struct link_qual *qual, const u32 count)
1042 {
1043 u8 up_bound;
1044 u8 low_bound;
1045
1046 /*
1047 * Determine r17 bounds.
1048 */
1049 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1050 low_bound = 0x28;
1051 up_bound = 0x48;
1052 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
1053 low_bound += 0x10;
1054 up_bound += 0x10;
1055 }
1056 } else {
1057 low_bound = 0x20;
1058 up_bound = 0x40;
1059 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
1060 low_bound += 0x10;
1061 up_bound += 0x10;
1062 }
1063 }
1064
1065 /*
1066 * If we are not associated, we should go straight to the
1067 * dynamic CCA tuning.
1068 */
1069 if (!rt2x00dev->intf_associated)
1070 goto dynamic_cca_tune;
1071
1072 /*
1073 * Special big-R17 for very short distance
1074 */
1075 if (qual->rssi >= -35) {
1076 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1077 return;
1078 }
1079
1080 /*
1081 * Special big-R17 for short distance
1082 */
1083 if (qual->rssi >= -58) {
1084 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1085 return;
1086 }
1087
1088 /*
1089 * Special big-R17 for middle-short distance
1090 */
1091 if (qual->rssi >= -66) {
1092 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1093 return;
1094 }
1095
1096 /*
1097 * Special mid-R17 for middle distance
1098 */
1099 if (qual->rssi >= -74) {
1100 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1101 return;
1102 }
1103
1104 /*
1105 * Special case: Change up_bound based on the rssi.
1106 * Lower up_bound when rssi is weaker then -74 dBm.
1107 */
1108 up_bound -= 2 * (-74 - qual->rssi);
1109 if (low_bound > up_bound)
1110 up_bound = low_bound;
1111
1112 if (qual->vgc_level > up_bound) {
1113 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1114 return;
1115 }
1116
1117 dynamic_cca_tune:
1118
1119 /*
1120 * r17 does not yet exceed upper limit, continue and base
1121 * the r17 tuning on the false CCA count.
1122 */
1123 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1124 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1125 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1126 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1127 }
1128
1129 /*
1130 * Queue handlers.
1131 */
1132 static void rt61pci_start_queue(struct data_queue *queue)
1133 {
1134 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1135 u32 reg;
1136
1137 switch (queue->qid) {
1138 case QID_RX:
1139 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1140 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1141 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1142 break;
1143 case QID_BEACON:
1144 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1145 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1146 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1147 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1148 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1149 break;
1150 default:
1151 break;
1152 }
1153 }
1154
1155 static void rt61pci_kick_queue(struct data_queue *queue)
1156 {
1157 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1158 u32 reg;
1159
1160 switch (queue->qid) {
1161 case QID_AC_VO:
1162 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1163 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1164 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1165 break;
1166 case QID_AC_VI:
1167 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1168 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1169 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1170 break;
1171 case QID_AC_BE:
1172 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1173 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1174 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1175 break;
1176 case QID_AC_BK:
1177 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1178 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1179 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1180 break;
1181 default:
1182 break;
1183 }
1184 }
1185
1186 static void rt61pci_stop_queue(struct data_queue *queue)
1187 {
1188 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1189 u32 reg;
1190
1191 switch (queue->qid) {
1192 case QID_AC_VO:
1193 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1194 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1195 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1196 break;
1197 case QID_AC_VI:
1198 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1199 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1200 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1201 break;
1202 case QID_AC_BE:
1203 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1204 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1205 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1206 break;
1207 case QID_AC_BK:
1208 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1209 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1210 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1211 break;
1212 case QID_RX:
1213 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1214 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1215 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1216 break;
1217 case QID_BEACON:
1218 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1219 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1220 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1221 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1222 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1223
1224 /*
1225 * Wait for possibly running tbtt tasklets.
1226 */
1227 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1228 break;
1229 default:
1230 break;
1231 }
1232 }
1233
1234 /*
1235 * Firmware functions
1236 */
1237 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1238 {
1239 u16 chip;
1240 char *fw_name;
1241
1242 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1243 switch (chip) {
1244 case RT2561_PCI_ID:
1245 fw_name = FIRMWARE_RT2561;
1246 break;
1247 case RT2561s_PCI_ID:
1248 fw_name = FIRMWARE_RT2561s;
1249 break;
1250 case RT2661_PCI_ID:
1251 fw_name = FIRMWARE_RT2661;
1252 break;
1253 default:
1254 fw_name = NULL;
1255 break;
1256 }
1257
1258 return fw_name;
1259 }
1260
1261 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1262 const u8 *data, const size_t len)
1263 {
1264 u16 fw_crc;
1265 u16 crc;
1266
1267 /*
1268 * Only support 8kb firmware files.
1269 */
1270 if (len != 8192)
1271 return FW_BAD_LENGTH;
1272
1273 /*
1274 * The last 2 bytes in the firmware array are the crc checksum itself.
1275 * This means that we should never pass those 2 bytes to the crc
1276 * algorithm.
1277 */
1278 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1279
1280 /*
1281 * Use the crc itu-t algorithm.
1282 */
1283 crc = crc_itu_t(0, data, len - 2);
1284 crc = crc_itu_t_byte(crc, 0);
1285 crc = crc_itu_t_byte(crc, 0);
1286
1287 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1288 }
1289
1290 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1291 const u8 *data, const size_t len)
1292 {
1293 int i;
1294 u32 reg;
1295
1296 /*
1297 * Wait for stable hardware.
1298 */
1299 for (i = 0; i < 100; i++) {
1300 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
1301 if (reg)
1302 break;
1303 msleep(1);
1304 }
1305
1306 if (!reg) {
1307 rt2x00_err(rt2x00dev, "Unstable hardware\n");
1308 return -EBUSY;
1309 }
1310
1311 /*
1312 * Prepare MCU and mailbox for firmware loading.
1313 */
1314 reg = 0;
1315 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1316 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1317 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1318 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1319 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1320
1321 /*
1322 * Write firmware to device.
1323 */
1324 reg = 0;
1325 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1326 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1327 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1328
1329 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1330 data, len);
1331
1332 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1333 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1334
1335 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1336 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1337
1338 for (i = 0; i < 100; i++) {
1339 rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1340 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1341 break;
1342 msleep(1);
1343 }
1344
1345 if (i == 100) {
1346 rt2x00_err(rt2x00dev, "MCU Control register not ready\n");
1347 return -EBUSY;
1348 }
1349
1350 /*
1351 * Hardware needs another millisecond before it is ready.
1352 */
1353 msleep(1);
1354
1355 /*
1356 * Reset MAC and BBP registers.
1357 */
1358 reg = 0;
1359 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1360 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1361 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1362
1363 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1364 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1365 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1366 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1367
1368 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1369 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1370 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1371
1372 return 0;
1373 }
1374
1375 /*
1376 * Initialization functions.
1377 */
1378 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1379 {
1380 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1381 u32 word;
1382
1383 if (entry->queue->qid == QID_RX) {
1384 rt2x00_desc_read(entry_priv->desc, 0, &word);
1385
1386 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1387 } else {
1388 rt2x00_desc_read(entry_priv->desc, 0, &word);
1389
1390 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1391 rt2x00_get_field32(word, TXD_W0_VALID));
1392 }
1393 }
1394
1395 static void rt61pci_clear_entry(struct queue_entry *entry)
1396 {
1397 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1398 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1399 u32 word;
1400
1401 if (entry->queue->qid == QID_RX) {
1402 rt2x00_desc_read(entry_priv->desc, 5, &word);
1403 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1404 skbdesc->skb_dma);
1405 rt2x00_desc_write(entry_priv->desc, 5, word);
1406
1407 rt2x00_desc_read(entry_priv->desc, 0, &word);
1408 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1409 rt2x00_desc_write(entry_priv->desc, 0, word);
1410 } else {
1411 rt2x00_desc_read(entry_priv->desc, 0, &word);
1412 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1413 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1414 rt2x00_desc_write(entry_priv->desc, 0, word);
1415 }
1416 }
1417
1418 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1419 {
1420 struct queue_entry_priv_mmio *entry_priv;
1421 u32 reg;
1422
1423 /*
1424 * Initialize registers.
1425 */
1426 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1427 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1428 rt2x00dev->tx[0].limit);
1429 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1430 rt2x00dev->tx[1].limit);
1431 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1432 rt2x00dev->tx[2].limit);
1433 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1434 rt2x00dev->tx[3].limit);
1435 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg);
1436
1437 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1438 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1439 rt2x00dev->tx[0].desc_size / 4);
1440 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg);
1441
1442 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1443 rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1444 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1445 entry_priv->desc_dma);
1446 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1447
1448 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1449 rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1450 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1451 entry_priv->desc_dma);
1452 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1453
1454 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1455 rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1456 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1457 entry_priv->desc_dma);
1458 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1459
1460 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1461 rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1462 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1463 entry_priv->desc_dma);
1464 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1465
1466 rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, &reg);
1467 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1468 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1469 rt2x00dev->rx->desc_size / 4);
1470 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1471 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg);
1472
1473 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1474 rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1475 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1476 entry_priv->desc_dma);
1477 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg);
1478
1479 rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1480 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1481 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1482 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1483 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1484 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1485
1486 rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1487 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1488 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1489 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1490 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1491 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1492
1493 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1494 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1495 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1496
1497 return 0;
1498 }
1499
1500 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1501 {
1502 u32 reg;
1503
1504 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1505 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1506 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1507 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1508 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1509
1510 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, &reg);
1511 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1512 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1513 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1514 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1515 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1516 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1517 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1518 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1519 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg);
1520
1521 /*
1522 * CCK TXD BBP registers
1523 */
1524 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, &reg);
1525 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1526 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1527 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1528 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1529 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1530 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1531 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1532 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1533 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg);
1534
1535 /*
1536 * OFDM TXD BBP registers
1537 */
1538 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, &reg);
1539 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1540 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1541 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1542 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1543 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1544 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1545 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg);
1546
1547 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, &reg);
1548 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1549 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1550 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1551 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1552 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg);
1553
1554 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, &reg);
1555 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1556 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1557 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1558 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1559 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg);
1560
1561 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1562 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1563 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1564 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1565 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1566 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1567 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1568 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1569
1570 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1571
1572 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1573
1574 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
1575 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1576 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
1577
1578 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1579
1580 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1581 return -EBUSY;
1582
1583 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1584
1585 /*
1586 * Invalidate all Shared Keys (SEC_CSR0),
1587 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1588 */
1589 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1590 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1591 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1592
1593 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1594 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1595 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1596 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1597
1598 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1599
1600 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1601
1602 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1603
1604 /*
1605 * Clear all beacons
1606 * For the Beacon base registers we only need to clear
1607 * the first byte since that byte contains the VALID and OWNER
1608 * bits which (when set to 0) will invalidate the entire beacon.
1609 */
1610 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1611 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1612 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1613 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1614
1615 /*
1616 * We must clear the error counters.
1617 * These registers are cleared on read,
1618 * so we may pass a useless variable to store the value.
1619 */
1620 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
1621 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
1622 rt2x00mmio_register_read(rt2x00dev, STA_CSR2, &reg);
1623
1624 /*
1625 * Reset MAC and BBP registers.
1626 */
1627 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1628 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1629 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1630 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1631
1632 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1633 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1634 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1635 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1636
1637 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1638 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1639 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1640
1641 return 0;
1642 }
1643
1644 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1645 {
1646 unsigned int i;
1647 u8 value;
1648
1649 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1650 rt61pci_bbp_read(rt2x00dev, 0, &value);
1651 if ((value != 0xff) && (value != 0x00))
1652 return 0;
1653 udelay(REGISTER_BUSY_DELAY);
1654 }
1655
1656 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1657 return -EACCES;
1658 }
1659
1660 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1661 {
1662 unsigned int i;
1663 u16 eeprom;
1664 u8 reg_id;
1665 u8 value;
1666
1667 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1668 return -EACCES;
1669
1670 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1671 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1672 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1673 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1674 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1675 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1676 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1677 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1678 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1679 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1680 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1681 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1682 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1683 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1684 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1685 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1686 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1687 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1688 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1689 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1690 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1691 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1692 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1693 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1694
1695 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1696 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1697
1698 if (eeprom != 0xffff && eeprom != 0x0000) {
1699 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1700 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1701 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1702 }
1703 }
1704
1705 return 0;
1706 }
1707
1708 /*
1709 * Device state switch handlers.
1710 */
1711 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1712 enum dev_state state)
1713 {
1714 int mask = (state == STATE_RADIO_IRQ_OFF);
1715 u32 reg;
1716 unsigned long flags;
1717
1718 /*
1719 * When interrupts are being enabled, the interrupt registers
1720 * should clear the register to assure a clean state.
1721 */
1722 if (state == STATE_RADIO_IRQ_ON) {
1723 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1724 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1725
1726 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1727 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1728 }
1729
1730 /*
1731 * Only toggle the interrupts bits we are going to use.
1732 * Non-checked interrupt bits are disabled by default.
1733 */
1734 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1735
1736 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1737 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1738 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1739 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
1740 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1741 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1742 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
1743
1744 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1745 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1746 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1747 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1748 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1749 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1750 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1751 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1752 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1753 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1754 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1755
1756 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1757
1758 if (state == STATE_RADIO_IRQ_OFF) {
1759 /*
1760 * Ensure that all tasklets are finished.
1761 */
1762 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1763 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1764 tasklet_kill(&rt2x00dev->autowake_tasklet);
1765 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1766 }
1767 }
1768
1769 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1770 {
1771 u32 reg;
1772
1773 /*
1774 * Initialize all registers.
1775 */
1776 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1777 rt61pci_init_registers(rt2x00dev) ||
1778 rt61pci_init_bbp(rt2x00dev)))
1779 return -EIO;
1780
1781 /*
1782 * Enable RX.
1783 */
1784 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1785 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1786 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1787
1788 return 0;
1789 }
1790
1791 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1792 {
1793 /*
1794 * Disable power
1795 */
1796 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1797 }
1798
1799 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1800 {
1801 u32 reg, reg2;
1802 unsigned int i;
1803 char put_to_sleep;
1804
1805 put_to_sleep = (state != STATE_AWAKE);
1806
1807 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg);
1808 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1809 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1810 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1811
1812 /*
1813 * Device is not guaranteed to be in the requested state yet.
1814 * We must wait until the register indicates that the
1815 * device has entered the correct state.
1816 */
1817 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1818 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg2);
1819 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1820 if (state == !put_to_sleep)
1821 return 0;
1822 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1823 msleep(10);
1824 }
1825
1826 return -EBUSY;
1827 }
1828
1829 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1830 enum dev_state state)
1831 {
1832 int retval = 0;
1833
1834 switch (state) {
1835 case STATE_RADIO_ON:
1836 retval = rt61pci_enable_radio(rt2x00dev);
1837 break;
1838 case STATE_RADIO_OFF:
1839 rt61pci_disable_radio(rt2x00dev);
1840 break;
1841 case STATE_RADIO_IRQ_ON:
1842 case STATE_RADIO_IRQ_OFF:
1843 rt61pci_toggle_irq(rt2x00dev, state);
1844 break;
1845 case STATE_DEEP_SLEEP:
1846 case STATE_SLEEP:
1847 case STATE_STANDBY:
1848 case STATE_AWAKE:
1849 retval = rt61pci_set_state(rt2x00dev, state);
1850 break;
1851 default:
1852 retval = -ENOTSUPP;
1853 break;
1854 }
1855
1856 if (unlikely(retval))
1857 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1858 state, retval);
1859
1860 return retval;
1861 }
1862
1863 /*
1864 * TX descriptor initialization
1865 */
1866 static void rt61pci_write_tx_desc(struct queue_entry *entry,
1867 struct txentry_desc *txdesc)
1868 {
1869 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1870 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1871 __le32 *txd = entry_priv->desc;
1872 u32 word;
1873
1874 /*
1875 * Start writing the descriptor words.
1876 */
1877 rt2x00_desc_read(txd, 1, &word);
1878 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1879 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1880 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1881 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1882 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1883 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1884 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1885 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1886 rt2x00_desc_write(txd, 1, word);
1887
1888 rt2x00_desc_read(txd, 2, &word);
1889 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1890 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1891 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1892 txdesc->u.plcp.length_low);
1893 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1894 txdesc->u.plcp.length_high);
1895 rt2x00_desc_write(txd, 2, word);
1896
1897 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1898 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1899 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1900 }
1901
1902 rt2x00_desc_read(txd, 5, &word);
1903 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1904 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1905 skbdesc->entry->entry_idx);
1906 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1907 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1908 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1909 rt2x00_desc_write(txd, 5, word);
1910
1911 if (entry->queue->qid != QID_BEACON) {
1912 rt2x00_desc_read(txd, 6, &word);
1913 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1914 skbdesc->skb_dma);
1915 rt2x00_desc_write(txd, 6, word);
1916
1917 rt2x00_desc_read(txd, 11, &word);
1918 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1919 txdesc->length);
1920 rt2x00_desc_write(txd, 11, word);
1921 }
1922
1923 /*
1924 * Writing TXD word 0 must the last to prevent a race condition with
1925 * the device, whereby the device may take hold of the TXD before we
1926 * finished updating it.
1927 */
1928 rt2x00_desc_read(txd, 0, &word);
1929 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1930 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1931 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1932 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1933 rt2x00_set_field32(&word, TXD_W0_ACK,
1934 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1935 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1936 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1937 rt2x00_set_field32(&word, TXD_W0_OFDM,
1938 (txdesc->rate_mode == RATE_MODE_OFDM));
1939 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1940 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1941 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1942 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1943 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1944 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1945 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1946 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1947 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1948 rt2x00_set_field32(&word, TXD_W0_BURST,
1949 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1950 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1951 rt2x00_desc_write(txd, 0, word);
1952
1953 /*
1954 * Register descriptor details in skb frame descriptor.
1955 */
1956 skbdesc->desc = txd;
1957 skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1958 TXD_DESC_SIZE;
1959 }
1960
1961 /*
1962 * TX data initialization
1963 */
1964 static void rt61pci_write_beacon(struct queue_entry *entry,
1965 struct txentry_desc *txdesc)
1966 {
1967 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1968 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1969 unsigned int beacon_base;
1970 unsigned int padding_len;
1971 u32 orig_reg, reg;
1972
1973 /*
1974 * Disable beaconing while we are reloading the beacon data,
1975 * otherwise we might be sending out invalid data.
1976 */
1977 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1978 orig_reg = reg;
1979 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1980 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1981
1982 /*
1983 * Write the TX descriptor for the beacon.
1984 */
1985 rt61pci_write_tx_desc(entry, txdesc);
1986
1987 /*
1988 * Dump beacon to userspace through debugfs.
1989 */
1990 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1991
1992 /*
1993 * Write entire beacon with descriptor and padding to register.
1994 */
1995 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1996 if (padding_len && skb_pad(entry->skb, padding_len)) {
1997 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1998 /* skb freed by skb_pad() on failure */
1999 entry->skb = NULL;
2000 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2001 return;
2002 }
2003
2004 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2005 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base,
2006 entry_priv->desc, TXINFO_SIZE);
2007 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
2008 entry->skb->data,
2009 entry->skb->len + padding_len);
2010
2011 /*
2012 * Enable beaconing again.
2013 *
2014 * For Wi-Fi faily generated beacons between participating
2015 * stations. Set TBTT phase adaptive adjustment step to 8us.
2016 */
2017 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2018
2019 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2020 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2021
2022 /*
2023 * Clean up beacon skb.
2024 */
2025 dev_kfree_skb_any(entry->skb);
2026 entry->skb = NULL;
2027 }
2028
2029 static void rt61pci_clear_beacon(struct queue_entry *entry)
2030 {
2031 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2032 u32 orig_reg, reg;
2033
2034 /*
2035 * Disable beaconing while we are reloading the beacon data,
2036 * otherwise we might be sending out invalid data.
2037 */
2038 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &orig_reg);
2039 reg = orig_reg;
2040 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2041 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2042
2043 /*
2044 * Clear beacon.
2045 */
2046 rt2x00mmio_register_write(rt2x00dev,
2047 HW_BEACON_OFFSET(entry->entry_idx), 0);
2048
2049 /*
2050 * Restore global beaconing state.
2051 */
2052 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2053 }
2054
2055 /*
2056 * RX control handlers
2057 */
2058 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
2059 {
2060 u8 offset = rt2x00dev->lna_gain;
2061 u8 lna;
2062
2063 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
2064 switch (lna) {
2065 case 3:
2066 offset += 90;
2067 break;
2068 case 2:
2069 offset += 74;
2070 break;
2071 case 1:
2072 offset += 64;
2073 break;
2074 default:
2075 return 0;
2076 }
2077
2078 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
2079 if (lna == 3 || lna == 2)
2080 offset += 10;
2081 }
2082
2083 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
2084 }
2085
2086 static void rt61pci_fill_rxdone(struct queue_entry *entry,
2087 struct rxdone_entry_desc *rxdesc)
2088 {
2089 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2090 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
2091 u32 word0;
2092 u32 word1;
2093
2094 rt2x00_desc_read(entry_priv->desc, 0, &word0);
2095 rt2x00_desc_read(entry_priv->desc, 1, &word1);
2096
2097 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
2098 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2099
2100 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2101 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
2102
2103 if (rxdesc->cipher != CIPHER_NONE) {
2104 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2105 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
2106 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2107
2108 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2109 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
2110
2111 /*
2112 * Hardware has stripped IV/EIV data from 802.11 frame during
2113 * decryption. It has provided the data separately but rt2x00lib
2114 * should decide if it should be reinserted.
2115 */
2116 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2117
2118 /*
2119 * The hardware has already checked the Michael Mic and has
2120 * stripped it from the frame. Signal this to mac80211.
2121 */
2122 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2123
2124 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2125 rxdesc->flags |= RX_FLAG_DECRYPTED;
2126 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2127 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2128 }
2129
2130 /*
2131 * Obtain the status about this packet.
2132 * When frame was received with an OFDM bitrate,
2133 * the signal is the PLCP value. If it was received with
2134 * a CCK bitrate the signal is the rate in 100kbit/s.
2135 */
2136 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2137 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2138 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2139
2140 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2141 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2142 else
2143 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2144 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2145 rxdesc->dev_flags |= RXDONE_MY_BSS;
2146 }
2147
2148 /*
2149 * Interrupt functions.
2150 */
2151 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2152 {
2153 struct data_queue *queue;
2154 struct queue_entry *entry;
2155 struct queue_entry *entry_done;
2156 struct queue_entry_priv_mmio *entry_priv;
2157 struct txdone_entry_desc txdesc;
2158 u32 word;
2159 u32 reg;
2160 int type;
2161 int index;
2162 int i;
2163
2164 /*
2165 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2166 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2167 * flag is not set anymore.
2168 *
2169 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2170 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2171 * tx ring size for now.
2172 */
2173 for (i = 0; i < rt2x00dev->tx->limit; i++) {
2174 rt2x00mmio_register_read(rt2x00dev, STA_CSR4, &reg);
2175 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2176 break;
2177
2178 /*
2179 * Skip this entry when it contains an invalid
2180 * queue identication number.
2181 */
2182 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2183 queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
2184 if (unlikely(!queue))
2185 continue;
2186
2187 /*
2188 * Skip this entry when it contains an invalid
2189 * index number.
2190 */
2191 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2192 if (unlikely(index >= queue->limit))
2193 continue;
2194
2195 entry = &queue->entries[index];
2196 entry_priv = entry->priv_data;
2197 rt2x00_desc_read(entry_priv->desc, 0, &word);
2198
2199 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2200 !rt2x00_get_field32(word, TXD_W0_VALID))
2201 return;
2202
2203 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2204 while (entry != entry_done) {
2205 /* Catch up.
2206 * Just report any entries we missed as failed.
2207 */
2208 rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n",
2209 entry_done->entry_idx);
2210
2211 rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
2212 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2213 }
2214
2215 /*
2216 * Obtain the status about this packet.
2217 */
2218 txdesc.flags = 0;
2219 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2220 case 0: /* Success, maybe with retry */
2221 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2222 break;
2223 case 6: /* Failure, excessive retries */
2224 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2225 /* Don't break, this is a failed frame! */
2226 default: /* Failure */
2227 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2228 }
2229 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2230
2231 /*
2232 * the frame was retried at least once
2233 * -> hw used fallback rates
2234 */
2235 if (txdesc.retry)
2236 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2237
2238 rt2x00lib_txdone(entry, &txdesc);
2239 }
2240 }
2241
2242 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2243 {
2244 struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf };
2245
2246 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2247 }
2248
2249 static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2250 struct rt2x00_field32 irq_field)
2251 {
2252 u32 reg;
2253
2254 /*
2255 * Enable a single interrupt. The interrupt mask register
2256 * access needs locking.
2257 */
2258 spin_lock_irq(&rt2x00dev->irqmask_lock);
2259
2260 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2261 rt2x00_set_field32(&reg, irq_field, 0);
2262 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2263
2264 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2265 }
2266
2267 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2268 struct rt2x00_field32 irq_field)
2269 {
2270 u32 reg;
2271
2272 /*
2273 * Enable a single MCU interrupt. The interrupt mask register
2274 * access needs locking.
2275 */
2276 spin_lock_irq(&rt2x00dev->irqmask_lock);
2277
2278 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2279 rt2x00_set_field32(&reg, irq_field, 0);
2280 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2281
2282 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2283 }
2284
2285 static void rt61pci_txstatus_tasklet(unsigned long data)
2286 {
2287 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2288 rt61pci_txdone(rt2x00dev);
2289 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2290 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2291 }
2292
2293 static void rt61pci_tbtt_tasklet(unsigned long data)
2294 {
2295 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2296 rt2x00lib_beacondone(rt2x00dev);
2297 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2298 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2299 }
2300
2301 static void rt61pci_rxdone_tasklet(unsigned long data)
2302 {
2303 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2304 if (rt2x00mmio_rxdone(rt2x00dev))
2305 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2306 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2307 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2308 }
2309
2310 static void rt61pci_autowake_tasklet(unsigned long data)
2311 {
2312 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2313 rt61pci_wakeup(rt2x00dev);
2314 rt2x00mmio_register_write(rt2x00dev,
2315 M2H_CMD_DONE_CSR, 0xffffffff);
2316 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2317 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2318 }
2319
2320 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2321 {
2322 struct rt2x00_dev *rt2x00dev = dev_instance;
2323 u32 reg_mcu, mask_mcu;
2324 u32 reg, mask;
2325
2326 /*
2327 * Get the interrupt sources & saved to local variable.
2328 * Write register value back to clear pending interrupts.
2329 */
2330 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2331 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2332
2333 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2334 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2335
2336 if (!reg && !reg_mcu)
2337 return IRQ_NONE;
2338
2339 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2340 return IRQ_HANDLED;
2341
2342 /*
2343 * Schedule tasklets for interrupt handling.
2344 */
2345 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2346 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2347
2348 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2349 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2350
2351 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2352 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2353
2354 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2355 tasklet_schedule(&rt2x00dev->autowake_tasklet);
2356
2357 /*
2358 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2359 * for interrupts and interrupt masks we can just use the value of
2360 * INT_SOURCE_CSR to create the interrupt mask.
2361 */
2362 mask = reg;
2363 mask_mcu = reg_mcu;
2364
2365 /*
2366 * Disable all interrupts for which a tasklet was scheduled right now,
2367 * the tasklet will reenable the appropriate interrupts.
2368 */
2369 spin_lock(&rt2x00dev->irqmask_lock);
2370
2371 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2372 reg |= mask;
2373 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2374
2375 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2376 reg |= mask_mcu;
2377 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2378
2379 spin_unlock(&rt2x00dev->irqmask_lock);
2380
2381 return IRQ_HANDLED;
2382 }
2383
2384 /*
2385 * Device probe functions.
2386 */
2387 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2388 {
2389 struct eeprom_93cx6 eeprom;
2390 u32 reg;
2391 u16 word;
2392 u8 *mac;
2393 s8 value;
2394
2395 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
2396
2397 eeprom.data = rt2x00dev;
2398 eeprom.register_read = rt61pci_eepromregister_read;
2399 eeprom.register_write = rt61pci_eepromregister_write;
2400 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2401 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2402 eeprom.reg_data_in = 0;
2403 eeprom.reg_data_out = 0;
2404 eeprom.reg_data_clock = 0;
2405 eeprom.reg_chip_select = 0;
2406
2407 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2408 EEPROM_SIZE / sizeof(u16));
2409
2410 /*
2411 * Start validation of the data that has been read.
2412 */
2413 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2414 if (!is_valid_ether_addr(mac)) {
2415 eth_random_addr(mac);
2416 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
2417 }
2418
2419 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2420 if (word == 0xffff) {
2421 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2422 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2423 ANTENNA_B);
2424 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2425 ANTENNA_B);
2426 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2427 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2428 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2429 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2430 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2431 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
2432 }
2433
2434 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2435 if (word == 0xffff) {
2436 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2437 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2438 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2439 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2440 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2441 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2442 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2443 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2444 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
2445 }
2446
2447 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2448 if (word == 0xffff) {
2449 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2450 LED_MODE_DEFAULT);
2451 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2452 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word);
2453 }
2454
2455 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2456 if (word == 0xffff) {
2457 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2458 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2459 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2460 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
2461 }
2462
2463 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2464 if (word == 0xffff) {
2465 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2466 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2467 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2468 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2469 } else {
2470 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2471 if (value < -10 || value > 10)
2472 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2473 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2474 if (value < -10 || value > 10)
2475 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2476 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2477 }
2478
2479 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2480 if (word == 0xffff) {
2481 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2482 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2483 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2484 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2485 } else {
2486 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2487 if (value < -10 || value > 10)
2488 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2489 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2490 if (value < -10 || value > 10)
2491 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2492 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2493 }
2494
2495 return 0;
2496 }
2497
2498 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2499 {
2500 u32 reg;
2501 u16 value;
2502 u16 eeprom;
2503
2504 /*
2505 * Read EEPROM word for configuration.
2506 */
2507 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2508
2509 /*
2510 * Identify RF chipset.
2511 */
2512 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2513 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
2514 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2515 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2516
2517 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2518 !rt2x00_rf(rt2x00dev, RF5325) &&
2519 !rt2x00_rf(rt2x00dev, RF2527) &&
2520 !rt2x00_rf(rt2x00dev, RF2529)) {
2521 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
2522 return -ENODEV;
2523 }
2524
2525 /*
2526 * Determine number of antennas.
2527 */
2528 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2529 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags);
2530
2531 /*
2532 * Identify default antenna configuration.
2533 */
2534 rt2x00dev->default_ant.tx =
2535 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2536 rt2x00dev->default_ant.rx =
2537 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2538
2539 /*
2540 * Read the Frame type.
2541 */
2542 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2543 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
2544
2545 /*
2546 * Detect if this device has a hardware controlled radio.
2547 */
2548 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2549 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
2550
2551 /*
2552 * Read frequency offset and RF programming sequence.
2553 */
2554 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2555 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2556 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags);
2557
2558 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2559
2560 /*
2561 * Read external LNA informations.
2562 */
2563 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2564
2565 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2566 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
2567 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2568 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
2569
2570 /*
2571 * When working with a RF2529 chip without double antenna,
2572 * the antenna settings should be gathered from the NIC
2573 * eeprom word.
2574 */
2575 if (rt2x00_rf(rt2x00dev, RF2529) &&
2576 !rt2x00_has_cap_double_antenna(rt2x00dev)) {
2577 rt2x00dev->default_ant.rx =
2578 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2579 rt2x00dev->default_ant.tx =
2580 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2581
2582 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2583 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2584 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2585 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2586 }
2587
2588 /*
2589 * Store led settings, for correct led behaviour.
2590 * If the eeprom value is invalid,
2591 * switch to default led mode.
2592 */
2593 #ifdef CONFIG_RT2X00_LIB_LEDS
2594 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2595 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2596
2597 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2598 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2599 if (value == LED_MODE_SIGNAL_STRENGTH)
2600 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2601 LED_TYPE_QUALITY);
2602
2603 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2604 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2605 rt2x00_get_field16(eeprom,
2606 EEPROM_LED_POLARITY_GPIO_0));
2607 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2608 rt2x00_get_field16(eeprom,
2609 EEPROM_LED_POLARITY_GPIO_1));
2610 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2611 rt2x00_get_field16(eeprom,
2612 EEPROM_LED_POLARITY_GPIO_2));
2613 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2614 rt2x00_get_field16(eeprom,
2615 EEPROM_LED_POLARITY_GPIO_3));
2616 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2617 rt2x00_get_field16(eeprom,
2618 EEPROM_LED_POLARITY_GPIO_4));
2619 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2620 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2621 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2622 rt2x00_get_field16(eeprom,
2623 EEPROM_LED_POLARITY_RDY_G));
2624 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2625 rt2x00_get_field16(eeprom,
2626 EEPROM_LED_POLARITY_RDY_A));
2627 #endif /* CONFIG_RT2X00_LIB_LEDS */
2628
2629 return 0;
2630 }
2631
2632 /*
2633 * RF value list for RF5225 & RF5325
2634 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2635 */
2636 static const struct rf_channel rf_vals_noseq[] = {
2637 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2638 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2639 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2640 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2641 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2642 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2643 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2644 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2645 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2646 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2647 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2648 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2649 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2650 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2651
2652 /* 802.11 UNI / HyperLan 2 */
2653 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2654 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2655 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2656 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2657 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2658 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2659 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2660 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2661
2662 /* 802.11 HyperLan 2 */
2663 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2664 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2665 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2666 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2667 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2668 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2669 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2670 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2671 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2672 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2673
2674 /* 802.11 UNII */
2675 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2676 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2677 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2678 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2679 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2680 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2681
2682 /* MMAC(Japan)J52 ch 34,38,42,46 */
2683 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2684 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2685 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2686 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2687 };
2688
2689 /*
2690 * RF value list for RF5225 & RF5325
2691 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2692 */
2693 static const struct rf_channel rf_vals_seq[] = {
2694 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2695 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2696 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2697 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2698 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2699 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2700 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2701 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2702 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2703 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2704 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2705 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2706 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2707 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2708
2709 /* 802.11 UNI / HyperLan 2 */
2710 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2711 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2712 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2713 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2714 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2715 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2716 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2717 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2718
2719 /* 802.11 HyperLan 2 */
2720 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2721 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2722 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2723 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2724 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2725 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2726 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2727 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2728 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2729 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2730
2731 /* 802.11 UNII */
2732 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2733 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2734 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2735 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2736 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2737 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2738
2739 /* MMAC(Japan)J52 ch 34,38,42,46 */
2740 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2741 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2742 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2743 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2744 };
2745
2746 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2747 {
2748 struct hw_mode_spec *spec = &rt2x00dev->spec;
2749 struct channel_info *info;
2750 char *tx_power;
2751 unsigned int i;
2752
2753 /*
2754 * Disable powersaving as default.
2755 */
2756 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2757
2758 /*
2759 * Initialize all hw fields.
2760 */
2761 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
2762 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
2763 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
2764 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
2765
2766 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2767 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2768 rt2x00_eeprom_addr(rt2x00dev,
2769 EEPROM_MAC_ADDR_0));
2770
2771 /*
2772 * As rt61 has a global fallback table we cannot specify
2773 * more then one tx rate per frame but since the hw will
2774 * try several rates (based on the fallback table) we should
2775 * initialize max_report_rates to the maximum number of rates
2776 * we are going to try. Otherwise mac80211 will truncate our
2777 * reported tx rates and the rc algortihm will end up with
2778 * incorrect data.
2779 */
2780 rt2x00dev->hw->max_rates = 1;
2781 rt2x00dev->hw->max_report_rates = 7;
2782 rt2x00dev->hw->max_rate_tries = 1;
2783
2784 /*
2785 * Initialize hw_mode information.
2786 */
2787 spec->supported_bands = SUPPORT_BAND_2GHZ;
2788 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2789
2790 if (!rt2x00_has_cap_rf_sequence(rt2x00dev)) {
2791 spec->num_channels = 14;
2792 spec->channels = rf_vals_noseq;
2793 } else {
2794 spec->num_channels = 14;
2795 spec->channels = rf_vals_seq;
2796 }
2797
2798 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2799 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2800 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2801 }
2802
2803 /*
2804 * Create channel information array
2805 */
2806 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2807 if (!info)
2808 return -ENOMEM;
2809
2810 spec->channels_info = info;
2811
2812 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2813 for (i = 0; i < 14; i++) {
2814 info[i].max_power = MAX_TXPOWER;
2815 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2816 }
2817
2818 if (spec->num_channels > 14) {
2819 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2820 for (i = 14; i < spec->num_channels; i++) {
2821 info[i].max_power = MAX_TXPOWER;
2822 info[i].default_power1 =
2823 TXPOWER_FROM_DEV(tx_power[i - 14]);
2824 }
2825 }
2826
2827 return 0;
2828 }
2829
2830 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2831 {
2832 int retval;
2833 u32 reg;
2834
2835 /*
2836 * Disable power saving.
2837 */
2838 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2839
2840 /*
2841 * Allocate eeprom data.
2842 */
2843 retval = rt61pci_validate_eeprom(rt2x00dev);
2844 if (retval)
2845 return retval;
2846
2847 retval = rt61pci_init_eeprom(rt2x00dev);
2848 if (retval)
2849 return retval;
2850
2851 /*
2852 * Enable rfkill polling by setting GPIO direction of the
2853 * rfkill switch GPIO pin correctly.
2854 */
2855 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
2856 rt2x00_set_field32(&reg, MAC_CSR13_DIR5, 1);
2857 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
2858
2859 /*
2860 * Initialize hw specifications.
2861 */
2862 retval = rt61pci_probe_hw_mode(rt2x00dev);
2863 if (retval)
2864 return retval;
2865
2866 /*
2867 * This device has multiple filters for control frames,
2868 * but has no a separate filter for PS Poll frames.
2869 */
2870 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2871
2872 /*
2873 * This device requires firmware and DMA mapped skbs.
2874 */
2875 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2876 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
2877 if (!modparam_nohwcrypt)
2878 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2879 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2880
2881 /*
2882 * Set the rssi offset.
2883 */
2884 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2885
2886 return 0;
2887 }
2888
2889 /*
2890 * IEEE80211 stack callback functions.
2891 */
2892 static int rt61pci_conf_tx(struct ieee80211_hw *hw,
2893 struct ieee80211_vif *vif, u16 queue_idx,
2894 const struct ieee80211_tx_queue_params *params)
2895 {
2896 struct rt2x00_dev *rt2x00dev = hw->priv;
2897 struct data_queue *queue;
2898 struct rt2x00_field32 field;
2899 int retval;
2900 u32 reg;
2901 u32 offset;
2902
2903 /*
2904 * First pass the configuration through rt2x00lib, that will
2905 * update the queue settings and validate the input. After that
2906 * we are free to update the registers based on the value
2907 * in the queue parameter.
2908 */
2909 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2910 if (retval)
2911 return retval;
2912
2913 /*
2914 * We only need to perform additional register initialization
2915 * for WMM queues.
2916 */
2917 if (queue_idx >= 4)
2918 return 0;
2919
2920 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2921
2922 /* Update WMM TXOP register */
2923 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2924 field.bit_offset = (queue_idx & 1) * 16;
2925 field.bit_mask = 0xffff << field.bit_offset;
2926
2927 rt2x00mmio_register_read(rt2x00dev, offset, &reg);
2928 rt2x00_set_field32(&reg, field, queue->txop);
2929 rt2x00mmio_register_write(rt2x00dev, offset, reg);
2930
2931 /* Update WMM registers */
2932 field.bit_offset = queue_idx * 4;
2933 field.bit_mask = 0xf << field.bit_offset;
2934
2935 rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, &reg);
2936 rt2x00_set_field32(&reg, field, queue->aifs);
2937 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg);
2938
2939 rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, &reg);
2940 rt2x00_set_field32(&reg, field, queue->cw_min);
2941 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg);
2942
2943 rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, &reg);
2944 rt2x00_set_field32(&reg, field, queue->cw_max);
2945 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg);
2946
2947 return 0;
2948 }
2949
2950 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2951 {
2952 struct rt2x00_dev *rt2x00dev = hw->priv;
2953 u64 tsf;
2954 u32 reg;
2955
2956 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, &reg);
2957 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2958 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, &reg);
2959 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2960
2961 return tsf;
2962 }
2963
2964 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2965 .tx = rt2x00mac_tx,
2966 .start = rt2x00mac_start,
2967 .stop = rt2x00mac_stop,
2968 .add_interface = rt2x00mac_add_interface,
2969 .remove_interface = rt2x00mac_remove_interface,
2970 .config = rt2x00mac_config,
2971 .configure_filter = rt2x00mac_configure_filter,
2972 .set_key = rt2x00mac_set_key,
2973 .sw_scan_start = rt2x00mac_sw_scan_start,
2974 .sw_scan_complete = rt2x00mac_sw_scan_complete,
2975 .get_stats = rt2x00mac_get_stats,
2976 .bss_info_changed = rt2x00mac_bss_info_changed,
2977 .conf_tx = rt61pci_conf_tx,
2978 .get_tsf = rt61pci_get_tsf,
2979 .rfkill_poll = rt2x00mac_rfkill_poll,
2980 .flush = rt2x00mac_flush,
2981 .set_antenna = rt2x00mac_set_antenna,
2982 .get_antenna = rt2x00mac_get_antenna,
2983 .get_ringparam = rt2x00mac_get_ringparam,
2984 .tx_frames_pending = rt2x00mac_tx_frames_pending,
2985 };
2986
2987 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2988 .irq_handler = rt61pci_interrupt,
2989 .txstatus_tasklet = rt61pci_txstatus_tasklet,
2990 .tbtt_tasklet = rt61pci_tbtt_tasklet,
2991 .rxdone_tasklet = rt61pci_rxdone_tasklet,
2992 .autowake_tasklet = rt61pci_autowake_tasklet,
2993 .probe_hw = rt61pci_probe_hw,
2994 .get_firmware_name = rt61pci_get_firmware_name,
2995 .check_firmware = rt61pci_check_firmware,
2996 .load_firmware = rt61pci_load_firmware,
2997 .initialize = rt2x00mmio_initialize,
2998 .uninitialize = rt2x00mmio_uninitialize,
2999 .get_entry_state = rt61pci_get_entry_state,
3000 .clear_entry = rt61pci_clear_entry,
3001 .set_device_state = rt61pci_set_device_state,
3002 .rfkill_poll = rt61pci_rfkill_poll,
3003 .link_stats = rt61pci_link_stats,
3004 .reset_tuner = rt61pci_reset_tuner,
3005 .link_tuner = rt61pci_link_tuner,
3006 .start_queue = rt61pci_start_queue,
3007 .kick_queue = rt61pci_kick_queue,
3008 .stop_queue = rt61pci_stop_queue,
3009 .flush_queue = rt2x00mmio_flush_queue,
3010 .write_tx_desc = rt61pci_write_tx_desc,
3011 .write_beacon = rt61pci_write_beacon,
3012 .clear_beacon = rt61pci_clear_beacon,
3013 .fill_rxdone = rt61pci_fill_rxdone,
3014 .config_shared_key = rt61pci_config_shared_key,
3015 .config_pairwise_key = rt61pci_config_pairwise_key,
3016 .config_filter = rt61pci_config_filter,
3017 .config_intf = rt61pci_config_intf,
3018 .config_erp = rt61pci_config_erp,
3019 .config_ant = rt61pci_config_ant,
3020 .config = rt61pci_config,
3021 };
3022
3023 static void rt61pci_queue_init(struct data_queue *queue)
3024 {
3025 switch (queue->qid) {
3026 case QID_RX:
3027 queue->limit = 32;
3028 queue->data_size = DATA_FRAME_SIZE;
3029 queue->desc_size = RXD_DESC_SIZE;
3030 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3031 break;
3032
3033 case QID_AC_VO:
3034 case QID_AC_VI:
3035 case QID_AC_BE:
3036 case QID_AC_BK:
3037 queue->limit = 32;
3038 queue->data_size = DATA_FRAME_SIZE;
3039 queue->desc_size = TXD_DESC_SIZE;
3040 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3041 break;
3042
3043 case QID_BEACON:
3044 queue->limit = 4;
3045 queue->data_size = 0; /* No DMA required for beacons */
3046 queue->desc_size = TXINFO_SIZE;
3047 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3048 break;
3049
3050 case QID_ATIM:
3051 /* fallthrough */
3052 default:
3053 BUG();
3054 break;
3055 }
3056 }
3057
3058 static const struct rt2x00_ops rt61pci_ops = {
3059 .name = KBUILD_MODNAME,
3060 .max_ap_intf = 4,
3061 .eeprom_size = EEPROM_SIZE,
3062 .rf_size = RF_SIZE,
3063 .tx_queues = NUM_TX_QUEUES,
3064 .queue_init = rt61pci_queue_init,
3065 .lib = &rt61pci_rt2x00_ops,
3066 .hw = &rt61pci_mac80211_ops,
3067 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
3068 .debugfs = &rt61pci_rt2x00debug,
3069 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3070 };
3071
3072 /*
3073 * RT61pci module information.
3074 */
3075 static const struct pci_device_id rt61pci_device_table[] = {
3076 /* RT2561s */
3077 { PCI_DEVICE(0x1814, 0x0301) },
3078 /* RT2561 v2 */
3079 { PCI_DEVICE(0x1814, 0x0302) },
3080 /* RT2661 */
3081 { PCI_DEVICE(0x1814, 0x0401) },
3082 { 0, }
3083 };
3084
3085 MODULE_AUTHOR(DRV_PROJECT);
3086 MODULE_VERSION(DRV_VERSION);
3087 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
3088 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
3089 "PCI & PCMCIA chipset based cards");
3090 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
3091 MODULE_FIRMWARE(FIRMWARE_RT2561);
3092 MODULE_FIRMWARE(FIRMWARE_RT2561s);
3093 MODULE_FIRMWARE(FIRMWARE_RT2661);
3094 MODULE_LICENSE("GPL");
3095
3096 static int rt61pci_probe(struct pci_dev *pci_dev,
3097 const struct pci_device_id *id)
3098 {
3099 return rt2x00pci_probe(pci_dev, &rt61pci_ops);
3100 }
3101
3102 static struct pci_driver rt61pci_driver = {
3103 .name = KBUILD_MODNAME,
3104 .id_table = rt61pci_device_table,
3105 .probe = rt61pci_probe,
3106 .remove = rt2x00pci_remove,
3107 .suspend = rt2x00pci_suspend,
3108 .resume = rt2x00pci_resume,
3109 };
3110
3111 module_pci_driver(rt61pci_driver);
Linux kernel - Deliverables
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