2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline struct pci_dev
*ctrl_dev(struct controller
*ctrl
)
46 return ctrl
->pcie
->port
;
49 static irqreturn_t
pcie_isr(int irq
, void *dev_id
);
50 static void start_int_poll_timer(struct controller
*ctrl
, int sec
);
52 /* This is the interrupt polling timeout function. */
53 static void int_poll_timeout(unsigned long data
)
55 struct controller
*ctrl
= (struct controller
*)data
;
57 /* Poll for interrupt events. regs == NULL => polling */
60 init_timer(&ctrl
->poll_timer
);
61 if (!pciehp_poll_time
)
62 pciehp_poll_time
= 2; /* default polling interval is 2 sec */
64 start_int_poll_timer(ctrl
, pciehp_poll_time
);
67 /* This function starts the interrupt polling timer. */
68 static void start_int_poll_timer(struct controller
*ctrl
, int sec
)
70 /* Clamp to sane value */
71 if ((sec
<= 0) || (sec
> 60))
74 ctrl
->poll_timer
.function
= &int_poll_timeout
;
75 ctrl
->poll_timer
.data
= (unsigned long)ctrl
;
76 ctrl
->poll_timer
.expires
= jiffies
+ sec
* HZ
;
77 add_timer(&ctrl
->poll_timer
);
80 static inline int pciehp_request_irq(struct controller
*ctrl
)
82 int retval
, irq
= ctrl
->pcie
->irq
;
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode
) {
86 init_timer(&ctrl
->poll_timer
);
87 start_int_poll_timer(ctrl
, 10);
91 /* Installs the interrupt handler */
92 retval
= request_irq(irq
, pcie_isr
, IRQF_SHARED
, MY_NAME
, ctrl
);
94 ctrl_err(ctrl
, "Cannot get irq %d for the hotplug controller\n",
99 static inline void pciehp_free_irq(struct controller
*ctrl
)
101 if (pciehp_poll_mode
)
102 del_timer_sync(&ctrl
->poll_timer
);
104 free_irq(ctrl
->pcie
->irq
, ctrl
);
107 static int pcie_poll_cmd(struct controller
*ctrl
, int timeout
)
109 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
112 pcie_capability_read_word(pdev
, PCI_EXP_SLTSTA
, &slot_status
);
113 if (slot_status
& PCI_EXP_SLTSTA_CC
) {
114 pcie_capability_write_word(pdev
, PCI_EXP_SLTSTA
,
118 while (timeout
> 0) {
121 pcie_capability_read_word(pdev
, PCI_EXP_SLTSTA
, &slot_status
);
122 if (slot_status
& PCI_EXP_SLTSTA_CC
) {
123 pcie_capability_write_word(pdev
, PCI_EXP_SLTSTA
,
128 return 0; /* timeout */
131 static void pcie_wait_cmd(struct controller
*ctrl
)
133 unsigned int msecs
= pciehp_poll_mode
? 2500 : 1000;
134 unsigned long duration
= msecs_to_jiffies(msecs
);
135 unsigned long cmd_timeout
= ctrl
->cmd_started
+ duration
;
136 unsigned long now
, timeout
;
140 * If the controller does not generate notifications for command
141 * completions, we never need to wait between writes.
143 if (NO_CMD_CMPL(ctrl
))
150 * Even if the command has already timed out, we want to call
151 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
154 if (time_before_eq(cmd_timeout
, now
))
157 timeout
= cmd_timeout
- now
;
159 if (ctrl
->slot_ctrl
& PCI_EXP_SLTCTL_HPIE
&&
160 ctrl
->slot_ctrl
& PCI_EXP_SLTCTL_CCIE
)
161 rc
= wait_event_timeout(ctrl
->queue
, !ctrl
->cmd_busy
, timeout
);
163 rc
= pcie_poll_cmd(ctrl
, jiffies_to_msecs(timeout
));
166 * Controllers with errata like Intel CF118 don't generate
167 * completion notifications unless the power/indicator/interlock
168 * control bits are changed. On such controllers, we'll emit this
169 * timeout message when we wait for completion of commands that
170 * don't change those bits, e.g., commands that merely enable
174 ctrl_info(ctrl
, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
176 jiffies_to_msecs(jiffies
- ctrl
->cmd_started
));
179 static void pcie_do_write_cmd(struct controller
*ctrl
, u16 cmd
,
182 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
185 mutex_lock(&ctrl
->ctrl_lock
);
188 * Always wait for any previous command that might still be in progress
192 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL
, &slot_ctrl
);
194 slot_ctrl
|= (cmd
& mask
);
197 pcie_capability_write_word(pdev
, PCI_EXP_SLTCTL
, slot_ctrl
);
198 ctrl
->cmd_started
= jiffies
;
199 ctrl
->slot_ctrl
= slot_ctrl
;
202 * Optionally wait for the hardware to be ready for a new command,
203 * indicating completion of the above issued command.
208 mutex_unlock(&ctrl
->ctrl_lock
);
212 * pcie_write_cmd - Issue controller command
213 * @ctrl: controller to which the command is issued
214 * @cmd: command value written to slot control register
215 * @mask: bitmask of slot control register to be modified
217 static void pcie_write_cmd(struct controller
*ctrl
, u16 cmd
, u16 mask
)
219 pcie_do_write_cmd(ctrl
, cmd
, mask
, true);
222 /* Same as above without waiting for the hardware to latch */
223 static void pcie_write_cmd_nowait(struct controller
*ctrl
, u16 cmd
, u16 mask
)
225 pcie_do_write_cmd(ctrl
, cmd
, mask
, false);
228 bool pciehp_check_link_active(struct controller
*ctrl
)
230 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
234 pcie_capability_read_word(pdev
, PCI_EXP_LNKSTA
, &lnk_status
);
235 ret
= !!(lnk_status
& PCI_EXP_LNKSTA_DLLLA
);
238 ctrl_dbg(ctrl
, "%s: lnk_status = %x\n", __func__
, lnk_status
);
243 static void __pcie_wait_link_active(struct controller
*ctrl
, bool active
)
247 if (pciehp_check_link_active(ctrl
) == active
)
249 while (timeout
> 0) {
252 if (pciehp_check_link_active(ctrl
) == active
)
255 ctrl_dbg(ctrl
, "Data Link Layer Link Active not %s in 1000 msec\n",
256 active
? "set" : "cleared");
259 static void pcie_wait_link_active(struct controller
*ctrl
)
261 __pcie_wait_link_active(ctrl
, true);
264 static bool pci_bus_check_dev(struct pci_bus
*bus
, int devfn
)
268 int delay
= 1000, step
= 20;
272 found
= pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 0);
282 if (count
> 1 && pciehp_debug
)
283 printk(KERN_DEBUG
"pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
284 pci_domain_nr(bus
), bus
->number
, PCI_SLOT(devfn
),
285 PCI_FUNC(devfn
), count
, step
, l
);
290 int pciehp_check_link_status(struct controller
*ctrl
)
292 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
297 * Data Link Layer Link Active Reporting must be capable for
298 * hot-plug capable downstream port. But old controller might
299 * not implement it. In this case, we wait for 1000 ms.
301 if (ctrl
->link_active_reporting
)
302 pcie_wait_link_active(ctrl
);
306 /* wait 100ms before read pci conf, and try in 1s */
308 found
= pci_bus_check_dev(ctrl
->pcie
->port
->subordinate
,
311 pcie_capability_read_word(pdev
, PCI_EXP_LNKSTA
, &lnk_status
);
312 ctrl_dbg(ctrl
, "%s: lnk_status = %x\n", __func__
, lnk_status
);
313 if ((lnk_status
& PCI_EXP_LNKSTA_LT
) ||
314 !(lnk_status
& PCI_EXP_LNKSTA_NLW
)) {
315 ctrl_err(ctrl
, "link training error: status %#06x\n",
320 pcie_update_link_speed(ctrl
->pcie
->port
->subordinate
, lnk_status
);
328 static int __pciehp_link_set(struct controller
*ctrl
, bool enable
)
330 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
333 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL
, &lnk_ctrl
);
336 lnk_ctrl
&= ~PCI_EXP_LNKCTL_LD
;
338 lnk_ctrl
|= PCI_EXP_LNKCTL_LD
;
340 pcie_capability_write_word(pdev
, PCI_EXP_LNKCTL
, lnk_ctrl
);
341 ctrl_dbg(ctrl
, "%s: lnk_ctrl = %x\n", __func__
, lnk_ctrl
);
345 static int pciehp_link_enable(struct controller
*ctrl
)
347 return __pciehp_link_set(ctrl
, true);
350 void pciehp_get_attention_status(struct slot
*slot
, u8
*status
)
352 struct controller
*ctrl
= slot
->ctrl
;
353 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
356 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL
, &slot_ctrl
);
357 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x, value read %x\n", __func__
,
358 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_ctrl
);
360 switch (slot_ctrl
& PCI_EXP_SLTCTL_AIC
) {
361 case PCI_EXP_SLTCTL_ATTN_IND_ON
:
362 *status
= 1; /* On */
364 case PCI_EXP_SLTCTL_ATTN_IND_BLINK
:
365 *status
= 2; /* Blink */
367 case PCI_EXP_SLTCTL_ATTN_IND_OFF
:
368 *status
= 0; /* Off */
376 void pciehp_get_power_status(struct slot
*slot
, u8
*status
)
378 struct controller
*ctrl
= slot
->ctrl
;
379 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
382 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL
, &slot_ctrl
);
383 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x value read %x\n", __func__
,
384 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_ctrl
);
386 switch (slot_ctrl
& PCI_EXP_SLTCTL_PCC
) {
387 case PCI_EXP_SLTCTL_PWR_ON
:
388 *status
= 1; /* On */
390 case PCI_EXP_SLTCTL_PWR_OFF
:
391 *status
= 0; /* Off */
399 void pciehp_get_latch_status(struct slot
*slot
, u8
*status
)
401 struct pci_dev
*pdev
= ctrl_dev(slot
->ctrl
);
404 pcie_capability_read_word(pdev
, PCI_EXP_SLTSTA
, &slot_status
);
405 *status
= !!(slot_status
& PCI_EXP_SLTSTA_MRLSS
);
408 void pciehp_get_adapter_status(struct slot
*slot
, u8
*status
)
410 struct pci_dev
*pdev
= ctrl_dev(slot
->ctrl
);
413 pcie_capability_read_word(pdev
, PCI_EXP_SLTSTA
, &slot_status
);
414 *status
= !!(slot_status
& PCI_EXP_SLTSTA_PDS
);
417 int pciehp_query_power_fault(struct slot
*slot
)
419 struct pci_dev
*pdev
= ctrl_dev(slot
->ctrl
);
422 pcie_capability_read_word(pdev
, PCI_EXP_SLTSTA
, &slot_status
);
423 return !!(slot_status
& PCI_EXP_SLTSTA_PFD
);
426 void pciehp_set_attention_status(struct slot
*slot
, u8 value
)
428 struct controller
*ctrl
= slot
->ctrl
;
435 case 0: /* turn off */
436 slot_cmd
= PCI_EXP_SLTCTL_ATTN_IND_OFF
;
438 case 1: /* turn on */
439 slot_cmd
= PCI_EXP_SLTCTL_ATTN_IND_ON
;
441 case 2: /* turn blink */
442 slot_cmd
= PCI_EXP_SLTCTL_ATTN_IND_BLINK
;
447 pcie_write_cmd_nowait(ctrl
, slot_cmd
, PCI_EXP_SLTCTL_AIC
);
448 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
449 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_cmd
);
452 void pciehp_green_led_on(struct slot
*slot
)
454 struct controller
*ctrl
= slot
->ctrl
;
459 pcie_write_cmd_nowait(ctrl
, PCI_EXP_SLTCTL_PWR_IND_ON
,
461 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
462 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
,
463 PCI_EXP_SLTCTL_PWR_IND_ON
);
466 void pciehp_green_led_off(struct slot
*slot
)
468 struct controller
*ctrl
= slot
->ctrl
;
473 pcie_write_cmd_nowait(ctrl
, PCI_EXP_SLTCTL_PWR_IND_OFF
,
475 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
476 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
,
477 PCI_EXP_SLTCTL_PWR_IND_OFF
);
480 void pciehp_green_led_blink(struct slot
*slot
)
482 struct controller
*ctrl
= slot
->ctrl
;
487 pcie_write_cmd_nowait(ctrl
, PCI_EXP_SLTCTL_PWR_IND_BLINK
,
489 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
490 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
,
491 PCI_EXP_SLTCTL_PWR_IND_BLINK
);
494 int pciehp_power_on_slot(struct slot
*slot
)
496 struct controller
*ctrl
= slot
->ctrl
;
497 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
501 /* Clear sticky power-fault bit from previous power failures */
502 pcie_capability_read_word(pdev
, PCI_EXP_SLTSTA
, &slot_status
);
503 if (slot_status
& PCI_EXP_SLTSTA_PFD
)
504 pcie_capability_write_word(pdev
, PCI_EXP_SLTSTA
,
506 ctrl
->power_fault_detected
= 0;
508 pcie_write_cmd(ctrl
, PCI_EXP_SLTCTL_PWR_ON
, PCI_EXP_SLTCTL_PCC
);
509 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
510 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
,
511 PCI_EXP_SLTCTL_PWR_ON
);
513 retval
= pciehp_link_enable(ctrl
);
515 ctrl_err(ctrl
, "%s: Can not enable the link!\n", __func__
);
520 void pciehp_power_off_slot(struct slot
*slot
)
522 struct controller
*ctrl
= slot
->ctrl
;
524 pcie_write_cmd(ctrl
, PCI_EXP_SLTCTL_PWR_OFF
, PCI_EXP_SLTCTL_PCC
);
525 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
526 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
,
527 PCI_EXP_SLTCTL_PWR_OFF
);
530 static irqreturn_t
pcie_isr(int irq
, void *dev_id
)
532 struct controller
*ctrl
= (struct controller
*)dev_id
;
533 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
534 struct pci_bus
*subordinate
= pdev
->subordinate
;
536 struct slot
*slot
= ctrl
->slot
;
537 u16 detected
, intr_loc
;
542 * In order to guarantee that all interrupt events are
543 * serviced, we need to re-inspect Slot Status register after
544 * clearing what is presumed to be the last pending interrupt.
548 pcie_capability_read_word(pdev
, PCI_EXP_SLTSTA
, &detected
);
550 detected
&= (PCI_EXP_SLTSTA_ABP
| PCI_EXP_SLTSTA_PFD
|
551 PCI_EXP_SLTSTA_MRLSC
| PCI_EXP_SLTSTA_PDC
|
552 PCI_EXP_SLTSTA_CC
| PCI_EXP_SLTSTA_DLLSC
);
553 detected
&= ~intr_loc
;
554 intr_loc
|= detected
;
558 pcie_capability_write_word(pdev
, PCI_EXP_SLTSTA
,
562 ctrl_dbg(ctrl
, "pending interrupts %#06x from Slot Status\n", intr_loc
);
564 /* Check Command Complete Interrupt Pending */
565 if (intr_loc
& PCI_EXP_SLTSTA_CC
) {
568 wake_up(&ctrl
->queue
);
572 list_for_each_entry(dev
, &subordinate
->devices
, bus_list
) {
573 if (dev
->ignore_hotplug
) {
574 ctrl_dbg(ctrl
, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
575 intr_loc
, pci_name(dev
));
581 if (!(intr_loc
& ~PCI_EXP_SLTSTA_CC
))
584 /* Check MRL Sensor Changed */
585 if (intr_loc
& PCI_EXP_SLTSTA_MRLSC
) {
586 pciehp_get_latch_status(slot
, &open
);
587 ctrl_info(ctrl
, "Latch %s on Slot(%s)\n",
588 open
? "open" : "close", slot_name(slot
));
589 pciehp_queue_interrupt_event(slot
, open
? INT_SWITCH_OPEN
:
593 /* Check Attention Button Pressed */
594 if (intr_loc
& PCI_EXP_SLTSTA_ABP
) {
595 ctrl_info(ctrl
, "Button pressed on Slot(%s)\n",
597 pciehp_queue_interrupt_event(slot
, INT_BUTTON_PRESS
);
600 /* Check Presence Detect Changed */
601 if (intr_loc
& PCI_EXP_SLTSTA_PDC
) {
602 pciehp_get_adapter_status(slot
, &present
);
603 ctrl_info(ctrl
, "Card %spresent on Slot(%s)\n",
604 present
? "" : "not ", slot_name(slot
));
605 pciehp_queue_interrupt_event(slot
, present
? INT_PRESENCE_ON
:
609 /* Check Power Fault Detected */
610 if ((intr_loc
& PCI_EXP_SLTSTA_PFD
) && !ctrl
->power_fault_detected
) {
611 ctrl
->power_fault_detected
= 1;
612 ctrl_err(ctrl
, "Power fault on slot %s\n", slot_name(slot
));
613 pciehp_queue_interrupt_event(slot
, INT_POWER_FAULT
);
616 if (intr_loc
& PCI_EXP_SLTSTA_DLLSC
) {
617 link
= pciehp_check_link_active(ctrl
);
618 ctrl_info(ctrl
, "slot(%s): Link %s event\n",
619 slot_name(slot
), link
? "Up" : "Down");
620 pciehp_queue_interrupt_event(slot
, link
? INT_LINK_UP
:
627 void pcie_enable_notification(struct controller
*ctrl
)
632 * TBD: Power fault detected software notification support.
634 * Power fault detected software notification is not enabled
635 * now, because it caused power fault detected interrupt storm
636 * on some machines. On those machines, power fault detected
637 * bit in the slot status register was set again immediately
638 * when it is cleared in the interrupt service routine, and
639 * next power fault detected interrupt was notified again.
643 * Always enable link events: thus link-up and link-down shall
644 * always be treated as hotplug and unplug respectively. Enable
645 * presence detect only if Attention Button is not present.
647 cmd
= PCI_EXP_SLTCTL_DLLSCE
;
648 if (ATTN_BUTTN(ctrl
))
649 cmd
|= PCI_EXP_SLTCTL_ABPE
;
651 cmd
|= PCI_EXP_SLTCTL_PDCE
;
653 cmd
|= PCI_EXP_SLTCTL_MRLSCE
;
654 if (!pciehp_poll_mode
)
655 cmd
|= PCI_EXP_SLTCTL_HPIE
| PCI_EXP_SLTCTL_CCIE
;
657 mask
= (PCI_EXP_SLTCTL_PDCE
| PCI_EXP_SLTCTL_ABPE
|
658 PCI_EXP_SLTCTL_MRLSCE
| PCI_EXP_SLTCTL_PFDE
|
659 PCI_EXP_SLTCTL_HPIE
| PCI_EXP_SLTCTL_CCIE
|
660 PCI_EXP_SLTCTL_DLLSCE
);
662 pcie_write_cmd_nowait(ctrl
, cmd
, mask
);
663 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
664 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, cmd
);
667 static void pcie_disable_notification(struct controller
*ctrl
)
671 mask
= (PCI_EXP_SLTCTL_PDCE
| PCI_EXP_SLTCTL_ABPE
|
672 PCI_EXP_SLTCTL_MRLSCE
| PCI_EXP_SLTCTL_PFDE
|
673 PCI_EXP_SLTCTL_HPIE
| PCI_EXP_SLTCTL_CCIE
|
674 PCI_EXP_SLTCTL_DLLSCE
);
675 pcie_write_cmd(ctrl
, 0, mask
);
676 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
677 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, 0);
681 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
682 * bus reset of the bridge, but at the same time we want to ensure that it is
683 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
684 * disable link state notification and presence detection change notification
685 * momentarily, if we see that they could interfere. Also, clear any spurious
688 int pciehp_reset_slot(struct slot
*slot
, int probe
)
690 struct controller
*ctrl
= slot
->ctrl
;
691 struct pci_dev
*pdev
= ctrl_dev(ctrl
);
692 u16 stat_mask
= 0, ctrl_mask
= 0;
697 if (!ATTN_BUTTN(ctrl
)) {
698 ctrl_mask
|= PCI_EXP_SLTCTL_PDCE
;
699 stat_mask
|= PCI_EXP_SLTSTA_PDC
;
701 ctrl_mask
|= PCI_EXP_SLTCTL_DLLSCE
;
702 stat_mask
|= PCI_EXP_SLTSTA_DLLSC
;
704 pcie_write_cmd(ctrl
, 0, ctrl_mask
);
705 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
706 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, 0);
707 if (pciehp_poll_mode
)
708 del_timer_sync(&ctrl
->poll_timer
);
710 pci_reset_bridge_secondary_bus(ctrl
->pcie
->port
);
712 pcie_capability_write_word(pdev
, PCI_EXP_SLTSTA
, stat_mask
);
713 pcie_write_cmd_nowait(ctrl
, ctrl_mask
, ctrl_mask
);
714 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
715 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, ctrl_mask
);
716 if (pciehp_poll_mode
)
717 int_poll_timeout(ctrl
->poll_timer
.data
);
722 int pcie_init_notification(struct controller
*ctrl
)
724 if (pciehp_request_irq(ctrl
))
726 pcie_enable_notification(ctrl
);
727 ctrl
->notification_enabled
= 1;
731 static void pcie_shutdown_notification(struct controller
*ctrl
)
733 if (ctrl
->notification_enabled
) {
734 pcie_disable_notification(ctrl
);
735 pciehp_free_irq(ctrl
);
736 ctrl
->notification_enabled
= 0;
740 static int pcie_init_slot(struct controller
*ctrl
)
744 slot
= kzalloc(sizeof(*slot
), GFP_KERNEL
);
748 slot
->wq
= alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl
));
753 mutex_init(&slot
->lock
);
754 mutex_init(&slot
->hotplug_lock
);
755 INIT_DELAYED_WORK(&slot
->work
, pciehp_queue_pushbutton_work
);
763 static void pcie_cleanup_slot(struct controller
*ctrl
)
765 struct slot
*slot
= ctrl
->slot
;
766 cancel_delayed_work(&slot
->work
);
767 destroy_workqueue(slot
->wq
);
771 static inline void dbg_ctrl(struct controller
*ctrl
)
773 struct pci_dev
*pdev
= ctrl
->pcie
->port
;
779 ctrl_info(ctrl
, "Slot Capabilities : 0x%08x\n", ctrl
->slot_cap
);
780 pcie_capability_read_word(pdev
, PCI_EXP_SLTSTA
, ®16
);
781 ctrl_info(ctrl
, "Slot Status : 0x%04x\n", reg16
);
782 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL
, ®16
);
783 ctrl_info(ctrl
, "Slot Control : 0x%04x\n", reg16
);
786 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
788 struct controller
*pcie_init(struct pcie_device
*dev
)
790 struct controller
*ctrl
;
791 u32 slot_cap
, link_cap
;
792 struct pci_dev
*pdev
= dev
->port
;
794 ctrl
= kzalloc(sizeof(*ctrl
), GFP_KERNEL
);
796 dev_err(&dev
->device
, "%s: Out of memory\n", __func__
);
800 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, &slot_cap
);
801 ctrl
->slot_cap
= slot_cap
;
802 mutex_init(&ctrl
->ctrl_lock
);
803 init_waitqueue_head(&ctrl
->queue
);
806 /* Check if Data Link Layer Link Active Reporting is implemented */
807 pcie_capability_read_dword(pdev
, PCI_EXP_LNKCAP
, &link_cap
);
808 if (link_cap
& PCI_EXP_LNKCAP_DLLLARC
)
809 ctrl
->link_active_reporting
= 1;
811 /* Clear all remaining event bits in Slot Status register */
812 pcie_capability_write_word(pdev
, PCI_EXP_SLTSTA
,
813 PCI_EXP_SLTSTA_ABP
| PCI_EXP_SLTSTA_PFD
|
814 PCI_EXP_SLTSTA_MRLSC
| PCI_EXP_SLTSTA_PDC
|
815 PCI_EXP_SLTSTA_CC
| PCI_EXP_SLTSTA_DLLSC
);
817 ctrl_info(ctrl
, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
818 (slot_cap
& PCI_EXP_SLTCAP_PSN
) >> 19,
819 FLAG(slot_cap
, PCI_EXP_SLTCAP_ABP
),
820 FLAG(slot_cap
, PCI_EXP_SLTCAP_PCP
),
821 FLAG(slot_cap
, PCI_EXP_SLTCAP_MRLSP
),
822 FLAG(slot_cap
, PCI_EXP_SLTCAP_AIP
),
823 FLAG(slot_cap
, PCI_EXP_SLTCAP_PIP
),
824 FLAG(slot_cap
, PCI_EXP_SLTCAP_HPC
),
825 FLAG(slot_cap
, PCI_EXP_SLTCAP_HPS
),
826 FLAG(slot_cap
, PCI_EXP_SLTCAP_EIP
),
827 FLAG(slot_cap
, PCI_EXP_SLTCAP_NCCS
),
828 FLAG(link_cap
, PCI_EXP_LNKCAP_DLLLARC
));
830 if (pcie_init_slot(ctrl
))
841 void pciehp_release_ctrl(struct controller
*ctrl
)
843 pcie_shutdown_notification(ctrl
);
844 pcie_cleanup_slot(ctrl
);