2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.3"
56 AHCI_MAX_SG
= 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY
= 0xffffffff,
58 AHCI_USE_CLUSTERING
= 0,
59 AHCI_CMD_SLOT_SZ
= 32 * 32,
61 AHCI_CMD_TBL_HDR
= 0x80,
62 AHCI_CMD_TBL_CDB
= 0x40,
63 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR
+ (AHCI_MAX_SG
* 16),
64 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_SZ
+
66 AHCI_IRQ_ON_SG
= (1 << 31),
67 AHCI_CMD_ATAPI
= (1 << 5),
68 AHCI_CMD_WRITE
= (1 << 6),
69 AHCI_CMD_PREFETCH
= (1 << 7),
70 AHCI_CMD_RESET
= (1 << 8),
71 AHCI_CMD_CLR_BUSY
= (1 << 10),
73 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
76 board_ahci_vt8251
= 1,
78 /* global controller registers */
79 HOST_CAP
= 0x00, /* host capabilities */
80 HOST_CTL
= 0x04, /* global host control */
81 HOST_IRQ_STAT
= 0x08, /* interrupt status */
82 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
83 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
86 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
87 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
88 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
91 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
92 HOST_CAP_CLO
= (1 << 24), /* Command List Override support */
94 /* registers for each SATA port */
95 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
96 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
97 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
98 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
99 PORT_IRQ_STAT
= 0x10, /* interrupt status */
100 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
101 PORT_CMD
= 0x18, /* port command */
102 PORT_TFDATA
= 0x20, /* taskfile data */
103 PORT_SIG
= 0x24, /* device TF signature */
104 PORT_CMD_ISSUE
= 0x38, /* command issue */
105 PORT_SCR
= 0x28, /* SATA phy register block */
106 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
107 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
108 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
109 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
111 /* PORT_IRQ_{STAT,MASK} bits */
112 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
113 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
114 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
115 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
116 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
117 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
118 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
119 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
121 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
122 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
123 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
124 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
125 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
126 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
127 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
128 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
129 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
131 PORT_IRQ_FATAL
= PORT_IRQ_TF_ERR
|
133 PORT_IRQ_HBUS_DATA_ERR
|
135 DEF_PORT_IRQ
= PORT_IRQ_FATAL
| PORT_IRQ_PHYRDY
|
136 PORT_IRQ_CONNECT
| PORT_IRQ_SG_DONE
|
137 PORT_IRQ_UNK_FIS
| PORT_IRQ_SDB_FIS
|
138 PORT_IRQ_DMAS_FIS
| PORT_IRQ_PIOS_FIS
|
139 PORT_IRQ_D2H_REG_FIS
,
142 PORT_CMD_ATAPI
= (1 << 24), /* Device is ATAPI */
143 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
144 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
145 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
146 PORT_CMD_CLO
= (1 << 3), /* Command list override */
147 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
148 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
149 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
151 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
152 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
153 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
155 /* hpriv->flags bits */
156 AHCI_FLAG_MSI
= (1 << 0),
159 AHCI_FLAG_RESET_NEEDS_CLO
= (1 << 24),
162 struct ahci_cmd_hdr
{
177 struct ahci_host_priv
{
179 u32 cap
; /* cache of HOST_CAP register */
180 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
183 struct ahci_port_priv
{
184 struct ahci_cmd_hdr
*cmd_slot
;
185 dma_addr_t cmd_slot_dma
;
187 dma_addr_t cmd_tbl_dma
;
188 struct ahci_sg
*cmd_tbl_sg
;
190 dma_addr_t rx_fis_dma
;
193 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
194 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
195 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
196 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
197 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
198 static int ahci_probe_reset(struct ata_port
*ap
, unsigned int *classes
);
199 static void ahci_irq_clear(struct ata_port
*ap
);
200 static void ahci_eng_timeout(struct ata_port
*ap
);
201 static int ahci_port_start(struct ata_port
*ap
);
202 static void ahci_port_stop(struct ata_port
*ap
);
203 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
204 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
205 static u8
ahci_check_status(struct ata_port
*ap
);
206 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
);
207 static void ahci_remove_one (struct pci_dev
*pdev
);
209 static struct scsi_host_template ahci_sht
= {
210 .module
= THIS_MODULE
,
212 .ioctl
= ata_scsi_ioctl
,
213 .queuecommand
= ata_scsi_queuecmd
,
214 .can_queue
= ATA_DEF_QUEUE
,
215 .this_id
= ATA_SHT_THIS_ID
,
216 .sg_tablesize
= AHCI_MAX_SG
,
217 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
218 .emulated
= ATA_SHT_EMULATED
,
219 .use_clustering
= AHCI_USE_CLUSTERING
,
220 .proc_name
= DRV_NAME
,
221 .dma_boundary
= AHCI_DMA_BOUNDARY
,
222 .slave_configure
= ata_scsi_slave_config
,
223 .bios_param
= ata_std_bios_param
,
226 static const struct ata_port_operations ahci_ops
= {
227 .port_disable
= ata_port_disable
,
229 .check_status
= ahci_check_status
,
230 .check_altstatus
= ahci_check_status
,
231 .dev_select
= ata_noop_dev_select
,
233 .tf_read
= ahci_tf_read
,
235 .probe_reset
= ahci_probe_reset
,
237 .qc_prep
= ahci_qc_prep
,
238 .qc_issue
= ahci_qc_issue
,
240 .eng_timeout
= ahci_eng_timeout
,
242 .irq_handler
= ahci_interrupt
,
243 .irq_clear
= ahci_irq_clear
,
245 .scr_read
= ahci_scr_read
,
246 .scr_write
= ahci_scr_write
,
248 .port_start
= ahci_port_start
,
249 .port_stop
= ahci_port_stop
,
252 static const struct ata_port_info ahci_port_info
[] = {
256 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
257 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
,
258 .pio_mask
= 0x1f, /* pio0-4 */
259 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
260 .port_ops
= &ahci_ops
,
262 /* board_ahci_vt8251 */
265 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
266 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
267 AHCI_FLAG_RESET_NEEDS_CLO
,
268 .pio_mask
= 0x1f, /* pio0-4 */
269 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
270 .port_ops
= &ahci_ops
,
274 static const struct pci_device_id ahci_pci_tbl
[] = {
275 { PCI_VENDOR_ID_INTEL
, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
276 board_ahci
}, /* ICH6 */
277 { PCI_VENDOR_ID_INTEL
, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
278 board_ahci
}, /* ICH6M */
279 { PCI_VENDOR_ID_INTEL
, 0x27c1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
280 board_ahci
}, /* ICH7 */
281 { PCI_VENDOR_ID_INTEL
, 0x27c5, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
282 board_ahci
}, /* ICH7M */
283 { PCI_VENDOR_ID_INTEL
, 0x27c3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
284 board_ahci
}, /* ICH7R */
285 { PCI_VENDOR_ID_AL
, 0x5288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
286 board_ahci
}, /* ULi M5288 */
287 { PCI_VENDOR_ID_INTEL
, 0x2681, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
288 board_ahci
}, /* ESB2 */
289 { PCI_VENDOR_ID_INTEL
, 0x2682, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
290 board_ahci
}, /* ESB2 */
291 { PCI_VENDOR_ID_INTEL
, 0x2683, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
292 board_ahci
}, /* ESB2 */
293 { PCI_VENDOR_ID_INTEL
, 0x27c6, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
294 board_ahci
}, /* ICH7-M DH */
295 { PCI_VENDOR_ID_INTEL
, 0x2821, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
296 board_ahci
}, /* ICH8 */
297 { PCI_VENDOR_ID_INTEL
, 0x2822, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
298 board_ahci
}, /* ICH8 */
299 { PCI_VENDOR_ID_INTEL
, 0x2824, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
300 board_ahci
}, /* ICH8 */
301 { PCI_VENDOR_ID_INTEL
, 0x2829, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
302 board_ahci
}, /* ICH8M */
303 { PCI_VENDOR_ID_INTEL
, 0x282a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
304 board_ahci
}, /* ICH8M */
305 { 0x197b, 0x2360, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
306 board_ahci
}, /* JMicron JMB360 */
307 { 0x197b, 0x2363, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
308 board_ahci
}, /* JMicron JMB363 */
309 { PCI_VENDOR_ID_ATI
, 0x4380, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
310 board_ahci
}, /* ATI SB600 non-raid */
311 { PCI_VENDOR_ID_ATI
, 0x4381, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
312 board_ahci
}, /* ATI SB600 raid */
313 { PCI_VENDOR_ID_VIA
, 0x3349, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
314 board_ahci_vt8251
}, /* VIA VT8251 */
315 { } /* terminate list */
319 static struct pci_driver ahci_pci_driver
= {
321 .id_table
= ahci_pci_tbl
,
322 .probe
= ahci_init_one
,
323 .remove
= ahci_remove_one
,
327 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
329 return base
+ 0x100 + (port
* 0x80);
332 static inline void __iomem
*ahci_port_base (void __iomem
*base
, unsigned int port
)
334 return (void __iomem
*) ahci_port_base_ul((unsigned long)base
, port
);
337 static int ahci_port_start(struct ata_port
*ap
)
339 struct device
*dev
= ap
->host_set
->dev
;
340 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
341 struct ahci_port_priv
*pp
;
342 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
343 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
348 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
351 memset(pp
, 0, sizeof(*pp
));
353 rc
= ata_pad_alloc(ap
, dev
);
359 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
361 ata_pad_free(ap
, dev
);
365 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
368 * First item in chunk of DMA memory: 32-slot command table,
369 * 32 bytes each in size
372 pp
->cmd_slot_dma
= mem_dma
;
374 mem
+= AHCI_CMD_SLOT_SZ
;
375 mem_dma
+= AHCI_CMD_SLOT_SZ
;
378 * Second item: Received-FIS area
381 pp
->rx_fis_dma
= mem_dma
;
383 mem
+= AHCI_RX_FIS_SZ
;
384 mem_dma
+= AHCI_RX_FIS_SZ
;
387 * Third item: data area for storing a single command
388 * and its scatter-gather table
391 pp
->cmd_tbl_dma
= mem_dma
;
393 pp
->cmd_tbl_sg
= mem
+ AHCI_CMD_TBL_HDR
;
395 ap
->private_data
= pp
;
397 if (hpriv
->cap
& HOST_CAP_64
)
398 writel((pp
->cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
399 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
400 readl(port_mmio
+ PORT_LST_ADDR
); /* flush */
402 if (hpriv
->cap
& HOST_CAP_64
)
403 writel((pp
->rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
404 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
405 readl(port_mmio
+ PORT_FIS_ADDR
); /* flush */
407 writel(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
408 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
409 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
410 readl(port_mmio
+ PORT_CMD
); /* flush */
416 static void ahci_port_stop(struct ata_port
*ap
)
418 struct device
*dev
= ap
->host_set
->dev
;
419 struct ahci_port_priv
*pp
= ap
->private_data
;
420 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
421 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
424 tmp
= readl(port_mmio
+ PORT_CMD
);
425 tmp
&= ~(PORT_CMD_START
| PORT_CMD_FIS_RX
);
426 writel(tmp
, port_mmio
+ PORT_CMD
);
427 readl(port_mmio
+ PORT_CMD
); /* flush */
429 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
430 * this is slightly incorrect.
434 ap
->private_data
= NULL
;
435 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
436 pp
->cmd_slot
, pp
->cmd_slot_dma
);
437 ata_pad_free(ap
, dev
);
441 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
446 case SCR_STATUS
: sc_reg
= 0; break;
447 case SCR_CONTROL
: sc_reg
= 1; break;
448 case SCR_ERROR
: sc_reg
= 2; break;
449 case SCR_ACTIVE
: sc_reg
= 3; break;
454 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
458 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
464 case SCR_STATUS
: sc_reg
= 0; break;
465 case SCR_CONTROL
: sc_reg
= 1; break;
466 case SCR_ERROR
: sc_reg
= 2; break;
467 case SCR_ACTIVE
: sc_reg
= 3; break;
472 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
475 static int ahci_stop_engine(struct ata_port
*ap
)
477 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
478 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
482 tmp
= readl(port_mmio
+ PORT_CMD
);
483 tmp
&= ~PORT_CMD_START
;
484 writel(tmp
, port_mmio
+ PORT_CMD
);
486 /* wait for engine to stop. TODO: this could be
487 * as long as 500 msec
491 tmp
= readl(port_mmio
+ PORT_CMD
);
492 if ((tmp
& PORT_CMD_LIST_ON
) == 0)
500 static void ahci_start_engine(struct ata_port
*ap
)
502 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
503 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
506 tmp
= readl(port_mmio
+ PORT_CMD
);
507 tmp
|= PORT_CMD_START
;
508 writel(tmp
, port_mmio
+ PORT_CMD
);
509 readl(port_mmio
+ PORT_CMD
); /* flush */
512 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
514 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
515 struct ata_taskfile tf
;
518 tmp
= readl(port_mmio
+ PORT_SIG
);
519 tf
.lbah
= (tmp
>> 24) & 0xff;
520 tf
.lbam
= (tmp
>> 16) & 0xff;
521 tf
.lbal
= (tmp
>> 8) & 0xff;
522 tf
.nsect
= (tmp
) & 0xff;
524 return ata_dev_classify(&tf
);
527 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, u32 opts
)
529 pp
->cmd_slot
[0].opts
= cpu_to_le32(opts
);
530 pp
->cmd_slot
[0].status
= 0;
531 pp
->cmd_slot
[0].tbl_addr
= cpu_to_le32(pp
->cmd_tbl_dma
& 0xffffffff);
532 pp
->cmd_slot
[0].tbl_addr_hi
= cpu_to_le32((pp
->cmd_tbl_dma
>> 16) >> 16);
535 static int ahci_clo(struct ata_port
*ap
)
537 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
538 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
541 if (!(hpriv
->cap
& HOST_CAP_CLO
))
544 tmp
= readl(port_mmio
+ PORT_CMD
);
546 writel(tmp
, port_mmio
+ PORT_CMD
);
548 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
549 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
550 if (tmp
& PORT_CMD_CLO
)
556 static int ahci_softreset(struct ata_port
*ap
, unsigned int *class)
558 struct ahci_port_priv
*pp
= ap
->private_data
;
559 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
560 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
561 const u32 cmd_fis_len
= 5; /* five dwords */
562 const char *reason
= NULL
;
563 struct ata_taskfile tf
;
570 if (!sata_dev_present(ap
)) {
571 DPRINTK("PHY reports no device\n");
572 *class = ATA_DEV_NONE
;
576 /* prepare for SRST (AHCI-1.1 10.4.1) */
577 rc
= ahci_stop_engine(ap
);
579 reason
= "failed to stop engine";
583 /* check BUSY/DRQ, perform Command List Override if necessary */
584 ahci_tf_read(ap
, &tf
);
585 if (tf
.command
& (ATA_BUSY
| ATA_DRQ
)) {
588 if (rc
== -EOPNOTSUPP
) {
589 reason
= "port busy but CLO unavailable";
592 reason
= "port busy but CLO failed";
598 ahci_start_engine(ap
);
600 ata_tf_init(ap
, &tf
, 0);
603 /* issue the first D2H Register FIS */
604 ahci_fill_cmd_slot(pp
, cmd_fis_len
| AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
);
607 ata_tf_to_fis(&tf
, fis
, 0);
608 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
610 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
612 tmp
= ata_wait_register(port_mmio
+ PORT_CMD_ISSUE
, 0x1, 0x1, 1, 500);
615 reason
= "1st FIS failed";
619 /* spec says at least 5us, but be generous and sleep for 1ms */
622 /* issue the second D2H Register FIS */
623 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
626 ata_tf_to_fis(&tf
, fis
, 0);
627 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
629 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
630 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
632 /* spec mandates ">= 2ms" before checking status.
633 * We wait 150ms, because that was the magic delay used for
634 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
635 * between when the ATA command register is written, and then
636 * status is checked. Because waiting for "a while" before
637 * checking status is fine, post SRST, we perform this magic
638 * delay here as well.
642 *class = ATA_DEV_NONE
;
643 if (sata_dev_present(ap
)) {
644 if (ata_busy_sleep(ap
, ATA_TMOUT_BOOT_QUICK
, ATA_TMOUT_BOOT
)) {
646 reason
= "device not ready";
649 *class = ahci_dev_classify(ap
);
652 DPRINTK("EXIT, class=%u\n", *class);
656 ahci_start_engine(ap
);
658 printk(KERN_ERR
"ata%u: softreset failed (%s)\n",
663 static int ahci_hardreset(struct ata_port
*ap
, unsigned int *class)
669 ahci_stop_engine(ap
);
670 rc
= sata_std_hardreset(ap
, class);
671 ahci_start_engine(ap
);
674 *class = ahci_dev_classify(ap
);
675 if (*class == ATA_DEV_UNKNOWN
)
676 *class = ATA_DEV_NONE
;
678 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
682 static void ahci_postreset(struct ata_port
*ap
, unsigned int *class)
684 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
687 ata_std_postreset(ap
, class);
689 /* Make sure port's ATAPI bit is set appropriately */
690 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
691 if (*class == ATA_DEV_ATAPI
)
692 new_tmp
|= PORT_CMD_ATAPI
;
694 new_tmp
&= ~PORT_CMD_ATAPI
;
695 if (new_tmp
!= tmp
) {
696 writel(new_tmp
, port_mmio
+ PORT_CMD
);
697 readl(port_mmio
+ PORT_CMD
); /* flush */
701 static int ahci_probe_reset(struct ata_port
*ap
, unsigned int *classes
)
703 if ((ap
->flags
& AHCI_FLAG_RESET_NEEDS_CLO
) &&
704 (ata_busy_wait(ap
, ATA_BUSY
, 1000) & ATA_BUSY
)) {
705 /* ATA_BUSY hasn't cleared, so send a CLO */
709 return ata_drive_probe_reset(ap
, ata_std_probeinit
,
710 ahci_softreset
, ahci_hardreset
,
711 ahci_postreset
, classes
);
714 static u8
ahci_check_status(struct ata_port
*ap
)
716 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
718 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
721 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
723 struct ahci_port_priv
*pp
= ap
->private_data
;
724 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
726 ata_tf_from_fis(d2h_fis
, tf
);
729 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
)
731 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
732 struct scatterlist
*sg
;
733 struct ahci_sg
*ahci_sg
;
734 unsigned int n_sg
= 0;
739 * Next, the S/G list.
741 ahci_sg
= pp
->cmd_tbl_sg
;
742 ata_for_each_sg(sg
, qc
) {
743 dma_addr_t addr
= sg_dma_address(sg
);
744 u32 sg_len
= sg_dma_len(sg
);
746 ahci_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
747 ahci_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
748 ahci_sg
->flags_size
= cpu_to_le32(sg_len
- 1);
757 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
759 struct ata_port
*ap
= qc
->ap
;
760 struct ahci_port_priv
*pp
= ap
->private_data
;
761 int is_atapi
= is_atapi_taskfile(&qc
->tf
);
763 const u32 cmd_fis_len
= 5; /* five dwords */
767 * Fill in command table information. First, the header,
768 * a SATA Register - Host to Device command FIS.
770 ata_tf_to_fis(&qc
->tf
, pp
->cmd_tbl
, 0);
772 memset(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
773 memcpy(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
,
778 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
779 n_elem
= ahci_fill_sg(qc
);
782 * Fill in command slot information.
784 opts
= cmd_fis_len
| n_elem
<< 16;
785 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
786 opts
|= AHCI_CMD_WRITE
;
788 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
790 ahci_fill_cmd_slot(pp
, opts
);
793 static void ahci_restart_port(struct ata_port
*ap
, u32 irq_stat
)
795 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
796 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
799 if ((ap
->device
[0].class != ATA_DEV_ATAPI
) ||
800 ((irq_stat
& PORT_IRQ_TF_ERR
) == 0))
801 printk(KERN_WARNING
"ata%u: port reset, "
802 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
805 readl(mmio
+ HOST_IRQ_STAT
),
806 readl(port_mmio
+ PORT_IRQ_STAT
),
807 readl(port_mmio
+ PORT_CMD
),
808 readl(port_mmio
+ PORT_TFDATA
),
809 readl(port_mmio
+ PORT_SCR_STAT
),
810 readl(port_mmio
+ PORT_SCR_ERR
));
813 ahci_stop_engine(ap
);
815 /* clear SATA phy error, if any */
816 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
817 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
819 /* if DRQ/BSY is set, device needs to be reset.
820 * if so, issue COMRESET
822 tmp
= readl(port_mmio
+ PORT_TFDATA
);
823 if (tmp
& (ATA_BUSY
| ATA_DRQ
)) {
824 writel(0x301, port_mmio
+ PORT_SCR_CTL
);
825 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
827 writel(0x300, port_mmio
+ PORT_SCR_CTL
);
828 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
832 ahci_start_engine(ap
);
835 static void ahci_eng_timeout(struct ata_port
*ap
)
837 struct ata_host_set
*host_set
= ap
->host_set
;
838 void __iomem
*mmio
= host_set
->mmio_base
;
839 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
840 struct ata_queued_cmd
*qc
;
843 printk(KERN_WARNING
"ata%u: handling error/timeout\n", ap
->id
);
845 spin_lock_irqsave(&host_set
->lock
, flags
);
847 ahci_restart_port(ap
, readl(port_mmio
+ PORT_IRQ_STAT
));
848 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
849 qc
->err_mask
|= AC_ERR_TIMEOUT
;
851 spin_unlock_irqrestore(&host_set
->lock
, flags
);
853 ata_eh_qc_complete(qc
);
856 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
858 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
859 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
860 u32 status
, serr
, ci
;
862 serr
= readl(port_mmio
+ PORT_SCR_ERR
);
863 writel(serr
, port_mmio
+ PORT_SCR_ERR
);
865 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
866 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
868 ci
= readl(port_mmio
+ PORT_CMD_ISSUE
);
869 if (likely((ci
& 0x1) == 0)) {
871 WARN_ON(qc
->err_mask
);
877 if (status
& PORT_IRQ_FATAL
) {
878 unsigned int err_mask
;
879 if (status
& PORT_IRQ_TF_ERR
)
880 err_mask
= AC_ERR_DEV
;
881 else if (status
& PORT_IRQ_IF_ERR
)
882 err_mask
= AC_ERR_ATA_BUS
;
884 err_mask
= AC_ERR_HOST_BUS
;
886 /* command processing has stopped due to error; restart */
887 ahci_restart_port(ap
, status
);
890 qc
->err_mask
|= err_mask
;
898 static void ahci_irq_clear(struct ata_port
*ap
)
903 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
905 struct ata_host_set
*host_set
= dev_instance
;
906 struct ahci_host_priv
*hpriv
;
907 unsigned int i
, handled
= 0;
909 u32 irq_stat
, irq_ack
= 0;
913 hpriv
= host_set
->private_data
;
914 mmio
= host_set
->mmio_base
;
916 /* sigh. 0xffffffff is a valid return from h/w */
917 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
918 irq_stat
&= hpriv
->port_map
;
922 spin_lock(&host_set
->lock
);
924 for (i
= 0; i
< host_set
->n_ports
; i
++) {
927 if (!(irq_stat
& (1 << i
)))
930 ap
= host_set
->ports
[i
];
932 struct ata_queued_cmd
*qc
;
933 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
934 if (!ahci_host_intr(ap
, qc
))
936 dev_printk(KERN_WARNING
, host_set
->dev
,
937 "unhandled interrupt on port %u\n",
940 VPRINTK("port %u\n", i
);
942 VPRINTK("port %u (no irq)\n", i
);
944 dev_printk(KERN_WARNING
, host_set
->dev
,
945 "interrupt on disabled port %u\n", i
);
952 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
956 spin_unlock(&host_set
->lock
);
960 return IRQ_RETVAL(handled
);
963 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
965 struct ata_port
*ap
= qc
->ap
;
966 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
968 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
969 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
974 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
975 unsigned int port_idx
)
977 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
978 base
= ahci_port_base_ul(base
, port_idx
);
979 VPRINTK("base now==0x%lx\n", base
);
981 port
->cmd_addr
= base
;
982 port
->scr_addr
= base
+ PORT_SCR
;
987 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
989 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
990 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
991 void __iomem
*mmio
= probe_ent
->mmio_base
;
993 unsigned int i
, j
, using_dac
;
995 void __iomem
*port_mmio
;
997 cap_save
= readl(mmio
+ HOST_CAP
);
998 cap_save
&= ( (1<<28) | (1<<17) );
999 cap_save
|= (1 << 27);
1001 /* global controller reset */
1002 tmp
= readl(mmio
+ HOST_CTL
);
1003 if ((tmp
& HOST_RESET
) == 0) {
1004 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
1005 readl(mmio
+ HOST_CTL
); /* flush */
1008 /* reset must complete within 1 second, or
1009 * the hardware should be considered fried.
1013 tmp
= readl(mmio
+ HOST_CTL
);
1014 if (tmp
& HOST_RESET
) {
1015 dev_printk(KERN_ERR
, &pdev
->dev
,
1016 "controller reset failed (0x%x)\n", tmp
);
1020 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
1021 (void) readl(mmio
+ HOST_CTL
); /* flush */
1022 writel(cap_save
, mmio
+ HOST_CAP
);
1023 writel(0xf, mmio
+ HOST_PORTS_IMPL
);
1024 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
1026 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
) {
1029 pci_read_config_word(pdev
, 0x92, &tmp16
);
1031 pci_write_config_word(pdev
, 0x92, tmp16
);
1034 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
1035 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
1036 probe_ent
->n_ports
= (hpriv
->cap
& 0x1f) + 1;
1038 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1039 hpriv
->cap
, hpriv
->port_map
, probe_ent
->n_ports
);
1041 using_dac
= hpriv
->cap
& HOST_CAP_64
;
1043 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
1044 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
1046 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1048 dev_printk(KERN_ERR
, &pdev
->dev
,
1049 "64-bit DMA enable failed\n");
1054 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1056 dev_printk(KERN_ERR
, &pdev
->dev
,
1057 "32-bit DMA enable failed\n");
1060 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1062 dev_printk(KERN_ERR
, &pdev
->dev
,
1063 "32-bit consistent DMA enable failed\n");
1068 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
1069 #if 0 /* BIOSen initialize this incorrectly */
1070 if (!(hpriv
->port_map
& (1 << i
)))
1074 port_mmio
= ahci_port_base(mmio
, i
);
1075 VPRINTK("mmio %p port_mmio %p\n", mmio
, port_mmio
);
1077 ahci_setup_port(&probe_ent
->port
[i
],
1078 (unsigned long) mmio
, i
);
1080 /* make sure port is not active */
1081 tmp
= readl(port_mmio
+ PORT_CMD
);
1082 VPRINTK("PORT_CMD 0x%x\n", tmp
);
1083 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
1084 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
1085 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
1086 PORT_CMD_FIS_RX
| PORT_CMD_START
);
1087 writel(tmp
, port_mmio
+ PORT_CMD
);
1088 readl(port_mmio
+ PORT_CMD
); /* flush */
1090 /* spec says 500 msecs for each bit, so
1091 * this is slightly incorrect.
1096 writel(PORT_CMD_SPIN_UP
, port_mmio
+ PORT_CMD
);
1101 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
1102 if ((tmp
& 0xf) == 0x3)
1107 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
1108 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
1109 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
1111 /* ack any pending irq events for this port */
1112 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1113 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
1115 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1117 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
1119 /* set irq mask (enables interrupts) */
1120 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
1123 tmp
= readl(mmio
+ HOST_CTL
);
1124 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1125 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
1126 tmp
= readl(mmio
+ HOST_CTL
);
1127 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1129 pci_set_master(pdev
);
1134 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
1136 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
1137 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1138 void __iomem
*mmio
= probe_ent
->mmio_base
;
1139 u32 vers
, cap
, impl
, speed
;
1140 const char *speed_s
;
1144 vers
= readl(mmio
+ HOST_VERSION
);
1146 impl
= hpriv
->port_map
;
1148 speed
= (cap
>> 20) & 0xf;
1151 else if (speed
== 2)
1156 pci_read_config_word(pdev
, 0x0a, &cc
);
1159 else if (cc
== 0x0106)
1161 else if (cc
== 0x0104)
1166 dev_printk(KERN_INFO
, &pdev
->dev
,
1167 "AHCI %02x%02x.%02x%02x "
1168 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1171 (vers
>> 24) & 0xff,
1172 (vers
>> 16) & 0xff,
1176 ((cap
>> 8) & 0x1f) + 1,
1182 dev_printk(KERN_INFO
, &pdev
->dev
,
1188 cap
& (1 << 31) ? "64bit " : "",
1189 cap
& (1 << 30) ? "ncq " : "",
1190 cap
& (1 << 28) ? "ilck " : "",
1191 cap
& (1 << 27) ? "stag " : "",
1192 cap
& (1 << 26) ? "pm " : "",
1193 cap
& (1 << 25) ? "led " : "",
1195 cap
& (1 << 24) ? "clo " : "",
1196 cap
& (1 << 19) ? "nz " : "",
1197 cap
& (1 << 18) ? "only " : "",
1198 cap
& (1 << 17) ? "pmp " : "",
1199 cap
& (1 << 15) ? "pio " : "",
1200 cap
& (1 << 14) ? "slum " : "",
1201 cap
& (1 << 13) ? "part " : ""
1205 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1207 static int printed_version
;
1208 struct ata_probe_ent
*probe_ent
= NULL
;
1209 struct ahci_host_priv
*hpriv
;
1211 void __iomem
*mmio_base
;
1212 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1213 int have_msi
, pci_dev_busy
= 0;
1218 if (!printed_version
++)
1219 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1221 rc
= pci_enable_device(pdev
);
1225 rc
= pci_request_regions(pdev
, DRV_NAME
);
1231 if (pci_enable_msi(pdev
) == 0)
1238 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1239 if (probe_ent
== NULL
) {
1244 memset(probe_ent
, 0, sizeof(*probe_ent
));
1245 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1246 INIT_LIST_HEAD(&probe_ent
->node
);
1248 mmio_base
= pci_iomap(pdev
, AHCI_PCI_BAR
, 0);
1249 if (mmio_base
== NULL
) {
1251 goto err_out_free_ent
;
1253 base
= (unsigned long) mmio_base
;
1255 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1258 goto err_out_iounmap
;
1260 memset(hpriv
, 0, sizeof(*hpriv
));
1262 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1263 probe_ent
->host_flags
= ahci_port_info
[board_idx
].host_flags
;
1264 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1265 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1266 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1268 probe_ent
->irq
= pdev
->irq
;
1269 probe_ent
->irq_flags
= SA_SHIRQ
;
1270 probe_ent
->mmio_base
= mmio_base
;
1271 probe_ent
->private_data
= hpriv
;
1274 hpriv
->flags
|= AHCI_FLAG_MSI
;
1276 /* JMicron-specific fixup: make sure we're in AHCI mode */
1277 if (pdev
->vendor
== 0x197b)
1278 pci_write_config_byte(pdev
, 0x41, 0xa1);
1280 /* initialize adapter */
1281 rc
= ahci_host_init(probe_ent
);
1285 ahci_print_info(probe_ent
);
1287 /* FIXME: check ata_device_add return value */
1288 ata_device_add(probe_ent
);
1296 pci_iounmap(pdev
, mmio_base
);
1301 pci_disable_msi(pdev
);
1304 pci_release_regions(pdev
);
1307 pci_disable_device(pdev
);
1311 static void ahci_remove_one (struct pci_dev
*pdev
)
1313 struct device
*dev
= pci_dev_to_dev(pdev
);
1314 struct ata_host_set
*host_set
= dev_get_drvdata(dev
);
1315 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
1316 struct ata_port
*ap
;
1320 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1321 ap
= host_set
->ports
[i
];
1323 scsi_remove_host(ap
->host
);
1326 have_msi
= hpriv
->flags
& AHCI_FLAG_MSI
;
1327 free_irq(host_set
->irq
, host_set
);
1329 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1330 ap
= host_set
->ports
[i
];
1332 ata_scsi_release(ap
->host
);
1333 scsi_host_put(ap
->host
);
1337 pci_iounmap(pdev
, host_set
->mmio_base
);
1341 pci_disable_msi(pdev
);
1344 pci_release_regions(pdev
);
1345 pci_disable_device(pdev
);
1346 dev_set_drvdata(dev
, NULL
);
1349 static int __init
ahci_init(void)
1351 return pci_module_init(&ahci_pci_driver
);
1354 static void __exit
ahci_exit(void)
1356 pci_unregister_driver(&ahci_pci_driver
);
1360 MODULE_AUTHOR("Jeff Garzik");
1361 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1362 MODULE_LICENSE("GPL");
1363 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1364 MODULE_VERSION(DRV_VERSION
);
1366 module_init(ahci_init
);
1367 module_exit(ahci_exit
);