ARM: tegra: fix erroneous address in dts
[deliverable/linux.git] / drivers / scsi / g_NCR5380.h
1 /*
2 * Generic Generic NCR5380 driver defines
3 *
4 * Copyright 1993, Drew Eckhardt
5 * Visionary Computing
6 * (Unix and Linux consulting and custom programming)
7 * drew@colorado.edu
8 * +1 (303) 440-4894
9 *
10 * NCR53C400 extensions (c) 1994,1995,1996, Kevin Lentin
11 * K.Lentin@cs.monash.edu.au
12 */
13
14 #ifndef GENERIC_NCR5380_H
15 #define GENERIC_NCR5380_H
16
17 #define __STRVAL(x) #x
18 #define STRVAL(x) __STRVAL(x)
19
20 #ifndef SCSI_G_NCR5380_MEM
21 #define DRV_MODULE_NAME "g_NCR5380"
22
23 #define NCR5380_map_type int
24 #define NCR5380_map_name port
25
26 #define NCR5380_read(reg) \
27 inb(instance->io_port + (reg))
28 #define NCR5380_write(reg, value) \
29 outb(value, instance->io_port + (reg))
30
31 #define NCR5380_implementation_fields \
32 int c400_ctl_status; \
33 int c400_blk_cnt; \
34 int c400_host_buf; \
35 int io_width;
36
37 #else
38 /* therefore SCSI_G_NCR5380_MEM */
39 #define DRV_MODULE_NAME "g_NCR5380_mmio"
40
41 #define NCR5380_map_type unsigned long
42 #define NCR5380_map_name base
43 #define NCR53C400_mem_base 0x3880
44 #define NCR53C400_host_buffer 0x3900
45 #define NCR53C400_region_size 0x3a00
46
47 #define NCR5380_read(reg) \
48 readb(((struct NCR5380_hostdata *)shost_priv(instance))->iomem + \
49 NCR53C400_mem_base + (reg))
50 #define NCR5380_write(reg, value) \
51 writeb(value, ((struct NCR5380_hostdata *)shost_priv(instance))->iomem + \
52 NCR53C400_mem_base + (reg))
53
54 #define NCR5380_implementation_fields \
55 void __iomem *iomem; \
56 resource_size_t iomem_size; \
57 int c400_ctl_status; \
58 int c400_blk_cnt; \
59 int c400_host_buf;
60
61 #endif
62
63 #define NCR5380_dma_xfer_len(instance, cmd, phase) \
64 generic_NCR5380_dma_xfer_len(instance, cmd)
65 #define NCR5380_dma_recv_setup generic_NCR5380_pread
66 #define NCR5380_dma_send_setup generic_NCR5380_pwrite
67 #define NCR5380_dma_residual(instance) (0)
68
69 #define NCR5380_intr generic_NCR5380_intr
70 #define NCR5380_queue_command generic_NCR5380_queue_command
71 #define NCR5380_abort generic_NCR5380_abort
72 #define NCR5380_bus_reset generic_NCR5380_bus_reset
73 #define NCR5380_info generic_NCR5380_info
74
75 #define NCR5380_io_delay(x) udelay(x)
76
77 #define BOARD_NCR5380 0
78 #define BOARD_NCR53C400 1
79 #define BOARD_NCR53C400A 2
80 #define BOARD_DTC3181E 3
81 #define BOARD_HP_C2502 4
82
83 #endif /* GENERIC_NCR5380_H */
84
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