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Fix: rseq: arm branch to failure
[deliverable/linux.git] / drivers / spi / spi-fsl-espi.c
1 /*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/fsl_devices.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/module.h>
17 #include <linux/mm.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/spi/spi.h>
24 #include <linux/pm_runtime.h>
25 #include <sysdev/fsl_soc.h>
26
27 #include "spi-fsl-lib.h"
28
29 /* eSPI Controller registers */
30 struct fsl_espi_reg {
31 __be32 mode; /* 0x000 - eSPI mode register */
32 __be32 event; /* 0x004 - eSPI event register */
33 __be32 mask; /* 0x008 - eSPI mask register */
34 __be32 command; /* 0x00c - eSPI command register */
35 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
36 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
37 u8 res[8]; /* 0x018 - 0x01c reserved */
38 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
39 };
40
41 struct fsl_espi_transfer {
42 const void *tx_buf;
43 void *rx_buf;
44 unsigned len;
45 unsigned n_tx;
46 unsigned n_rx;
47 unsigned actual_length;
48 int status;
49 };
50
51 /* eSPI Controller mode register definitions */
52 #define SPMODE_ENABLE (1 << 31)
53 #define SPMODE_LOOP (1 << 30)
54 #define SPMODE_TXTHR(x) ((x) << 8)
55 #define SPMODE_RXTHR(x) ((x) << 0)
56
57 /* eSPI Controller CS mode register definitions */
58 #define CSMODE_CI_INACTIVEHIGH (1 << 31)
59 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
60 #define CSMODE_REV (1 << 29)
61 #define CSMODE_DIV16 (1 << 28)
62 #define CSMODE_PM(x) ((x) << 24)
63 #define CSMODE_POL_1 (1 << 20)
64 #define CSMODE_LEN(x) ((x) << 16)
65 #define CSMODE_BEF(x) ((x) << 12)
66 #define CSMODE_AFT(x) ((x) << 8)
67 #define CSMODE_CG(x) ((x) << 3)
68
69 /* Default mode/csmode for eSPI controller */
70 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
71 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
72 | CSMODE_AFT(0) | CSMODE_CG(1))
73
74 /* SPIE register values */
75 #define SPIE_NE 0x00000200 /* Not empty */
76 #define SPIE_NF 0x00000100 /* Not full */
77
78 /* SPIM register values */
79 #define SPIM_NE 0x00000200 /* Not empty */
80 #define SPIM_NF 0x00000100 /* Not full */
81 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
82 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
83
84 /* SPCOM register values */
85 #define SPCOM_CS(x) ((x) << 30)
86 #define SPCOM_TRANLEN(x) ((x) << 0)
87 #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
88
89 #define AUTOSUSPEND_TIMEOUT 2000
90
91 static void fsl_espi_change_mode(struct spi_device *spi)
92 {
93 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
94 struct spi_mpc8xxx_cs *cs = spi->controller_state;
95 struct fsl_espi_reg *reg_base = mspi->reg_base;
96 __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
97 __be32 __iomem *espi_mode = &reg_base->mode;
98 u32 tmp;
99 unsigned long flags;
100
101 /* Turn off IRQs locally to minimize time that SPI is disabled. */
102 local_irq_save(flags);
103
104 /* Turn off SPI unit prior changing mode */
105 tmp = mpc8xxx_spi_read_reg(espi_mode);
106 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
107 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
108 mpc8xxx_spi_write_reg(espi_mode, tmp);
109
110 local_irq_restore(flags);
111 }
112
113 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
114 {
115 u32 data;
116 u16 data_h;
117 u16 data_l;
118 const u32 *tx = mpc8xxx_spi->tx;
119
120 if (!tx)
121 return 0;
122
123 data = *tx++ << mpc8xxx_spi->tx_shift;
124 data_l = data & 0xffff;
125 data_h = (data >> 16) & 0xffff;
126 swab16s(&data_l);
127 swab16s(&data_h);
128 data = data_h | data_l;
129
130 mpc8xxx_spi->tx = tx;
131 return data;
132 }
133
134 static int fsl_espi_setup_transfer(struct spi_device *spi,
135 struct spi_transfer *t)
136 {
137 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
138 int bits_per_word = 0;
139 u8 pm;
140 u32 hz = 0;
141 struct spi_mpc8xxx_cs *cs = spi->controller_state;
142
143 if (t) {
144 bits_per_word = t->bits_per_word;
145 hz = t->speed_hz;
146 }
147
148 /* spi_transfer level calls that work per-word */
149 if (!bits_per_word)
150 bits_per_word = spi->bits_per_word;
151
152 if (!hz)
153 hz = spi->max_speed_hz;
154
155 cs->rx_shift = 0;
156 cs->tx_shift = 0;
157 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
158 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
159 if (bits_per_word <= 8) {
160 cs->rx_shift = 8 - bits_per_word;
161 } else {
162 cs->rx_shift = 16 - bits_per_word;
163 if (spi->mode & SPI_LSB_FIRST)
164 cs->get_tx = fsl_espi_tx_buf_lsb;
165 }
166
167 mpc8xxx_spi->rx_shift = cs->rx_shift;
168 mpc8xxx_spi->tx_shift = cs->tx_shift;
169 mpc8xxx_spi->get_rx = cs->get_rx;
170 mpc8xxx_spi->get_tx = cs->get_tx;
171
172 bits_per_word = bits_per_word - 1;
173
174 /* mask out bits we are going to set */
175 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
176
177 cs->hw_mode |= CSMODE_LEN(bits_per_word);
178
179 if ((mpc8xxx_spi->spibrg / hz) > 64) {
180 cs->hw_mode |= CSMODE_DIV16;
181 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
182
183 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
184 "Will use %d Hz instead.\n", dev_name(&spi->dev),
185 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
186 if (pm > 33)
187 pm = 33;
188 } else {
189 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
190 }
191 if (pm)
192 pm--;
193 if (pm < 2)
194 pm = 2;
195
196 cs->hw_mode |= CSMODE_PM(pm);
197
198 fsl_espi_change_mode(spi);
199 return 0;
200 }
201
202 static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
203 unsigned int len)
204 {
205 u32 word;
206 struct fsl_espi_reg *reg_base = mspi->reg_base;
207
208 mspi->count = len;
209
210 /* enable rx ints */
211 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
212
213 /* transmit word */
214 word = mspi->get_tx(mspi);
215 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
216
217 return 0;
218 }
219
220 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
221 {
222 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
223 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
224 unsigned int len = t->len;
225 int ret;
226
227 mpc8xxx_spi->len = t->len;
228 len = roundup(len, 4) / 4;
229
230 mpc8xxx_spi->tx = t->tx_buf;
231 mpc8xxx_spi->rx = t->rx_buf;
232
233 reinit_completion(&mpc8xxx_spi->done);
234
235 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
236 if (t->len > SPCOM_TRANLEN_MAX) {
237 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
238 " beyond the SPCOM[TRANLEN] field\n", t->len);
239 return -EINVAL;
240 }
241 mpc8xxx_spi_write_reg(&reg_base->command,
242 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
243
244 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
245 if (ret)
246 return ret;
247
248 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
249 ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ);
250 if (ret == 0)
251 dev_err(mpc8xxx_spi->dev,
252 "Transaction hanging up (left %d bytes)\n",
253 mpc8xxx_spi->count);
254
255 /* disable rx ints */
256 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
257
258 return mpc8xxx_spi->count;
259 }
260
261 static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
262 {
263 if (cmd) {
264 cmd[1] = (u8)(addr >> 16);
265 cmd[2] = (u8)(addr >> 8);
266 cmd[3] = (u8)(addr >> 0);
267 }
268 }
269
270 static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
271 {
272 if (cmd)
273 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
274
275 return 0;
276 }
277
278 static void fsl_espi_do_trans(struct spi_message *m,
279 struct fsl_espi_transfer *tr)
280 {
281 struct spi_device *spi = m->spi;
282 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
283 struct fsl_espi_transfer *espi_trans = tr;
284 struct spi_message message;
285 struct spi_transfer *t, *first, trans;
286 int status = 0;
287
288 spi_message_init(&message);
289 memset(&trans, 0, sizeof(trans));
290
291 first = list_first_entry(&m->transfers, struct spi_transfer,
292 transfer_list);
293 list_for_each_entry(t, &m->transfers, transfer_list) {
294 if ((first->bits_per_word != t->bits_per_word) ||
295 (first->speed_hz != t->speed_hz)) {
296 espi_trans->status = -EINVAL;
297 dev_err(mspi->dev,
298 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
299 return;
300 }
301
302 trans.speed_hz = t->speed_hz;
303 trans.bits_per_word = t->bits_per_word;
304 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
305 }
306
307 trans.len = espi_trans->len;
308 trans.tx_buf = espi_trans->tx_buf;
309 trans.rx_buf = espi_trans->rx_buf;
310 spi_message_add_tail(&trans, &message);
311
312 list_for_each_entry(t, &message.transfers, transfer_list) {
313 if (t->bits_per_word || t->speed_hz) {
314 status = -EINVAL;
315
316 status = fsl_espi_setup_transfer(spi, t);
317 if (status < 0)
318 break;
319 }
320
321 if (t->len)
322 status = fsl_espi_bufs(spi, t);
323
324 if (status) {
325 status = -EMSGSIZE;
326 break;
327 }
328
329 if (t->delay_usecs)
330 udelay(t->delay_usecs);
331 }
332
333 espi_trans->status = status;
334 fsl_espi_setup_transfer(spi, NULL);
335 }
336
337 static void fsl_espi_cmd_trans(struct spi_message *m,
338 struct fsl_espi_transfer *trans, u8 *rx_buff)
339 {
340 struct spi_transfer *t;
341 u8 *local_buf;
342 int i = 0;
343 struct fsl_espi_transfer *espi_trans = trans;
344
345 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
346 if (!local_buf) {
347 espi_trans->status = -ENOMEM;
348 return;
349 }
350
351 list_for_each_entry(t, &m->transfers, transfer_list) {
352 if (t->tx_buf) {
353 memcpy(local_buf + i, t->tx_buf, t->len);
354 i += t->len;
355 }
356 }
357
358 espi_trans->tx_buf = local_buf;
359 espi_trans->rx_buf = local_buf;
360 fsl_espi_do_trans(m, espi_trans);
361
362 espi_trans->actual_length = espi_trans->len;
363 kfree(local_buf);
364 }
365
366 static void fsl_espi_rw_trans(struct spi_message *m,
367 struct fsl_espi_transfer *trans, u8 *rx_buff)
368 {
369 struct fsl_espi_transfer *espi_trans = trans;
370 unsigned int total_len = espi_trans->len;
371 struct spi_transfer *t;
372 u8 *local_buf;
373 u8 *rx_buf = rx_buff;
374 unsigned int trans_len;
375 unsigned int addr;
376 unsigned int tx_only;
377 unsigned int rx_pos = 0;
378 unsigned int pos;
379 int i, loop;
380
381 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
382 if (!local_buf) {
383 espi_trans->status = -ENOMEM;
384 return;
385 }
386
387 for (pos = 0, loop = 0; pos < total_len; pos += trans_len, loop++) {
388 trans_len = total_len - pos;
389
390 i = 0;
391 tx_only = 0;
392 list_for_each_entry(t, &m->transfers, transfer_list) {
393 if (t->tx_buf) {
394 memcpy(local_buf + i, t->tx_buf, t->len);
395 i += t->len;
396 if (!t->rx_buf)
397 tx_only += t->len;
398 }
399 }
400
401 /* Add additional TX bytes to compensate SPCOM_TRANLEN_MAX */
402 if (loop > 0)
403 trans_len += tx_only;
404
405 if (trans_len > SPCOM_TRANLEN_MAX)
406 trans_len = SPCOM_TRANLEN_MAX;
407
408 /* Update device offset */
409 if (pos > 0) {
410 addr = fsl_espi_cmd2addr(local_buf);
411 addr += rx_pos;
412 fsl_espi_addr2cmd(addr, local_buf);
413 }
414
415 espi_trans->len = trans_len;
416 espi_trans->tx_buf = local_buf;
417 espi_trans->rx_buf = local_buf;
418 fsl_espi_do_trans(m, espi_trans);
419
420 /* If there is at least one RX byte then copy it to rx_buf */
421 if (tx_only < SPCOM_TRANLEN_MAX)
422 memcpy(rx_buf + rx_pos, espi_trans->rx_buf + tx_only,
423 trans_len - tx_only);
424
425 rx_pos += trans_len - tx_only;
426
427 if (loop > 0)
428 espi_trans->actual_length += espi_trans->len - tx_only;
429 else
430 espi_trans->actual_length += espi_trans->len;
431 }
432
433 kfree(local_buf);
434 }
435
436 static int fsl_espi_do_one_msg(struct spi_master *master,
437 struct spi_message *m)
438 {
439 struct spi_transfer *t;
440 u8 *rx_buf = NULL;
441 unsigned int n_tx = 0;
442 unsigned int n_rx = 0;
443 unsigned int xfer_len = 0;
444 struct fsl_espi_transfer espi_trans;
445
446 list_for_each_entry(t, &m->transfers, transfer_list) {
447 if (t->tx_buf)
448 n_tx += t->len;
449 if (t->rx_buf) {
450 n_rx += t->len;
451 rx_buf = t->rx_buf;
452 }
453 if ((t->tx_buf) || (t->rx_buf))
454 xfer_len += t->len;
455 }
456
457 espi_trans.n_tx = n_tx;
458 espi_trans.n_rx = n_rx;
459 espi_trans.len = xfer_len;
460 espi_trans.actual_length = 0;
461 espi_trans.status = 0;
462
463 if (!rx_buf)
464 fsl_espi_cmd_trans(m, &espi_trans, NULL);
465 else
466 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
467
468 m->actual_length = espi_trans.actual_length;
469 m->status = espi_trans.status;
470 spi_finalize_current_message(master);
471 return 0;
472 }
473
474 static int fsl_espi_setup(struct spi_device *spi)
475 {
476 struct mpc8xxx_spi *mpc8xxx_spi;
477 struct fsl_espi_reg *reg_base;
478 int retval;
479 u32 hw_mode;
480 u32 loop_mode;
481 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
482
483 if (!spi->max_speed_hz)
484 return -EINVAL;
485
486 if (!cs) {
487 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
488 if (!cs)
489 return -ENOMEM;
490 spi_set_ctldata(spi, cs);
491 }
492
493 mpc8xxx_spi = spi_master_get_devdata(spi->master);
494 reg_base = mpc8xxx_spi->reg_base;
495
496 pm_runtime_get_sync(mpc8xxx_spi->dev);
497
498 hw_mode = cs->hw_mode; /* Save original settings */
499 cs->hw_mode = mpc8xxx_spi_read_reg(
500 &reg_base->csmode[spi->chip_select]);
501 /* mask out bits we are going to set */
502 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
503 | CSMODE_REV);
504
505 if (spi->mode & SPI_CPHA)
506 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
507 if (spi->mode & SPI_CPOL)
508 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
509 if (!(spi->mode & SPI_LSB_FIRST))
510 cs->hw_mode |= CSMODE_REV;
511
512 /* Handle the loop mode */
513 loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
514 loop_mode &= ~SPMODE_LOOP;
515 if (spi->mode & SPI_LOOP)
516 loop_mode |= SPMODE_LOOP;
517 mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
518
519 retval = fsl_espi_setup_transfer(spi, NULL);
520
521 pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
522 pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
523
524 if (retval < 0) {
525 cs->hw_mode = hw_mode; /* Restore settings */
526 return retval;
527 }
528 return 0;
529 }
530
531 static void fsl_espi_cleanup(struct spi_device *spi)
532 {
533 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
534
535 kfree(cs);
536 spi_set_ctldata(spi, NULL);
537 }
538
539 void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
540 {
541 struct fsl_espi_reg *reg_base = mspi->reg_base;
542
543 /* We need handle RX first */
544 if (events & SPIE_NE) {
545 u32 rx_data, tmp;
546 u8 rx_data_8;
547 int rx_nr_bytes = 4;
548 int ret;
549
550 /* Spin until RX is done */
551 if (SPIE_RXCNT(events) < min(4, mspi->len)) {
552 ret = spin_event_timeout(
553 !(SPIE_RXCNT(events =
554 mpc8xxx_spi_read_reg(&reg_base->event)) <
555 min(4, mspi->len)),
556 10000, 0); /* 10 msec */
557 if (!ret)
558 dev_err(mspi->dev,
559 "tired waiting for SPIE_RXCNT\n");
560 }
561
562 if (mspi->len >= 4) {
563 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
564 } else if (mspi->len <= 0) {
565 dev_err(mspi->dev,
566 "unexpected RX(SPIE_NE) interrupt occurred,\n"
567 "(local rxlen %d bytes, reg rxlen %d bytes)\n",
568 min(4, mspi->len), SPIE_RXCNT(events));
569 rx_nr_bytes = 0;
570 } else {
571 rx_nr_bytes = mspi->len;
572 tmp = mspi->len;
573 rx_data = 0;
574 while (tmp--) {
575 rx_data_8 = in_8((u8 *)&reg_base->receive);
576 rx_data |= (rx_data_8 << (tmp * 8));
577 }
578
579 rx_data <<= (4 - mspi->len) * 8;
580 }
581
582 mspi->len -= rx_nr_bytes;
583
584 if (mspi->rx)
585 mspi->get_rx(rx_data, mspi);
586 }
587
588 if (!(events & SPIE_NF)) {
589 int ret;
590
591 /* spin until TX is done */
592 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
593 &reg_base->event)) & SPIE_NF), 1000, 0);
594 if (!ret) {
595 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
596
597 /* Clear the SPIE bits */
598 mpc8xxx_spi_write_reg(&reg_base->event, events);
599 complete(&mspi->done);
600 return;
601 }
602 }
603
604 /* Clear the events */
605 mpc8xxx_spi_write_reg(&reg_base->event, events);
606
607 mspi->count -= 1;
608 if (mspi->count) {
609 u32 word = mspi->get_tx(mspi);
610
611 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
612 } else {
613 complete(&mspi->done);
614 }
615 }
616
617 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
618 {
619 struct mpc8xxx_spi *mspi = context_data;
620 struct fsl_espi_reg *reg_base = mspi->reg_base;
621 irqreturn_t ret = IRQ_NONE;
622 u32 events;
623
624 /* Get interrupt events(tx/rx) */
625 events = mpc8xxx_spi_read_reg(&reg_base->event);
626 if (events)
627 ret = IRQ_HANDLED;
628
629 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
630
631 fsl_espi_cpu_irq(mspi, events);
632
633 return ret;
634 }
635
636 #ifdef CONFIG_PM
637 static int fsl_espi_runtime_suspend(struct device *dev)
638 {
639 struct spi_master *master = dev_get_drvdata(dev);
640 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
641 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
642 u32 regval;
643
644 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
645 regval &= ~SPMODE_ENABLE;
646 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
647
648 return 0;
649 }
650
651 static int fsl_espi_runtime_resume(struct device *dev)
652 {
653 struct spi_master *master = dev_get_drvdata(dev);
654 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
655 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
656 u32 regval;
657
658 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
659 regval |= SPMODE_ENABLE;
660 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
661
662 return 0;
663 }
664 #endif
665
666 static size_t fsl_espi_max_transfer_size(struct spi_device *spi)
667 {
668 return SPCOM_TRANLEN_MAX;
669 }
670
671 static struct spi_master * fsl_espi_probe(struct device *dev,
672 struct resource *mem, unsigned int irq)
673 {
674 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
675 struct spi_master *master;
676 struct mpc8xxx_spi *mpc8xxx_spi;
677 struct fsl_espi_reg *reg_base;
678 struct device_node *nc;
679 const __be32 *prop;
680 u32 regval, csmode;
681 int i, len, ret = 0;
682
683 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
684 if (!master) {
685 ret = -ENOMEM;
686 goto err;
687 }
688
689 dev_set_drvdata(dev, master);
690
691 mpc8xxx_spi_probe(dev, mem, irq);
692
693 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
694 master->setup = fsl_espi_setup;
695 master->cleanup = fsl_espi_cleanup;
696 master->transfer_one_message = fsl_espi_do_one_msg;
697 master->auto_runtime_pm = true;
698 master->max_transfer_size = fsl_espi_max_transfer_size;
699
700 mpc8xxx_spi = spi_master_get_devdata(master);
701
702 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
703 if (IS_ERR(mpc8xxx_spi->reg_base)) {
704 ret = PTR_ERR(mpc8xxx_spi->reg_base);
705 goto err_probe;
706 }
707
708 reg_base = mpc8xxx_spi->reg_base;
709
710 /* Register for SPI Interrupt */
711 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
712 0, "fsl_espi", mpc8xxx_spi);
713 if (ret)
714 goto err_probe;
715
716 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
717 mpc8xxx_spi->rx_shift = 16;
718 mpc8xxx_spi->tx_shift = 24;
719 }
720
721 /* SPI controller initializations */
722 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
723 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
724 mpc8xxx_spi_write_reg(&reg_base->command, 0);
725 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
726
727 /* Init eSPI CS mode register */
728 for_each_available_child_of_node(master->dev.of_node, nc) {
729 /* get chip select */
730 prop = of_get_property(nc, "reg", &len);
731 if (!prop || len < sizeof(*prop))
732 continue;
733 i = be32_to_cpup(prop);
734 if (i < 0 || i >= pdata->max_chipselect)
735 continue;
736
737 csmode = CSMODE_INIT_VAL;
738 /* check if CSBEF is set in device tree */
739 prop = of_get_property(nc, "fsl,csbef", &len);
740 if (prop && len >= sizeof(*prop)) {
741 csmode &= ~(CSMODE_BEF(0xf));
742 csmode |= CSMODE_BEF(be32_to_cpup(prop));
743 }
744 /* check if CSAFT is set in device tree */
745 prop = of_get_property(nc, "fsl,csaft", &len);
746 if (prop && len >= sizeof(*prop)) {
747 csmode &= ~(CSMODE_AFT(0xf));
748 csmode |= CSMODE_AFT(be32_to_cpup(prop));
749 }
750 mpc8xxx_spi_write_reg(&reg_base->csmode[i], csmode);
751
752 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
753 }
754
755 /* Enable SPI interface */
756 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
757
758 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
759
760 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
761 pm_runtime_use_autosuspend(dev);
762 pm_runtime_set_active(dev);
763 pm_runtime_enable(dev);
764 pm_runtime_get_sync(dev);
765
766 ret = devm_spi_register_master(dev, master);
767 if (ret < 0)
768 goto err_pm;
769
770 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
771
772 pm_runtime_mark_last_busy(dev);
773 pm_runtime_put_autosuspend(dev);
774
775 return master;
776
777 err_pm:
778 pm_runtime_put_noidle(dev);
779 pm_runtime_disable(dev);
780 pm_runtime_set_suspended(dev);
781 err_probe:
782 spi_master_put(master);
783 err:
784 return ERR_PTR(ret);
785 }
786
787 static int of_fsl_espi_get_chipselects(struct device *dev)
788 {
789 struct device_node *np = dev->of_node;
790 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
791 const u32 *prop;
792 int len;
793
794 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
795 if (!prop || len < sizeof(*prop)) {
796 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
797 return -EINVAL;
798 }
799
800 pdata->max_chipselect = *prop;
801 pdata->cs_control = NULL;
802
803 return 0;
804 }
805
806 static int of_fsl_espi_probe(struct platform_device *ofdev)
807 {
808 struct device *dev = &ofdev->dev;
809 struct device_node *np = ofdev->dev.of_node;
810 struct spi_master *master;
811 struct resource mem;
812 unsigned int irq;
813 int ret = -ENOMEM;
814
815 ret = of_mpc8xxx_spi_probe(ofdev);
816 if (ret)
817 return ret;
818
819 ret = of_fsl_espi_get_chipselects(dev);
820 if (ret)
821 goto err;
822
823 ret = of_address_to_resource(np, 0, &mem);
824 if (ret)
825 goto err;
826
827 irq = irq_of_parse_and_map(np, 0);
828 if (!irq) {
829 ret = -EINVAL;
830 goto err;
831 }
832
833 master = fsl_espi_probe(dev, &mem, irq);
834 if (IS_ERR(master)) {
835 ret = PTR_ERR(master);
836 goto err;
837 }
838
839 return 0;
840
841 err:
842 return ret;
843 }
844
845 static int of_fsl_espi_remove(struct platform_device *dev)
846 {
847 pm_runtime_disable(&dev->dev);
848
849 return 0;
850 }
851
852 #ifdef CONFIG_PM_SLEEP
853 static int of_fsl_espi_suspend(struct device *dev)
854 {
855 struct spi_master *master = dev_get_drvdata(dev);
856 int ret;
857
858 ret = spi_master_suspend(master);
859 if (ret) {
860 dev_warn(dev, "cannot suspend master\n");
861 return ret;
862 }
863
864 ret = pm_runtime_force_suspend(dev);
865 if (ret < 0)
866 return ret;
867
868 return 0;
869 }
870
871 static int of_fsl_espi_resume(struct device *dev)
872 {
873 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
874 struct spi_master *master = dev_get_drvdata(dev);
875 struct mpc8xxx_spi *mpc8xxx_spi;
876 struct fsl_espi_reg *reg_base;
877 u32 regval;
878 int i, ret;
879
880 mpc8xxx_spi = spi_master_get_devdata(master);
881 reg_base = mpc8xxx_spi->reg_base;
882
883 /* SPI controller initializations */
884 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
885 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
886 mpc8xxx_spi_write_reg(&reg_base->command, 0);
887 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
888
889 /* Init eSPI CS mode register */
890 for (i = 0; i < pdata->max_chipselect; i++)
891 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
892
893 /* Enable SPI interface */
894 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
895
896 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
897
898 ret = pm_runtime_force_resume(dev);
899 if (ret < 0)
900 return ret;
901
902 return spi_master_resume(master);
903 }
904 #endif /* CONFIG_PM_SLEEP */
905
906 static const struct dev_pm_ops espi_pm = {
907 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
908 fsl_espi_runtime_resume, NULL)
909 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
910 };
911
912 static const struct of_device_id of_fsl_espi_match[] = {
913 { .compatible = "fsl,mpc8536-espi" },
914 {}
915 };
916 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
917
918 static struct platform_driver fsl_espi_driver = {
919 .driver = {
920 .name = "fsl_espi",
921 .of_match_table = of_fsl_espi_match,
922 .pm = &espi_pm,
923 },
924 .probe = of_fsl_espi_probe,
925 .remove = of_fsl_espi_remove,
926 };
927 module_platform_driver(fsl_espi_driver);
928
929 MODULE_AUTHOR("Mingkai Hu");
930 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
931 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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