drivers/spi/spi-fsl-espi.c

   1 /*
   2  * Freescale eSPI controller driver.
   3  *
   4  * Copyright 2010 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/fsl_devices.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/module.h>
  16 #include <linux/mm.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/pm_runtime.h>
  24 #include <sysdev/fsl_soc.h>
  25
  26 #include "spi-fsl-lib.h"
  27
  28 /* eSPI Controller registers */
  29 struct fsl_espi_reg {
  30         __be32 mode;            /* 0x000 - eSPI mode register */
  31         __be32 event;           /* 0x004 - eSPI event register */
  32         __be32 mask;            /* 0x008 - eSPI mask register */
  33         __be32 command;         /* 0x00c - eSPI command register */
  34         __be32 transmit;        /* 0x010 - eSPI transmit FIFO access register*/
  35         __be32 receive;         /* 0x014 - eSPI receive FIFO access register*/
  36         u8 res[8];              /* 0x018 - 0x01c reserved */
  37         __be32 csmode[4];       /* 0x020 - 0x02c eSPI cs mode register */
  38 };
  39
  40 /* eSPI Controller mode register definitions */
  41 #define SPMODE_ENABLE           (1 << 31)
  42 #define SPMODE_LOOP             (1 << 30)
  43 #define SPMODE_TXTHR(x)         ((x) << 8)
  44 #define SPMODE_RXTHR(x)         ((x) << 0)
  45
  46 /* eSPI Controller CS mode register definitions */
  47 #define CSMODE_CI_INACTIVEHIGH  (1 << 31)
  48 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
  49 #define CSMODE_REV              (1 << 29)
  50 #define CSMODE_DIV16            (1 << 28)
  51 #define CSMODE_PM(x)            ((x) << 24)
  52 #define CSMODE_POL_1            (1 << 20)
  53 #define CSMODE_LEN(x)           ((x) << 16)
  54 #define CSMODE_BEF(x)           ((x) << 12)
  55 #define CSMODE_AFT(x)           ((x) << 8)
  56 #define CSMODE_CG(x)            ((x) << 3)
  57
  58 /* Default mode/csmode for eSPI controller */
  59 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
  60 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
  61                 | CSMODE_AFT(0) | CSMODE_CG(1))
  62
  63 /* SPIE register values */
  64 #define SPIE_NE         0x00000200      /* Not empty */
  65 #define SPIE_NF         0x00000100      /* Not full */
  66
  67 /* SPIM register values */
  68 #define SPIM_NE         0x00000200      /* Not empty */
  69 #define SPIM_NF         0x00000100      /* Not full */
  70 #define SPIE_RXCNT(reg)     ((reg >> 24) & 0x3F)
  71 #define SPIE_TXCNT(reg)     ((reg >> 16) & 0x3F)
  72
  73 /* SPCOM register values */
  74 #define SPCOM_CS(x)             ((x) << 30)
  75 #define SPCOM_TRANLEN(x)        ((x) << 0)
  76 #define SPCOM_TRANLEN_MAX       0x10000 /* Max transaction length */
  77
  78 #define AUTOSUSPEND_TIMEOUT 2000
  79
  80 static void fsl_espi_copy_to_buf(struct spi_message *m,
  81                                  struct mpc8xxx_spi *mspi)
  82 {
  83         struct spi_transfer *t;
  84         u8 *buf = mspi->local_buf;
  85
  86         list_for_each_entry(t, &m->transfers, transfer_list) {
  87                 if (t->tx_buf)
  88                         memcpy(buf, t->tx_buf, t->len);
  89                 else
  90                         memset(buf, 0, t->len);
  91                 buf += t->len;
  92         }
  93 }
  94
  95 static void fsl_espi_copy_from_buf(struct spi_message *m,
  96                                    struct mpc8xxx_spi *mspi)
  97 {
  98         struct spi_transfer *t;
  99         u8 *buf = mspi->local_buf;
 100
 101         list_for_each_entry(t, &m->transfers, transfer_list) {
 102                 if (t->rx_buf)
 103                         memcpy(t->rx_buf, buf, t->len);
 104                 buf += t->len;
 105         }
 106 }
 107
 108 static int fsl_espi_check_message(struct spi_message *m)
 109 {
 110         struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
 111         struct spi_transfer *t, *first;
 112
 113         if (m->frame_length > SPCOM_TRANLEN_MAX) {
 114                 dev_err(mspi->dev, "message too long, size is %u bytes\n",
 115                         m->frame_length);
 116                 return -EMSGSIZE;
 117         }
 118
 119         first = list_first_entry(&m->transfers, struct spi_transfer,
 120                                  transfer_list);
 121         list_for_each_entry(t, &m->transfers, transfer_list) {
 122                 if (first->bits_per_word != t->bits_per_word ||
 123                     first->speed_hz != t->speed_hz) {
 124                         dev_err(mspi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
 125                         return -EINVAL;
 126                 }
 127         }
 128
 129         return 0;
 130 }
 131
 132 static void fsl_espi_change_mode(struct spi_device *spi)
 133 {
 134         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
 135         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 136         struct fsl_espi_reg *reg_base = mspi->reg_base;
 137         __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
 138         __be32 __iomem *espi_mode = &reg_base->mode;
 139         u32 tmp;
 140         unsigned long flags;
 141
 142         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 143         local_irq_save(flags);
 144
 145         /* Turn off SPI unit prior changing mode */
 146         tmp = mpc8xxx_spi_read_reg(espi_mode);
 147         mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
 148         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 149         mpc8xxx_spi_write_reg(espi_mode, tmp);
 150
 151         local_irq_restore(flags);
 152 }
 153
 154 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
 155 {
 156         u32 data;
 157         u16 data_h;
 158         u16 data_l;
 159         const u32 *tx = mpc8xxx_spi->tx;
 160
 161         if (!tx)
 162                 return 0;
 163
 164         data = *tx++ << mpc8xxx_spi->tx_shift;
 165         data_l = data & 0xffff;
 166         data_h = (data >> 16) & 0xffff;
 167         swab16s(&data_l);
 168         swab16s(&data_h);
 169         data = data_h | data_l;
 170
 171         mpc8xxx_spi->tx = tx;
 172         return data;
 173 }
 174
 175 static void fsl_espi_setup_transfer(struct spi_device *spi,
 176                                         struct spi_transfer *t)
 177 {
 178         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 179         int bits_per_word = 0;
 180         u8 pm;
 181         u32 hz = 0;
 182         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 183
 184         if (t) {
 185                 bits_per_word = t->bits_per_word;
 186                 hz = t->speed_hz;
 187         }
 188
 189         /* spi_transfer level calls that work per-word */
 190         if (!bits_per_word)
 191                 bits_per_word = spi->bits_per_word;
 192
 193         if (!hz)
 194                 hz = spi->max_speed_hz;
 195
 196         cs->rx_shift = 0;
 197         cs->tx_shift = 0;
 198         cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 199         cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 200         if (bits_per_word <= 8) {
 201                 cs->rx_shift = 8 - bits_per_word;
 202         } else {
 203                 cs->rx_shift = 16 - bits_per_word;
 204                 if (spi->mode & SPI_LSB_FIRST)
 205                         cs->get_tx = fsl_espi_tx_buf_lsb;
 206         }
 207
 208         mpc8xxx_spi->rx_shift = cs->rx_shift;
 209         mpc8xxx_spi->tx_shift = cs->tx_shift;
 210         mpc8xxx_spi->get_rx = cs->get_rx;
 211         mpc8xxx_spi->get_tx = cs->get_tx;
 212
 213         /* mask out bits we are going to set */
 214         cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
 215
 216         cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
 217
 218         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 219                 cs->hw_mode |= CSMODE_DIV16;
 220                 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
 221
 222                 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
 223                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 224                                 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
 225                 if (pm > 33)
 226                         pm = 33;
 227         } else {
 228                 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
 229         }
 230         if (pm)
 231                 pm--;
 232         if (pm < 2)
 233                 pm = 2;
 234
 235         cs->hw_mode |= CSMODE_PM(pm);
 236
 237         fsl_espi_change_mode(spi);
 238 }
 239
 240 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
 241 {
 242         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 243         struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
 244         u32 word;
 245         int ret;
 246
 247         mpc8xxx_spi->len = t->len;
 248         mpc8xxx_spi->count = roundup(t->len, 4) / 4;
 249
 250         mpc8xxx_spi->tx = t->tx_buf;
 251         mpc8xxx_spi->rx = t->rx_buf;
 252
 253         reinit_completion(&mpc8xxx_spi->done);
 254
 255         /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
 256         mpc8xxx_spi_write_reg(&reg_base->command,
 257                 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
 258
 259         /* enable rx ints */
 260         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 261
 262         /* transmit word */
 263         word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
 264         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 265
 266         /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
 267         ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ);
 268         if (ret == 0)
 269                 dev_err(mpc8xxx_spi->dev,
 270                         "Transaction hanging up (left %d bytes)\n",
 271                         mpc8xxx_spi->count);
 272
 273         /* disable rx ints */
 274         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 275
 276         return mpc8xxx_spi->count > 0 ? -EMSGSIZE : 0;
 277 }
 278
 279 static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
 280 {
 281         struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
 282         struct spi_device *spi = m->spi;
 283         int ret;
 284
 285         fsl_espi_copy_to_buf(m, mspi);
 286         fsl_espi_setup_transfer(spi, trans);
 287
 288         ret = fsl_espi_bufs(spi, trans);
 289
 290         if (trans->delay_usecs)
 291                 udelay(trans->delay_usecs);
 292
 293         fsl_espi_setup_transfer(spi, NULL);
 294
 295         if (!ret)
 296                 fsl_espi_copy_from_buf(m, mspi);
 297
 298         return ret;
 299 }
 300
 301 static int fsl_espi_do_one_msg(struct spi_master *master,
 302                                struct spi_message *m)
 303 {
 304         struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
 305         unsigned int delay_usecs = 0;
 306         struct spi_transfer *t, trans = {};
 307         int ret;
 308
 309         ret = fsl_espi_check_message(m);
 310         if (ret)
 311                 goto out;
 312
 313         list_for_each_entry(t, &m->transfers, transfer_list) {
 314                 if (t->delay_usecs > delay_usecs)
 315                         delay_usecs = t->delay_usecs;
 316         }
 317
 318         t = list_first_entry(&m->transfers, struct spi_transfer,
 319                              transfer_list);
 320
 321         trans.len = m->frame_length;
 322         trans.speed_hz = t->speed_hz;
 323         trans.bits_per_word = t->bits_per_word;
 324         trans.delay_usecs = delay_usecs;
 325         trans.tx_buf = mspi->local_buf;
 326         trans.rx_buf = mspi->local_buf;
 327
 328         if (trans.len)
 329                 ret = fsl_espi_trans(m, &trans);
 330
 331         m->actual_length = ret ? 0 : trans.len;
 332 out:
 333         if (m->status == -EINPROGRESS)
 334                 m->status = ret;
 335
 336         spi_finalize_current_message(master);
 337
 338         return ret;
 339 }
 340
 341 static int fsl_espi_setup(struct spi_device *spi)
 342 {
 343         struct mpc8xxx_spi *mpc8xxx_spi;
 344         struct fsl_espi_reg *reg_base;
 345         u32 hw_mode;
 346         u32 loop_mode;
 347         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 348
 349         if (!spi->max_speed_hz)
 350                 return -EINVAL;
 351
 352         if (!cs) {
 353                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 354                 if (!cs)
 355                         return -ENOMEM;
 356                 spi_set_ctldata(spi, cs);
 357         }
 358
 359         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 360         reg_base = mpc8xxx_spi->reg_base;
 361
 362         pm_runtime_get_sync(mpc8xxx_spi->dev);
 363
 364         hw_mode = cs->hw_mode; /* Save original settings */
 365         cs->hw_mode = mpc8xxx_spi_read_reg(
 366                         &reg_base->csmode[spi->chip_select]);
 367         /* mask out bits we are going to set */
 368         cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
 369                          | CSMODE_REV);
 370
 371         if (spi->mode & SPI_CPHA)
 372                 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
 373         if (spi->mode & SPI_CPOL)
 374                 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
 375         if (!(spi->mode & SPI_LSB_FIRST))
 376                 cs->hw_mode |= CSMODE_REV;
 377
 378         /* Handle the loop mode */
 379         loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 380         loop_mode &= ~SPMODE_LOOP;
 381         if (spi->mode & SPI_LOOP)
 382                 loop_mode |= SPMODE_LOOP;
 383         mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
 384
 385         fsl_espi_setup_transfer(spi, NULL);
 386
 387         pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
 388         pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
 389
 390         return 0;
 391 }
 392
 393 static void fsl_espi_cleanup(struct spi_device *spi)
 394 {
 395         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 396
 397         kfree(cs);
 398         spi_set_ctldata(spi, NULL);
 399 }
 400
 401 static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 402 {
 403         struct fsl_espi_reg *reg_base = mspi->reg_base;
 404
 405         /* We need handle RX first */
 406         if (events & SPIE_NE) {
 407                 u32 rx_data, tmp;
 408                 u8 rx_data_8;
 409                 int rx_nr_bytes = 4;
 410                 int ret;
 411
 412                 /* Spin until RX is done */
 413                 if (SPIE_RXCNT(events) < min(4, mspi->len)) {
 414                         ret = spin_event_timeout(
 415                                 !(SPIE_RXCNT(events =
 416                                 mpc8xxx_spi_read_reg(&reg_base->event)) <
 417                                                 min(4, mspi->len)),
 418                                                 10000, 0); /* 10 msec */
 419                         if (!ret)
 420                                 dev_err(mspi->dev,
 421                                          "tired waiting for SPIE_RXCNT\n");
 422                 }
 423
 424                 if (mspi->len >= 4) {
 425                         rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 426                 } else if (mspi->len <= 0) {
 427                         dev_err(mspi->dev,
 428                                 "unexpected RX(SPIE_NE) interrupt occurred,\n"
 429                                 "(local rxlen %d bytes, reg rxlen %d bytes)\n",
 430                                 min(4, mspi->len), SPIE_RXCNT(events));
 431                         rx_nr_bytes = 0;
 432                 } else {
 433                         rx_nr_bytes = mspi->len;
 434                         tmp = mspi->len;
 435                         rx_data = 0;
 436                         while (tmp--) {
 437                                 rx_data_8 = in_8((u8 *)&reg_base->receive);
 438                                 rx_data |= (rx_data_8 << (tmp * 8));
 439                         }
 440
 441                         rx_data <<= (4 - mspi->len) * 8;
 442                 }
 443
 444                 mspi->len -= rx_nr_bytes;
 445
 446                 if (mspi->rx)
 447                         mspi->get_rx(rx_data, mspi);
 448         }
 449
 450         if (!(events & SPIE_NF)) {
 451                 int ret;
 452
 453                 /* spin until TX is done */
 454                 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
 455                                 &reg_base->event)) & SPIE_NF), 1000, 0);
 456                 if (!ret) {
 457                         dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
 458
 459                         /* Clear the SPIE bits */
 460                         mpc8xxx_spi_write_reg(&reg_base->event, events);
 461                         complete(&mspi->done);
 462                         return;
 463                 }
 464         }
 465
 466         /* Clear the events */
 467         mpc8xxx_spi_write_reg(&reg_base->event, events);
 468
 469         mspi->count -= 1;
 470         if (mspi->count) {
 471                 u32 word = mspi->get_tx(mspi);
 472
 473                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 474         } else {
 475                 complete(&mspi->done);
 476         }
 477 }
 478
 479 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
 480 {
 481         struct mpc8xxx_spi *mspi = context_data;
 482         struct fsl_espi_reg *reg_base = mspi->reg_base;
 483         irqreturn_t ret = IRQ_NONE;
 484         u32 events;
 485
 486         /* Get interrupt events(tx/rx) */
 487         events = mpc8xxx_spi_read_reg(&reg_base->event);
 488         if (events)
 489                 ret = IRQ_HANDLED;
 490
 491         dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
 492
 493         fsl_espi_cpu_irq(mspi, events);
 494
 495         return ret;
 496 }
 497
 498 #ifdef CONFIG_PM
 499 static int fsl_espi_runtime_suspend(struct device *dev)
 500 {
 501         struct spi_master *master = dev_get_drvdata(dev);
 502         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 503         struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
 504         u32 regval;
 505
 506         regval = mpc8xxx_spi_read_reg(&reg_base->mode);
 507         regval &= ~SPMODE_ENABLE;
 508         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 509
 510         return 0;
 511 }
 512
 513 static int fsl_espi_runtime_resume(struct device *dev)
 514 {
 515         struct spi_master *master = dev_get_drvdata(dev);
 516         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 517         struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
 518         u32 regval;
 519
 520         regval = mpc8xxx_spi_read_reg(&reg_base->mode);
 521         regval |= SPMODE_ENABLE;
 522         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 523
 524         return 0;
 525 }
 526 #endif
 527
 528 static size_t fsl_espi_max_message_size(struct spi_device *spi)
 529 {
 530         return SPCOM_TRANLEN_MAX;
 531 }
 532
 533 static struct spi_master * fsl_espi_probe(struct device *dev,
 534                 struct resource *mem, unsigned int irq)
 535 {
 536         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 537         struct spi_master *master;
 538         struct mpc8xxx_spi *mpc8xxx_spi;
 539         struct fsl_espi_reg *reg_base;
 540         struct device_node *nc;
 541         const __be32 *prop;
 542         u32 regval, csmode;
 543         int i, len, ret = 0;
 544
 545         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 546         if (!master) {
 547                 ret = -ENOMEM;
 548                 goto err;
 549         }
 550
 551         dev_set_drvdata(dev, master);
 552
 553         mpc8xxx_spi_probe(dev, mem, irq);
 554
 555         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
 556         master->setup = fsl_espi_setup;
 557         master->cleanup = fsl_espi_cleanup;
 558         master->transfer_one_message = fsl_espi_do_one_msg;
 559         master->auto_runtime_pm = true;
 560         master->max_message_size = fsl_espi_max_message_size;
 561
 562         mpc8xxx_spi = spi_master_get_devdata(master);
 563
 564         mpc8xxx_spi->local_buf =
 565                 devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL);
 566         if (!mpc8xxx_spi->local_buf) {
 567                 ret = -ENOMEM;
 568                 goto err_probe;
 569         }
 570
 571         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 572         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 573                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 574                 goto err_probe;
 575         }
 576
 577         reg_base = mpc8xxx_spi->reg_base;
 578
 579         /* Register for SPI Interrupt */
 580         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
 581                           0, "fsl_espi", mpc8xxx_spi);
 582         if (ret)
 583                 goto err_probe;
 584
 585         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
 586                 mpc8xxx_spi->rx_shift = 16;
 587                 mpc8xxx_spi->tx_shift = 24;
 588         }
 589
 590         /* SPI controller initializations */
 591         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 592         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 593         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 594         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 595
 596         /* Init eSPI CS mode register */
 597         for_each_available_child_of_node(master->dev.of_node, nc) {
 598                 /* get chip select */
 599                 prop = of_get_property(nc, "reg", &len);
 600                 if (!prop || len < sizeof(*prop))
 601                         continue;
 602                 i = be32_to_cpup(prop);
 603                 if (i < 0 || i >= pdata->max_chipselect)
 604                         continue;
 605
 606                 csmode = CSMODE_INIT_VAL;
 607                 /* check if CSBEF is set in device tree */
 608                 prop = of_get_property(nc, "fsl,csbef", &len);
 609                 if (prop && len >= sizeof(*prop)) {
 610                         csmode &= ~(CSMODE_BEF(0xf));
 611                         csmode |= CSMODE_BEF(be32_to_cpup(prop));
 612                 }
 613                 /* check if CSAFT is set in device tree */
 614                 prop = of_get_property(nc, "fsl,csaft", &len);
 615                 if (prop && len >= sizeof(*prop)) {
 616                         csmode &= ~(CSMODE_AFT(0xf));
 617                         csmode |= CSMODE_AFT(be32_to_cpup(prop));
 618                 }
 619                 mpc8xxx_spi_write_reg(&reg_base->csmode[i], csmode);
 620
 621                 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
 622         }
 623
 624         /* Enable SPI interface */
 625         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 626
 627         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 628
 629         pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
 630         pm_runtime_use_autosuspend(dev);
 631         pm_runtime_set_active(dev);
 632         pm_runtime_enable(dev);
 633         pm_runtime_get_sync(dev);
 634
 635         ret = devm_spi_register_master(dev, master);
 636         if (ret < 0)
 637                 goto err_pm;
 638
 639         dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
 640
 641         pm_runtime_mark_last_busy(dev);
 642         pm_runtime_put_autosuspend(dev);
 643
 644         return master;
 645
 646 err_pm:
 647         pm_runtime_put_noidle(dev);
 648         pm_runtime_disable(dev);
 649         pm_runtime_set_suspended(dev);
 650 err_probe:
 651         spi_master_put(master);
 652 err:
 653         return ERR_PTR(ret);
 654 }
 655
 656 static int of_fsl_espi_get_chipselects(struct device *dev)
 657 {
 658         struct device_node *np = dev->of_node;
 659         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 660         const u32 *prop;
 661         int len;
 662
 663         prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
 664         if (!prop || len < sizeof(*prop)) {
 665                 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
 666                 return -EINVAL;
 667         }
 668
 669         pdata->max_chipselect = *prop;
 670         pdata->cs_control = NULL;
 671
 672         return 0;
 673 }
 674
 675 static int of_fsl_espi_probe(struct platform_device *ofdev)
 676 {
 677         struct device *dev = &ofdev->dev;
 678         struct device_node *np = ofdev->dev.of_node;
 679         struct spi_master *master;
 680         struct resource mem;
 681         unsigned int irq;
 682         int ret = -ENOMEM;
 683
 684         ret = of_mpc8xxx_spi_probe(ofdev);
 685         if (ret)
 686                 return ret;
 687
 688         ret = of_fsl_espi_get_chipselects(dev);
 689         if (ret)
 690                 goto err;
 691
 692         ret = of_address_to_resource(np, 0, &mem);
 693         if (ret)
 694                 goto err;
 695
 696         irq = irq_of_parse_and_map(np, 0);
 697         if (!irq) {
 698                 ret = -EINVAL;
 699                 goto err;
 700         }
 701
 702         master = fsl_espi_probe(dev, &mem, irq);
 703         if (IS_ERR(master)) {
 704                 ret = PTR_ERR(master);
 705                 goto err;
 706         }
 707
 708         return 0;
 709
 710 err:
 711         return ret;
 712 }
 713
 714 static int of_fsl_espi_remove(struct platform_device *dev)
 715 {
 716         pm_runtime_disable(&dev->dev);
 717
 718         return 0;
 719 }
 720
 721 #ifdef CONFIG_PM_SLEEP
 722 static int of_fsl_espi_suspend(struct device *dev)
 723 {
 724         struct spi_master *master = dev_get_drvdata(dev);
 725         int ret;
 726
 727         ret = spi_master_suspend(master);
 728         if (ret) {
 729                 dev_warn(dev, "cannot suspend master\n");
 730                 return ret;
 731         }
 732
 733         ret = pm_runtime_force_suspend(dev);
 734         if (ret < 0)
 735                 return ret;
 736
 737         return 0;
 738 }
 739
 740 static int of_fsl_espi_resume(struct device *dev)
 741 {
 742         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 743         struct spi_master *master = dev_get_drvdata(dev);
 744         struct mpc8xxx_spi *mpc8xxx_spi;
 745         struct fsl_espi_reg *reg_base;
 746         u32 regval;
 747         int i, ret;
 748
 749         mpc8xxx_spi = spi_master_get_devdata(master);
 750         reg_base = mpc8xxx_spi->reg_base;
 751
 752         /* SPI controller initializations */
 753         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 754         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 755         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 756         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 757
 758         /* Init eSPI CS mode register */
 759         for (i = 0; i < pdata->max_chipselect; i++)
 760                 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
 761
 762         /* Enable SPI interface */
 763         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 764
 765         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 766
 767         ret = pm_runtime_force_resume(dev);
 768         if (ret < 0)
 769                 return ret;
 770
 771         return spi_master_resume(master);
 772 }
 773 #endif /* CONFIG_PM_SLEEP */
 774
 775 static const struct dev_pm_ops espi_pm = {
 776         SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
 777                            fsl_espi_runtime_resume, NULL)
 778         SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
 779 };
 780
 781 static const struct of_device_id of_fsl_espi_match[] = {
 782         { .compatible = "fsl,mpc8536-espi" },
 783         {}
 784 };
 785 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
 786
 787 static struct platform_driver fsl_espi_driver = {
 788         .driver = {
 789                 .name = "fsl_espi",
 790                 .of_match_table = of_fsl_espi_match,
 791                 .pm = &espi_pm,
 792         },
 793         .probe          = of_fsl_espi_probe,
 794         .remove         = of_fsl_espi_remove,
 795 };
 796 module_platform_driver(fsl_espi_driver);
 797
 798 MODULE_AUTHOR("Mingkai Hu");
 799 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
 800 MODULE_LICENSE("GPL");