4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/omap-dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
32 #include <linux/of_device.h>
33 #include <linux/pinctrl/consumer.h>
35 #include <linux/spi/spi.h>
42 struct completion transfer_complete
;
44 /* list synchronization */
45 struct mutex list_lock
;
47 struct spi_master
*master
;
49 void __iomem
*ctrl_base
;
50 void __iomem
*mmap_base
;
54 struct ti_qspi_regs ctx_reg
;
56 u32 spi_max_frequency
;
63 #define QSPI_PID (0x0)
64 #define QSPI_SYSCONFIG (0x10)
65 #define QSPI_INTR_STATUS_RAW_SET (0x20)
66 #define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
67 #define QSPI_INTR_ENABLE_SET_REG (0x28)
68 #define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
69 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
70 #define QSPI_SPI_DC_REG (0x44)
71 #define QSPI_SPI_CMD_REG (0x48)
72 #define QSPI_SPI_STATUS_REG (0x4c)
73 #define QSPI_SPI_DATA_REG (0x50)
74 #define QSPI_SPI_SETUP0_REG (0x54)
75 #define QSPI_SPI_SWITCH_REG (0x64)
76 #define QSPI_SPI_SETUP1_REG (0x58)
77 #define QSPI_SPI_SETUP2_REG (0x5c)
78 #define QSPI_SPI_SETUP3_REG (0x60)
79 #define QSPI_SPI_DATA_REG_1 (0x68)
80 #define QSPI_SPI_DATA_REG_2 (0x6c)
81 #define QSPI_SPI_DATA_REG_3 (0x70)
83 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
85 #define QSPI_FCLK 192000000
88 #define QSPI_CLK_EN (1 << 31)
89 #define QSPI_CLK_DIV_MAX 0xffff
92 #define QSPI_EN_CS(n) (n << 28)
93 #define QSPI_WLEN(n) ((n - 1) << 19)
94 #define QSPI_3_PIN (1 << 18)
95 #define QSPI_RD_SNGL (1 << 16)
96 #define QSPI_WR_SNGL (2 << 16)
97 #define QSPI_RD_DUAL (3 << 16)
98 #define QSPI_RD_QUAD (7 << 16)
99 #define QSPI_INVAL (4 << 16)
100 #define QSPI_WC_CMD_INT_EN (1 << 14)
101 #define QSPI_FLEN(n) ((n - 1) << 0)
102 #define QSPI_WLEN_MAX_BITS 128
103 #define QSPI_WLEN_MAX_BYTES 16
105 /* STATUS REGISTER */
109 /* INTERRUPT REGISTER */
110 #define QSPI_WC_INT_EN (1 << 1)
111 #define QSPI_WC_INT_DISABLE (1 << 1)
114 #define QSPI_DD(m, n) (m << (3 + n * 8))
115 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
116 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
117 #define QSPI_CKPOL(n) (1 << (n * 8))
119 #define QSPI_FRAME 4096
121 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
123 static inline unsigned long ti_qspi_read(struct ti_qspi
*qspi
,
126 return readl(qspi
->base
+ reg
);
129 static inline void ti_qspi_write(struct ti_qspi
*qspi
,
130 unsigned long val
, unsigned long reg
)
132 writel(val
, qspi
->base
+ reg
);
135 static int ti_qspi_setup(struct spi_device
*spi
)
137 struct ti_qspi
*qspi
= spi_master_get_devdata(spi
->master
);
138 struct ti_qspi_regs
*ctx_reg
= &qspi
->ctx_reg
;
139 int clk_div
= 0, ret
;
140 u32 clk_ctrl_reg
, clk_rate
, clk_mask
;
142 if (spi
->master
->busy
) {
143 dev_dbg(qspi
->dev
, "master busy doing other trasnfers\n");
147 if (!qspi
->spi_max_frequency
) {
148 dev_err(qspi
->dev
, "spi max frequency not defined\n");
152 clk_rate
= clk_get_rate(qspi
->fclk
);
154 clk_div
= DIV_ROUND_UP(clk_rate
, qspi
->spi_max_frequency
) - 1;
157 dev_dbg(qspi
->dev
, "clock divider < 0, using /1 divider\n");
161 if (clk_div
> QSPI_CLK_DIV_MAX
) {
162 dev_dbg(qspi
->dev
, "clock divider >%d , using /%d divider\n",
163 QSPI_CLK_DIV_MAX
, QSPI_CLK_DIV_MAX
+ 1);
167 dev_dbg(qspi
->dev
, "hz: %d, clock divider %d\n",
168 qspi
->spi_max_frequency
, clk_div
);
170 ret
= pm_runtime_get_sync(qspi
->dev
);
172 dev_err(qspi
->dev
, "pm_runtime_get_sync() failed\n");
176 clk_ctrl_reg
= ti_qspi_read(qspi
, QSPI_SPI_CLOCK_CNTRL_REG
);
178 clk_ctrl_reg
&= ~QSPI_CLK_EN
;
181 ti_qspi_write(qspi
, clk_ctrl_reg
, QSPI_SPI_CLOCK_CNTRL_REG
);
184 clk_mask
= QSPI_CLK_EN
| clk_div
;
185 ti_qspi_write(qspi
, clk_mask
, QSPI_SPI_CLOCK_CNTRL_REG
);
186 ctx_reg
->clkctrl
= clk_mask
;
188 pm_runtime_mark_last_busy(qspi
->dev
);
189 ret
= pm_runtime_put_autosuspend(qspi
->dev
);
191 dev_err(qspi
->dev
, "pm_runtime_put_autosuspend() failed\n");
198 static void ti_qspi_restore_ctx(struct ti_qspi
*qspi
)
200 struct ti_qspi_regs
*ctx_reg
= &qspi
->ctx_reg
;
202 ti_qspi_write(qspi
, ctx_reg
->clkctrl
, QSPI_SPI_CLOCK_CNTRL_REG
);
205 static inline u32
qspi_is_busy(struct ti_qspi
*qspi
)
208 unsigned long timeout
= jiffies
+ QSPI_COMPLETION_TIMEOUT
;
210 stat
= ti_qspi_read(qspi
, QSPI_SPI_STATUS_REG
);
211 while ((stat
& BUSY
) && time_after(timeout
, jiffies
)) {
213 stat
= ti_qspi_read(qspi
, QSPI_SPI_STATUS_REG
);
216 WARN(stat
& BUSY
, "qspi busy\n");
220 static int qspi_write_msg(struct ti_qspi
*qspi
, struct spi_transfer
*t
)
222 int wlen
, count
, xfer_len
;
228 cmd
= qspi
->cmd
| QSPI_WR_SNGL
;
230 wlen
= t
->bits_per_word
>> 3; /* in bytes */
234 if (qspi_is_busy(qspi
))
239 dev_dbg(qspi
->dev
, "tx cmd %08x dc %08x data %02x\n",
240 cmd
, qspi
->dc
, *txbuf
);
241 if (count
>= QSPI_WLEN_MAX_BYTES
) {
242 u32
*txp
= (u32
*)txbuf
;
244 data
= cpu_to_be32(*txp
++);
245 writel(data
, qspi
->base
+
246 QSPI_SPI_DATA_REG_3
);
247 data
= cpu_to_be32(*txp
++);
248 writel(data
, qspi
->base
+
249 QSPI_SPI_DATA_REG_2
);
250 data
= cpu_to_be32(*txp
++);
251 writel(data
, qspi
->base
+
252 QSPI_SPI_DATA_REG_1
);
253 data
= cpu_to_be32(*txp
++);
254 writel(data
, qspi
->base
+
256 xfer_len
= QSPI_WLEN_MAX_BYTES
;
257 cmd
|= QSPI_WLEN(QSPI_WLEN_MAX_BITS
);
259 writeb(*txbuf
, qspi
->base
+ QSPI_SPI_DATA_REG
);
260 cmd
= qspi
->cmd
| QSPI_WR_SNGL
;
262 cmd
|= QSPI_WLEN(wlen
);
266 dev_dbg(qspi
->dev
, "tx cmd %08x dc %08x data %04x\n",
267 cmd
, qspi
->dc
, *txbuf
);
268 writew(*((u16
*)txbuf
), qspi
->base
+ QSPI_SPI_DATA_REG
);
271 dev_dbg(qspi
->dev
, "tx cmd %08x dc %08x data %08x\n",
272 cmd
, qspi
->dc
, *txbuf
);
273 writel(*((u32
*)txbuf
), qspi
->base
+ QSPI_SPI_DATA_REG
);
277 ti_qspi_write(qspi
, cmd
, QSPI_SPI_CMD_REG
);
278 if (!wait_for_completion_timeout(&qspi
->transfer_complete
,
279 QSPI_COMPLETION_TIMEOUT
)) {
280 dev_err(qspi
->dev
, "write timed out\n");
290 static int qspi_read_msg(struct ti_qspi
*qspi
, struct spi_transfer
*t
)
298 switch (t
->rx_nbits
) {
310 wlen
= t
->bits_per_word
>> 3; /* in bytes */
313 dev_dbg(qspi
->dev
, "rx cmd %08x dc %08x\n", cmd
, qspi
->dc
);
314 if (qspi_is_busy(qspi
))
317 ti_qspi_write(qspi
, cmd
, QSPI_SPI_CMD_REG
);
318 if (!wait_for_completion_timeout(&qspi
->transfer_complete
,
319 QSPI_COMPLETION_TIMEOUT
)) {
320 dev_err(qspi
->dev
, "read timed out\n");
325 *rxbuf
= readb(qspi
->base
+ QSPI_SPI_DATA_REG
);
328 *((u16
*)rxbuf
) = readw(qspi
->base
+ QSPI_SPI_DATA_REG
);
331 *((u32
*)rxbuf
) = readl(qspi
->base
+ QSPI_SPI_DATA_REG
);
341 static int qspi_transfer_msg(struct ti_qspi
*qspi
, struct spi_transfer
*t
)
346 ret
= qspi_write_msg(qspi
, t
);
348 dev_dbg(qspi
->dev
, "Error while writing\n");
354 ret
= qspi_read_msg(qspi
, t
);
356 dev_dbg(qspi
->dev
, "Error while reading\n");
364 static int ti_qspi_start_transfer_one(struct spi_master
*master
,
365 struct spi_message
*m
)
367 struct ti_qspi
*qspi
= spi_master_get_devdata(master
);
368 struct spi_device
*spi
= m
->spi
;
369 struct spi_transfer
*t
;
373 /* setup device control reg */
376 if (spi
->mode
& SPI_CPHA
)
377 qspi
->dc
|= QSPI_CKPHA(spi
->chip_select
);
378 if (spi
->mode
& SPI_CPOL
)
379 qspi
->dc
|= QSPI_CKPOL(spi
->chip_select
);
380 if (spi
->mode
& SPI_CS_HIGH
)
381 qspi
->dc
|= QSPI_CSPOL(spi
->chip_select
);
383 frame_length
= (m
->frame_length
<< 3) / spi
->bits_per_word
;
385 frame_length
= clamp(frame_length
, 0, QSPI_FRAME
);
387 /* setup command reg */
389 qspi
->cmd
|= QSPI_EN_CS(spi
->chip_select
);
390 qspi
->cmd
|= QSPI_FLEN(frame_length
);
391 qspi
->cmd
|= QSPI_WC_CMD_INT_EN
;
393 ti_qspi_write(qspi
, QSPI_WC_INT_EN
, QSPI_INTR_ENABLE_SET_REG
);
394 ti_qspi_write(qspi
, qspi
->dc
, QSPI_SPI_DC_REG
);
396 mutex_lock(&qspi
->list_lock
);
398 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
399 qspi
->cmd
|= QSPI_WLEN(t
->bits_per_word
);
401 ret
= qspi_transfer_msg(qspi
, t
);
403 dev_dbg(qspi
->dev
, "transfer message failed\n");
404 mutex_unlock(&qspi
->list_lock
);
408 m
->actual_length
+= t
->len
;
411 mutex_unlock(&qspi
->list_lock
);
414 spi_finalize_current_message(master
);
416 ti_qspi_write(qspi
, qspi
->cmd
| QSPI_INVAL
, QSPI_SPI_CMD_REG
);
421 static irqreturn_t
ti_qspi_isr(int irq
, void *dev_id
)
423 struct ti_qspi
*qspi
= dev_id
;
427 irqreturn_t ret
= IRQ_HANDLED
;
429 int_stat
= ti_qspi_read(qspi
, QSPI_INTR_STATUS_ENABLED_CLEAR
);
430 stat
= ti_qspi_read(qspi
, QSPI_SPI_STATUS_REG
);
433 dev_dbg(qspi
->dev
, "No IRQ triggered\n");
438 ti_qspi_write(qspi
, QSPI_WC_INT_DISABLE
,
439 QSPI_INTR_STATUS_ENABLED_CLEAR
);
441 complete(&qspi
->transfer_complete
);
446 static int ti_qspi_runtime_resume(struct device
*dev
)
448 struct ti_qspi
*qspi
;
450 qspi
= dev_get_drvdata(dev
);
451 ti_qspi_restore_ctx(qspi
);
456 static const struct of_device_id ti_qspi_match
[] = {
457 {.compatible
= "ti,dra7xxx-qspi" },
458 {.compatible
= "ti,am4372-qspi" },
461 MODULE_DEVICE_TABLE(of
, ti_qspi_match
);
463 static int ti_qspi_probe(struct platform_device
*pdev
)
465 struct ti_qspi
*qspi
;
466 struct spi_master
*master
;
467 struct resource
*r
, *res_ctrl
, *res_mmap
;
468 struct device_node
*np
= pdev
->dev
.of_node
;
470 int ret
= 0, num_cs
, irq
;
472 master
= spi_alloc_master(&pdev
->dev
, sizeof(*qspi
));
476 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_RX_DUAL
| SPI_RX_QUAD
;
478 master
->flags
= SPI_MASTER_HALF_DUPLEX
;
479 master
->setup
= ti_qspi_setup
;
480 master
->auto_runtime_pm
= true;
481 master
->transfer_one_message
= ti_qspi_start_transfer_one
;
482 master
->dev
.of_node
= pdev
->dev
.of_node
;
483 master
->bits_per_word_mask
= SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
486 if (!of_property_read_u32(np
, "num-cs", &num_cs
))
487 master
->num_chipselect
= num_cs
;
489 qspi
= spi_master_get_devdata(master
);
490 qspi
->master
= master
;
491 qspi
->dev
= &pdev
->dev
;
492 platform_set_drvdata(pdev
, qspi
);
494 r
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "qspi_base");
496 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
498 dev_err(&pdev
->dev
, "missing platform data\n");
503 res_mmap
= platform_get_resource_byname(pdev
,
504 IORESOURCE_MEM
, "qspi_mmap");
505 if (res_mmap
== NULL
) {
506 res_mmap
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
507 if (res_mmap
== NULL
) {
509 "memory mapped resource not required\n");
513 res_ctrl
= platform_get_resource_byname(pdev
,
514 IORESOURCE_MEM
, "qspi_ctrlmod");
515 if (res_ctrl
== NULL
) {
516 res_ctrl
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
517 if (res_ctrl
== NULL
) {
519 "control module resources not required\n");
523 irq
= platform_get_irq(pdev
, 0);
525 dev_err(&pdev
->dev
, "no irq resource?\n");
529 mutex_init(&qspi
->list_lock
);
531 qspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
532 if (IS_ERR(qspi
->base
)) {
533 ret
= PTR_ERR(qspi
->base
);
538 qspi
->ctrl_mod
= true;
539 qspi
->ctrl_base
= devm_ioremap_resource(&pdev
->dev
, res_ctrl
);
540 if (IS_ERR(qspi
->ctrl_base
)) {
541 ret
= PTR_ERR(qspi
->ctrl_base
);
547 qspi
->mmap_base
= devm_ioremap_resource(&pdev
->dev
, res_mmap
);
548 if (IS_ERR(qspi
->mmap_base
)) {
549 ret
= PTR_ERR(qspi
->mmap_base
);
554 ret
= devm_request_irq(&pdev
->dev
, irq
, ti_qspi_isr
, 0,
555 dev_name(&pdev
->dev
), qspi
);
557 dev_err(&pdev
->dev
, "Failed to register ISR for IRQ %d\n",
562 qspi
->fclk
= devm_clk_get(&pdev
->dev
, "fck");
563 if (IS_ERR(qspi
->fclk
)) {
564 ret
= PTR_ERR(qspi
->fclk
);
565 dev_err(&pdev
->dev
, "could not get clk: %d\n", ret
);
568 init_completion(&qspi
->transfer_complete
);
570 pm_runtime_use_autosuspend(&pdev
->dev
);
571 pm_runtime_set_autosuspend_delay(&pdev
->dev
, QSPI_AUTOSUSPEND_TIMEOUT
);
572 pm_runtime_enable(&pdev
->dev
);
574 if (!of_property_read_u32(np
, "spi-max-frequency", &max_freq
))
575 qspi
->spi_max_frequency
= max_freq
;
577 ret
= devm_spi_register_master(&pdev
->dev
, master
);
584 spi_master_put(master
);
588 static int ti_qspi_remove(struct platform_device
*pdev
)
590 struct ti_qspi
*qspi
= platform_get_drvdata(pdev
);
593 ret
= pm_runtime_get_sync(qspi
->dev
);
595 dev_err(qspi
->dev
, "pm_runtime_get_sync() failed\n");
599 ti_qspi_write(qspi
, QSPI_WC_INT_DISABLE
, QSPI_INTR_ENABLE_CLEAR_REG
);
601 pm_runtime_put(qspi
->dev
);
602 pm_runtime_disable(&pdev
->dev
);
607 static const struct dev_pm_ops ti_qspi_pm_ops
= {
608 .runtime_resume
= ti_qspi_runtime_resume
,
611 static struct platform_driver ti_qspi_driver
= {
612 .probe
= ti_qspi_probe
,
613 .remove
= ti_qspi_remove
,
616 .pm
= &ti_qspi_pm_ops
,
617 .of_match_table
= ti_qspi_match
,
621 module_platform_driver(ti_qspi_driver
);
623 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
624 MODULE_LICENSE("GPL v2");
625 MODULE_DESCRIPTION("TI QSPI controller driver");
626 MODULE_ALIAS("platform:ti-qspi");