2 * High Speed Serial Ports on NXP LPC32xx SoC
4 * Authors: Kevin Wells <kevin.wells@nxp.com>
5 * Roland Stigge <stigge@antcom.de>
7 * Copyright (C) 2010 NXP Semiconductors
8 * Copyright (C) 2012 Roland Stigge
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/module.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
32 #include <linux/nmi.h>
34 #include <linux/irq.h>
35 #include <linux/gpio.h>
37 #include <mach/platform.h>
38 #include <mach/hardware.h>
41 * High Speed UART register offsets
43 #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
44 #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
45 #define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
46 #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
47 #define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
49 #define LPC32XX_HSU_BREAK_DATA (1 << 10)
50 #define LPC32XX_HSU_ERROR_DATA (1 << 9)
51 #define LPC32XX_HSU_RX_EMPTY (1 << 8)
53 #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
54 #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
56 #define LPC32XX_HSU_TX_INT_SET (1 << 6)
57 #define LPC32XX_HSU_RX_OE_INT (1 << 5)
58 #define LPC32XX_HSU_BRK_INT (1 << 4)
59 #define LPC32XX_HSU_FE_INT (1 << 3)
60 #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
61 #define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
62 #define LPC32XX_HSU_TX_INT (1 << 0)
64 #define LPC32XX_HSU_HRTS_INV (1 << 21)
65 #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
66 #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
67 #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
68 #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
69 #define LPC32XX_HSU_HRTS_EN (1 << 18)
70 #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
71 #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
72 #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
73 #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
74 #define LPC32XX_HSU_HCTS_INV (1 << 15)
75 #define LPC32XX_HSU_HCTS_EN (1 << 14)
76 #define LPC32XX_HSU_OFFSET(n) ((n) << 9)
77 #define LPC32XX_HSU_BREAK (1 << 8)
78 #define LPC32XX_HSU_ERR_INT_EN (1 << 7)
79 #define LPC32XX_HSU_RX_INT_EN (1 << 6)
80 #define LPC32XX_HSU_TX_INT_EN (1 << 5)
81 #define LPC32XX_HSU_RX_TL1B (0x0 << 2)
82 #define LPC32XX_HSU_RX_TL4B (0x1 << 2)
83 #define LPC32XX_HSU_RX_TL8B (0x2 << 2)
84 #define LPC32XX_HSU_RX_TL16B (0x3 << 2)
85 #define LPC32XX_HSU_RX_TL32B (0x4 << 2)
86 #define LPC32XX_HSU_RX_TL48B (0x5 << 2)
87 #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
88 #define LPC32XX_HSU_TX_TL0B (0x0 << 0)
89 #define LPC32XX_HSU_TX_TL4B (0x1 << 0)
90 #define LPC32XX_HSU_TX_TL8B (0x2 << 0)
91 #define LPC32XX_HSU_TX_TL16B (0x3 << 0)
93 #define MODNAME "lpc32xx_hsuart"
95 struct lpc32xx_hsuart_port
{
96 struct uart_port port
;
99 #define FIFO_READ_LIMIT 128
101 #define LPC32XX_TTY_NAME "ttyTX"
102 static struct lpc32xx_hsuart_port lpc32xx_hs_ports
[MAX_PORTS
];
104 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
105 static void wait_for_xmit_empty(struct uart_port
*port
)
107 unsigned int timeout
= 10000;
110 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
111 port
->membase
))) == 0)
119 static void wait_for_xmit_ready(struct uart_port
*port
)
121 unsigned int timeout
= 10000;
124 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
125 port
->membase
))) < 32)
133 static void lpc32xx_hsuart_console_putchar(struct uart_port
*port
, int ch
)
135 wait_for_xmit_ready(port
);
136 writel((u32
)ch
, LPC32XX_HSUART_FIFO(port
->membase
));
139 static void lpc32xx_hsuart_console_write(struct console
*co
, const char *s
,
142 struct lpc32xx_hsuart_port
*up
= &lpc32xx_hs_ports
[co
->index
];
146 touch_nmi_watchdog();
147 local_irq_save(flags
);
150 else if (oops_in_progress
)
151 locked
= spin_trylock(&up
->port
.lock
);
153 spin_lock(&up
->port
.lock
);
155 uart_console_write(&up
->port
, s
, count
, lpc32xx_hsuart_console_putchar
);
156 wait_for_xmit_empty(&up
->port
);
159 spin_unlock(&up
->port
.lock
);
160 local_irq_restore(flags
);
163 static int __init
lpc32xx_hsuart_console_setup(struct console
*co
,
166 struct uart_port
*port
;
172 if (co
->index
>= MAX_PORTS
)
175 port
= &lpc32xx_hs_ports
[co
->index
].port
;
180 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
182 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
185 static struct uart_driver lpc32xx_hsuart_reg
;
186 static struct console lpc32xx_hsuart_console
= {
187 .name
= LPC32XX_TTY_NAME
,
188 .write
= lpc32xx_hsuart_console_write
,
189 .device
= uart_console_device
,
190 .setup
= lpc32xx_hsuart_console_setup
,
191 .flags
= CON_PRINTBUFFER
,
193 .data
= &lpc32xx_hsuart_reg
,
196 static int __init
lpc32xx_hsuart_console_init(void)
198 register_console(&lpc32xx_hsuart_console
);
201 console_initcall(lpc32xx_hsuart_console_init
);
203 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
205 #define LPC32XX_HSUART_CONSOLE NULL
208 static struct uart_driver lpc32xx_hs_reg
= {
209 .owner
= THIS_MODULE
,
210 .driver_name
= MODNAME
,
211 .dev_name
= LPC32XX_TTY_NAME
,
213 .cons
= LPC32XX_HSUART_CONSOLE
,
215 static int uarts_registered
;
217 static unsigned int __serial_get_clock_div(unsigned long uartclk
,
220 u32 div
, goodrate
, hsu_rate
, l_hsu_rate
, comprate
;
223 /* Find the closest divider to get the desired clock rate */
224 div
= uartclk
/ rate
;
225 goodrate
= hsu_rate
= (div
/ 14) - 1;
230 l_hsu_rate
= hsu_rate
+ 3;
231 rate_diff
= 0xFFFFFFFF;
233 while (hsu_rate
< l_hsu_rate
) {
234 comprate
= uartclk
/ ((hsu_rate
+ 1) * 14);
235 if (abs(comprate
- rate
) < rate_diff
) {
237 rate_diff
= abs(comprate
- rate
);
248 static void __serial_uart_flush(struct uart_port
*port
)
253 while ((readl(LPC32XX_HSUART_LEVEL(port
->membase
)) > 0) &&
254 (cnt
++ < FIFO_READ_LIMIT
))
255 tmp
= readl(LPC32XX_HSUART_FIFO(port
->membase
));
258 static void __serial_lpc32xx_rx(struct uart_port
*port
)
260 struct tty_port
*tport
= &port
->state
->port
;
261 unsigned int tmp
, flag
;
263 /* Read data from FIFO and push into terminal */
264 tmp
= readl(LPC32XX_HSUART_FIFO(port
->membase
));
265 while (!(tmp
& LPC32XX_HSU_RX_EMPTY
)) {
269 if (tmp
& LPC32XX_HSU_ERROR_DATA
) {
271 writel(LPC32XX_HSU_FE_INT
,
272 LPC32XX_HSUART_IIR(port
->membase
));
273 port
->icount
.frame
++;
275 tty_insert_flip_char(tport
, 0, TTY_FRAME
);
278 tty_insert_flip_char(tport
, (tmp
& 0xFF), flag
);
280 tmp
= readl(LPC32XX_HSUART_FIFO(port
->membase
));
282 tty_flip_buffer_push(tport
);
285 static void __serial_lpc32xx_tx(struct uart_port
*port
)
287 struct circ_buf
*xmit
= &port
->state
->xmit
;
291 writel((u32
)port
->x_char
, LPC32XX_HSUART_FIFO(port
->membase
));
297 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
))
301 while (LPC32XX_HSU_TX_LEV(readl(
302 LPC32XX_HSUART_LEVEL(port
->membase
))) < 64) {
303 writel((u32
) xmit
->buf
[xmit
->tail
],
304 LPC32XX_HSUART_FIFO(port
->membase
));
305 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
307 if (uart_circ_empty(xmit
))
311 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
312 uart_write_wakeup(port
);
315 if (uart_circ_empty(xmit
)) {
316 tmp
= readl(LPC32XX_HSUART_CTRL(port
->membase
));
317 tmp
&= ~LPC32XX_HSU_TX_INT_EN
;
318 writel(tmp
, LPC32XX_HSUART_CTRL(port
->membase
));
322 static irqreturn_t
serial_lpc32xx_interrupt(int irq
, void *dev_id
)
324 struct uart_port
*port
= dev_id
;
325 struct tty_port
*port
= &port
->state
->port
;
326 struct tty_struct
*tty
= tty_port_tty_get(tport
);
329 spin_lock(&port
->lock
);
331 /* Read UART status and clear latched interrupts */
332 status
= readl(LPC32XX_HSUART_IIR(port
->membase
));
334 if (status
& LPC32XX_HSU_BRK_INT
) {
336 writel(LPC32XX_HSU_BRK_INT
, LPC32XX_HSUART_IIR(port
->membase
));
338 uart_handle_break(port
);
342 if (status
& LPC32XX_HSU_FE_INT
)
343 writel(LPC32XX_HSU_FE_INT
, LPC32XX_HSUART_IIR(port
->membase
));
345 if (status
& LPC32XX_HSU_RX_OE_INT
) {
346 /* Receive FIFO overrun */
347 writel(LPC32XX_HSU_RX_OE_INT
,
348 LPC32XX_HSUART_IIR(port
->membase
));
349 port
->icount
.overrun
++;
350 tty_insert_flip_char(tport
, 0, TTY_OVERRUN
);
352 tty_schedule_flip(tty
);
357 if (status
& (LPC32XX_HSU_RX_TIMEOUT_INT
| LPC32XX_HSU_RX_TRIG_INT
)) {
358 __serial_lpc32xx_rx(port
);
359 tty_flip_buffer_push(tport
);
362 /* Transmit data request? */
363 if ((status
& LPC32XX_HSU_TX_INT
) && (!uart_tx_stopped(port
))) {
364 writel(LPC32XX_HSU_TX_INT
, LPC32XX_HSUART_IIR(port
->membase
));
365 __serial_lpc32xx_tx(port
);
368 spin_unlock(&port
->lock
);
374 /* port->lock is not held. */
375 static unsigned int serial_lpc32xx_tx_empty(struct uart_port
*port
)
377 unsigned int ret
= 0;
379 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port
->membase
))) == 0)
385 /* port->lock held by caller. */
386 static void serial_lpc32xx_set_mctrl(struct uart_port
*port
,
389 /* No signals are supported on HS UARTs */
392 /* port->lock is held by caller and interrupts are disabled. */
393 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port
*port
)
395 /* No signals are supported on HS UARTs */
396 return TIOCM_CAR
| TIOCM_DSR
| TIOCM_CTS
;
399 /* port->lock held by caller. */
400 static void serial_lpc32xx_stop_tx(struct uart_port
*port
)
404 tmp
= readl(LPC32XX_HSUART_CTRL(port
->membase
));
405 tmp
&= ~LPC32XX_HSU_TX_INT_EN
;
406 writel(tmp
, LPC32XX_HSUART_CTRL(port
->membase
));
409 /* port->lock held by caller. */
410 static void serial_lpc32xx_start_tx(struct uart_port
*port
)
414 __serial_lpc32xx_tx(port
);
415 tmp
= readl(LPC32XX_HSUART_CTRL(port
->membase
));
416 tmp
|= LPC32XX_HSU_TX_INT_EN
;
417 writel(tmp
, LPC32XX_HSUART_CTRL(port
->membase
));
420 /* port->lock held by caller. */
421 static void serial_lpc32xx_stop_rx(struct uart_port
*port
)
425 tmp
= readl(LPC32XX_HSUART_CTRL(port
->membase
));
426 tmp
&= ~(LPC32XX_HSU_RX_INT_EN
| LPC32XX_HSU_ERR_INT_EN
);
427 writel(tmp
, LPC32XX_HSUART_CTRL(port
->membase
));
429 writel((LPC32XX_HSU_BRK_INT
| LPC32XX_HSU_RX_OE_INT
|
430 LPC32XX_HSU_FE_INT
), LPC32XX_HSUART_IIR(port
->membase
));
433 /* port->lock held by caller. */
434 static void serial_lpc32xx_enable_ms(struct uart_port
*port
)
436 /* Modem status is not supported */
439 /* port->lock is not held. */
440 static void serial_lpc32xx_break_ctl(struct uart_port
*port
,
446 spin_lock_irqsave(&port
->lock
, flags
);
447 tmp
= readl(LPC32XX_HSUART_CTRL(port
->membase
));
448 if (break_state
!= 0)
449 tmp
|= LPC32XX_HSU_BREAK
;
451 tmp
&= ~LPC32XX_HSU_BREAK
;
452 writel(tmp
, LPC32XX_HSUART_CTRL(port
->membase
));
453 spin_unlock_irqrestore(&port
->lock
, flags
);
456 /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
457 static void lpc32xx_loopback_set(resource_size_t mapbase
, int state
)
463 case LPC32XX_HS_UART1_BASE
:
466 case LPC32XX_HS_UART2_BASE
:
469 case LPC32XX_HS_UART7_BASE
:
473 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase
);
477 tmp
= readl(LPC32XX_UARTCTL_CLOOP
);
482 writel(tmp
, LPC32XX_UARTCTL_CLOOP
);
485 /* port->lock is not held. */
486 static int serial_lpc32xx_startup(struct uart_port
*port
)
492 spin_lock_irqsave(&port
->lock
, flags
);
494 __serial_uart_flush(port
);
496 writel((LPC32XX_HSU_TX_INT
| LPC32XX_HSU_FE_INT
|
497 LPC32XX_HSU_BRK_INT
| LPC32XX_HSU_RX_OE_INT
),
498 LPC32XX_HSUART_IIR(port
->membase
));
500 writel(0xFF, LPC32XX_HSUART_RATE(port
->membase
));
503 * Set receiver timeout, HSU offset of 20, no break, no interrupts,
504 * and default FIFO trigger levels
506 tmp
= LPC32XX_HSU_TX_TL8B
| LPC32XX_HSU_RX_TL32B
|
507 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B
;
508 writel(tmp
, LPC32XX_HSUART_CTRL(port
->membase
));
510 lpc32xx_loopback_set(port
->mapbase
, 0); /* get out of loopback mode */
512 spin_unlock_irqrestore(&port
->lock
, flags
);
514 retval
= request_irq(port
->irq
, serial_lpc32xx_interrupt
,
517 writel((tmp
| LPC32XX_HSU_RX_INT_EN
| LPC32XX_HSU_ERR_INT_EN
),
518 LPC32XX_HSUART_CTRL(port
->membase
));
523 /* port->lock is not held. */
524 static void serial_lpc32xx_shutdown(struct uart_port
*port
)
529 spin_lock_irqsave(&port
->lock
, flags
);
531 tmp
= LPC32XX_HSU_TX_TL8B
| LPC32XX_HSU_RX_TL32B
|
532 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B
;
533 writel(tmp
, LPC32XX_HSUART_CTRL(port
->membase
));
535 lpc32xx_loopback_set(port
->mapbase
, 1); /* go to loopback mode */
537 spin_unlock_irqrestore(&port
->lock
, flags
);
539 free_irq(port
->irq
, port
);
542 /* port->lock is not held. */
543 static void serial_lpc32xx_set_termios(struct uart_port
*port
,
544 struct ktermios
*termios
,
545 struct ktermios
*old
)
548 unsigned int baud
, quot
;
551 /* Always 8-bit, no parity, 1 stop bit */
552 termios
->c_cflag
&= ~(CSIZE
| CSTOPB
| PARENB
| PARODD
);
553 termios
->c_cflag
|= CS8
;
555 termios
->c_cflag
&= ~(HUPCL
| CMSPAR
| CLOCAL
| CRTSCTS
);
557 baud
= uart_get_baud_rate(port
, termios
, old
, 0,
560 quot
= __serial_get_clock_div(port
->uartclk
, baud
);
562 spin_lock_irqsave(&port
->lock
, flags
);
564 /* Ignore characters? */
565 tmp
= readl(LPC32XX_HSUART_CTRL(port
->membase
));
566 if ((termios
->c_cflag
& CREAD
) == 0)
567 tmp
&= ~(LPC32XX_HSU_RX_INT_EN
| LPC32XX_HSU_ERR_INT_EN
);
569 tmp
|= LPC32XX_HSU_RX_INT_EN
| LPC32XX_HSU_ERR_INT_EN
;
570 writel(tmp
, LPC32XX_HSUART_CTRL(port
->membase
));
572 writel(quot
, LPC32XX_HSUART_RATE(port
->membase
));
574 uart_update_timeout(port
, termios
->c_cflag
, baud
);
576 spin_unlock_irqrestore(&port
->lock
, flags
);
578 /* Don't rewrite B0 */
579 if (tty_termios_baud_rate(termios
))
580 tty_termios_encode_baud_rate(termios
, baud
, baud
);
583 static const char *serial_lpc32xx_type(struct uart_port
*port
)
588 static void serial_lpc32xx_release_port(struct uart_port
*port
)
590 if ((port
->iotype
== UPIO_MEM32
) && (port
->mapbase
)) {
591 if (port
->flags
& UPF_IOREMAP
) {
592 iounmap(port
->membase
);
593 port
->membase
= NULL
;
596 release_mem_region(port
->mapbase
, SZ_4K
);
600 static int serial_lpc32xx_request_port(struct uart_port
*port
)
604 if ((port
->iotype
== UPIO_MEM32
) && (port
->mapbase
)) {
607 if (!request_mem_region(port
->mapbase
, SZ_4K
, MODNAME
))
609 else if (port
->flags
& UPF_IOREMAP
) {
610 port
->membase
= ioremap(port
->mapbase
, SZ_4K
);
611 if (!port
->membase
) {
612 release_mem_region(port
->mapbase
, SZ_4K
);
621 static void serial_lpc32xx_config_port(struct uart_port
*port
, int uflags
)
625 ret
= serial_lpc32xx_request_port(port
);
628 port
->type
= PORT_UART00
;
631 __serial_uart_flush(port
);
633 writel((LPC32XX_HSU_TX_INT
| LPC32XX_HSU_FE_INT
|
634 LPC32XX_HSU_BRK_INT
| LPC32XX_HSU_RX_OE_INT
),
635 LPC32XX_HSUART_IIR(port
->membase
));
637 writel(0xFF, LPC32XX_HSUART_RATE(port
->membase
));
639 /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
640 and default FIFO trigger levels */
641 writel(LPC32XX_HSU_TX_TL8B
| LPC32XX_HSU_RX_TL32B
|
642 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B
,
643 LPC32XX_HSUART_CTRL(port
->membase
));
646 static int serial_lpc32xx_verify_port(struct uart_port
*port
,
647 struct serial_struct
*ser
)
651 if (ser
->type
!= PORT_UART00
)
657 static struct uart_ops serial_lpc32xx_pops
= {
658 .tx_empty
= serial_lpc32xx_tx_empty
,
659 .set_mctrl
= serial_lpc32xx_set_mctrl
,
660 .get_mctrl
= serial_lpc32xx_get_mctrl
,
661 .stop_tx
= serial_lpc32xx_stop_tx
,
662 .start_tx
= serial_lpc32xx_start_tx
,
663 .stop_rx
= serial_lpc32xx_stop_rx
,
664 .enable_ms
= serial_lpc32xx_enable_ms
,
665 .break_ctl
= serial_lpc32xx_break_ctl
,
666 .startup
= serial_lpc32xx_startup
,
667 .shutdown
= serial_lpc32xx_shutdown
,
668 .set_termios
= serial_lpc32xx_set_termios
,
669 .type
= serial_lpc32xx_type
,
670 .release_port
= serial_lpc32xx_release_port
,
671 .request_port
= serial_lpc32xx_request_port
,
672 .config_port
= serial_lpc32xx_config_port
,
673 .verify_port
= serial_lpc32xx_verify_port
,
677 * Register a set of serial devices attached to a platform device
679 static int serial_hs_lpc32xx_probe(struct platform_device
*pdev
)
681 struct lpc32xx_hsuart_port
*p
= &lpc32xx_hs_ports
[uarts_registered
];
683 struct resource
*res
;
685 if (uarts_registered
>= MAX_PORTS
) {
687 "Error: Number of possible ports exceeded (%d)!\n",
688 uarts_registered
+ 1);
692 memset(p
, 0, sizeof(*p
));
694 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
697 "Error getting mem resource for HS UART port %d\n",
701 p
->port
.mapbase
= res
->start
;
702 p
->port
.membase
= NULL
;
704 p
->port
.irq
= platform_get_irq(pdev
, 0);
705 if (p
->port
.irq
< 0) {
706 dev_err(&pdev
->dev
, "Error getting irq for HS UART port %d\n",
711 p
->port
.iotype
= UPIO_MEM32
;
712 p
->port
.uartclk
= LPC32XX_MAIN_OSC_FREQ
;
713 p
->port
.regshift
= 2;
714 p
->port
.flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_PORT
| UPF_IOREMAP
;
715 p
->port
.dev
= &pdev
->dev
;
716 p
->port
.ops
= &serial_lpc32xx_pops
;
717 p
->port
.line
= uarts_registered
++;
718 spin_lock_init(&p
->port
.lock
);
720 /* send port to loopback mode by default */
721 lpc32xx_loopback_set(p
->port
.mapbase
, 1);
723 ret
= uart_add_one_port(&lpc32xx_hs_reg
, &p
->port
);
725 platform_set_drvdata(pdev
, p
);
731 * Remove serial ports registered against a platform device.
733 static int serial_hs_lpc32xx_remove(struct platform_device
*pdev
)
735 struct lpc32xx_hsuart_port
*p
= platform_get_drvdata(pdev
);
737 uart_remove_one_port(&lpc32xx_hs_reg
, &p
->port
);
744 static int serial_hs_lpc32xx_suspend(struct platform_device
*pdev
,
747 struct lpc32xx_hsuart_port
*p
= platform_get_drvdata(pdev
);
749 uart_suspend_port(&lpc32xx_hs_reg
, &p
->port
);
754 static int serial_hs_lpc32xx_resume(struct platform_device
*pdev
)
756 struct lpc32xx_hsuart_port
*p
= platform_get_drvdata(pdev
);
758 uart_resume_port(&lpc32xx_hs_reg
, &p
->port
);
763 #define serial_hs_lpc32xx_suspend NULL
764 #define serial_hs_lpc32xx_resume NULL
767 static const struct of_device_id serial_hs_lpc32xx_dt_ids
[] = {
768 { .compatible
= "nxp,lpc3220-hsuart" },
772 MODULE_DEVICE_TABLE(of
, serial_hs_lpc32xx_dt_ids
);
774 static struct platform_driver serial_hs_lpc32xx_driver
= {
775 .probe
= serial_hs_lpc32xx_probe
,
776 .remove
= serial_hs_lpc32xx_remove
,
777 .suspend
= serial_hs_lpc32xx_suspend
,
778 .resume
= serial_hs_lpc32xx_resume
,
781 .owner
= THIS_MODULE
,
782 .of_match_table
= serial_hs_lpc32xx_dt_ids
,
786 static int __init
lpc32xx_hsuart_init(void)
790 ret
= uart_register_driver(&lpc32xx_hs_reg
);
794 ret
= platform_driver_register(&serial_hs_lpc32xx_driver
);
796 uart_unregister_driver(&lpc32xx_hs_reg
);
801 static void __exit
lpc32xx_hsuart_exit(void)
803 platform_driver_unregister(&serial_hs_lpc32xx_driver
);
804 uart_unregister_driver(&lpc32xx_hs_reg
);
807 module_init(lpc32xx_hsuart_init
);
808 module_exit(lpc32xx_hsuart_exit
);
810 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
811 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
812 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
813 MODULE_LICENSE("GPL");