2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
6 * (C) Copyright 2010 Intel Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX
19 * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
20 * asserted, only when the HW is reset the DDCD and DDSR will
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/slab.h>
29 #include <linux/serial_reg.h>
30 #include <linux/circ_buf.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial_mfd.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/pci.h>
39 #include <linux/nmi.h>
41 #include <linux/debugfs.h>
42 #include <linux/pm_runtime.h>
44 #define HSU_DMA_BUF_SIZE 2048
46 #define chan_readl(chan, offset) readl(chan->reg + offset)
47 #define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
49 #define mfd_readl(obj, offset) readl(obj->reg + offset)
50 #define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
52 static int hsu_dma_enable
;
53 module_param(hsu_dma_enable
, int, 0);
54 MODULE_PARM_DESC(hsu_dma_enable
,
55 "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
57 struct hsu_dma_buffer
{
66 enum dma_data_direction dirt
;
67 struct uart_hsu_port
*uport
;
71 struct uart_hsu_port
{
72 struct uart_port port
;
76 unsigned int lsr_break_flag
;
81 struct hsu_dma_chan
*txc
;
82 struct hsu_dma_chan
*rxc
;
83 struct hsu_dma_buffer txbuf
;
84 struct hsu_dma_buffer rxbuf
;
85 int use_dma
; /* flag for DMA/PIO */
90 /* Top level data structure of HSU */
97 struct uart_hsu_port port
[3];
98 struct hsu_dma_chan chans
[10];
100 struct dentry
*debugfs
;
103 static inline unsigned int serial_in(struct uart_hsu_port
*up
, int offset
)
107 if (offset
> UART_MSR
) {
109 val
= readl(up
->port
.membase
+ offset
);
111 val
= (unsigned int)readb(up
->port
.membase
+ offset
);
116 static inline void serial_out(struct uart_hsu_port
*up
, int offset
, int value
)
118 if (offset
> UART_MSR
) {
120 writel(value
, up
->port
.membase
+ offset
);
122 unsigned char val
= value
& 0xff;
123 writeb(val
, up
->port
.membase
+ offset
);
127 #ifdef CONFIG_DEBUG_FS
129 #define HSU_REGS_BUFSIZE 1024
132 static ssize_t
port_show_regs(struct file
*file
, char __user
*user_buf
,
133 size_t count
, loff_t
*ppos
)
135 struct uart_hsu_port
*up
= file
->private_data
;
140 buf
= kzalloc(HSU_REGS_BUFSIZE
, GFP_KERNEL
);
144 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
145 "MFD HSU port[%d] regs:\n", up
->index
);
147 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
148 "=================================\n");
149 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
150 "IER: \t\t0x%08x\n", serial_in(up
, UART_IER
));
151 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
152 "IIR: \t\t0x%08x\n", serial_in(up
, UART_IIR
));
153 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
154 "LCR: \t\t0x%08x\n", serial_in(up
, UART_LCR
));
155 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
156 "MCR: \t\t0x%08x\n", serial_in(up
, UART_MCR
));
157 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
158 "LSR: \t\t0x%08x\n", serial_in(up
, UART_LSR
));
159 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
160 "MSR: \t\t0x%08x\n", serial_in(up
, UART_MSR
));
161 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
162 "FOR: \t\t0x%08x\n", serial_in(up
, UART_FOR
));
163 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
164 "PS: \t\t0x%08x\n", serial_in(up
, UART_PS
));
165 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
166 "MUL: \t\t0x%08x\n", serial_in(up
, UART_MUL
));
167 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
168 "DIV: \t\t0x%08x\n", serial_in(up
, UART_DIV
));
170 if (len
> HSU_REGS_BUFSIZE
)
171 len
= HSU_REGS_BUFSIZE
;
173 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
178 static ssize_t
dma_show_regs(struct file
*file
, char __user
*user_buf
,
179 size_t count
, loff_t
*ppos
)
181 struct hsu_dma_chan
*chan
= file
->private_data
;
186 buf
= kzalloc(HSU_REGS_BUFSIZE
, GFP_KERNEL
);
190 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
191 "MFD HSU DMA channel [%d] regs:\n", chan
->id
);
193 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
194 "=================================\n");
195 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
196 "CR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_CR
));
197 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
198 "DCR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_DCR
));
199 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
200 "BSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_BSR
));
201 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
202 "MOTSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_MOTSR
));
203 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
204 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D0SAR
));
205 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
206 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D0TSR
));
207 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
208 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D1SAR
));
209 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
210 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D1TSR
));
211 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
212 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D2SAR
));
213 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
214 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D2TSR
));
215 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
216 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D3SAR
));
217 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
218 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D3TSR
));
220 if (len
> HSU_REGS_BUFSIZE
)
221 len
= HSU_REGS_BUFSIZE
;
223 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
228 static const struct file_operations port_regs_ops
= {
229 .owner
= THIS_MODULE
,
231 .read
= port_show_regs
,
232 .llseek
= default_llseek
,
235 static const struct file_operations dma_regs_ops
= {
236 .owner
= THIS_MODULE
,
238 .read
= dma_show_regs
,
239 .llseek
= default_llseek
,
242 static int hsu_debugfs_init(struct hsu_port
*hsu
)
247 hsu
->debugfs
= debugfs_create_dir("hsu", NULL
);
251 for (i
= 0; i
< 3; i
++) {
252 snprintf(name
, sizeof(name
), "port_%d_regs", i
);
253 debugfs_create_file(name
, S_IFREG
| S_IRUGO
,
254 hsu
->debugfs
, (void *)(&hsu
->port
[i
]), &port_regs_ops
);
257 for (i
= 0; i
< 6; i
++) {
258 snprintf(name
, sizeof(name
), "dma_chan_%d_regs", i
);
259 debugfs_create_file(name
, S_IFREG
| S_IRUGO
,
260 hsu
->debugfs
, (void *)&hsu
->chans
[i
], &dma_regs_ops
);
266 static void hsu_debugfs_remove(struct hsu_port
*hsu
)
269 debugfs_remove_recursive(hsu
->debugfs
);
273 static inline int hsu_debugfs_init(struct hsu_port
*hsu
)
278 static inline void hsu_debugfs_remove(struct hsu_port
*hsu
)
281 #endif /* CONFIG_DEBUG_FS */
283 static void serial_hsu_enable_ms(struct uart_port
*port
)
285 struct uart_hsu_port
*up
=
286 container_of(port
, struct uart_hsu_port
, port
);
288 up
->ier
|= UART_IER_MSI
;
289 serial_out(up
, UART_IER
, up
->ier
);
292 void hsu_dma_tx(struct uart_hsu_port
*up
)
294 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
295 struct hsu_dma_buffer
*dbuf
= &up
->txbuf
;
298 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
302 /* Update the circ buf info */
303 xmit
->tail
+= dbuf
->ofs
;
304 xmit
->tail
&= UART_XMIT_SIZE
- 1;
306 up
->port
.icount
.tx
+= dbuf
->ofs
;
309 /* Disable the channel */
310 chan_writel(up
->txc
, HSU_CH_CR
, 0x0);
312 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&up
->port
)) {
313 dma_sync_single_for_device(up
->port
.dev
,
318 count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
321 /* Reprogram the channel */
322 chan_writel(up
->txc
, HSU_CH_D0SAR
, dbuf
->dma_addr
+ xmit
->tail
);
323 chan_writel(up
->txc
, HSU_CH_D0TSR
, count
);
325 /* Reenable the channel */
326 chan_writel(up
->txc
, HSU_CH_DCR
, 0x1
331 chan_writel(up
->txc
, HSU_CH_CR
, 0x1);
334 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
335 uart_write_wakeup(&up
->port
);
338 /* The buffer is already cache coherent */
339 void hsu_dma_start_rx_chan(struct hsu_dma_chan
*rxc
, struct hsu_dma_buffer
*dbuf
)
343 chan_writel(rxc
, HSU_CH_BSR
, 32);
344 chan_writel(rxc
, HSU_CH_MOTSR
, 4);
346 chan_writel(rxc
, HSU_CH_D0SAR
, dbuf
->dma_addr
);
347 chan_writel(rxc
, HSU_CH_D0TSR
, dbuf
->dma_size
);
348 chan_writel(rxc
, HSU_CH_DCR
, 0x1 | (0x1 << 8)
350 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
352 chan_writel(rxc
, HSU_CH_CR
, 0x3);
355 /* Protected by spin_lock_irqsave(port->lock) */
356 static void serial_hsu_start_tx(struct uart_port
*port
)
358 struct uart_hsu_port
*up
=
359 container_of(port
, struct uart_hsu_port
, port
);
363 } else if (!(up
->ier
& UART_IER_THRI
)) {
364 up
->ier
|= UART_IER_THRI
;
365 serial_out(up
, UART_IER
, up
->ier
);
369 static void serial_hsu_stop_tx(struct uart_port
*port
)
371 struct uart_hsu_port
*up
=
372 container_of(port
, struct uart_hsu_port
, port
);
373 struct hsu_dma_chan
*txc
= up
->txc
;
376 chan_writel(txc
, HSU_CH_CR
, 0x0);
377 else if (up
->ier
& UART_IER_THRI
) {
378 up
->ier
&= ~UART_IER_THRI
;
379 serial_out(up
, UART_IER
, up
->ier
);
383 /* This is always called in spinlock protected mode, so
384 * modify timeout timer is safe here */
385 void hsu_dma_rx(struct uart_hsu_port
*up
, u32 int_sts
)
387 struct hsu_dma_buffer
*dbuf
= &up
->rxbuf
;
388 struct hsu_dma_chan
*chan
= up
->rxc
;
389 struct uart_port
*port
= &up
->port
;
390 struct tty_port
*tport
= &port
->state
->port
;
394 * First need to know how many is already transferred,
395 * then check if its a timeout DMA irq, and return
396 * the trail bytes out, push them up and reenable the
400 /* Timeout IRQ, need wait some time, see Errata 2 */
404 /* Stop the channel */
405 chan_writel(chan
, HSU_CH_CR
, 0x0);
407 count
= chan_readl(chan
, HSU_CH_D0SAR
) - dbuf
->dma_addr
;
409 /* Restart the channel before we leave */
410 chan_writel(chan
, HSU_CH_CR
, 0x3);
414 dma_sync_single_for_cpu(port
->dev
, dbuf
->dma_addr
,
415 dbuf
->dma_size
, DMA_FROM_DEVICE
);
418 * Head will only wrap around when we recycle
419 * the DMA buffer, and when that happens, we
420 * explicitly set tail to 0. So head will
421 * always be greater than tail.
423 tty_insert_flip_string(tport
, dbuf
->buf
, count
);
424 port
->icount
.rx
+= count
;
426 dma_sync_single_for_device(up
->port
.dev
, dbuf
->dma_addr
,
427 dbuf
->dma_size
, DMA_FROM_DEVICE
);
429 /* Reprogram the channel */
430 chan_writel(chan
, HSU_CH_D0SAR
, dbuf
->dma_addr
);
431 chan_writel(chan
, HSU_CH_D0TSR
, dbuf
->dma_size
);
432 chan_writel(chan
, HSU_CH_DCR
, 0x1
435 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
437 tty_flip_buffer_push(tport
);
439 chan_writel(chan
, HSU_CH_CR
, 0x3);
443 static void serial_hsu_stop_rx(struct uart_port
*port
)
445 struct uart_hsu_port
*up
=
446 container_of(port
, struct uart_hsu_port
, port
);
447 struct hsu_dma_chan
*chan
= up
->rxc
;
450 chan_writel(chan
, HSU_CH_CR
, 0x2);
452 up
->ier
&= ~UART_IER_RLSI
;
453 up
->port
.read_status_mask
&= ~UART_LSR_DR
;
454 serial_out(up
, UART_IER
, up
->ier
);
458 static inline void receive_chars(struct uart_hsu_port
*up
, int *status
)
460 unsigned int ch
, flag
;
461 unsigned int max_count
= 256;
464 ch
= serial_in(up
, UART_RX
);
466 up
->port
.icount
.rx
++;
468 if (unlikely(*status
& (UART_LSR_BI
| UART_LSR_PE
|
469 UART_LSR_FE
| UART_LSR_OE
))) {
471 dev_warn(up
->dev
, "We really rush into ERR/BI case"
472 "status = 0x%02x", *status
);
473 /* For statistics only */
474 if (*status
& UART_LSR_BI
) {
475 *status
&= ~(UART_LSR_FE
| UART_LSR_PE
);
476 up
->port
.icount
.brk
++;
478 * We do the SysRQ and SAK checking
479 * here because otherwise the break
480 * may get masked by ignore_status_mask
481 * or read_status_mask.
483 if (uart_handle_break(&up
->port
))
485 } else if (*status
& UART_LSR_PE
)
486 up
->port
.icount
.parity
++;
487 else if (*status
& UART_LSR_FE
)
488 up
->port
.icount
.frame
++;
489 if (*status
& UART_LSR_OE
)
490 up
->port
.icount
.overrun
++;
492 /* Mask off conditions which should be ignored. */
493 *status
&= up
->port
.read_status_mask
;
495 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
497 up
->port
.cons
->index
== up
->port
.line
) {
498 /* Recover the break flag from console xmit */
499 *status
|= up
->lsr_break_flag
;
500 up
->lsr_break_flag
= 0;
503 if (*status
& UART_LSR_BI
) {
505 } else if (*status
& UART_LSR_PE
)
507 else if (*status
& UART_LSR_FE
)
511 if (uart_handle_sysrq_char(&up
->port
, ch
))
514 uart_insert_char(&up
->port
, *status
, UART_LSR_OE
, ch
, flag
);
516 *status
= serial_in(up
, UART_LSR
);
517 } while ((*status
& UART_LSR_DR
) && max_count
--);
518 tty_flip_buffer_push(&up
->port
.state
->port
);
521 static void transmit_chars(struct uart_hsu_port
*up
)
523 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
526 if (up
->port
.x_char
) {
527 serial_out(up
, UART_TX
, up
->port
.x_char
);
528 up
->port
.icount
.tx
++;
532 if (uart_circ_empty(xmit
) || uart_tx_stopped(&up
->port
)) {
533 serial_hsu_stop_tx(&up
->port
);
537 /* The IRQ is for TX FIFO half-empty */
538 count
= up
->port
.fifosize
/ 2;
541 serial_out(up
, UART_TX
, xmit
->buf
[xmit
->tail
]);
542 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
544 up
->port
.icount
.tx
++;
545 if (uart_circ_empty(xmit
))
547 } while (--count
> 0);
549 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
550 uart_write_wakeup(&up
->port
);
552 if (uart_circ_empty(xmit
))
553 serial_hsu_stop_tx(&up
->port
);
556 static inline void check_modem_status(struct uart_hsu_port
*up
)
560 status
= serial_in(up
, UART_MSR
);
562 if ((status
& UART_MSR_ANY_DELTA
) == 0)
565 if (status
& UART_MSR_TERI
)
566 up
->port
.icount
.rng
++;
567 if (status
& UART_MSR_DDSR
)
568 up
->port
.icount
.dsr
++;
569 /* We may only get DDCD when HW init and reset */
570 if (status
& UART_MSR_DDCD
)
571 uart_handle_dcd_change(&up
->port
, status
& UART_MSR_DCD
);
572 /* Will start/stop_tx accordingly */
573 if (status
& UART_MSR_DCTS
)
574 uart_handle_cts_change(&up
->port
, status
& UART_MSR_CTS
);
576 wake_up_interruptible(&up
->port
.state
->port
.delta_msr_wait
);
580 * This handles the interrupt from one port.
582 static irqreturn_t
port_irq(int irq
, void *dev_id
)
584 struct uart_hsu_port
*up
= dev_id
;
585 unsigned int iir
, lsr
;
588 if (unlikely(!up
->running
))
591 spin_lock_irqsave(&up
->port
.lock
, flags
);
593 lsr
= serial_in(up
, UART_LSR
);
594 if (unlikely(lsr
& (UART_LSR_BI
| UART_LSR_PE
|
595 UART_LSR_FE
| UART_LSR_OE
)))
597 "Got lsr irq while using DMA, lsr = 0x%2x\n",
599 check_modem_status(up
);
600 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
604 iir
= serial_in(up
, UART_IIR
);
605 if (iir
& UART_IIR_NO_INT
) {
606 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
610 lsr
= serial_in(up
, UART_LSR
);
611 if (lsr
& UART_LSR_DR
)
612 receive_chars(up
, &lsr
);
613 check_modem_status(up
);
615 /* lsr will be renewed during the receive_chars */
616 if (lsr
& UART_LSR_THRE
)
619 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
623 static inline void dma_chan_irq(struct hsu_dma_chan
*chan
)
625 struct uart_hsu_port
*up
= chan
->uport
;
629 spin_lock_irqsave(&up
->port
.lock
, flags
);
631 if (!up
->use_dma
|| !up
->running
)
635 * No matter what situation, need read clear the IRQ status
636 * There is a bug, see Errata 5, HSD 2900918
638 int_sts
= chan_readl(chan
, HSU_CH_SR
);
641 if (chan
->dirt
== DMA_FROM_DEVICE
)
642 hsu_dma_rx(up
, int_sts
);
645 if (chan
->dirt
== DMA_TO_DEVICE
) {
646 chan_writel(chan
, HSU_CH_CR
, 0x0);
652 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
656 static irqreturn_t
dma_irq(int irq
, void *dev_id
)
658 struct hsu_port
*hsu
= dev_id
;
661 int_sts
= mfd_readl(hsu
, HSU_GBL_DMAISR
);
663 /* Currently we only have 6 channels may be used */
664 for (i
= 0; i
< 6; i
++) {
666 dma_chan_irq(&hsu
->chans
[i
]);
673 static unsigned int serial_hsu_tx_empty(struct uart_port
*port
)
675 struct uart_hsu_port
*up
=
676 container_of(port
, struct uart_hsu_port
, port
);
680 spin_lock_irqsave(&up
->port
.lock
, flags
);
681 ret
= serial_in(up
, UART_LSR
) & UART_LSR_TEMT
? TIOCSER_TEMT
: 0;
682 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
687 static unsigned int serial_hsu_get_mctrl(struct uart_port
*port
)
689 struct uart_hsu_port
*up
=
690 container_of(port
, struct uart_hsu_port
, port
);
691 unsigned char status
;
694 status
= serial_in(up
, UART_MSR
);
697 if (status
& UART_MSR_DCD
)
699 if (status
& UART_MSR_RI
)
701 if (status
& UART_MSR_DSR
)
703 if (status
& UART_MSR_CTS
)
708 static void serial_hsu_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
710 struct uart_hsu_port
*up
=
711 container_of(port
, struct uart_hsu_port
, port
);
712 unsigned char mcr
= 0;
714 if (mctrl
& TIOCM_RTS
)
716 if (mctrl
& TIOCM_DTR
)
718 if (mctrl
& TIOCM_OUT1
)
719 mcr
|= UART_MCR_OUT1
;
720 if (mctrl
& TIOCM_OUT2
)
721 mcr
|= UART_MCR_OUT2
;
722 if (mctrl
& TIOCM_LOOP
)
723 mcr
|= UART_MCR_LOOP
;
727 serial_out(up
, UART_MCR
, mcr
);
730 static void serial_hsu_break_ctl(struct uart_port
*port
, int break_state
)
732 struct uart_hsu_port
*up
=
733 container_of(port
, struct uart_hsu_port
, port
);
736 spin_lock_irqsave(&up
->port
.lock
, flags
);
737 if (break_state
== -1)
738 up
->lcr
|= UART_LCR_SBC
;
740 up
->lcr
&= ~UART_LCR_SBC
;
741 serial_out(up
, UART_LCR
, up
->lcr
);
742 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
746 * What special to do:
747 * 1. chose the 64B fifo mode
748 * 2. start dma or pio depends on configuration
749 * 3. we only allocate dma memory when needed
751 static int serial_hsu_startup(struct uart_port
*port
)
753 struct uart_hsu_port
*up
=
754 container_of(port
, struct uart_hsu_port
, port
);
757 pm_runtime_get_sync(up
->dev
);
760 * Clear the FIFO buffers and disable them.
761 * (they will be reenabled in set_termios())
763 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
764 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
765 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
766 serial_out(up
, UART_FCR
, 0);
768 /* Clear the interrupt registers. */
769 (void) serial_in(up
, UART_LSR
);
770 (void) serial_in(up
, UART_RX
);
771 (void) serial_in(up
, UART_IIR
);
772 (void) serial_in(up
, UART_MSR
);
774 /* Now, initialize the UART, default is 8n1 */
775 serial_out(up
, UART_LCR
, UART_LCR_WLEN8
);
777 spin_lock_irqsave(&up
->port
.lock
, flags
);
779 up
->port
.mctrl
|= TIOCM_OUT2
;
780 serial_hsu_set_mctrl(&up
->port
, up
->port
.mctrl
);
783 * Finally, enable interrupts. Note: Modem status interrupts
784 * are set via set_termios(), which will be occurring imminently
785 * anyway, so we don't enable them here.
788 up
->ier
= UART_IER_RLSI
| UART_IER_RDI
| UART_IER_RTOIE
;
791 serial_out(up
, UART_IER
, up
->ier
);
793 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
797 struct hsu_dma_buffer
*dbuf
;
798 struct circ_buf
*xmit
= &port
->state
->xmit
;
802 /* First allocate the RX buffer */
804 dbuf
->buf
= kzalloc(HSU_DMA_BUF_SIZE
, GFP_KERNEL
);
809 dbuf
->dma_addr
= dma_map_single(port
->dev
,
813 dbuf
->dma_size
= HSU_DMA_BUF_SIZE
;
815 /* Start the RX channel right now */
816 hsu_dma_start_rx_chan(up
->rxc
, dbuf
);
818 /* Next init the TX DMA */
820 dbuf
->buf
= xmit
->buf
;
821 dbuf
->dma_addr
= dma_map_single(port
->dev
,
825 dbuf
->dma_size
= UART_XMIT_SIZE
;
827 /* This should not be changed all around */
828 chan_writel(up
->txc
, HSU_CH_BSR
, 32);
829 chan_writel(up
->txc
, HSU_CH_MOTSR
, 4);
834 /* And clear the interrupt registers again for luck. */
835 (void) serial_in(up
, UART_LSR
);
836 (void) serial_in(up
, UART_RX
);
837 (void) serial_in(up
, UART_IIR
);
838 (void) serial_in(up
, UART_MSR
);
844 static void serial_hsu_shutdown(struct uart_port
*port
)
846 struct uart_hsu_port
*up
=
847 container_of(port
, struct uart_hsu_port
, port
);
850 /* Disable interrupts from this port */
852 serial_out(up
, UART_IER
, 0);
855 spin_lock_irqsave(&up
->port
.lock
, flags
);
856 up
->port
.mctrl
&= ~TIOCM_OUT2
;
857 serial_hsu_set_mctrl(&up
->port
, up
->port
.mctrl
);
858 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
860 /* Disable break condition and FIFOs */
861 serial_out(up
, UART_LCR
, serial_in(up
, UART_LCR
) & ~UART_LCR_SBC
);
862 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
863 UART_FCR_CLEAR_RCVR
|
864 UART_FCR_CLEAR_XMIT
);
865 serial_out(up
, UART_FCR
, 0);
867 pm_runtime_put(up
->dev
);
871 serial_hsu_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
872 struct ktermios
*old
)
874 struct uart_hsu_port
*up
=
875 container_of(port
, struct uart_hsu_port
, port
);
876 unsigned char cval
, fcr
= 0;
878 unsigned int baud
, quot
;
881 switch (termios
->c_cflag
& CSIZE
) {
883 cval
= UART_LCR_WLEN5
;
886 cval
= UART_LCR_WLEN6
;
889 cval
= UART_LCR_WLEN7
;
893 cval
= UART_LCR_WLEN8
;
897 /* CMSPAR isn't supported by this driver */
898 termios
->c_cflag
&= ~CMSPAR
;
900 if (termios
->c_cflag
& CSTOPB
)
901 cval
|= UART_LCR_STOP
;
902 if (termios
->c_cflag
& PARENB
)
903 cval
|= UART_LCR_PARITY
;
904 if (!(termios
->c_cflag
& PARODD
))
905 cval
|= UART_LCR_EPAR
;
908 * The base clk is 50Mhz, and the baud rate come from:
909 * baud = 50M * MUL / (DIV * PS * DLAB)
911 * For those basic low baud rate we can get the direct
912 * scalar from 2746800, like 115200 = 2746800/24. For those
913 * higher baud rate, we handle them case by case, mainly by
914 * adjusting the MUL/PS registers, and DIV register is kept
915 * as default value 0x3d09 to make things simple
917 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 4000000);
936 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
937 mul
= baud
/ 500000 * 0x9C4;
940 /* Use uart_get_divisor to get quot for other baud rates */
945 quot
= uart_get_divisor(port
, baud
);
947 if ((up
->port
.uartclk
/ quot
) < (2400 * 16))
948 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_HSU_64_1B
;
949 else if ((up
->port
.uartclk
/ quot
) < (230400 * 16))
950 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_HSU_64_16B
;
952 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_HSU_64_32B
;
954 fcr
|= UART_FCR_HSU_64B_FIFO
;
957 * Ok, we're now changing the port state. Do it with
958 * interrupts disabled.
960 spin_lock_irqsave(&up
->port
.lock
, flags
);
962 /* Update the per-port timeout */
963 uart_update_timeout(port
, termios
->c_cflag
, baud
);
965 up
->port
.read_status_mask
= UART_LSR_OE
| UART_LSR_THRE
| UART_LSR_DR
;
966 if (termios
->c_iflag
& INPCK
)
967 up
->port
.read_status_mask
|= UART_LSR_FE
| UART_LSR_PE
;
968 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
969 up
->port
.read_status_mask
|= UART_LSR_BI
;
971 /* Characters to ignore */
972 up
->port
.ignore_status_mask
= 0;
973 if (termios
->c_iflag
& IGNPAR
)
974 up
->port
.ignore_status_mask
|= UART_LSR_PE
| UART_LSR_FE
;
975 if (termios
->c_iflag
& IGNBRK
) {
976 up
->port
.ignore_status_mask
|= UART_LSR_BI
;
978 * If we're ignoring parity and break indicators,
979 * ignore overruns too (for real raw support).
981 if (termios
->c_iflag
& IGNPAR
)
982 up
->port
.ignore_status_mask
|= UART_LSR_OE
;
985 /* Ignore all characters if CREAD is not set */
986 if ((termios
->c_cflag
& CREAD
) == 0)
987 up
->port
.ignore_status_mask
|= UART_LSR_DR
;
990 * CTS flow control flag and modem status interrupts, disable
993 up
->ier
&= ~UART_IER_MSI
;
994 if (UART_ENABLE_MS(&up
->port
, termios
->c_cflag
))
995 up
->ier
|= UART_IER_MSI
;
997 serial_out(up
, UART_IER
, up
->ier
);
999 if (termios
->c_cflag
& CRTSCTS
)
1000 up
->mcr
|= UART_MCR_AFE
| UART_MCR_RTS
;
1002 up
->mcr
&= ~UART_MCR_AFE
;
1004 serial_out(up
, UART_LCR
, cval
| UART_LCR_DLAB
); /* set DLAB */
1005 serial_out(up
, UART_DLL
, quot
& 0xff); /* LS of divisor */
1006 serial_out(up
, UART_DLM
, quot
>> 8); /* MS of divisor */
1007 serial_out(up
, UART_LCR
, cval
); /* reset DLAB */
1008 serial_out(up
, UART_MUL
, mul
); /* set MUL */
1009 serial_out(up
, UART_PS
, ps
); /* set PS */
1010 up
->lcr
= cval
; /* Save LCR */
1011 serial_hsu_set_mctrl(&up
->port
, up
->port
.mctrl
);
1012 serial_out(up
, UART_FCR
, fcr
);
1013 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
1017 serial_hsu_pm(struct uart_port
*port
, unsigned int state
,
1018 unsigned int oldstate
)
1022 static void serial_hsu_release_port(struct uart_port
*port
)
1026 static int serial_hsu_request_port(struct uart_port
*port
)
1031 static void serial_hsu_config_port(struct uart_port
*port
, int flags
)
1033 struct uart_hsu_port
*up
=
1034 container_of(port
, struct uart_hsu_port
, port
);
1035 up
->port
.type
= PORT_MFD
;
1039 serial_hsu_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1041 /* We don't want the core code to modify any port params */
1046 serial_hsu_type(struct uart_port
*port
)
1048 struct uart_hsu_port
*up
=
1049 container_of(port
, struct uart_hsu_port
, port
);
1053 /* Mainly for uart console use */
1054 static struct uart_hsu_port
*serial_hsu_ports
[3];
1055 static struct uart_driver serial_hsu_reg
;
1057 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1059 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1061 /* Wait for transmitter & holding register to empty */
1062 static inline void wait_for_xmitr(struct uart_hsu_port
*up
)
1064 unsigned int status
, tmout
= 1000;
1066 /* Wait up to 1ms for the character to be sent. */
1068 status
= serial_in(up
, UART_LSR
);
1070 if (status
& UART_LSR_BI
)
1071 up
->lsr_break_flag
= UART_LSR_BI
;
1076 } while (!(status
& BOTH_EMPTY
));
1078 /* Wait up to 1s for flow control if necessary */
1079 if (up
->port
.flags
& UPF_CONS_FLOW
) {
1082 ((serial_in(up
, UART_MSR
) & UART_MSR_CTS
) == 0))
1087 static void serial_hsu_console_putchar(struct uart_port
*port
, int ch
)
1089 struct uart_hsu_port
*up
=
1090 container_of(port
, struct uart_hsu_port
, port
);
1093 serial_out(up
, UART_TX
, ch
);
1097 * Print a string to the serial port trying not to disturb
1098 * any possible real use of the port...
1100 * The console_lock must be held when we get here.
1103 serial_hsu_console_write(struct console
*co
, const char *s
, unsigned int count
)
1105 struct uart_hsu_port
*up
= serial_hsu_ports
[co
->index
];
1106 unsigned long flags
;
1110 touch_nmi_watchdog();
1112 local_irq_save(flags
);
1115 else if (oops_in_progress
) {
1116 locked
= spin_trylock(&up
->port
.lock
);
1118 spin_lock(&up
->port
.lock
);
1120 /* First save the IER then disable the interrupts */
1121 ier
= serial_in(up
, UART_IER
);
1122 serial_out(up
, UART_IER
, 0);
1124 uart_console_write(&up
->port
, s
, count
, serial_hsu_console_putchar
);
1127 * Finally, wait for transmitter to become empty
1128 * and restore the IER
1131 serial_out(up
, UART_IER
, ier
);
1134 spin_unlock(&up
->port
.lock
);
1135 local_irq_restore(flags
);
1138 static struct console serial_hsu_console
;
1141 serial_hsu_console_setup(struct console
*co
, char *options
)
1143 struct uart_hsu_port
*up
;
1149 if (co
->index
== -1 || co
->index
>= serial_hsu_reg
.nr
)
1151 up
= serial_hsu_ports
[co
->index
];
1156 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1158 return uart_set_options(&up
->port
, co
, baud
, parity
, bits
, flow
);
1161 static struct console serial_hsu_console
= {
1163 .write
= serial_hsu_console_write
,
1164 .device
= uart_console_device
,
1165 .setup
= serial_hsu_console_setup
,
1166 .flags
= CON_PRINTBUFFER
,
1168 .data
= &serial_hsu_reg
,
1171 #define SERIAL_HSU_CONSOLE (&serial_hsu_console)
1173 #define SERIAL_HSU_CONSOLE NULL
1176 struct uart_ops serial_hsu_pops
= {
1177 .tx_empty
= serial_hsu_tx_empty
,
1178 .set_mctrl
= serial_hsu_set_mctrl
,
1179 .get_mctrl
= serial_hsu_get_mctrl
,
1180 .stop_tx
= serial_hsu_stop_tx
,
1181 .start_tx
= serial_hsu_start_tx
,
1182 .stop_rx
= serial_hsu_stop_rx
,
1183 .enable_ms
= serial_hsu_enable_ms
,
1184 .break_ctl
= serial_hsu_break_ctl
,
1185 .startup
= serial_hsu_startup
,
1186 .shutdown
= serial_hsu_shutdown
,
1187 .set_termios
= serial_hsu_set_termios
,
1188 .pm
= serial_hsu_pm
,
1189 .type
= serial_hsu_type
,
1190 .release_port
= serial_hsu_release_port
,
1191 .request_port
= serial_hsu_request_port
,
1192 .config_port
= serial_hsu_config_port
,
1193 .verify_port
= serial_hsu_verify_port
,
1196 static struct uart_driver serial_hsu_reg
= {
1197 .owner
= THIS_MODULE
,
1198 .driver_name
= "MFD serial",
1199 .dev_name
= "ttyMFD",
1203 .cons
= SERIAL_HSU_CONSOLE
,
1207 static int serial_hsu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1209 void *priv
= pci_get_drvdata(pdev
);
1210 struct uart_hsu_port
*up
;
1212 /* Make sure this is not the internal dma controller */
1213 if (priv
&& (pdev
->device
!= 0x081E)) {
1215 uart_suspend_port(&serial_hsu_reg
, &up
->port
);
1218 pci_save_state(pdev
);
1219 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1223 static int serial_hsu_resume(struct pci_dev
*pdev
)
1225 void *priv
= pci_get_drvdata(pdev
);
1226 struct uart_hsu_port
*up
;
1229 pci_set_power_state(pdev
, PCI_D0
);
1230 pci_restore_state(pdev
);
1232 ret
= pci_enable_device(pdev
);
1234 dev_warn(&pdev
->dev
,
1235 "HSU: can't re-enable device, try to continue\n");
1237 if (priv
&& (pdev
->device
!= 0x081E)) {
1239 uart_resume_port(&serial_hsu_reg
, &up
->port
);
1244 #define serial_hsu_suspend NULL
1245 #define serial_hsu_resume NULL
1248 #ifdef CONFIG_PM_RUNTIME
1249 static int serial_hsu_runtime_idle(struct device
*dev
)
1253 err
= pm_schedule_suspend(dev
, 500);
1260 static int serial_hsu_runtime_suspend(struct device
*dev
)
1265 static int serial_hsu_runtime_resume(struct device
*dev
)
1270 #define serial_hsu_runtime_idle NULL
1271 #define serial_hsu_runtime_suspend NULL
1272 #define serial_hsu_runtime_resume NULL
1275 static const struct dev_pm_ops serial_hsu_pm_ops
= {
1276 .runtime_suspend
= serial_hsu_runtime_suspend
,
1277 .runtime_resume
= serial_hsu_runtime_resume
,
1278 .runtime_idle
= serial_hsu_runtime_idle
,
1281 /* temp global pointer before we settle down on using one or four PCI dev */
1282 static struct hsu_port
*phsu
;
1284 static int serial_hsu_probe(struct pci_dev
*pdev
,
1285 const struct pci_device_id
*ent
)
1287 struct uart_hsu_port
*uport
;
1290 printk(KERN_INFO
"HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1291 pdev
->vendor
, pdev
->device
);
1293 switch (pdev
->device
) {
1304 /* internal DMA controller */
1308 dev_err(&pdev
->dev
, "HSU: out of index!");
1312 ret
= pci_enable_device(pdev
);
1317 /* DMA controller */
1318 ret
= request_irq(pdev
->irq
, dma_irq
, 0, "hsu_dma", phsu
);
1320 dev_err(&pdev
->dev
, "can not get IRQ\n");
1323 pci_set_drvdata(pdev
, phsu
);
1326 uport
= &phsu
->port
[index
];
1327 uport
->port
.irq
= pdev
->irq
;
1328 uport
->port
.dev
= &pdev
->dev
;
1329 uport
->dev
= &pdev
->dev
;
1331 ret
= request_irq(pdev
->irq
, port_irq
, 0, uport
->name
, uport
);
1333 dev_err(&pdev
->dev
, "can not get IRQ\n");
1336 uart_add_one_port(&serial_hsu_reg
, &uport
->port
);
1338 pci_set_drvdata(pdev
, uport
);
1341 pm_runtime_put_noidle(&pdev
->dev
);
1342 pm_runtime_allow(&pdev
->dev
);
1347 pci_disable_device(pdev
);
1351 static void hsu_global_init(void)
1353 struct hsu_port
*hsu
;
1354 struct uart_hsu_port
*uport
;
1355 struct hsu_dma_chan
*dchan
;
1358 hsu
= kzalloc(sizeof(struct hsu_port
), GFP_KERNEL
);
1362 /* Get basic io resource and map it */
1363 hsu
->paddr
= 0xffa28000;
1364 hsu
->iolen
= 0x1000;
1366 if (!(request_mem_region(hsu
->paddr
, hsu
->iolen
, "HSU global")))
1367 pr_warning("HSU: error in request mem region\n");
1369 hsu
->reg
= ioremap_nocache((unsigned long)hsu
->paddr
, hsu
->iolen
);
1371 pr_err("HSU: error in ioremap\n");
1373 goto err_free_region
;
1376 /* Initialise the 3 UART ports */
1378 for (i
= 0; i
< 3; i
++) {
1379 uport
->port
.type
= PORT_MFD
;
1380 uport
->port
.iotype
= UPIO_MEM
;
1381 uport
->port
.mapbase
= (resource_size_t
)hsu
->paddr
1382 + HSU_PORT_REG_OFFSET
1383 + i
* HSU_PORT_REG_LENGTH
;
1384 uport
->port
.membase
= hsu
->reg
+ HSU_PORT_REG_OFFSET
1385 + i
* HSU_PORT_REG_LENGTH
;
1387 sprintf(uport
->name
, "hsu_port%d", i
);
1388 uport
->port
.fifosize
= 64;
1389 uport
->port
.ops
= &serial_hsu_pops
;
1390 uport
->port
.line
= i
;
1391 uport
->port
.flags
= UPF_IOREMAP
;
1392 /* set the scalable maxim support rate to 2746800 bps */
1393 uport
->port
.uartclk
= 115200 * 24 * 16;
1396 uport
->txc
= &hsu
->chans
[i
* 2];
1397 uport
->rxc
= &hsu
->chans
[i
* 2 + 1];
1399 serial_hsu_ports
[i
] = uport
;
1402 if (hsu_dma_enable
& (1<<i
))
1410 /* Initialise 6 dma channels */
1412 for (i
= 0; i
< 6; i
++) {
1414 dchan
->dirt
= (i
& 0x1) ? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
1415 dchan
->uport
= &hsu
->port
[i
/2];
1416 dchan
->reg
= hsu
->reg
+ HSU_DMA_CHANS_REG_OFFSET
+
1417 i
* HSU_DMA_CHANS_REG_LENGTH
;
1423 hsu_debugfs_init(hsu
);
1427 release_mem_region(hsu
->paddr
, hsu
->iolen
);
1432 static void serial_hsu_remove(struct pci_dev
*pdev
)
1434 void *priv
= pci_get_drvdata(pdev
);
1435 struct uart_hsu_port
*up
;
1440 pm_runtime_forbid(&pdev
->dev
);
1441 pm_runtime_get_noresume(&pdev
->dev
);
1443 /* For port 0/1/2, priv is the address of uart_hsu_port */
1444 if (pdev
->device
!= 0x081E) {
1446 uart_remove_one_port(&serial_hsu_reg
, &up
->port
);
1449 pci_set_drvdata(pdev
, NULL
);
1450 free_irq(pdev
->irq
, priv
);
1451 pci_disable_device(pdev
);
1454 /* First 3 are UART ports, and the 4th is the DMA */
1455 static const struct pci_device_id pci_ids
[] = {
1456 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081B) },
1457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081C) },
1458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081D) },
1459 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081E) },
1463 static struct pci_driver hsu_pci_driver
= {
1464 .name
= "HSU serial",
1465 .id_table
= pci_ids
,
1466 .probe
= serial_hsu_probe
,
1467 .remove
= serial_hsu_remove
,
1468 .suspend
= serial_hsu_suspend
,
1469 .resume
= serial_hsu_resume
,
1471 .pm
= &serial_hsu_pm_ops
,
1475 static int __init
hsu_pci_init(void)
1481 ret
= uart_register_driver(&serial_hsu_reg
);
1485 return pci_register_driver(&hsu_pci_driver
);
1488 static void __exit
hsu_pci_exit(void)
1490 pci_unregister_driver(&hsu_pci_driver
);
1491 uart_unregister_driver(&serial_hsu_reg
);
1493 hsu_debugfs_remove(phsu
);
1498 module_init(hsu_pci_init
);
1499 module_exit(hsu_pci_exit
);
1501 MODULE_LICENSE("GPL v2");
1502 MODULE_ALIAS("platform:medfield-hsu");