2 * MSM 7k/8k High speed uart driver
4 * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
5 * Copyright (c) 2008 Google Inc.
6 * Modified: Nick Pelly <npelly@google.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 * See the GNU General Public License for more details.
17 * Has optional support for uart power management independent of linux
21 * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
22 * UART RX pin). This should only be used if there is not a wakeup
23 * GPIO on the UART CTS, and the first RX byte is known (for example, with the
24 * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
25 * always be lost. RTS will be asserted even while the UART is off in this mode
26 * of operation. See msm_serial_hs_platform_data.rx_wakeup_irq.
29 #include <linux/module.h>
31 #include <linux/serial.h>
32 #include <linux/serial_core.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/slab.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/irq.h>
40 #include <linux/ioport.h>
41 #include <linux/kernel.h>
42 #include <linux/timer.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/dmapool.h>
48 #include <linux/wait.h>
49 #include <linux/workqueue.h>
51 #include <linux/atomic.h>
54 #include <mach/hardware.h>
56 #include <linux/platform_data/msm_serial_hs.h>
58 /* HSUART Registers */
59 #define UARTDM_MR1_ADDR 0x0
60 #define UARTDM_MR2_ADDR 0x4
62 /* Data Mover result codes */
63 #define RSLT_FIFO_CNTR_BMSK (0xE << 28)
64 #define RSLT_VLD BIT(1)
66 /* write only register */
67 #define UARTDM_CSR_ADDR 0x8
68 #define UARTDM_CSR_115200 0xFF
69 #define UARTDM_CSR_57600 0xEE
70 #define UARTDM_CSR_38400 0xDD
71 #define UARTDM_CSR_28800 0xCC
72 #define UARTDM_CSR_19200 0xBB
73 #define UARTDM_CSR_14400 0xAA
74 #define UARTDM_CSR_9600 0x99
75 #define UARTDM_CSR_7200 0x88
76 #define UARTDM_CSR_4800 0x77
77 #define UARTDM_CSR_3600 0x66
78 #define UARTDM_CSR_2400 0x55
79 #define UARTDM_CSR_1200 0x44
80 #define UARTDM_CSR_600 0x33
81 #define UARTDM_CSR_300 0x22
82 #define UARTDM_CSR_150 0x11
83 #define UARTDM_CSR_75 0x00
85 /* write only register */
86 #define UARTDM_TF_ADDR 0x70
87 #define UARTDM_TF2_ADDR 0x74
88 #define UARTDM_TF3_ADDR 0x78
89 #define UARTDM_TF4_ADDR 0x7C
91 /* write only register */
92 #define UARTDM_CR_ADDR 0x10
93 #define UARTDM_IMR_ADDR 0x14
95 #define UARTDM_IPR_ADDR 0x18
96 #define UARTDM_TFWR_ADDR 0x1c
97 #define UARTDM_RFWR_ADDR 0x20
98 #define UARTDM_HCR_ADDR 0x24
99 #define UARTDM_DMRX_ADDR 0x34
100 #define UARTDM_IRDA_ADDR 0x38
101 #define UARTDM_DMEN_ADDR 0x3c
103 /* UART_DM_NO_CHARS_FOR_TX */
104 #define UARTDM_NCF_TX_ADDR 0x40
106 #define UARTDM_BADR_ADDR 0x44
108 #define UARTDM_SIM_CFG_ADDR 0x80
109 /* Read Only register */
110 #define UARTDM_SR_ADDR 0x8
112 /* Read Only register */
113 #define UARTDM_RF_ADDR 0x70
114 #define UARTDM_RF2_ADDR 0x74
115 #define UARTDM_RF3_ADDR 0x78
116 #define UARTDM_RF4_ADDR 0x7C
118 /* Read Only register */
119 #define UARTDM_MISR_ADDR 0x10
121 /* Read Only register */
122 #define UARTDM_ISR_ADDR 0x14
123 #define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
125 #define UARTDM_RXFS_ADDR 0x50
127 /* Register field Mask Mapping */
128 #define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
129 #define UARTDM_SR_OVERRUN_BMSK BIT(4)
130 #define UARTDM_SR_TXEMT_BMSK BIT(3)
131 #define UARTDM_SR_TXRDY_BMSK BIT(2)
132 #define UARTDM_SR_RXRDY_BMSK BIT(0)
134 #define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
135 #define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
136 #define UARTDM_CR_TX_EN_BMSK BIT(2)
137 #define UARTDM_CR_RX_EN_BMSK BIT(0)
139 /* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
140 #define RESET_RX 0x10
141 #define RESET_TX 0x20
142 #define RESET_ERROR_STATUS 0x30
143 #define RESET_BREAK_INT 0x40
144 #define START_BREAK 0x50
145 #define STOP_BREAK 0x60
146 #define RESET_CTS 0x70
147 #define RESET_STALE_INT 0x80
149 #define RFR_HIGH 0xE0
150 #define CR_PROTECTION_EN 0x100
151 #define STALE_EVENT_ENABLE 0x500
152 #define STALE_EVENT_DISABLE 0x600
153 #define FORCE_STALE_EVENT 0x400
154 #define CLEAR_TX_READY 0x300
155 #define RESET_TX_ERROR 0x800
156 #define RESET_TX_DONE 0x810
158 #define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
159 #define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
160 #define UARTDM_MR1_CTS_CTL_BMSK 0x40
161 #define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
163 #define UARTDM_MR2_ERROR_MODE_BMSK 0x40
164 #define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
166 /* bits per character configuration */
167 #define FIVE_BPC (0 << 4)
168 #define SIX_BPC (1 << 4)
169 #define SEVEN_BPC (2 << 4)
170 #define EIGHT_BPC (3 << 4)
172 #define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
173 #define STOP_BIT_ONE (1 << 2)
174 #define STOP_BIT_TWO (3 << 2)
176 #define UARTDM_MR2_PARITY_MODE_BMSK 0x3
178 /* Parity configuration */
179 #define NO_PARITY 0x0
180 #define EVEN_PARITY 0x1
181 #define ODD_PARITY 0x2
182 #define SPACE_PARITY 0x3
184 #define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
185 #define UARTDM_IPR_STALE_LSB_BMSK 0x1f
187 /* These can be used for both ISR and IMR register */
188 #define UARTDM_ISR_TX_READY_BMSK BIT(7)
189 #define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
190 #define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
191 #define UARTDM_ISR_RXLEV_BMSK BIT(4)
192 #define UARTDM_ISR_RXSTALE_BMSK BIT(3)
193 #define UARTDM_ISR_RXBREAK_BMSK BIT(2)
194 #define UARTDM_ISR_RXHUNT_BMSK BIT(1)
195 #define UARTDM_ISR_TXLEV_BMSK BIT(0)
197 /* Field definitions for UART_DM_DMEN*/
198 #define UARTDM_TX_DM_EN_BMSK 0x1
199 #define UARTDM_RX_DM_EN_BMSK 0x2
201 #define UART_FIFOSIZE 64
202 #define UARTCLK 7372800
204 /* Rx DMA request states */
208 FLUSH_DATA_INVALID
, /* values after this indicate invalid data */
209 FLUSH_IGNORE
= FLUSH_DATA_INVALID
,
214 /* UART clock states */
215 enum msm_hs_clk_states_e
{
216 MSM_HS_CLK_PORT_OFF
, /* port not in use */
217 MSM_HS_CLK_OFF
, /* clock disabled */
218 MSM_HS_CLK_REQUEST_OFF
, /* disable after TX and RX flushed */
219 MSM_HS_CLK_ON
, /* clock enabled */
222 /* Track the forced RXSTALE flush during clock off sequence.
223 * These states are only valid during MSM_HS_CLK_REQUEST_OFF */
224 enum msm_hs_clk_req_off_state_e
{
226 CLK_REQ_OFF_RXSTALE_ISSUED
,
227 CLK_REQ_OFF_FLUSH_ISSUED
,
228 CLK_REQ_OFF_RXSTALE_FLUSHED
,
233 * @tx_ready_int_en: ok to dma more tx?
234 * @dma_in_flight: tx dma in progress
235 * @xfer: top level DMA command pointer structure
236 * @command_ptr: third level command struct pointer
237 * @command_ptr_ptr: second level command list struct pointer
238 * @mapped_cmd_ptr: DMA view of third level command struct
239 * @mapped_cmd_ptr_ptr: DMA view of second level command list struct
240 * @tx_count: number of bytes to transfer in DMA transfer
241 * @dma_base: DMA view of UART xmit buffer
243 * This structure describes a single Tx DMA transaction. MSM DMA
244 * commands have two levels of indirection. The top level command
245 * ptr points to a list of command ptr which in turn points to a
246 * single DMA 'command'. In our case each Tx transaction consists
247 * of a single second level pointer pointing to a 'box type' command.
250 unsigned int tx_ready_int_en
;
251 unsigned int dma_in_flight
;
252 struct msm_dmov_cmd xfer
;
253 dmov_box
*command_ptr
;
254 u32
*command_ptr_ptr
;
255 dma_addr_t mapped_cmd_ptr
;
256 dma_addr_t mapped_cmd_ptr_ptr
;
263 * @flush: Rx DMA request state
264 * @xfer: top level DMA command pointer structure
265 * @cmdptr_dmaaddr: DMA view of second level command structure
266 * @command_ptr: third level DMA command pointer structure
267 * @command_ptr_ptr: second level DMA command list pointer
268 * @mapped_cmd_ptr: DMA view of the third level command structure
269 * @wait: wait for DMA completion before shutdown
270 * @buffer: destination buffer for RX DMA
271 * @rbuffer: DMA view of buffer
272 * @pool: dma pool out of which coherent rx buffer is allocated
273 * @tty_work: private work-queue for tty flip buffer push task
275 * This structure describes a single Rx DMA transaction. Rx DMA
276 * transactions use box mode DMA commands.
279 enum flush_reason flush
;
280 struct msm_dmov_cmd xfer
;
281 dma_addr_t cmdptr_dmaaddr
;
282 dmov_box
*command_ptr
;
283 u32
*command_ptr_ptr
;
284 dma_addr_t mapped_cmd_ptr
;
285 wait_queue_head_t wait
;
287 unsigned char *buffer
;
288 struct dma_pool
*pool
;
289 struct work_struct tty_work
;
293 * struct msm_hs_rx_wakeup
294 * @irq: IRQ line to be configured as interrupt source on Rx activity
295 * @ignore: boolean value. 1 = ignore the wakeup interrupt
296 * @rx_to_inject: extra character to be inserted to Rx tty on wakeup
297 * @inject_rx: 1 = insert rx_to_inject. 0 = do not insert extra character
299 * This is an optional structure required for UART Rx GPIO IRQ based
300 * wakeup from low power state. UART wakeup can be triggered by RX activity
301 * (using a wakeup GPIO on the UART RX pin). This should only be used if
302 * there is not a wakeup GPIO on the UART CTS, and the first RX byte is
303 * known (eg., with the Bluetooth Texas Instruments HCILL protocol),
304 * since the first RX byte will always be lost. RTS will be asserted even
305 * while the UART is clocked off in this mode of operation.
307 struct msm_hs_rx_wakeup
{
308 int irq
; /* < 0 indicates low power wakeup disabled */
309 unsigned char ignore
;
310 unsigned char inject_rx
;
316 * @uport: embedded uart port structure
317 * @imr_reg: shadow value of UARTDM_IMR
318 * @clk: uart input clock handle
319 * @tx: Tx transaction related data structure
320 * @rx: Rx transaction related data structure
321 * @dma_tx_channel: Tx DMA command channel
322 * @dma_rx_channel Rx DMA command channel
323 * @dma_tx_crci: Tx channel rate control interface number
324 * @dma_rx_crci: Rx channel rate control interface number
325 * @clk_off_timer: Timer to poll DMA event completion before clock off
326 * @clk_off_delay: clk_off_timer poll interval
327 * @clk_state: overall clock state
328 * @clk_req_off_state: post flush clock states
329 * @rx_wakeup: optional rx_wakeup feature related data
330 * @exit_lpm_cb: optional callback to exit low power mode
332 * Low level serial port structure.
335 struct uart_port uport
;
336 unsigned long imr_reg
;
346 struct hrtimer clk_off_timer
;
347 ktime_t clk_off_delay
;
348 enum msm_hs_clk_states_e clk_state
;
349 enum msm_hs_clk_req_off_state_e clk_req_off_state
;
351 struct msm_hs_rx_wakeup rx_wakeup
;
352 void (*exit_lpm_cb
)(struct uart_port
*);
355 #define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */
356 #define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE
357 #define UARTDM_RX_BUF_SIZE 512
361 static struct msm_hs_port q_uart_port
[UARTDM_NR
];
362 static struct platform_driver msm_serial_hs_platform_driver
;
363 static struct uart_driver msm_hs_driver
;
364 static struct uart_ops msm_hs_ops
;
365 static struct workqueue_struct
*msm_hs_workqueue
;
367 #define UARTDM_TO_MSM(uart_port) \
368 container_of((uart_port), struct msm_hs_port, uport)
370 static unsigned int use_low_power_rx_wakeup(struct msm_hs_port
373 return (msm_uport
->rx_wakeup
.irq
>= 0);
376 static unsigned int msm_hs_read(struct uart_port
*uport
,
379 return ioread32(uport
->membase
+ offset
);
382 static void msm_hs_write(struct uart_port
*uport
, unsigned int offset
,
385 iowrite32(value
, uport
->membase
+ offset
);
388 static void msm_hs_release_port(struct uart_port
*port
)
390 iounmap(port
->membase
);
393 static int msm_hs_request_port(struct uart_port
*port
)
395 port
->membase
= ioremap(port
->mapbase
, PAGE_SIZE
);
396 if (unlikely(!port
->membase
))
399 /* configure the CR Protection to Enable */
400 msm_hs_write(port
, UARTDM_CR_ADDR
, CR_PROTECTION_EN
);
404 static int msm_hs_remove(struct platform_device
*pdev
)
407 struct msm_hs_port
*msm_uport
;
410 if (pdev
->id
< 0 || pdev
->id
>= UARTDM_NR
) {
411 printk(KERN_ERR
"Invalid plaform device ID = %d\n", pdev
->id
);
415 msm_uport
= &q_uart_port
[pdev
->id
];
416 dev
= msm_uport
->uport
.dev
;
418 dma_unmap_single(dev
, msm_uport
->rx
.mapped_cmd_ptr
, sizeof(dmov_box
),
420 dma_pool_free(msm_uport
->rx
.pool
, msm_uport
->rx
.buffer
,
421 msm_uport
->rx
.rbuffer
);
422 dma_pool_destroy(msm_uport
->rx
.pool
);
424 dma_unmap_single(dev
, msm_uport
->rx
.cmdptr_dmaaddr
, sizeof(u32
),
426 dma_unmap_single(dev
, msm_uport
->tx
.mapped_cmd_ptr_ptr
, sizeof(u32
),
428 dma_unmap_single(dev
, msm_uport
->tx
.mapped_cmd_ptr
, sizeof(dmov_box
),
431 uart_remove_one_port(&msm_hs_driver
, &msm_uport
->uport
);
432 clk_put(msm_uport
->clk
);
434 /* Free the tx resources */
435 kfree(msm_uport
->tx
.command_ptr
);
436 kfree(msm_uport
->tx
.command_ptr_ptr
);
438 /* Free the rx resources */
439 kfree(msm_uport
->rx
.command_ptr
);
440 kfree(msm_uport
->rx
.command_ptr_ptr
);
442 iounmap(msm_uport
->uport
.membase
);
447 static int msm_hs_init_clk_locked(struct uart_port
*uport
)
450 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
452 ret
= clk_enable(msm_uport
->clk
);
454 printk(KERN_ERR
"Error could not turn on UART clk\n");
458 /* Set up the MREG/NREG/DREG/MNDREG */
459 ret
= clk_set_rate(msm_uport
->clk
, uport
->uartclk
);
461 printk(KERN_WARNING
"Error setting clock rate on UART\n");
462 clk_disable(msm_uport
->clk
);
466 msm_uport
->clk_state
= MSM_HS_CLK_ON
;
470 /* Enable and Disable clocks (Used for power management) */
471 static void msm_hs_pm(struct uart_port
*uport
, unsigned int state
,
472 unsigned int oldstate
)
474 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
476 if (use_low_power_rx_wakeup(msm_uport
) ||
477 msm_uport
->exit_lpm_cb
)
478 return; /* ignore linux PM states,
479 use msm_hs_request_clock API */
483 clk_enable(msm_uport
->clk
);
486 clk_disable(msm_uport
->clk
);
489 dev_err(uport
->dev
, "msm_serial: Unknown PM state %d\n",
495 * programs the UARTDM_CSR register with correct bit rates
497 * Interrupts should be disabled before we are called, as
498 * we modify Set Baud rate
499 * Set receive stale interrupt level, dependent on Bit Rate
500 * Goal is to have around 8 ms before indicate stale.
501 * roundup (((Bit Rate * .008) / 10) + 1
503 static void msm_hs_set_bps_locked(struct uart_port
*uport
,
506 unsigned long rxstale
;
508 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
512 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_75
);
516 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_150
);
520 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_300
);
524 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_600
);
528 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_1200
);
532 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_2400
);
536 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_3600
);
540 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_4800
);
544 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_7200
);
548 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_9600
);
552 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_14400
);
556 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_19200
);
560 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_28800
);
564 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_57600
);
568 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_115200
);
581 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_115200
);
585 msm_hs_write(uport
, UARTDM_CSR_ADDR
, UARTDM_CSR_2400
);
586 /* default to 9600 */
592 uport
->uartclk
= bps
* 16;
594 uport
->uartclk
= UARTCLK
;
596 if (clk_set_rate(msm_uport
->clk
, uport
->uartclk
)) {
597 printk(KERN_WARNING
"Error setting clock rate on UART\n");
601 data
= rxstale
& UARTDM_IPR_STALE_LSB_BMSK
;
602 data
|= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK
& (rxstale
<< 2);
604 msm_hs_write(uport
, UARTDM_IPR_ADDR
, data
);
608 * termios : new ktermios
609 * oldtermios: old ktermios previous setting
611 * Configure the serial port
613 static void msm_hs_set_termios(struct uart_port
*uport
,
614 struct ktermios
*termios
,
615 struct ktermios
*oldtermios
)
620 unsigned int c_cflag
= termios
->c_cflag
;
621 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
623 spin_lock_irqsave(&uport
->lock
, flags
);
624 clk_enable(msm_uport
->clk
);
626 /* 300 is the minimum baud support by the driver */
627 bps
= uart_get_baud_rate(uport
, termios
, oldtermios
, 200, 4000000);
629 /* Temporary remapping 200 BAUD to 3.2 mbps */
633 msm_hs_set_bps_locked(uport
, bps
);
635 data
= msm_hs_read(uport
, UARTDM_MR2_ADDR
);
636 data
&= ~UARTDM_MR2_PARITY_MODE_BMSK
;
638 if (PARENB
== (c_cflag
& PARENB
)) {
639 if (PARODD
== (c_cflag
& PARODD
))
641 else if (CMSPAR
== (c_cflag
& CMSPAR
))
642 data
|= SPACE_PARITY
;
647 /* Set bits per char */
648 data
&= ~UARTDM_MR2_BITS_PER_CHAR_BMSK
;
650 switch (c_cflag
& CSIZE
) {
665 if (c_cflag
& CSTOPB
) {
666 data
|= STOP_BIT_TWO
;
668 /* otherwise 1 stop bit */
669 data
|= STOP_BIT_ONE
;
671 data
|= UARTDM_MR2_ERROR_MODE_BMSK
;
672 /* write parity/bits per char/stop bit configuration */
673 msm_hs_write(uport
, UARTDM_MR2_ADDR
, data
);
675 /* Configure HW flow control */
676 data
= msm_hs_read(uport
, UARTDM_MR1_ADDR
);
678 data
&= ~(UARTDM_MR1_CTS_CTL_BMSK
| UARTDM_MR1_RX_RDY_CTL_BMSK
);
680 if (c_cflag
& CRTSCTS
) {
681 data
|= UARTDM_MR1_CTS_CTL_BMSK
;
682 data
|= UARTDM_MR1_RX_RDY_CTL_BMSK
;
685 msm_hs_write(uport
, UARTDM_MR1_ADDR
, data
);
687 uport
->ignore_status_mask
= termios
->c_iflag
& INPCK
;
688 uport
->ignore_status_mask
|= termios
->c_iflag
& IGNPAR
;
689 uport
->read_status_mask
= (termios
->c_cflag
& CREAD
);
691 msm_hs_write(uport
, UARTDM_IMR_ADDR
, 0);
693 /* Set Transmit software time out */
694 uart_update_timeout(uport
, c_cflag
, bps
);
696 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_RX
);
697 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_TX
);
699 if (msm_uport
->rx
.flush
== FLUSH_NONE
) {
700 msm_uport
->rx
.flush
= FLUSH_IGNORE
;
701 msm_dmov_stop_cmd(msm_uport
->dma_rx_channel
, NULL
, 1);
704 msm_hs_write(uport
, UARTDM_IMR_ADDR
, msm_uport
->imr_reg
);
706 clk_disable(msm_uport
->clk
);
707 spin_unlock_irqrestore(&uport
->lock
, flags
);
711 * Standard API, Transmitter
712 * Any character in the transmit shift register is sent
714 static unsigned int msm_hs_tx_empty(struct uart_port
*uport
)
717 unsigned int ret
= 0;
718 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
720 clk_enable(msm_uport
->clk
);
722 data
= msm_hs_read(uport
, UARTDM_SR_ADDR
);
723 if (data
& UARTDM_SR_TXEMT_BMSK
)
726 clk_disable(msm_uport
->clk
);
732 * Standard API, Stop transmitter.
733 * Any character in the transmit shift register is sent as
734 * well as the current data mover transfer .
736 static void msm_hs_stop_tx_locked(struct uart_port
*uport
)
738 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
740 msm_uport
->tx
.tx_ready_int_en
= 0;
744 * Standard API, Stop receiver as soon as possible.
746 * Function immediately terminates the operation of the
747 * channel receiver and any incoming characters are lost. None
748 * of the receiver status bits are affected by this command and
749 * characters that are already in the receive FIFO there.
751 static void msm_hs_stop_rx_locked(struct uart_port
*uport
)
753 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
756 clk_enable(msm_uport
->clk
);
759 data
= msm_hs_read(uport
, UARTDM_DMEN_ADDR
);
760 data
&= ~UARTDM_RX_DM_EN_BMSK
;
761 msm_hs_write(uport
, UARTDM_DMEN_ADDR
, data
);
763 /* Disable the receiver */
764 if (msm_uport
->rx
.flush
== FLUSH_NONE
)
765 msm_dmov_stop_cmd(msm_uport
->dma_rx_channel
, NULL
, 1);
767 if (msm_uport
->rx
.flush
!= FLUSH_SHUTDOWN
)
768 msm_uport
->rx
.flush
= FLUSH_STOP
;
770 clk_disable(msm_uport
->clk
);
773 /* Transmit the next chunk of data */
774 static void msm_hs_submit_tx_locked(struct uart_port
*uport
)
779 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
780 struct msm_hs_tx
*tx
= &msm_uport
->tx
;
781 struct circ_buf
*tx_buf
= &msm_uport
->uport
.state
->xmit
;
783 if (uart_circ_empty(tx_buf
) || uport
->state
->port
.tty
->stopped
) {
784 msm_hs_stop_tx_locked(uport
);
788 tx
->dma_in_flight
= 1;
790 tx_count
= uart_circ_chars_pending(tx_buf
);
792 if (UARTDM_TX_BUF_SIZE
< tx_count
)
793 tx_count
= UARTDM_TX_BUF_SIZE
;
795 left
= UART_XMIT_SIZE
- tx_buf
->tail
;
800 src_addr
= tx
->dma_base
+ tx_buf
->tail
;
801 dma_sync_single_for_device(uport
->dev
, src_addr
, tx_count
,
804 tx
->command_ptr
->num_rows
= (((tx_count
+ 15) >> 4) << 16) |
805 ((tx_count
+ 15) >> 4);
806 tx
->command_ptr
->src_row_addr
= src_addr
;
808 dma_sync_single_for_device(uport
->dev
, tx
->mapped_cmd_ptr
,
809 sizeof(dmov_box
), DMA_TO_DEVICE
);
811 *tx
->command_ptr_ptr
= CMD_PTR_LP
| DMOV_CMD_ADDR(tx
->mapped_cmd_ptr
);
813 dma_sync_single_for_device(uport
->dev
, tx
->mapped_cmd_ptr_ptr
,
814 sizeof(u32
), DMA_TO_DEVICE
);
816 /* Save tx_count to use in Callback */
817 tx
->tx_count
= tx_count
;
818 msm_hs_write(uport
, UARTDM_NCF_TX_ADDR
, tx_count
);
820 /* Disable the tx_ready interrupt */
821 msm_uport
->imr_reg
&= ~UARTDM_ISR_TX_READY_BMSK
;
822 msm_hs_write(uport
, UARTDM_IMR_ADDR
, msm_uport
->imr_reg
);
823 msm_dmov_enqueue_cmd(msm_uport
->dma_tx_channel
, &tx
->xfer
);
826 /* Start to receive the next chunk of data */
827 static void msm_hs_start_rx_locked(struct uart_port
*uport
)
829 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
831 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_STALE_INT
);
832 msm_hs_write(uport
, UARTDM_DMRX_ADDR
, UARTDM_RX_BUF_SIZE
);
833 msm_hs_write(uport
, UARTDM_CR_ADDR
, STALE_EVENT_ENABLE
);
834 msm_uport
->imr_reg
|= UARTDM_ISR_RXLEV_BMSK
;
835 msm_hs_write(uport
, UARTDM_IMR_ADDR
, msm_uport
->imr_reg
);
837 msm_uport
->rx
.flush
= FLUSH_NONE
;
838 msm_dmov_enqueue_cmd(msm_uport
->dma_rx_channel
, &msm_uport
->rx
.xfer
);
840 /* might have finished RX and be ready to clock off */
841 hrtimer_start(&msm_uport
->clk_off_timer
, msm_uport
->clk_off_delay
,
845 /* Enable the transmitter Interrupt */
846 static void msm_hs_start_tx_locked(struct uart_port
*uport
)
848 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
850 clk_enable(msm_uport
->clk
);
852 if (msm_uport
->exit_lpm_cb
)
853 msm_uport
->exit_lpm_cb(uport
);
855 if (msm_uport
->tx
.tx_ready_int_en
== 0) {
856 msm_uport
->tx
.tx_ready_int_en
= 1;
857 msm_hs_submit_tx_locked(uport
);
860 clk_disable(msm_uport
->clk
);
864 * This routine is called when we are done with a DMA transfer
866 * This routine is registered with Data mover when we set
867 * up a Data Mover transfer. It is called from Data mover ISR
868 * when the DMA transfer is done.
870 static void msm_hs_dmov_tx_callback(struct msm_dmov_cmd
*cmd_ptr
,
872 struct msm_dmov_errdata
*err
)
875 struct msm_hs_port
*msm_uport
;
877 /* DMA did not finish properly */
878 WARN_ON((((result
& RSLT_FIFO_CNTR_BMSK
) >> 28) == 1) &&
879 !(result
& RSLT_VLD
));
881 msm_uport
= container_of(cmd_ptr
, struct msm_hs_port
, tx
.xfer
);
883 spin_lock_irqsave(&msm_uport
->uport
.lock
, flags
);
884 clk_enable(msm_uport
->clk
);
886 msm_uport
->imr_reg
|= UARTDM_ISR_TX_READY_BMSK
;
887 msm_hs_write(&msm_uport
->uport
, UARTDM_IMR_ADDR
, msm_uport
->imr_reg
);
889 clk_disable(msm_uport
->clk
);
890 spin_unlock_irqrestore(&msm_uport
->uport
.lock
, flags
);
894 * This routine is called when we are done with a DMA transfer or the
895 * a flush has been sent to the data mover driver.
897 * This routine is registered with Data mover when we set up a Data Mover
898 * transfer. It is called from Data mover ISR when the DMA transfer is done.
900 static void msm_hs_dmov_rx_callback(struct msm_dmov_cmd
*cmd_ptr
,
902 struct msm_dmov_errdata
*err
)
906 unsigned long status
;
907 unsigned int error_f
= 0;
910 struct tty_struct
*tty
;
911 struct tty_port
*port
;
912 struct uart_port
*uport
;
913 struct msm_hs_port
*msm_uport
;
915 msm_uport
= container_of(cmd_ptr
, struct msm_hs_port
, rx
.xfer
);
916 uport
= &msm_uport
->uport
;
918 spin_lock_irqsave(&uport
->lock
, flags
);
919 clk_enable(msm_uport
->clk
);
921 port
= &uport
->state
->port
;
924 msm_hs_write(uport
, UARTDM_CR_ADDR
, STALE_EVENT_DISABLE
);
926 status
= msm_hs_read(uport
, UARTDM_SR_ADDR
);
928 /* overflow is not connect to data in a FIFO */
929 if (unlikely((status
& UARTDM_SR_OVERRUN_BMSK
) &&
930 (uport
->read_status_mask
& CREAD
))) {
931 tty_insert_flip_char(port
, 0, TTY_OVERRUN
);
932 uport
->icount
.buf_overrun
++;
936 if (!(uport
->ignore_status_mask
& INPCK
))
937 status
= status
& ~(UARTDM_SR_PAR_FRAME_BMSK
);
939 if (unlikely(status
& UARTDM_SR_PAR_FRAME_BMSK
)) {
940 /* Can not tell difference between parity & frame error */
941 uport
->icount
.parity
++;
943 if (uport
->ignore_status_mask
& IGNPAR
)
944 tty_insert_flip_char(port
, 0, TTY_PARITY
);
948 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_ERROR_STATUS
);
950 if (msm_uport
->clk_req_off_state
== CLK_REQ_OFF_FLUSH_ISSUED
)
951 msm_uport
->clk_req_off_state
= CLK_REQ_OFF_RXSTALE_FLUSHED
;
953 flush
= msm_uport
->rx
.flush
;
954 if (flush
== FLUSH_IGNORE
)
955 msm_hs_start_rx_locked(uport
);
956 if (flush
== FLUSH_STOP
)
957 msm_uport
->rx
.flush
= FLUSH_SHUTDOWN
;
958 if (flush
>= FLUSH_DATA_INVALID
)
961 rx_count
= msm_hs_read(uport
, UARTDM_RX_TOTAL_SNAP_ADDR
);
963 if (0 != (uport
->read_status_mask
& CREAD
)) {
964 retval
= tty_insert_flip_string(port
, msm_uport
->rx
.buffer
,
966 BUG_ON(retval
!= rx_count
);
969 msm_hs_start_rx_locked(uport
);
972 clk_disable(msm_uport
->clk
);
974 spin_unlock_irqrestore(&uport
->lock
, flags
);
976 if (flush
< FLUSH_DATA_INVALID
)
977 queue_work(msm_hs_workqueue
, &msm_uport
->rx
.tty_work
);
980 static void msm_hs_tty_flip_buffer_work(struct work_struct
*work
)
982 struct msm_hs_port
*msm_uport
=
983 container_of(work
, struct msm_hs_port
, rx
.tty_work
);
985 tty_flip_buffer_push(&msm_uport
->uport
.state
->port
);
989 * Standard API, Current states of modem control inputs
991 * Since CTS can be handled entirely by HARDWARE we always
992 * indicate clear to send and count on the TX FIFO to block when
999 * (Unsupported) DCD and DSR will return them high. RI will return low.
1001 static unsigned int msm_hs_get_mctrl_locked(struct uart_port
*uport
)
1003 return TIOCM_DSR
| TIOCM_CAR
| TIOCM_CTS
;
1007 * True enables UART auto RFR, which indicates we are ready for data if the RX
1008 * buffer is not full. False disables auto RFR, and deasserts RFR to indicate
1009 * we are not ready for data. Must be called with UART clock on.
1011 static void set_rfr_locked(struct uart_port
*uport
, int auto_rfr
)
1015 data
= msm_hs_read(uport
, UARTDM_MR1_ADDR
);
1018 /* enable auto ready-for-receiving */
1019 data
|= UARTDM_MR1_RX_RDY_CTL_BMSK
;
1020 msm_hs_write(uport
, UARTDM_MR1_ADDR
, data
);
1022 /* disable auto ready-for-receiving */
1023 data
&= ~UARTDM_MR1_RX_RDY_CTL_BMSK
;
1024 msm_hs_write(uport
, UARTDM_MR1_ADDR
, data
);
1025 /* RFR is active low, set high */
1026 msm_hs_write(uport
, UARTDM_CR_ADDR
, RFR_HIGH
);
1031 * Standard API, used to set or clear RFR
1033 static void msm_hs_set_mctrl_locked(struct uart_port
*uport
,
1036 unsigned int auto_rfr
;
1037 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1039 clk_enable(msm_uport
->clk
);
1041 auto_rfr
= TIOCM_RTS
& mctrl
? 1 : 0;
1042 set_rfr_locked(uport
, auto_rfr
);
1044 clk_disable(msm_uport
->clk
);
1047 /* Standard API, Enable modem status (CTS) interrupt */
1048 static void msm_hs_enable_ms_locked(struct uart_port
*uport
)
1050 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1052 clk_enable(msm_uport
->clk
);
1054 /* Enable DELTA_CTS Interrupt */
1055 msm_uport
->imr_reg
|= UARTDM_ISR_DELTA_CTS_BMSK
;
1056 msm_hs_write(uport
, UARTDM_IMR_ADDR
, msm_uport
->imr_reg
);
1058 clk_disable(msm_uport
->clk
);
1063 * Standard API, Break Signal
1065 * Control the transmission of a break signal. ctl eq 0 => break
1066 * signal terminate ctl ne 0 => start break signal
1068 static void msm_hs_break_ctl(struct uart_port
*uport
, int ctl
)
1070 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1072 clk_enable(msm_uport
->clk
);
1073 msm_hs_write(uport
, UARTDM_CR_ADDR
, ctl
? START_BREAK
: STOP_BREAK
);
1074 clk_disable(msm_uport
->clk
);
1077 static void msm_hs_config_port(struct uart_port
*uport
, int cfg_flags
)
1079 unsigned long flags
;
1081 spin_lock_irqsave(&uport
->lock
, flags
);
1082 if (cfg_flags
& UART_CONFIG_TYPE
) {
1083 uport
->type
= PORT_MSM
;
1084 msm_hs_request_port(uport
);
1086 spin_unlock_irqrestore(&uport
->lock
, flags
);
1089 /* Handle CTS changes (Called from interrupt handler) */
1090 static void msm_hs_handle_delta_cts_locked(struct uart_port
*uport
)
1092 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1094 clk_enable(msm_uport
->clk
);
1096 /* clear interrupt */
1097 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_CTS
);
1098 uport
->icount
.cts
++;
1100 clk_disable(msm_uport
->clk
);
1102 /* clear the IOCTL TIOCMIWAIT if called */
1103 wake_up_interruptible(&uport
->state
->port
.delta_msr_wait
);
1106 /* check if the TX path is flushed, and if so clock off
1107 * returns 0 did not clock off, need to retry (still sending final byte)
1108 * -1 did not clock off, do not retry
1109 * 1 if we clocked off
1111 static int msm_hs_check_clock_off_locked(struct uart_port
*uport
)
1113 unsigned long sr_status
;
1114 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1115 struct circ_buf
*tx_buf
= &uport
->state
->xmit
;
1117 /* Cancel if tx tty buffer is not empty, dma is in flight,
1118 * or tx fifo is not empty, or rx fifo is not empty */
1119 if (msm_uport
->clk_state
!= MSM_HS_CLK_REQUEST_OFF
||
1120 !uart_circ_empty(tx_buf
) || msm_uport
->tx
.dma_in_flight
||
1121 (msm_uport
->imr_reg
& UARTDM_ISR_TXLEV_BMSK
) ||
1122 !(msm_uport
->imr_reg
& UARTDM_ISR_RXLEV_BMSK
)) {
1126 /* Make sure the uart is finished with the last byte */
1127 sr_status
= msm_hs_read(uport
, UARTDM_SR_ADDR
);
1128 if (!(sr_status
& UARTDM_SR_TXEMT_BMSK
))
1129 return 0; /* retry */
1131 /* Make sure forced RXSTALE flush complete */
1132 switch (msm_uport
->clk_req_off_state
) {
1133 case CLK_REQ_OFF_START
:
1134 msm_uport
->clk_req_off_state
= CLK_REQ_OFF_RXSTALE_ISSUED
;
1135 msm_hs_write(uport
, UARTDM_CR_ADDR
, FORCE_STALE_EVENT
);
1136 return 0; /* RXSTALE flush not complete - retry */
1137 case CLK_REQ_OFF_RXSTALE_ISSUED
:
1138 case CLK_REQ_OFF_FLUSH_ISSUED
:
1139 return 0; /* RXSTALE flush not complete - retry */
1140 case CLK_REQ_OFF_RXSTALE_FLUSHED
:
1141 break; /* continue */
1144 if (msm_uport
->rx
.flush
!= FLUSH_SHUTDOWN
) {
1145 if (msm_uport
->rx
.flush
== FLUSH_NONE
)
1146 msm_hs_stop_rx_locked(uport
);
1147 return 0; /* come back later to really clock off */
1150 /* we really want to clock off */
1151 clk_disable(msm_uport
->clk
);
1152 msm_uport
->clk_state
= MSM_HS_CLK_OFF
;
1154 if (use_low_power_rx_wakeup(msm_uport
)) {
1155 msm_uport
->rx_wakeup
.ignore
= 1;
1156 enable_irq(msm_uport
->rx_wakeup
.irq
);
1161 static enum hrtimer_restart
msm_hs_clk_off_retry(struct hrtimer
*timer
)
1163 unsigned long flags
;
1164 int ret
= HRTIMER_NORESTART
;
1165 struct msm_hs_port
*msm_uport
= container_of(timer
, struct msm_hs_port
,
1167 struct uart_port
*uport
= &msm_uport
->uport
;
1169 spin_lock_irqsave(&uport
->lock
, flags
);
1171 if (!msm_hs_check_clock_off_locked(uport
)) {
1172 hrtimer_forward_now(timer
, msm_uport
->clk_off_delay
);
1173 ret
= HRTIMER_RESTART
;
1176 spin_unlock_irqrestore(&uport
->lock
, flags
);
1181 static irqreturn_t
msm_hs_isr(int irq
, void *dev
)
1183 unsigned long flags
;
1184 unsigned long isr_status
;
1185 struct msm_hs_port
*msm_uport
= dev
;
1186 struct uart_port
*uport
= &msm_uport
->uport
;
1187 struct circ_buf
*tx_buf
= &uport
->state
->xmit
;
1188 struct msm_hs_tx
*tx
= &msm_uport
->tx
;
1189 struct msm_hs_rx
*rx
= &msm_uport
->rx
;
1191 spin_lock_irqsave(&uport
->lock
, flags
);
1193 isr_status
= msm_hs_read(uport
, UARTDM_MISR_ADDR
);
1195 /* Uart RX starting */
1196 if (isr_status
& UARTDM_ISR_RXLEV_BMSK
) {
1197 msm_uport
->imr_reg
&= ~UARTDM_ISR_RXLEV_BMSK
;
1198 msm_hs_write(uport
, UARTDM_IMR_ADDR
, msm_uport
->imr_reg
);
1200 /* Stale rx interrupt */
1201 if (isr_status
& UARTDM_ISR_RXSTALE_BMSK
) {
1202 msm_hs_write(uport
, UARTDM_CR_ADDR
, STALE_EVENT_DISABLE
);
1203 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_STALE_INT
);
1205 if (msm_uport
->clk_req_off_state
== CLK_REQ_OFF_RXSTALE_ISSUED
)
1206 msm_uport
->clk_req_off_state
=
1207 CLK_REQ_OFF_FLUSH_ISSUED
;
1208 if (rx
->flush
== FLUSH_NONE
) {
1209 rx
->flush
= FLUSH_DATA_READY
;
1210 msm_dmov_stop_cmd(msm_uport
->dma_rx_channel
, NULL
, 1);
1213 /* tx ready interrupt */
1214 if (isr_status
& UARTDM_ISR_TX_READY_BMSK
) {
1215 /* Clear TX Ready */
1216 msm_hs_write(uport
, UARTDM_CR_ADDR
, CLEAR_TX_READY
);
1218 if (msm_uport
->clk_state
== MSM_HS_CLK_REQUEST_OFF
) {
1219 msm_uport
->imr_reg
|= UARTDM_ISR_TXLEV_BMSK
;
1220 msm_hs_write(uport
, UARTDM_IMR_ADDR
,
1221 msm_uport
->imr_reg
);
1224 /* Complete DMA TX transactions and submit new transactions */
1225 tx_buf
->tail
= (tx_buf
->tail
+ tx
->tx_count
) & ~UART_XMIT_SIZE
;
1227 tx
->dma_in_flight
= 0;
1229 uport
->icount
.tx
+= tx
->tx_count
;
1230 if (tx
->tx_ready_int_en
)
1231 msm_hs_submit_tx_locked(uport
);
1233 if (uart_circ_chars_pending(tx_buf
) < WAKEUP_CHARS
)
1234 uart_write_wakeup(uport
);
1236 if (isr_status
& UARTDM_ISR_TXLEV_BMSK
) {
1237 /* TX FIFO is empty */
1238 msm_uport
->imr_reg
&= ~UARTDM_ISR_TXLEV_BMSK
;
1239 msm_hs_write(uport
, UARTDM_IMR_ADDR
, msm_uport
->imr_reg
);
1240 if (!msm_hs_check_clock_off_locked(uport
))
1241 hrtimer_start(&msm_uport
->clk_off_timer
,
1242 msm_uport
->clk_off_delay
,
1246 /* Change in CTS interrupt */
1247 if (isr_status
& UARTDM_ISR_DELTA_CTS_BMSK
)
1248 msm_hs_handle_delta_cts_locked(uport
);
1250 spin_unlock_irqrestore(&uport
->lock
, flags
);
1255 void msm_hs_request_clock_off_locked(struct uart_port
*uport
)
1257 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1259 if (msm_uport
->clk_state
== MSM_HS_CLK_ON
) {
1260 msm_uport
->clk_state
= MSM_HS_CLK_REQUEST_OFF
;
1261 msm_uport
->clk_req_off_state
= CLK_REQ_OFF_START
;
1262 if (!use_low_power_rx_wakeup(msm_uport
))
1263 set_rfr_locked(uport
, 0);
1264 msm_uport
->imr_reg
|= UARTDM_ISR_TXLEV_BMSK
;
1265 msm_hs_write(uport
, UARTDM_IMR_ADDR
, msm_uport
->imr_reg
);
1270 * msm_hs_request_clock_off - request to (i.e. asynchronously) turn off uart
1271 * clock once pending TX is flushed and Rx DMA command is terminated.
1272 * @uport: uart_port structure for the device instance.
1274 * This functions puts the device into a partially active low power mode. It
1275 * waits to complete all pending tx transactions, flushes ongoing Rx DMA
1276 * command and terminates UART side Rx transaction, puts UART HW in non DMA
1277 * mode and then clocks off the device. A client calls this when no UART
1278 * data is expected. msm_request_clock_on() must be called before any further
1279 * UART can be sent or received.
1281 void msm_hs_request_clock_off(struct uart_port
*uport
)
1283 unsigned long flags
;
1285 spin_lock_irqsave(&uport
->lock
, flags
);
1286 msm_hs_request_clock_off_locked(uport
);
1287 spin_unlock_irqrestore(&uport
->lock
, flags
);
1290 void msm_hs_request_clock_on_locked(struct uart_port
*uport
)
1292 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1295 switch (msm_uport
->clk_state
) {
1296 case MSM_HS_CLK_OFF
:
1297 clk_enable(msm_uport
->clk
);
1298 disable_irq_nosync(msm_uport
->rx_wakeup
.irq
);
1300 case MSM_HS_CLK_REQUEST_OFF
:
1301 if (msm_uport
->rx
.flush
== FLUSH_STOP
||
1302 msm_uport
->rx
.flush
== FLUSH_SHUTDOWN
) {
1303 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_RX
);
1304 data
= msm_hs_read(uport
, UARTDM_DMEN_ADDR
);
1305 data
|= UARTDM_RX_DM_EN_BMSK
;
1306 msm_hs_write(uport
, UARTDM_DMEN_ADDR
, data
);
1308 hrtimer_try_to_cancel(&msm_uport
->clk_off_timer
);
1309 if (msm_uport
->rx
.flush
== FLUSH_SHUTDOWN
)
1310 msm_hs_start_rx_locked(uport
);
1311 if (!use_low_power_rx_wakeup(msm_uport
))
1312 set_rfr_locked(uport
, 1);
1313 if (msm_uport
->rx
.flush
== FLUSH_STOP
)
1314 msm_uport
->rx
.flush
= FLUSH_IGNORE
;
1315 msm_uport
->clk_state
= MSM_HS_CLK_ON
;
1319 case MSM_HS_CLK_PORT_OFF
:
1325 * msm_hs_request_clock_on - Switch the device from partially active low
1326 * power mode to fully active (i.e. clock on) mode.
1327 * @uport: uart_port structure for the device.
1329 * This function switches on the input clock, puts UART HW into DMA mode
1330 * and enqueues an Rx DMA command if the device was in partially active
1331 * mode. It has no effect if called with the device in inactive state.
1333 void msm_hs_request_clock_on(struct uart_port
*uport
)
1335 unsigned long flags
;
1337 spin_lock_irqsave(&uport
->lock
, flags
);
1338 msm_hs_request_clock_on_locked(uport
);
1339 spin_unlock_irqrestore(&uport
->lock
, flags
);
1342 static irqreturn_t
msm_hs_rx_wakeup_isr(int irq
, void *dev
)
1344 unsigned int wakeup
= 0;
1345 unsigned long flags
;
1346 struct msm_hs_port
*msm_uport
= dev
;
1347 struct uart_port
*uport
= &msm_uport
->uport
;
1349 spin_lock_irqsave(&uport
->lock
, flags
);
1350 if (msm_uport
->clk_state
== MSM_HS_CLK_OFF
) {
1351 /* ignore the first irq - it is a pending irq that occurred
1352 * before enable_irq() */
1353 if (msm_uport
->rx_wakeup
.ignore
)
1354 msm_uport
->rx_wakeup
.ignore
= 0;
1360 /* the uart was clocked off during an rx, wake up and
1361 * optionally inject char into tty rx */
1362 msm_hs_request_clock_on_locked(uport
);
1363 if (msm_uport
->rx_wakeup
.inject_rx
) {
1364 tty_insert_flip_char(&uport
->state
->port
,
1365 msm_uport
->rx_wakeup
.rx_to_inject
,
1367 queue_work(msm_hs_workqueue
, &msm_uport
->rx
.tty_work
);
1371 spin_unlock_irqrestore(&uport
->lock
, flags
);
1376 static const char *msm_hs_type(struct uart_port
*port
)
1378 return (port
->type
== PORT_MSM
) ? "MSM_HS_UART" : NULL
;
1381 /* Called when port is opened */
1382 static int msm_hs_startup(struct uart_port
*uport
)
1386 unsigned long flags
;
1388 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1389 struct circ_buf
*tx_buf
= &uport
->state
->xmit
;
1390 struct msm_hs_tx
*tx
= &msm_uport
->tx
;
1391 struct msm_hs_rx
*rx
= &msm_uport
->rx
;
1393 rfr_level
= uport
->fifosize
;
1397 tx
->dma_base
= dma_map_single(uport
->dev
, tx_buf
->buf
, UART_XMIT_SIZE
,
1400 /* do not let tty layer execute RX in global workqueue, use a
1401 * dedicated workqueue managed by this driver */
1402 uport
->state
->port
.low_latency
= 1;
1404 /* turn on uart clk */
1405 ret
= msm_hs_init_clk_locked(uport
);
1406 if (unlikely(ret
)) {
1407 printk(KERN_ERR
"Turning uartclk failed!\n");
1408 goto err_msm_hs_init_clk
;
1411 /* Set auto RFR Level */
1412 data
= msm_hs_read(uport
, UARTDM_MR1_ADDR
);
1413 data
&= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK
;
1414 data
&= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK
;
1415 data
|= (UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK
& (rfr_level
<< 2));
1416 data
|= (UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK
& rfr_level
);
1417 msm_hs_write(uport
, UARTDM_MR1_ADDR
, data
);
1419 /* Make sure RXSTALE count is non-zero */
1420 data
= msm_hs_read(uport
, UARTDM_IPR_ADDR
);
1422 data
|= 0x1f & UARTDM_IPR_STALE_LSB_BMSK
;
1423 msm_hs_write(uport
, UARTDM_IPR_ADDR
, data
);
1426 /* Enable Data Mover Mode */
1427 data
= UARTDM_TX_DM_EN_BMSK
| UARTDM_RX_DM_EN_BMSK
;
1428 msm_hs_write(uport
, UARTDM_DMEN_ADDR
, data
);
1431 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_TX
);
1432 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_RX
);
1433 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_ERROR_STATUS
);
1434 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_BREAK_INT
);
1435 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_STALE_INT
);
1436 msm_hs_write(uport
, UARTDM_CR_ADDR
, RESET_CTS
);
1437 msm_hs_write(uport
, UARTDM_CR_ADDR
, RFR_LOW
);
1438 /* Turn on Uart Receiver */
1439 msm_hs_write(uport
, UARTDM_CR_ADDR
, UARTDM_CR_RX_EN_BMSK
);
1441 /* Turn on Uart Transmitter */
1442 msm_hs_write(uport
, UARTDM_CR_ADDR
, UARTDM_CR_TX_EN_BMSK
);
1444 /* Initialize the tx */
1445 tx
->tx_ready_int_en
= 0;
1446 tx
->dma_in_flight
= 0;
1448 tx
->xfer
.complete_func
= msm_hs_dmov_tx_callback
;
1449 tx
->xfer
.execute_func
= NULL
;
1451 tx
->command_ptr
->cmd
= CMD_LC
|
1452 CMD_DST_CRCI(msm_uport
->dma_tx_crci
) | CMD_MODE_BOX
;
1454 tx
->command_ptr
->src_dst_len
= (MSM_UARTDM_BURST_SIZE
<< 16)
1455 | (MSM_UARTDM_BURST_SIZE
);
1457 tx
->command_ptr
->row_offset
= (MSM_UARTDM_BURST_SIZE
<< 16);
1459 tx
->command_ptr
->dst_row_addr
=
1460 msm_uport
->uport
.mapbase
+ UARTDM_TF_ADDR
;
1463 /* Turn on Uart Receive */
1464 rx
->xfer
.complete_func
= msm_hs_dmov_rx_callback
;
1465 rx
->xfer
.execute_func
= NULL
;
1467 rx
->command_ptr
->cmd
= CMD_LC
|
1468 CMD_SRC_CRCI(msm_uport
->dma_rx_crci
) | CMD_MODE_BOX
;
1470 rx
->command_ptr
->src_dst_len
= (MSM_UARTDM_BURST_SIZE
<< 16)
1471 | (MSM_UARTDM_BURST_SIZE
);
1472 rx
->command_ptr
->row_offset
= MSM_UARTDM_BURST_SIZE
;
1473 rx
->command_ptr
->src_row_addr
= uport
->mapbase
+ UARTDM_RF_ADDR
;
1476 msm_uport
->imr_reg
|= UARTDM_ISR_RXSTALE_BMSK
;
1477 /* Enable reading the current CTS, no harm even if CTS is ignored */
1478 msm_uport
->imr_reg
|= UARTDM_ISR_CURRENT_CTS_BMSK
;
1480 msm_hs_write(uport
, UARTDM_TFWR_ADDR
, 0); /* TXLEV on empty TX fifo */
1483 ret
= request_irq(uport
->irq
, msm_hs_isr
, IRQF_TRIGGER_HIGH
,
1484 "msm_hs_uart", msm_uport
);
1485 if (unlikely(ret
)) {
1486 printk(KERN_ERR
"Request msm_hs_uart IRQ failed!\n");
1487 goto err_request_irq
;
1489 if (use_low_power_rx_wakeup(msm_uport
)) {
1490 ret
= request_irq(msm_uport
->rx_wakeup
.irq
,
1491 msm_hs_rx_wakeup_isr
,
1492 IRQF_TRIGGER_FALLING
,
1493 "msm_hs_rx_wakeup", msm_uport
);
1494 if (unlikely(ret
)) {
1495 printk(KERN_ERR
"Request msm_hs_rx_wakeup IRQ failed!\n");
1496 free_irq(uport
->irq
, msm_uport
);
1497 goto err_request_irq
;
1499 disable_irq(msm_uport
->rx_wakeup
.irq
);
1502 spin_lock_irqsave(&uport
->lock
, flags
);
1504 msm_hs_write(uport
, UARTDM_RFWR_ADDR
, 0);
1505 msm_hs_start_rx_locked(uport
);
1507 spin_unlock_irqrestore(&uport
->lock
, flags
);
1508 ret
= pm_runtime_set_active(uport
->dev
);
1510 dev_err(uport
->dev
, "set active error:%d\n", ret
);
1511 pm_runtime_enable(uport
->dev
);
1516 err_msm_hs_init_clk
:
1517 dma_unmap_single(uport
->dev
, tx
->dma_base
,
1518 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
1522 /* Initialize tx and rx data structures */
1523 static int uartdm_init_port(struct uart_port
*uport
)
1526 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1527 struct msm_hs_tx
*tx
= &msm_uport
->tx
;
1528 struct msm_hs_rx
*rx
= &msm_uport
->rx
;
1530 /* Allocate the command pointer. Needs to be 64 bit aligned */
1531 tx
->command_ptr
= kmalloc(sizeof(dmov_box
), GFP_KERNEL
| __GFP_DMA
);
1532 if (!tx
->command_ptr
)
1535 tx
->command_ptr_ptr
= kmalloc(sizeof(u32
), GFP_KERNEL
| __GFP_DMA
);
1536 if (!tx
->command_ptr_ptr
) {
1538 goto err_tx_command_ptr_ptr
;
1541 tx
->mapped_cmd_ptr
= dma_map_single(uport
->dev
, tx
->command_ptr
,
1542 sizeof(dmov_box
), DMA_TO_DEVICE
);
1543 tx
->mapped_cmd_ptr_ptr
= dma_map_single(uport
->dev
,
1544 tx
->command_ptr_ptr
,
1545 sizeof(u32
), DMA_TO_DEVICE
);
1546 tx
->xfer
.cmdptr
= DMOV_CMD_ADDR(tx
->mapped_cmd_ptr_ptr
);
1548 init_waitqueue_head(&rx
->wait
);
1550 rx
->pool
= dma_pool_create("rx_buffer_pool", uport
->dev
,
1551 UARTDM_RX_BUF_SIZE
, 16, 0);
1553 pr_err("%s(): cannot allocate rx_buffer_pool", __func__
);
1555 goto err_dma_pool_create
;
1558 rx
->buffer
= dma_pool_alloc(rx
->pool
, GFP_KERNEL
, &rx
->rbuffer
);
1560 pr_err("%s(): cannot allocate rx->buffer", __func__
);
1562 goto err_dma_pool_alloc
;
1565 /* Allocate the command pointer. Needs to be 64 bit aligned */
1566 rx
->command_ptr
= kmalloc(sizeof(dmov_box
), GFP_KERNEL
| __GFP_DMA
);
1567 if (!rx
->command_ptr
) {
1568 pr_err("%s(): cannot allocate rx->command_ptr", __func__
);
1570 goto err_rx_command_ptr
;
1573 rx
->command_ptr_ptr
= kmalloc(sizeof(u32
), GFP_KERNEL
| __GFP_DMA
);
1574 if (!rx
->command_ptr_ptr
) {
1575 pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__
);
1577 goto err_rx_command_ptr_ptr
;
1580 rx
->command_ptr
->num_rows
= ((UARTDM_RX_BUF_SIZE
>> 4) << 16) |
1581 (UARTDM_RX_BUF_SIZE
>> 4);
1583 rx
->command_ptr
->dst_row_addr
= rx
->rbuffer
;
1585 rx
->mapped_cmd_ptr
= dma_map_single(uport
->dev
, rx
->command_ptr
,
1586 sizeof(dmov_box
), DMA_TO_DEVICE
);
1588 *rx
->command_ptr_ptr
= CMD_PTR_LP
| DMOV_CMD_ADDR(rx
->mapped_cmd_ptr
);
1590 rx
->cmdptr_dmaaddr
= dma_map_single(uport
->dev
, rx
->command_ptr_ptr
,
1591 sizeof(u32
), DMA_TO_DEVICE
);
1592 rx
->xfer
.cmdptr
= DMOV_CMD_ADDR(rx
->cmdptr_dmaaddr
);
1594 INIT_WORK(&rx
->tty_work
, msm_hs_tty_flip_buffer_work
);
1598 err_rx_command_ptr_ptr
:
1599 kfree(rx
->command_ptr
);
1601 dma_pool_free(msm_uport
->rx
.pool
, msm_uport
->rx
.buffer
,
1602 msm_uport
->rx
.rbuffer
);
1604 dma_pool_destroy(msm_uport
->rx
.pool
);
1605 err_dma_pool_create
:
1606 dma_unmap_single(uport
->dev
, msm_uport
->tx
.mapped_cmd_ptr_ptr
,
1607 sizeof(u32
), DMA_TO_DEVICE
);
1608 dma_unmap_single(uport
->dev
, msm_uport
->tx
.mapped_cmd_ptr
,
1609 sizeof(dmov_box
), DMA_TO_DEVICE
);
1610 kfree(msm_uport
->tx
.command_ptr_ptr
);
1611 err_tx_command_ptr_ptr
:
1612 kfree(msm_uport
->tx
.command_ptr
);
1616 static int msm_hs_probe(struct platform_device
*pdev
)
1619 struct uart_port
*uport
;
1620 struct msm_hs_port
*msm_uport
;
1621 struct resource
*resource
;
1622 const struct msm_serial_hs_platform_data
*pdata
=
1623 pdev
->dev
.platform_data
;
1625 if (pdev
->id
< 0 || pdev
->id
>= UARTDM_NR
) {
1626 printk(KERN_ERR
"Invalid plaform device ID = %d\n", pdev
->id
);
1630 msm_uport
= &q_uart_port
[pdev
->id
];
1631 uport
= &msm_uport
->uport
;
1633 uport
->dev
= &pdev
->dev
;
1635 resource
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1636 if (unlikely(!resource
))
1639 uport
->mapbase
= resource
->start
;
1640 uport
->irq
= platform_get_irq(pdev
, 0);
1641 if (unlikely(uport
->irq
< 0))
1644 if (unlikely(irq_set_irq_wake(uport
->irq
, 1)))
1647 if (pdata
== NULL
|| pdata
->rx_wakeup_irq
< 0)
1648 msm_uport
->rx_wakeup
.irq
= -1;
1650 msm_uport
->rx_wakeup
.irq
= pdata
->rx_wakeup_irq
;
1651 msm_uport
->rx_wakeup
.ignore
= 1;
1652 msm_uport
->rx_wakeup
.inject_rx
= pdata
->inject_rx_on_wakeup
;
1653 msm_uport
->rx_wakeup
.rx_to_inject
= pdata
->rx_to_inject
;
1655 if (unlikely(msm_uport
->rx_wakeup
.irq
< 0))
1658 if (unlikely(irq_set_irq_wake(msm_uport
->rx_wakeup
.irq
, 1)))
1663 msm_uport
->exit_lpm_cb
= NULL
;
1665 msm_uport
->exit_lpm_cb
= pdata
->exit_lpm_cb
;
1667 resource
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
,
1669 if (unlikely(!resource
))
1672 msm_uport
->dma_tx_channel
= resource
->start
;
1673 msm_uport
->dma_rx_channel
= resource
->end
;
1675 resource
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
,
1677 if (unlikely(!resource
))
1680 msm_uport
->dma_tx_crci
= resource
->start
;
1681 msm_uport
->dma_rx_crci
= resource
->end
;
1683 uport
->iotype
= UPIO_MEM
;
1684 uport
->fifosize
= UART_FIFOSIZE
;
1685 uport
->ops
= &msm_hs_ops
;
1686 uport
->flags
= UPF_BOOT_AUTOCONF
;
1687 uport
->uartclk
= UARTCLK
;
1688 msm_uport
->imr_reg
= 0x0;
1689 msm_uport
->clk
= clk_get(&pdev
->dev
, "uartdm_clk");
1690 if (IS_ERR(msm_uport
->clk
))
1691 return PTR_ERR(msm_uport
->clk
);
1693 ret
= uartdm_init_port(uport
);
1697 msm_uport
->clk_state
= MSM_HS_CLK_PORT_OFF
;
1698 hrtimer_init(&msm_uport
->clk_off_timer
, CLOCK_MONOTONIC
,
1700 msm_uport
->clk_off_timer
.function
= msm_hs_clk_off_retry
;
1701 msm_uport
->clk_off_delay
= ktime_set(0, 1000000); /* 1ms */
1703 uport
->line
= pdev
->id
;
1704 return uart_add_one_port(&msm_hs_driver
, uport
);
1707 static int __init
msm_serial_hs_init(void)
1711 /* Init all UARTS as non-configured */
1712 for (i
= 0; i
< UARTDM_NR
; i
++)
1713 q_uart_port
[i
].uport
.type
= PORT_UNKNOWN
;
1715 msm_hs_workqueue
= create_singlethread_workqueue("msm_serial_hs");
1716 if (unlikely(!msm_hs_workqueue
))
1719 ret
= uart_register_driver(&msm_hs_driver
);
1720 if (unlikely(ret
)) {
1721 printk(KERN_ERR
"%s failed to load\n", __func__
);
1722 goto err_uart_register_driver
;
1725 ret
= platform_driver_register(&msm_serial_hs_platform_driver
);
1727 printk(KERN_ERR
"%s failed to load\n", __func__
);
1728 goto err_platform_driver_register
;
1733 err_platform_driver_register
:
1734 uart_unregister_driver(&msm_hs_driver
);
1735 err_uart_register_driver
:
1736 destroy_workqueue(msm_hs_workqueue
);
1739 module_init(msm_serial_hs_init
);
1742 * Called by the upper layer when port is closed.
1743 * - Disables the port
1746 static void msm_hs_shutdown(struct uart_port
*uport
)
1748 unsigned long flags
;
1749 struct msm_hs_port
*msm_uport
= UARTDM_TO_MSM(uport
);
1751 BUG_ON(msm_uport
->rx
.flush
< FLUSH_STOP
);
1753 spin_lock_irqsave(&uport
->lock
, flags
);
1754 clk_enable(msm_uport
->clk
);
1756 /* Disable the transmitter */
1757 msm_hs_write(uport
, UARTDM_CR_ADDR
, UARTDM_CR_TX_DISABLE_BMSK
);
1758 /* Disable the receiver */
1759 msm_hs_write(uport
, UARTDM_CR_ADDR
, UARTDM_CR_RX_DISABLE_BMSK
);
1761 pm_runtime_disable(uport
->dev
);
1762 pm_runtime_set_suspended(uport
->dev
);
1764 /* Free the interrupt */
1765 free_irq(uport
->irq
, msm_uport
);
1766 if (use_low_power_rx_wakeup(msm_uport
))
1767 free_irq(msm_uport
->rx_wakeup
.irq
, msm_uport
);
1769 msm_uport
->imr_reg
= 0;
1770 msm_hs_write(uport
, UARTDM_IMR_ADDR
, msm_uport
->imr_reg
);
1772 wait_event(msm_uport
->rx
.wait
, msm_uport
->rx
.flush
== FLUSH_SHUTDOWN
);
1774 clk_disable(msm_uport
->clk
); /* to balance local clk_enable() */
1775 if (msm_uport
->clk_state
!= MSM_HS_CLK_OFF
)
1776 clk_disable(msm_uport
->clk
); /* to balance clk_state */
1777 msm_uport
->clk_state
= MSM_HS_CLK_PORT_OFF
;
1779 dma_unmap_single(uport
->dev
, msm_uport
->tx
.dma_base
,
1780 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
1782 spin_unlock_irqrestore(&uport
->lock
, flags
);
1784 if (cancel_work_sync(&msm_uport
->rx
.tty_work
))
1785 msm_hs_tty_flip_buffer_work(&msm_uport
->rx
.tty_work
);
1788 static void __exit
msm_serial_hs_exit(void)
1790 flush_workqueue(msm_hs_workqueue
);
1791 destroy_workqueue(msm_hs_workqueue
);
1792 platform_driver_unregister(&msm_serial_hs_platform_driver
);
1793 uart_unregister_driver(&msm_hs_driver
);
1795 module_exit(msm_serial_hs_exit
);
1797 #ifdef CONFIG_PM_RUNTIME
1798 static int msm_hs_runtime_idle(struct device
*dev
)
1801 * returning success from idle results in runtime suspend to be
1807 static int msm_hs_runtime_resume(struct device
*dev
)
1809 struct platform_device
*pdev
= container_of(dev
, struct
1810 platform_device
, dev
);
1811 struct msm_hs_port
*msm_uport
= &q_uart_port
[pdev
->id
];
1813 msm_hs_request_clock_on(&msm_uport
->uport
);
1817 static int msm_hs_runtime_suspend(struct device
*dev
)
1819 struct platform_device
*pdev
= container_of(dev
, struct
1820 platform_device
, dev
);
1821 struct msm_hs_port
*msm_uport
= &q_uart_port
[pdev
->id
];
1823 msm_hs_request_clock_off(&msm_uport
->uport
);
1827 #define msm_hs_runtime_idle NULL
1828 #define msm_hs_runtime_resume NULL
1829 #define msm_hs_runtime_suspend NULL
1832 static const struct dev_pm_ops msm_hs_dev_pm_ops
= {
1833 .runtime_suspend
= msm_hs_runtime_suspend
,
1834 .runtime_resume
= msm_hs_runtime_resume
,
1835 .runtime_idle
= msm_hs_runtime_idle
,
1838 static struct platform_driver msm_serial_hs_platform_driver
= {
1839 .probe
= msm_hs_probe
,
1840 .remove
= msm_hs_remove
,
1842 .name
= "msm_serial_hs",
1843 .owner
= THIS_MODULE
,
1844 .pm
= &msm_hs_dev_pm_ops
,
1848 static struct uart_driver msm_hs_driver
= {
1849 .owner
= THIS_MODULE
,
1850 .driver_name
= "msm_serial_hs",
1851 .dev_name
= "ttyHS",
1856 static struct uart_ops msm_hs_ops
= {
1857 .tx_empty
= msm_hs_tx_empty
,
1858 .set_mctrl
= msm_hs_set_mctrl_locked
,
1859 .get_mctrl
= msm_hs_get_mctrl_locked
,
1860 .stop_tx
= msm_hs_stop_tx_locked
,
1861 .start_tx
= msm_hs_start_tx_locked
,
1862 .stop_rx
= msm_hs_stop_rx_locked
,
1863 .enable_ms
= msm_hs_enable_ms_locked
,
1864 .break_ctl
= msm_hs_break_ctl
,
1865 .startup
= msm_hs_startup
,
1866 .shutdown
= msm_hs_shutdown
,
1867 .set_termios
= msm_hs_set_termios
,
1869 .type
= msm_hs_type
,
1870 .config_port
= msm_hs_config_port
,
1871 .release_port
= msm_hs_release_port
,
1872 .request_port
= msm_hs_request_port
,
1875 MODULE_DESCRIPTION("High Speed UART Driver for the MSM chipset");
1876 MODULE_VERSION("1.2");
1877 MODULE_LICENSE("GPL v2");