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TTY: switch tty_flip_buffer_push
[deliverable/linux.git] / drivers / tty / serial / pch_uart.c
1 /*
2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/dmi.h>
28 #include <linux/console.h>
29 #include <linux/nmi.h>
30 #include <linux/delay.h>
31
32 #include <linux/debugfs.h>
33 #include <linux/dmaengine.h>
34 #include <linux/pch_dma.h>
35
36 enum {
37 PCH_UART_HANDLED_RX_INT_SHIFT,
38 PCH_UART_HANDLED_TX_INT_SHIFT,
39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
41 PCH_UART_HANDLED_MS_INT_SHIFT,
42 PCH_UART_HANDLED_LS_INT_SHIFT,
43 };
44
45 enum {
46 PCH_UART_8LINE,
47 PCH_UART_2LINE,
48 };
49
50 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
51
52 /* Set the max number of UART port
53 * Intel EG20T PCH: 4 port
54 * LAPIS Semiconductor ML7213 IOH: 3 port
55 * LAPIS Semiconductor ML7223 IOH: 2 port
56 */
57 #define PCH_UART_NR 4
58
59 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
60 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
61 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
62 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
63 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
64 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
65 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
66
67 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
68
69 #define PCH_UART_RBR 0x00
70 #define PCH_UART_THR 0x00
71
72 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
73 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
74 #define PCH_UART_IER_ERBFI 0x00000001
75 #define PCH_UART_IER_ETBEI 0x00000002
76 #define PCH_UART_IER_ELSI 0x00000004
77 #define PCH_UART_IER_EDSSI 0x00000008
78
79 #define PCH_UART_IIR_IP 0x00000001
80 #define PCH_UART_IIR_IID 0x00000006
81 #define PCH_UART_IIR_MSI 0x00000000
82 #define PCH_UART_IIR_TRI 0x00000002
83 #define PCH_UART_IIR_RRI 0x00000004
84 #define PCH_UART_IIR_REI 0x00000006
85 #define PCH_UART_IIR_TOI 0x00000008
86 #define PCH_UART_IIR_FIFO256 0x00000020
87 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
88 #define PCH_UART_IIR_FE 0x000000C0
89
90 #define PCH_UART_FCR_FIFOE 0x00000001
91 #define PCH_UART_FCR_RFR 0x00000002
92 #define PCH_UART_FCR_TFR 0x00000004
93 #define PCH_UART_FCR_DMS 0x00000008
94 #define PCH_UART_FCR_FIFO256 0x00000020
95 #define PCH_UART_FCR_RFTL 0x000000C0
96
97 #define PCH_UART_FCR_RFTL1 0x00000000
98 #define PCH_UART_FCR_RFTL64 0x00000040
99 #define PCH_UART_FCR_RFTL128 0x00000080
100 #define PCH_UART_FCR_RFTL224 0x000000C0
101 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
102 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
103 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
104 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
105 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
106 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
107 #define PCH_UART_FCR_RFTL_SHIFT 6
108
109 #define PCH_UART_LCR_WLS 0x00000003
110 #define PCH_UART_LCR_STB 0x00000004
111 #define PCH_UART_LCR_PEN 0x00000008
112 #define PCH_UART_LCR_EPS 0x00000010
113 #define PCH_UART_LCR_SP 0x00000020
114 #define PCH_UART_LCR_SB 0x00000040
115 #define PCH_UART_LCR_DLAB 0x00000080
116 #define PCH_UART_LCR_NP 0x00000000
117 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
118 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
119 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
120 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
121 PCH_UART_LCR_SP)
122
123 #define PCH_UART_LCR_5BIT 0x00000000
124 #define PCH_UART_LCR_6BIT 0x00000001
125 #define PCH_UART_LCR_7BIT 0x00000002
126 #define PCH_UART_LCR_8BIT 0x00000003
127
128 #define PCH_UART_MCR_DTR 0x00000001
129 #define PCH_UART_MCR_RTS 0x00000002
130 #define PCH_UART_MCR_OUT 0x0000000C
131 #define PCH_UART_MCR_LOOP 0x00000010
132 #define PCH_UART_MCR_AFE 0x00000020
133
134 #define PCH_UART_LSR_DR 0x00000001
135 #define PCH_UART_LSR_ERR (1<<7)
136
137 #define PCH_UART_MSR_DCTS 0x00000001
138 #define PCH_UART_MSR_DDSR 0x00000002
139 #define PCH_UART_MSR_TERI 0x00000004
140 #define PCH_UART_MSR_DDCD 0x00000008
141 #define PCH_UART_MSR_CTS 0x00000010
142 #define PCH_UART_MSR_DSR 0x00000020
143 #define PCH_UART_MSR_RI 0x00000040
144 #define PCH_UART_MSR_DCD 0x00000080
145 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
146 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
147
148 #define PCH_UART_DLL 0x00
149 #define PCH_UART_DLM 0x01
150
151 #define PCH_UART_BRCSR 0x0E
152
153 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
154 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
155 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
156 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
157 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
158
159 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
160 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
161 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
162 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
163 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
164 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
165 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
166 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
167 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
168 #define PCH_UART_HAL_STB1 0
169 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
170
171 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
172 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
173 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
174 PCH_UART_HAL_CLR_RX_FIFO)
175
176 #define PCH_UART_HAL_DMA_MODE0 0
177 #define PCH_UART_HAL_FIFO_DIS 0
178 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
179 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
180 PCH_UART_FCR_FIFO256)
181 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
182 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
183 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
184 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
185 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
186 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
187 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
188 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
189 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
190 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
191 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
192 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
193 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
194 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
195
196 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
197 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
198 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
199 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
200 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
201
202 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
203 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
204 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
205 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
206 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
207
208 #define PCI_VENDOR_ID_ROHM 0x10DB
209
210 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
211
212 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
213 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
214 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
215 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
216 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
217
218 struct pch_uart_buffer {
219 unsigned char *buf;
220 int size;
221 };
222
223 struct eg20t_port {
224 struct uart_port port;
225 int port_type;
226 void __iomem *membase;
227 resource_size_t mapbase;
228 unsigned int iobase;
229 struct pci_dev *pdev;
230 int fifo_size;
231 int uartclk;
232 int start_tx;
233 int start_rx;
234 int tx_empty;
235 int trigger;
236 int trigger_level;
237 struct pch_uart_buffer rxbuf;
238 unsigned int dmsr;
239 unsigned int fcr;
240 unsigned int mcr;
241 unsigned int use_dma;
242 struct dma_async_tx_descriptor *desc_tx;
243 struct dma_async_tx_descriptor *desc_rx;
244 struct pch_dma_slave param_tx;
245 struct pch_dma_slave param_rx;
246 struct dma_chan *chan_tx;
247 struct dma_chan *chan_rx;
248 struct scatterlist *sg_tx_p;
249 int nent;
250 struct scatterlist sg_rx;
251 int tx_dma_use;
252 void *rx_buf_virt;
253 dma_addr_t rx_buf_dma;
254
255 struct dentry *debugfs;
256
257 /* protect the eg20t_port private structure and io access to membase */
258 spinlock_t lock;
259 };
260
261 /**
262 * struct pch_uart_driver_data - private data structure for UART-DMA
263 * @port_type: The number of DMA channel
264 * @line_no: UART port line number (0, 1, 2...)
265 */
266 struct pch_uart_driver_data {
267 int port_type;
268 int line_no;
269 };
270
271 enum pch_uart_num_t {
272 pch_et20t_uart0 = 0,
273 pch_et20t_uart1,
274 pch_et20t_uart2,
275 pch_et20t_uart3,
276 pch_ml7213_uart0,
277 pch_ml7213_uart1,
278 pch_ml7213_uart2,
279 pch_ml7223_uart0,
280 pch_ml7223_uart1,
281 pch_ml7831_uart0,
282 pch_ml7831_uart1,
283 };
284
285 static struct pch_uart_driver_data drv_dat[] = {
286 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
287 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
288 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
289 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
290 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
291 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
292 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
293 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
294 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
295 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
296 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
297 };
298
299 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
300 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
301 #endif
302 static unsigned int default_baud = 9600;
303 static unsigned int user_uartclk = 0;
304 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
305 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
306 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
307 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
308
309 #ifdef CONFIG_DEBUG_FS
310
311 #define PCH_REGS_BUFSIZE 1024
312
313
314 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
315 size_t count, loff_t *ppos)
316 {
317 struct eg20t_port *priv = file->private_data;
318 char *buf;
319 u32 len = 0;
320 ssize_t ret;
321 unsigned char lcr;
322
323 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
324 if (!buf)
325 return 0;
326
327 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
328 "PCH EG20T port[%d] regs:\n", priv->port.line);
329
330 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
331 "=================================\n");
332 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
333 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
337 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
339 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
341 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
343 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
345 "BRCSR: \t0x%02x\n",
346 ioread8(priv->membase + PCH_UART_BRCSR));
347
348 lcr = ioread8(priv->membase + UART_LCR);
349 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
350 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
351 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
352 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
353 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
354 iowrite8(lcr, priv->membase + UART_LCR);
355
356 if (len > PCH_REGS_BUFSIZE)
357 len = PCH_REGS_BUFSIZE;
358
359 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
360 kfree(buf);
361 return ret;
362 }
363
364 static const struct file_operations port_regs_ops = {
365 .owner = THIS_MODULE,
366 .open = simple_open,
367 .read = port_show_regs,
368 .llseek = default_llseek,
369 };
370 #endif /* CONFIG_DEBUG_FS */
371
372 /* Return UART clock, checking for board specific clocks. */
373 static int pch_uart_get_uartclk(void)
374 {
375 const char *cmp;
376
377 if (user_uartclk)
378 return user_uartclk;
379
380 cmp = dmi_get_system_info(DMI_BOARD_NAME);
381 if (cmp && strstr(cmp, "CM-iTC"))
382 return CMITC_UARTCLK;
383
384 cmp = dmi_get_system_info(DMI_BIOS_VERSION);
385 if (cmp && strnstr(cmp, "FRI2", 4))
386 return FRI2_64_UARTCLK;
387
388 cmp = dmi_get_system_info(DMI_PRODUCT_NAME);
389 if (cmp && strstr(cmp, "Fish River Island II"))
390 return FRI2_48_UARTCLK;
391
392 /* Kontron COMe-mTT10 (nanoETXexpress-TT) */
393 cmp = dmi_get_system_info(DMI_BOARD_NAME);
394 if (cmp && (strstr(cmp, "COMe-mTT") ||
395 strstr(cmp, "nanoETXexpress-TT")))
396 return NTC1_UARTCLK;
397
398 return DEFAULT_UARTCLK;
399 }
400
401 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
402 unsigned int flag)
403 {
404 u8 ier = ioread8(priv->membase + UART_IER);
405 ier |= flag & PCH_UART_IER_MASK;
406 iowrite8(ier, priv->membase + UART_IER);
407 }
408
409 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
410 unsigned int flag)
411 {
412 u8 ier = ioread8(priv->membase + UART_IER);
413 ier &= ~(flag & PCH_UART_IER_MASK);
414 iowrite8(ier, priv->membase + UART_IER);
415 }
416
417 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
418 unsigned int parity, unsigned int bits,
419 unsigned int stb)
420 {
421 unsigned int dll, dlm, lcr;
422 int div;
423
424 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
425 if (div < 0 || USHRT_MAX <= div) {
426 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
427 return -EINVAL;
428 }
429
430 dll = (unsigned int)div & 0x00FFU;
431 dlm = ((unsigned int)div >> 8) & 0x00FFU;
432
433 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
434 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
435 return -EINVAL;
436 }
437
438 if (bits & ~PCH_UART_LCR_WLS) {
439 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
440 return -EINVAL;
441 }
442
443 if (stb & ~PCH_UART_LCR_STB) {
444 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
445 return -EINVAL;
446 }
447
448 lcr = parity;
449 lcr |= bits;
450 lcr |= stb;
451
452 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
453 __func__, baud, div, lcr, jiffies);
454 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
455 iowrite8(dll, priv->membase + PCH_UART_DLL);
456 iowrite8(dlm, priv->membase + PCH_UART_DLM);
457 iowrite8(lcr, priv->membase + UART_LCR);
458
459 return 0;
460 }
461
462 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
463 unsigned int flag)
464 {
465 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
466 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
467 __func__, flag);
468 return -EINVAL;
469 }
470
471 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
472 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
473 priv->membase + UART_FCR);
474 iowrite8(priv->fcr, priv->membase + UART_FCR);
475
476 return 0;
477 }
478
479 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
480 unsigned int dmamode,
481 unsigned int fifo_size, unsigned int trigger)
482 {
483 u8 fcr;
484
485 if (dmamode & ~PCH_UART_FCR_DMS) {
486 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
487 __func__, dmamode);
488 return -EINVAL;
489 }
490
491 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
492 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
493 __func__, fifo_size);
494 return -EINVAL;
495 }
496
497 if (trigger & ~PCH_UART_FCR_RFTL) {
498 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
499 __func__, trigger);
500 return -EINVAL;
501 }
502
503 switch (priv->fifo_size) {
504 case 256:
505 priv->trigger_level =
506 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
507 break;
508 case 64:
509 priv->trigger_level =
510 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
511 break;
512 case 16:
513 priv->trigger_level =
514 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
515 break;
516 default:
517 priv->trigger_level =
518 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
519 break;
520 }
521 fcr =
522 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
523 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
524 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
525 priv->membase + UART_FCR);
526 iowrite8(fcr, priv->membase + UART_FCR);
527 priv->fcr = fcr;
528
529 return 0;
530 }
531
532 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
533 {
534 unsigned int msr = ioread8(priv->membase + UART_MSR);
535 priv->dmsr = msr & PCH_UART_MSR_DELTA;
536 return (u8)msr;
537 }
538
539 static void pch_uart_hal_write(struct eg20t_port *priv,
540 const unsigned char *buf, int tx_size)
541 {
542 int i;
543 unsigned int thr;
544
545 for (i = 0; i < tx_size;) {
546 thr = buf[i++];
547 iowrite8(thr, priv->membase + PCH_UART_THR);
548 }
549 }
550
551 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
552 int rx_size)
553 {
554 int i;
555 u8 rbr, lsr;
556
557 lsr = ioread8(priv->membase + UART_LSR);
558 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
559 i < rx_size && lsr & UART_LSR_DR;
560 lsr = ioread8(priv->membase + UART_LSR)) {
561 rbr = ioread8(priv->membase + PCH_UART_RBR);
562 buf[i++] = rbr;
563 }
564 return i;
565 }
566
567 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
568 {
569 return ioread8(priv->membase + UART_IIR) &\
570 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
571 }
572
573 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
574 {
575 return ioread8(priv->membase + UART_LSR);
576 }
577
578 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
579 {
580 unsigned int lcr;
581
582 lcr = ioread8(priv->membase + UART_LCR);
583 if (on)
584 lcr |= PCH_UART_LCR_SB;
585 else
586 lcr &= ~PCH_UART_LCR_SB;
587
588 iowrite8(lcr, priv->membase + UART_LCR);
589 }
590
591 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
592 int size)
593 {
594 struct uart_port *port = &priv->port;
595 struct tty_port *tport = &port->state->port;
596
597 tty_insert_flip_string(tport, buf, size);
598 tty_flip_buffer_push(tport);
599
600 return 0;
601 }
602
603 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
604 {
605 int ret = 0;
606 struct uart_port *port = &priv->port;
607
608 if (port->x_char) {
609 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
610 __func__, port->x_char, jiffies);
611 buf[0] = port->x_char;
612 port->x_char = 0;
613 ret = 1;
614 }
615
616 return ret;
617 }
618
619 static int dma_push_rx(struct eg20t_port *priv, int size)
620 {
621 struct tty_struct *tty;
622 int room;
623 struct uart_port *port = &priv->port;
624 struct tty_port *tport = &port->state->port;
625
626 port = &priv->port;
627 tty = tty_port_tty_get(tport);
628 if (!tty) {
629 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
630 return 0;
631 }
632
633 room = tty_buffer_request_room(tport, size);
634
635 if (room < size)
636 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
637 size - room);
638 if (!room)
639 return room;
640
641 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
642
643 port->icount.rx += room;
644 tty_kref_put(tty);
645
646 return room;
647 }
648
649 static void pch_free_dma(struct uart_port *port)
650 {
651 struct eg20t_port *priv;
652 priv = container_of(port, struct eg20t_port, port);
653
654 if (priv->chan_tx) {
655 dma_release_channel(priv->chan_tx);
656 priv->chan_tx = NULL;
657 }
658 if (priv->chan_rx) {
659 dma_release_channel(priv->chan_rx);
660 priv->chan_rx = NULL;
661 }
662
663 if (priv->rx_buf_dma) {
664 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
665 priv->rx_buf_dma);
666 priv->rx_buf_virt = NULL;
667 priv->rx_buf_dma = 0;
668 }
669
670 return;
671 }
672
673 static bool filter(struct dma_chan *chan, void *slave)
674 {
675 struct pch_dma_slave *param = slave;
676
677 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
678 chan->device->dev)) {
679 chan->private = param;
680 return true;
681 } else {
682 return false;
683 }
684 }
685
686 static void pch_request_dma(struct uart_port *port)
687 {
688 dma_cap_mask_t mask;
689 struct dma_chan *chan;
690 struct pci_dev *dma_dev;
691 struct pch_dma_slave *param;
692 struct eg20t_port *priv =
693 container_of(port, struct eg20t_port, port);
694 dma_cap_zero(mask);
695 dma_cap_set(DMA_SLAVE, mask);
696
697 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
698 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
699 information */
700 /* Set Tx DMA */
701 param = &priv->param_tx;
702 param->dma_dev = &dma_dev->dev;
703 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
704
705 param->tx_reg = port->mapbase + UART_TX;
706 chan = dma_request_channel(mask, filter, param);
707 if (!chan) {
708 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
709 __func__);
710 return;
711 }
712 priv->chan_tx = chan;
713
714 /* Set Rx DMA */
715 param = &priv->param_rx;
716 param->dma_dev = &dma_dev->dev;
717 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
718
719 param->rx_reg = port->mapbase + UART_RX;
720 chan = dma_request_channel(mask, filter, param);
721 if (!chan) {
722 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
723 __func__);
724 dma_release_channel(priv->chan_tx);
725 priv->chan_tx = NULL;
726 return;
727 }
728
729 /* Get Consistent memory for DMA */
730 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
731 &priv->rx_buf_dma, GFP_KERNEL);
732 priv->chan_rx = chan;
733 }
734
735 static void pch_dma_rx_complete(void *arg)
736 {
737 struct eg20t_port *priv = arg;
738 struct uart_port *port = &priv->port;
739 int count;
740
741 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
742 count = dma_push_rx(priv, priv->trigger_level);
743 if (count)
744 tty_flip_buffer_push(&port->state->port);
745 async_tx_ack(priv->desc_rx);
746 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
747 PCH_UART_HAL_RX_ERR_INT);
748 }
749
750 static void pch_dma_tx_complete(void *arg)
751 {
752 struct eg20t_port *priv = arg;
753 struct uart_port *port = &priv->port;
754 struct circ_buf *xmit = &port->state->xmit;
755 struct scatterlist *sg = priv->sg_tx_p;
756 int i;
757
758 for (i = 0; i < priv->nent; i++, sg++) {
759 xmit->tail += sg_dma_len(sg);
760 port->icount.tx += sg_dma_len(sg);
761 }
762 xmit->tail &= UART_XMIT_SIZE - 1;
763 async_tx_ack(priv->desc_tx);
764 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
765 priv->tx_dma_use = 0;
766 priv->nent = 0;
767 kfree(priv->sg_tx_p);
768 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
769 }
770
771 static int pop_tx(struct eg20t_port *priv, int size)
772 {
773 int count = 0;
774 struct uart_port *port = &priv->port;
775 struct circ_buf *xmit = &port->state->xmit;
776
777 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
778 goto pop_tx_end;
779
780 do {
781 int cnt_to_end =
782 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
783 int sz = min(size - count, cnt_to_end);
784 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
785 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
786 count += sz;
787 } while (!uart_circ_empty(xmit) && count < size);
788
789 pop_tx_end:
790 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
791 count, size - count, jiffies);
792
793 return count;
794 }
795
796 static int handle_rx_to(struct eg20t_port *priv)
797 {
798 struct pch_uart_buffer *buf;
799 int rx_size;
800 int ret;
801 if (!priv->start_rx) {
802 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
803 PCH_UART_HAL_RX_ERR_INT);
804 return 0;
805 }
806 buf = &priv->rxbuf;
807 do {
808 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
809 ret = push_rx(priv, buf->buf, rx_size);
810 if (ret)
811 return 0;
812 } while (rx_size == buf->size);
813
814 return PCH_UART_HANDLED_RX_INT;
815 }
816
817 static int handle_rx(struct eg20t_port *priv)
818 {
819 return handle_rx_to(priv);
820 }
821
822 static int dma_handle_rx(struct eg20t_port *priv)
823 {
824 struct uart_port *port = &priv->port;
825 struct dma_async_tx_descriptor *desc;
826 struct scatterlist *sg;
827
828 priv = container_of(port, struct eg20t_port, port);
829 sg = &priv->sg_rx;
830
831 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
832
833 sg_dma_len(sg) = priv->trigger_level;
834
835 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
836 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
837 ~PAGE_MASK);
838
839 sg_dma_address(sg) = priv->rx_buf_dma;
840
841 desc = dmaengine_prep_slave_sg(priv->chan_rx,
842 sg, 1, DMA_DEV_TO_MEM,
843 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
844
845 if (!desc)
846 return 0;
847
848 priv->desc_rx = desc;
849 desc->callback = pch_dma_rx_complete;
850 desc->callback_param = priv;
851 desc->tx_submit(desc);
852 dma_async_issue_pending(priv->chan_rx);
853
854 return PCH_UART_HANDLED_RX_INT;
855 }
856
857 static unsigned int handle_tx(struct eg20t_port *priv)
858 {
859 struct uart_port *port = &priv->port;
860 struct circ_buf *xmit = &port->state->xmit;
861 int fifo_size;
862 int tx_size;
863 int size;
864 int tx_empty;
865
866 if (!priv->start_tx) {
867 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
868 __func__, jiffies);
869 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
870 priv->tx_empty = 1;
871 return 0;
872 }
873
874 fifo_size = max(priv->fifo_size, 1);
875 tx_empty = 1;
876 if (pop_tx_x(priv, xmit->buf)) {
877 pch_uart_hal_write(priv, xmit->buf, 1);
878 port->icount.tx++;
879 tx_empty = 0;
880 fifo_size--;
881 }
882 size = min(xmit->head - xmit->tail, fifo_size);
883 if (size < 0)
884 size = fifo_size;
885
886 tx_size = pop_tx(priv, size);
887 if (tx_size > 0) {
888 port->icount.tx += tx_size;
889 tx_empty = 0;
890 }
891
892 priv->tx_empty = tx_empty;
893
894 if (tx_empty) {
895 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
896 uart_write_wakeup(port);
897 }
898
899 return PCH_UART_HANDLED_TX_INT;
900 }
901
902 static unsigned int dma_handle_tx(struct eg20t_port *priv)
903 {
904 struct uart_port *port = &priv->port;
905 struct circ_buf *xmit = &port->state->xmit;
906 struct scatterlist *sg;
907 int nent;
908 int fifo_size;
909 int tx_empty;
910 struct dma_async_tx_descriptor *desc;
911 int num;
912 int i;
913 int bytes;
914 int size;
915 int rem;
916
917 if (!priv->start_tx) {
918 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
919 __func__, jiffies);
920 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
921 priv->tx_empty = 1;
922 return 0;
923 }
924
925 if (priv->tx_dma_use) {
926 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
927 __func__, jiffies);
928 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
929 priv->tx_empty = 1;
930 return 0;
931 }
932
933 fifo_size = max(priv->fifo_size, 1);
934 tx_empty = 1;
935 if (pop_tx_x(priv, xmit->buf)) {
936 pch_uart_hal_write(priv, xmit->buf, 1);
937 port->icount.tx++;
938 tx_empty = 0;
939 fifo_size--;
940 }
941
942 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
943 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
944 xmit->tail, UART_XMIT_SIZE));
945 if (!bytes) {
946 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
947 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
948 uart_write_wakeup(port);
949 return 0;
950 }
951
952 if (bytes > fifo_size) {
953 num = bytes / fifo_size + 1;
954 size = fifo_size;
955 rem = bytes % fifo_size;
956 } else {
957 num = 1;
958 size = bytes;
959 rem = bytes;
960 }
961
962 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
963 __func__, num, size, rem);
964
965 priv->tx_dma_use = 1;
966
967 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
968 if (!priv->sg_tx_p) {
969 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
970 return 0;
971 }
972
973 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
974 sg = priv->sg_tx_p;
975
976 for (i = 0; i < num; i++, sg++) {
977 if (i == (num - 1))
978 sg_set_page(sg, virt_to_page(xmit->buf),
979 rem, fifo_size * i);
980 else
981 sg_set_page(sg, virt_to_page(xmit->buf),
982 size, fifo_size * i);
983 }
984
985 sg = priv->sg_tx_p;
986 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
987 if (!nent) {
988 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
989 return 0;
990 }
991 priv->nent = nent;
992
993 for (i = 0; i < nent; i++, sg++) {
994 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
995 fifo_size * i;
996 sg_dma_address(sg) = (sg_dma_address(sg) &
997 ~(UART_XMIT_SIZE - 1)) + sg->offset;
998 if (i == (nent - 1))
999 sg_dma_len(sg) = rem;
1000 else
1001 sg_dma_len(sg) = size;
1002 }
1003
1004 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1005 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1006 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1007 if (!desc) {
1008 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1009 __func__);
1010 return 0;
1011 }
1012 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1013 priv->desc_tx = desc;
1014 desc->callback = pch_dma_tx_complete;
1015 desc->callback_param = priv;
1016
1017 desc->tx_submit(desc);
1018
1019 dma_async_issue_pending(priv->chan_tx);
1020
1021 return PCH_UART_HANDLED_TX_INT;
1022 }
1023
1024 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1025 {
1026 u8 fcr = ioread8(priv->membase + UART_FCR);
1027
1028 /* Reset FIFO */
1029 fcr |= UART_FCR_CLEAR_RCVR;
1030 iowrite8(fcr, priv->membase + UART_FCR);
1031
1032 if (lsr & PCH_UART_LSR_ERR)
1033 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
1034
1035 if (lsr & UART_LSR_FE)
1036 dev_err(&priv->pdev->dev, "Framing Error\n");
1037
1038 if (lsr & UART_LSR_PE)
1039 dev_err(&priv->pdev->dev, "Parity Error\n");
1040
1041 if (lsr & UART_LSR_OE)
1042 dev_err(&priv->pdev->dev, "Overrun Error\n");
1043 }
1044
1045 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1046 {
1047 struct eg20t_port *priv = dev_id;
1048 unsigned int handled;
1049 u8 lsr;
1050 int ret = 0;
1051 unsigned char iid;
1052 unsigned long flags;
1053 int next = 1;
1054 u8 msr;
1055
1056 spin_lock_irqsave(&priv->lock, flags);
1057 handled = 0;
1058 while (next) {
1059 iid = pch_uart_hal_get_iid(priv);
1060 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1061 break;
1062 switch (iid) {
1063 case PCH_UART_IID_RLS: /* Receiver Line Status */
1064 lsr = pch_uart_hal_get_line_status(priv);
1065 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1066 UART_LSR_PE | UART_LSR_OE)) {
1067 pch_uart_err_ir(priv, lsr);
1068 ret = PCH_UART_HANDLED_RX_ERR_INT;
1069 } else {
1070 ret = PCH_UART_HANDLED_LS_INT;
1071 }
1072 break;
1073 case PCH_UART_IID_RDR: /* Received Data Ready */
1074 if (priv->use_dma) {
1075 pch_uart_hal_disable_interrupt(priv,
1076 PCH_UART_HAL_RX_INT |
1077 PCH_UART_HAL_RX_ERR_INT);
1078 ret = dma_handle_rx(priv);
1079 if (!ret)
1080 pch_uart_hal_enable_interrupt(priv,
1081 PCH_UART_HAL_RX_INT |
1082 PCH_UART_HAL_RX_ERR_INT);
1083 } else {
1084 ret = handle_rx(priv);
1085 }
1086 break;
1087 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1088 (FIFO Timeout) */
1089 ret = handle_rx_to(priv);
1090 break;
1091 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1092 Empty */
1093 if (priv->use_dma)
1094 ret = dma_handle_tx(priv);
1095 else
1096 ret = handle_tx(priv);
1097 break;
1098 case PCH_UART_IID_MS: /* Modem Status */
1099 msr = pch_uart_hal_get_modem(priv);
1100 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1101 means final interrupt */
1102 if ((msr & UART_MSR_ANY_DELTA) == 0)
1103 break;
1104 ret |= PCH_UART_HANDLED_MS_INT;
1105 break;
1106 default: /* Never junp to this label */
1107 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1108 iid, jiffies);
1109 ret = -1;
1110 next = 0;
1111 break;
1112 }
1113 handled |= (unsigned int)ret;
1114 }
1115
1116 spin_unlock_irqrestore(&priv->lock, flags);
1117 return IRQ_RETVAL(handled);
1118 }
1119
1120 /* This function tests whether the transmitter fifo and shifter for the port
1121 described by 'port' is empty. */
1122 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1123 {
1124 struct eg20t_port *priv;
1125
1126 priv = container_of(port, struct eg20t_port, port);
1127 if (priv->tx_empty)
1128 return TIOCSER_TEMT;
1129 else
1130 return 0;
1131 }
1132
1133 /* Returns the current state of modem control inputs. */
1134 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1135 {
1136 struct eg20t_port *priv;
1137 u8 modem;
1138 unsigned int ret = 0;
1139
1140 priv = container_of(port, struct eg20t_port, port);
1141 modem = pch_uart_hal_get_modem(priv);
1142
1143 if (modem & UART_MSR_DCD)
1144 ret |= TIOCM_CAR;
1145
1146 if (modem & UART_MSR_RI)
1147 ret |= TIOCM_RNG;
1148
1149 if (modem & UART_MSR_DSR)
1150 ret |= TIOCM_DSR;
1151
1152 if (modem & UART_MSR_CTS)
1153 ret |= TIOCM_CTS;
1154
1155 return ret;
1156 }
1157
1158 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1159 {
1160 u32 mcr = 0;
1161 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1162
1163 if (mctrl & TIOCM_DTR)
1164 mcr |= UART_MCR_DTR;
1165 if (mctrl & TIOCM_RTS)
1166 mcr |= UART_MCR_RTS;
1167 if (mctrl & TIOCM_LOOP)
1168 mcr |= UART_MCR_LOOP;
1169
1170 if (priv->mcr & UART_MCR_AFE)
1171 mcr |= UART_MCR_AFE;
1172
1173 if (mctrl)
1174 iowrite8(mcr, priv->membase + UART_MCR);
1175 }
1176
1177 static void pch_uart_stop_tx(struct uart_port *port)
1178 {
1179 struct eg20t_port *priv;
1180 priv = container_of(port, struct eg20t_port, port);
1181 priv->start_tx = 0;
1182 priv->tx_dma_use = 0;
1183 }
1184
1185 static void pch_uart_start_tx(struct uart_port *port)
1186 {
1187 struct eg20t_port *priv;
1188
1189 priv = container_of(port, struct eg20t_port, port);
1190
1191 if (priv->use_dma) {
1192 if (priv->tx_dma_use) {
1193 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1194 __func__);
1195 return;
1196 }
1197 }
1198
1199 priv->start_tx = 1;
1200 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1201 }
1202
1203 static void pch_uart_stop_rx(struct uart_port *port)
1204 {
1205 struct eg20t_port *priv;
1206 priv = container_of(port, struct eg20t_port, port);
1207 priv->start_rx = 0;
1208 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1209 PCH_UART_HAL_RX_ERR_INT);
1210 }
1211
1212 /* Enable the modem status interrupts. */
1213 static void pch_uart_enable_ms(struct uart_port *port)
1214 {
1215 struct eg20t_port *priv;
1216 priv = container_of(port, struct eg20t_port, port);
1217 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1218 }
1219
1220 /* Control the transmission of a break signal. */
1221 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1222 {
1223 struct eg20t_port *priv;
1224 unsigned long flags;
1225
1226 priv = container_of(port, struct eg20t_port, port);
1227 spin_lock_irqsave(&priv->lock, flags);
1228 pch_uart_hal_set_break(priv, ctl);
1229 spin_unlock_irqrestore(&priv->lock, flags);
1230 }
1231
1232 /* Grab any interrupt resources and initialise any low level driver state. */
1233 static int pch_uart_startup(struct uart_port *port)
1234 {
1235 struct eg20t_port *priv;
1236 int ret;
1237 int fifo_size;
1238 int trigger_level;
1239
1240 priv = container_of(port, struct eg20t_port, port);
1241 priv->tx_empty = 1;
1242
1243 if (port->uartclk)
1244 priv->uartclk = port->uartclk;
1245 else
1246 port->uartclk = priv->uartclk;
1247
1248 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1249 ret = pch_uart_hal_set_line(priv, default_baud,
1250 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1251 PCH_UART_HAL_STB1);
1252 if (ret)
1253 return ret;
1254
1255 switch (priv->fifo_size) {
1256 case 256:
1257 fifo_size = PCH_UART_HAL_FIFO256;
1258 break;
1259 case 64:
1260 fifo_size = PCH_UART_HAL_FIFO64;
1261 break;
1262 case 16:
1263 fifo_size = PCH_UART_HAL_FIFO16;
1264 break;
1265 case 1:
1266 default:
1267 fifo_size = PCH_UART_HAL_FIFO_DIS;
1268 break;
1269 }
1270
1271 switch (priv->trigger) {
1272 case PCH_UART_HAL_TRIGGER1:
1273 trigger_level = 1;
1274 break;
1275 case PCH_UART_HAL_TRIGGER_L:
1276 trigger_level = priv->fifo_size / 4;
1277 break;
1278 case PCH_UART_HAL_TRIGGER_M:
1279 trigger_level = priv->fifo_size / 2;
1280 break;
1281 case PCH_UART_HAL_TRIGGER_H:
1282 default:
1283 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1284 break;
1285 }
1286
1287 priv->trigger_level = trigger_level;
1288 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1289 fifo_size, priv->trigger);
1290 if (ret < 0)
1291 return ret;
1292
1293 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1294 KBUILD_MODNAME, priv);
1295 if (ret < 0)
1296 return ret;
1297
1298 if (priv->use_dma)
1299 pch_request_dma(port);
1300
1301 priv->start_rx = 1;
1302 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1303 PCH_UART_HAL_RX_ERR_INT);
1304 uart_update_timeout(port, CS8, default_baud);
1305
1306 return 0;
1307 }
1308
1309 static void pch_uart_shutdown(struct uart_port *port)
1310 {
1311 struct eg20t_port *priv;
1312 int ret;
1313
1314 priv = container_of(port, struct eg20t_port, port);
1315 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1316 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1317 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1318 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1319 if (ret)
1320 dev_err(priv->port.dev,
1321 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1322
1323 pch_free_dma(port);
1324
1325 free_irq(priv->port.irq, priv);
1326 }
1327
1328 /* Change the port parameters, including word length, parity, stop
1329 *bits. Update read_status_mask and ignore_status_mask to indicate
1330 *the types of events we are interested in receiving. */
1331 static void pch_uart_set_termios(struct uart_port *port,
1332 struct ktermios *termios, struct ktermios *old)
1333 {
1334 int baud;
1335 int rtn;
1336 unsigned int parity, bits, stb;
1337 struct eg20t_port *priv;
1338 unsigned long flags;
1339
1340 priv = container_of(port, struct eg20t_port, port);
1341 switch (termios->c_cflag & CSIZE) {
1342 case CS5:
1343 bits = PCH_UART_HAL_5BIT;
1344 break;
1345 case CS6:
1346 bits = PCH_UART_HAL_6BIT;
1347 break;
1348 case CS7:
1349 bits = PCH_UART_HAL_7BIT;
1350 break;
1351 default: /* CS8 */
1352 bits = PCH_UART_HAL_8BIT;
1353 break;
1354 }
1355 if (termios->c_cflag & CSTOPB)
1356 stb = PCH_UART_HAL_STB2;
1357 else
1358 stb = PCH_UART_HAL_STB1;
1359
1360 if (termios->c_cflag & PARENB) {
1361 if (termios->c_cflag & PARODD)
1362 parity = PCH_UART_HAL_PARITY_ODD;
1363 else
1364 parity = PCH_UART_HAL_PARITY_EVEN;
1365
1366 } else
1367 parity = PCH_UART_HAL_PARITY_NONE;
1368
1369 /* Only UART0 has auto hardware flow function */
1370 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1371 priv->mcr |= UART_MCR_AFE;
1372 else
1373 priv->mcr &= ~UART_MCR_AFE;
1374
1375 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1376
1377 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1378
1379 spin_lock_irqsave(&priv->lock, flags);
1380 spin_lock(&port->lock);
1381
1382 uart_update_timeout(port, termios->c_cflag, baud);
1383 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1384 if (rtn)
1385 goto out;
1386
1387 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1388 /* Don't rewrite B0 */
1389 if (tty_termios_baud_rate(termios))
1390 tty_termios_encode_baud_rate(termios, baud, baud);
1391
1392 out:
1393 spin_unlock(&port->lock);
1394 spin_unlock_irqrestore(&priv->lock, flags);
1395 }
1396
1397 static const char *pch_uart_type(struct uart_port *port)
1398 {
1399 return KBUILD_MODNAME;
1400 }
1401
1402 static void pch_uart_release_port(struct uart_port *port)
1403 {
1404 struct eg20t_port *priv;
1405
1406 priv = container_of(port, struct eg20t_port, port);
1407 pci_iounmap(priv->pdev, priv->membase);
1408 pci_release_regions(priv->pdev);
1409 }
1410
1411 static int pch_uart_request_port(struct uart_port *port)
1412 {
1413 struct eg20t_port *priv;
1414 int ret;
1415 void __iomem *membase;
1416
1417 priv = container_of(port, struct eg20t_port, port);
1418 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1419 if (ret < 0)
1420 return -EBUSY;
1421
1422 membase = pci_iomap(priv->pdev, 1, 0);
1423 if (!membase) {
1424 pci_release_regions(priv->pdev);
1425 return -EBUSY;
1426 }
1427 priv->membase = port->membase = membase;
1428
1429 return 0;
1430 }
1431
1432 static void pch_uart_config_port(struct uart_port *port, int type)
1433 {
1434 struct eg20t_port *priv;
1435
1436 priv = container_of(port, struct eg20t_port, port);
1437 if (type & UART_CONFIG_TYPE) {
1438 port->type = priv->port_type;
1439 pch_uart_request_port(port);
1440 }
1441 }
1442
1443 static int pch_uart_verify_port(struct uart_port *port,
1444 struct serial_struct *serinfo)
1445 {
1446 struct eg20t_port *priv;
1447
1448 priv = container_of(port, struct eg20t_port, port);
1449 if (serinfo->flags & UPF_LOW_LATENCY) {
1450 dev_info(priv->port.dev,
1451 "PCH UART : Use PIO Mode (without DMA)\n");
1452 priv->use_dma = 0;
1453 serinfo->flags &= ~UPF_LOW_LATENCY;
1454 } else {
1455 #ifndef CONFIG_PCH_DMA
1456 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1457 __func__);
1458 return -EOPNOTSUPP;
1459 #endif
1460 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1461 if (!priv->use_dma)
1462 pch_request_dma(port);
1463 priv->use_dma = 1;
1464 }
1465
1466 return 0;
1467 }
1468
1469 static struct uart_ops pch_uart_ops = {
1470 .tx_empty = pch_uart_tx_empty,
1471 .set_mctrl = pch_uart_set_mctrl,
1472 .get_mctrl = pch_uart_get_mctrl,
1473 .stop_tx = pch_uart_stop_tx,
1474 .start_tx = pch_uart_start_tx,
1475 .stop_rx = pch_uart_stop_rx,
1476 .enable_ms = pch_uart_enable_ms,
1477 .break_ctl = pch_uart_break_ctl,
1478 .startup = pch_uart_startup,
1479 .shutdown = pch_uart_shutdown,
1480 .set_termios = pch_uart_set_termios,
1481 /* .pm = pch_uart_pm, Not supported yet */
1482 /* .set_wake = pch_uart_set_wake, Not supported yet */
1483 .type = pch_uart_type,
1484 .release_port = pch_uart_release_port,
1485 .request_port = pch_uart_request_port,
1486 .config_port = pch_uart_config_port,
1487 .verify_port = pch_uart_verify_port
1488 };
1489
1490 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1491
1492 /*
1493 * Wait for transmitter & holding register to empty
1494 */
1495 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1496 {
1497 unsigned int status, tmout = 10000;
1498
1499 /* Wait up to 10ms for the character(s) to be sent. */
1500 for (;;) {
1501 status = ioread8(up->membase + UART_LSR);
1502
1503 if ((status & bits) == bits)
1504 break;
1505 if (--tmout == 0)
1506 break;
1507 udelay(1);
1508 }
1509
1510 /* Wait up to 1s for flow control if necessary */
1511 if (up->port.flags & UPF_CONS_FLOW) {
1512 unsigned int tmout;
1513 for (tmout = 1000000; tmout; tmout--) {
1514 unsigned int msr = ioread8(up->membase + UART_MSR);
1515 if (msr & UART_MSR_CTS)
1516 break;
1517 udelay(1);
1518 touch_nmi_watchdog();
1519 }
1520 }
1521 }
1522
1523 static void pch_console_putchar(struct uart_port *port, int ch)
1524 {
1525 struct eg20t_port *priv =
1526 container_of(port, struct eg20t_port, port);
1527
1528 wait_for_xmitr(priv, UART_LSR_THRE);
1529 iowrite8(ch, priv->membase + PCH_UART_THR);
1530 }
1531
1532 /*
1533 * Print a string to the serial port trying not to disturb
1534 * any possible real use of the port...
1535 *
1536 * The console_lock must be held when we get here.
1537 */
1538 static void
1539 pch_console_write(struct console *co, const char *s, unsigned int count)
1540 {
1541 struct eg20t_port *priv;
1542 unsigned long flags;
1543 int priv_locked = 1;
1544 int port_locked = 1;
1545 u8 ier;
1546
1547 priv = pch_uart_ports[co->index];
1548
1549 touch_nmi_watchdog();
1550
1551 local_irq_save(flags);
1552 if (priv->port.sysrq) {
1553 spin_lock(&priv->lock);
1554 /* serial8250_handle_port() already took the port lock */
1555 port_locked = 0;
1556 } else if (oops_in_progress) {
1557 priv_locked = spin_trylock(&priv->lock);
1558 port_locked = spin_trylock(&priv->port.lock);
1559 } else {
1560 spin_lock(&priv->lock);
1561 spin_lock(&priv->port.lock);
1562 }
1563
1564 /*
1565 * First save the IER then disable the interrupts
1566 */
1567 ier = ioread8(priv->membase + UART_IER);
1568
1569 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1570
1571 uart_console_write(&priv->port, s, count, pch_console_putchar);
1572
1573 /*
1574 * Finally, wait for transmitter to become empty
1575 * and restore the IER
1576 */
1577 wait_for_xmitr(priv, BOTH_EMPTY);
1578 iowrite8(ier, priv->membase + UART_IER);
1579
1580 if (port_locked)
1581 spin_unlock(&priv->port.lock);
1582 if (priv_locked)
1583 spin_unlock(&priv->lock);
1584 local_irq_restore(flags);
1585 }
1586
1587 static int __init pch_console_setup(struct console *co, char *options)
1588 {
1589 struct uart_port *port;
1590 int baud = default_baud;
1591 int bits = 8;
1592 int parity = 'n';
1593 int flow = 'n';
1594
1595 /*
1596 * Check whether an invalid uart number has been specified, and
1597 * if so, search for the first available port that does have
1598 * console support.
1599 */
1600 if (co->index >= PCH_UART_NR)
1601 co->index = 0;
1602 port = &pch_uart_ports[co->index]->port;
1603
1604 if (!port || (!port->iobase && !port->membase))
1605 return -ENODEV;
1606
1607 port->uartclk = pch_uart_get_uartclk();
1608
1609 if (options)
1610 uart_parse_options(options, &baud, &parity, &bits, &flow);
1611
1612 return uart_set_options(port, co, baud, parity, bits, flow);
1613 }
1614
1615 static struct uart_driver pch_uart_driver;
1616
1617 static struct console pch_console = {
1618 .name = PCH_UART_DRIVER_DEVICE,
1619 .write = pch_console_write,
1620 .device = uart_console_device,
1621 .setup = pch_console_setup,
1622 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1623 .index = -1,
1624 .data = &pch_uart_driver,
1625 };
1626
1627 #define PCH_CONSOLE (&pch_console)
1628 #else
1629 #define PCH_CONSOLE NULL
1630 #endif
1631
1632 static struct uart_driver pch_uart_driver = {
1633 .owner = THIS_MODULE,
1634 .driver_name = KBUILD_MODNAME,
1635 .dev_name = PCH_UART_DRIVER_DEVICE,
1636 .major = 0,
1637 .minor = 0,
1638 .nr = PCH_UART_NR,
1639 .cons = PCH_CONSOLE,
1640 };
1641
1642 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1643 const struct pci_device_id *id)
1644 {
1645 struct eg20t_port *priv;
1646 int ret;
1647 unsigned int iobase;
1648 unsigned int mapbase;
1649 unsigned char *rxbuf;
1650 int fifosize;
1651 int port_type;
1652 struct pch_uart_driver_data *board;
1653 char name[32]; /* for debugfs file name */
1654
1655 board = &drv_dat[id->driver_data];
1656 port_type = board->port_type;
1657
1658 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1659 if (priv == NULL)
1660 goto init_port_alloc_err;
1661
1662 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1663 if (!rxbuf)
1664 goto init_port_free_txbuf;
1665
1666 switch (port_type) {
1667 case PORT_UNKNOWN:
1668 fifosize = 256; /* EG20T/ML7213: UART0 */
1669 break;
1670 case PORT_8250:
1671 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1672 break;
1673 default:
1674 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1675 goto init_port_hal_free;
1676 }
1677
1678 pci_enable_msi(pdev);
1679 pci_set_master(pdev);
1680
1681 spin_lock_init(&priv->lock);
1682
1683 iobase = pci_resource_start(pdev, 0);
1684 mapbase = pci_resource_start(pdev, 1);
1685 priv->mapbase = mapbase;
1686 priv->iobase = iobase;
1687 priv->pdev = pdev;
1688 priv->tx_empty = 1;
1689 priv->rxbuf.buf = rxbuf;
1690 priv->rxbuf.size = PAGE_SIZE;
1691
1692 priv->fifo_size = fifosize;
1693 priv->uartclk = pch_uart_get_uartclk();
1694 priv->port_type = PORT_MAX_8250 + port_type + 1;
1695 priv->port.dev = &pdev->dev;
1696 priv->port.iobase = iobase;
1697 priv->port.membase = NULL;
1698 priv->port.mapbase = mapbase;
1699 priv->port.irq = pdev->irq;
1700 priv->port.iotype = UPIO_PORT;
1701 priv->port.ops = &pch_uart_ops;
1702 priv->port.flags = UPF_BOOT_AUTOCONF;
1703 priv->port.fifosize = fifosize;
1704 priv->port.line = board->line_no;
1705 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1706
1707 spin_lock_init(&priv->port.lock);
1708
1709 pci_set_drvdata(pdev, priv);
1710 priv->trigger_level = 1;
1711 priv->fcr = 0;
1712
1713 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1714 pch_uart_ports[board->line_no] = priv;
1715 #endif
1716 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1717 if (ret < 0)
1718 goto init_port_hal_free;
1719
1720 #ifdef CONFIG_DEBUG_FS
1721 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1722 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1723 NULL, priv, &port_regs_ops);
1724 #endif
1725
1726 return priv;
1727
1728 init_port_hal_free:
1729 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1730 pch_uart_ports[board->line_no] = NULL;
1731 #endif
1732 free_page((unsigned long)rxbuf);
1733 init_port_free_txbuf:
1734 kfree(priv);
1735 init_port_alloc_err:
1736
1737 return NULL;
1738 }
1739
1740 static void pch_uart_exit_port(struct eg20t_port *priv)
1741 {
1742
1743 #ifdef CONFIG_DEBUG_FS
1744 if (priv->debugfs)
1745 debugfs_remove(priv->debugfs);
1746 #endif
1747 uart_remove_one_port(&pch_uart_driver, &priv->port);
1748 pci_set_drvdata(priv->pdev, NULL);
1749 free_page((unsigned long)priv->rxbuf.buf);
1750 }
1751
1752 static void pch_uart_pci_remove(struct pci_dev *pdev)
1753 {
1754 struct eg20t_port *priv = pci_get_drvdata(pdev);
1755
1756 pci_disable_msi(pdev);
1757
1758 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1759 pch_uart_ports[priv->port.line] = NULL;
1760 #endif
1761 pch_uart_exit_port(priv);
1762 pci_disable_device(pdev);
1763 kfree(priv);
1764 return;
1765 }
1766 #ifdef CONFIG_PM
1767 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1768 {
1769 struct eg20t_port *priv = pci_get_drvdata(pdev);
1770
1771 uart_suspend_port(&pch_uart_driver, &priv->port);
1772
1773 pci_save_state(pdev);
1774 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1775 return 0;
1776 }
1777
1778 static int pch_uart_pci_resume(struct pci_dev *pdev)
1779 {
1780 struct eg20t_port *priv = pci_get_drvdata(pdev);
1781 int ret;
1782
1783 pci_set_power_state(pdev, PCI_D0);
1784 pci_restore_state(pdev);
1785
1786 ret = pci_enable_device(pdev);
1787 if (ret) {
1788 dev_err(&pdev->dev,
1789 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1790 return ret;
1791 }
1792
1793 uart_resume_port(&pch_uart_driver, &priv->port);
1794
1795 return 0;
1796 }
1797 #else
1798 #define pch_uart_pci_suspend NULL
1799 #define pch_uart_pci_resume NULL
1800 #endif
1801
1802 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1803 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1804 .driver_data = pch_et20t_uart0},
1805 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1806 .driver_data = pch_et20t_uart1},
1807 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1808 .driver_data = pch_et20t_uart2},
1809 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1810 .driver_data = pch_et20t_uart3},
1811 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1812 .driver_data = pch_ml7213_uart0},
1813 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1814 .driver_data = pch_ml7213_uart1},
1815 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1816 .driver_data = pch_ml7213_uart2},
1817 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1818 .driver_data = pch_ml7223_uart0},
1819 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1820 .driver_data = pch_ml7223_uart1},
1821 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1822 .driver_data = pch_ml7831_uart0},
1823 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1824 .driver_data = pch_ml7831_uart1},
1825 {0,},
1826 };
1827
1828 static int pch_uart_pci_probe(struct pci_dev *pdev,
1829 const struct pci_device_id *id)
1830 {
1831 int ret;
1832 struct eg20t_port *priv;
1833
1834 ret = pci_enable_device(pdev);
1835 if (ret < 0)
1836 goto probe_error;
1837
1838 priv = pch_uart_init_port(pdev, id);
1839 if (!priv) {
1840 ret = -EBUSY;
1841 goto probe_disable_device;
1842 }
1843 pci_set_drvdata(pdev, priv);
1844
1845 return ret;
1846
1847 probe_disable_device:
1848 pci_disable_msi(pdev);
1849 pci_disable_device(pdev);
1850 probe_error:
1851 return ret;
1852 }
1853
1854 static struct pci_driver pch_uart_pci_driver = {
1855 .name = "pch_uart",
1856 .id_table = pch_uart_pci_id,
1857 .probe = pch_uart_pci_probe,
1858 .remove = pch_uart_pci_remove,
1859 .suspend = pch_uart_pci_suspend,
1860 .resume = pch_uart_pci_resume,
1861 };
1862
1863 static int __init pch_uart_module_init(void)
1864 {
1865 int ret;
1866
1867 /* register as UART driver */
1868 ret = uart_register_driver(&pch_uart_driver);
1869 if (ret < 0)
1870 return ret;
1871
1872 /* register as PCI driver */
1873 ret = pci_register_driver(&pch_uart_pci_driver);
1874 if (ret < 0)
1875 uart_unregister_driver(&pch_uart_driver);
1876
1877 return ret;
1878 }
1879 module_init(pch_uart_module_init);
1880
1881 static void __exit pch_uart_module_exit(void)
1882 {
1883 pci_unregister_driver(&pch_uart_pci_driver);
1884 uart_unregister_driver(&pch_uart_driver);
1885 }
1886 module_exit(pch_uart_module_exit);
1887
1888 MODULE_LICENSE("GPL v2");
1889 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1890 module_param(default_baud, uint, S_IRUGO);
1891 MODULE_PARM_DESC(default_baud,
1892 "Default BAUD for initial driver state and console (default 9600)");
1893 module_param(user_uartclk, uint, S_IRUGO);
1894 MODULE_PARM_DESC(user_uartclk,
1895 "Override UART default or board specific UART clock");
Linux kernel - Deliverables
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