2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
51 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
52 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
66 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
82 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
84 return DWC3_DSTS_USBLNKST(reg
);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc
->revision
>= DWC3_REVISION_194A
) {
106 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
107 if (reg
& DWC3_DSTS_DCNRD
)
117 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
118 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
120 /* set requested state */
121 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
122 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc
->revision
>= DWC3_REVISION_194A
)
131 /* wait for a change in DSTS */
134 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
136 if (DWC3_DSTS_USBLNKST(reg
) == state
)
142 dwc3_trace(trace_dwc3_gadget
,
143 "link state change request timed out");
148 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
151 dep
->trb_enqueue
%= DWC3_TRB_NUM
;
154 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
157 dep
->trb_dequeue
%= DWC3_TRB_NUM
;
160 static int dwc3_ep_is_last_trb(unsigned int index
)
162 return index
== DWC3_TRB_NUM
- 1;
165 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
168 struct dwc3
*dwc
= dep
->dwc
;
174 dwc3_ep_inc_deq(dep
);
176 * Skip LINK TRB. We can't use req->trb and check for
177 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
178 * just completed (not the LINK TRB).
180 if (dwc3_ep_is_last_trb(dep
->trb_dequeue
))
181 dwc3_ep_inc_deq(dep
);
182 } while(++i
< req
->request
.num_mapped_sgs
);
183 req
->started
= false;
185 list_del(&req
->list
);
188 if (req
->request
.status
== -EINPROGRESS
)
189 req
->request
.status
= status
;
191 if (dwc
->ep0_bounced
&& dep
->number
== 0)
192 dwc
->ep0_bounced
= false;
194 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
197 trace_dwc3_gadget_giveback(req
);
199 spin_unlock(&dwc
->lock
);
200 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
201 spin_lock(&dwc
->lock
);
204 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
209 trace_dwc3_gadget_generic_cmd(cmd
, param
);
211 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
212 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
215 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
216 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
217 dwc3_trace(trace_dwc3_gadget
,
218 "Command Complete --> %d",
219 DWC3_DGCMD_STATUS(reg
));
220 if (DWC3_DGCMD_STATUS(reg
))
226 * We can't sleep here, because it's also called from
231 dwc3_trace(trace_dwc3_gadget
,
232 "Command Timed Out");
239 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
241 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
242 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
244 struct dwc3_ep
*dep
= dwc
->eps
[ep
];
251 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
);
254 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
255 * we're issuing an endpoint command, we must check if
256 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
258 * We will also set SUSPHY bit to what it was before returning as stated
259 * by the same section on Synopsys databook.
261 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
262 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
264 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
265 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
268 if (cmd
== DWC3_DEPCMD_STARTTRANSFER
) {
271 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
272 dwc
->link_state
== DWC3_LINK_STATE_U2
||
273 dwc
->link_state
== DWC3_LINK_STATE_U3
);
275 if (unlikely(needs_wakeup
)) {
276 ret
= __dwc3_gadget_wakeup(dwc
);
277 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
282 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR0(ep
), params
->param0
);
283 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR1(ep
), params
->param1
);
284 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR2(ep
), params
->param2
);
286 dwc3_writel(dwc
->regs
, DWC3_DEPCMD(ep
), cmd
| DWC3_DEPCMD_CMDACT
);
288 reg
= dwc3_readl(dwc
->regs
, DWC3_DEPCMD(ep
));
289 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
290 int cmd_status
= DWC3_DEPCMD_STATUS(reg
);
292 dwc3_trace(trace_dwc3_gadget
,
293 "Command Complete --> %d",
296 switch (cmd_status
) {
300 case DEPEVT_TRANSFER_NO_RESOURCE
:
301 dwc3_trace(trace_dwc3_gadget
, "%s: no resource available");
304 case DEPEVT_TRANSFER_BUS_EXPIRY
:
306 * SW issues START TRANSFER command to
307 * isochronous ep with future frame interval. If
308 * future interval time has already passed when
309 * core receives the command, it will respond
310 * with an error status of 'Bus Expiry'.
312 * Instead of always returning -EINVAL, let's
313 * give a hint to the gadget driver that this is
314 * the case by returning -EAGAIN.
316 dwc3_trace(trace_dwc3_gadget
, "%s: bus expiry");
320 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
327 * We can't sleep here, because it is also called from
332 dwc3_trace(trace_dwc3_gadget
,
333 "Command Timed Out");
341 if (unlikely(susphy
)) {
342 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
343 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
344 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
350 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
351 struct dwc3_trb
*trb
)
353 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
355 return dep
->trb_pool_dma
+ offset
;
358 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
360 struct dwc3
*dwc
= dep
->dwc
;
365 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
366 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
367 &dep
->trb_pool_dma
, GFP_KERNEL
);
368 if (!dep
->trb_pool
) {
369 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
377 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
379 struct dwc3
*dwc
= dep
->dwc
;
381 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
382 dep
->trb_pool
, dep
->trb_pool_dma
);
384 dep
->trb_pool
= NULL
;
385 dep
->trb_pool_dma
= 0;
388 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
391 * dwc3_gadget_start_config - Configure EP resources
392 * @dwc: pointer to our controller context structure
393 * @dep: endpoint that is being enabled
395 * The assignment of transfer resources cannot perfectly follow the
396 * data book due to the fact that the controller driver does not have
397 * all knowledge of the configuration in advance. It is given this
398 * information piecemeal by the composite gadget framework after every
399 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
400 * programming model in this scenario can cause errors. For two
403 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
404 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
405 * multiple interfaces.
407 * 2) The databook does not mention doing more DEPXFERCFG for new
408 * endpoint on alt setting (8.1.6).
410 * The following simplified method is used instead:
412 * All hardware endpoints can be assigned a transfer resource and this
413 * setting will stay persistent until either a core reset or
414 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
415 * do DEPXFERCFG for every hardware endpoint as well. We are
416 * guaranteed that there are as many transfer resources as endpoints.
418 * This function is called for each endpoint when it is being enabled
419 * but is triggered only when called for EP0-out, which always happens
420 * first, and which should only happen in one of the above conditions.
422 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
424 struct dwc3_gadget_ep_cmd_params params
;
432 memset(¶ms
, 0x00, sizeof(params
));
433 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
435 ret
= dwc3_send_gadget_ep_cmd(dwc
, 0, cmd
, ¶ms
);
439 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
440 struct dwc3_ep
*dep
= dwc
->eps
[i
];
445 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
453 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
454 const struct usb_endpoint_descriptor
*desc
,
455 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
456 bool ignore
, bool restore
)
458 struct dwc3_gadget_ep_cmd_params params
;
460 memset(¶ms
, 0x00, sizeof(params
));
462 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
463 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
465 /* Burst size is only needed in SuperSpeed mode */
466 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
467 u32 burst
= dep
->endpoint
.maxburst
;
472 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
473 nump
= DWC3_DCFG_NUMP(reg
);
474 nump
= max(nump
, burst
);
475 reg
&= ~DWC3_DCFG_NUMP_MASK
;
476 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
477 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
479 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
483 params
.param0
|= DWC3_DEPCFG_IGN_SEQ_NUM
;
486 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
487 params
.param2
|= dep
->saved_state
;
490 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
491 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
493 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
494 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
495 | DWC3_DEPCFG_STREAM_EVENT_EN
;
496 dep
->stream_capable
= true;
499 if (!usb_endpoint_xfer_control(desc
))
500 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
503 * We are doing 1:1 mapping for endpoints, meaning
504 * Physical Endpoints 2 maps to Logical Endpoint 2 and
505 * so on. We consider the direction bit as part of the physical
506 * endpoint number. So USB endpoint 0x81 is 0x03.
508 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
511 * We must use the lower 16 TX FIFOs even though
515 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
517 if (desc
->bInterval
) {
518 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
519 dep
->interval
= 1 << (desc
->bInterval
- 1);
522 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
523 DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
526 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
528 struct dwc3_gadget_ep_cmd_params params
;
530 memset(¶ms
, 0x00, sizeof(params
));
532 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
534 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
535 DWC3_DEPCMD_SETTRANSFRESOURCE
, ¶ms
);
539 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
540 * @dep: endpoint to be initialized
541 * @desc: USB Endpoint Descriptor
543 * Caller should take care of locking
545 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
546 const struct usb_endpoint_descriptor
*desc
,
547 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
548 bool ignore
, bool restore
)
550 struct dwc3
*dwc
= dep
->dwc
;
554 dwc3_trace(trace_dwc3_gadget
, "Enabling %s", dep
->name
);
556 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
557 ret
= dwc3_gadget_start_config(dwc
, dep
);
562 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, ignore
,
567 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
568 struct dwc3_trb
*trb_st_hw
;
569 struct dwc3_trb
*trb_link
;
571 dep
->endpoint
.desc
= desc
;
572 dep
->comp_desc
= comp_desc
;
573 dep
->type
= usb_endpoint_type(desc
);
574 dep
->flags
|= DWC3_EP_ENABLED
;
576 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
577 reg
|= DWC3_DALEPENA_EP(dep
->number
);
578 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
580 if (usb_endpoint_xfer_control(desc
))
583 /* Link TRB. The HWO bit is never reset */
584 trb_st_hw
= &dep
->trb_pool
[0];
586 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
587 memset(trb_link
, 0, sizeof(*trb_link
));
589 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
590 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
591 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
592 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
596 switch (usb_endpoint_type(desc
)) {
597 case USB_ENDPOINT_XFER_CONTROL
:
598 /* don't change name */
600 case USB_ENDPOINT_XFER_ISOC
:
601 strlcat(dep
->name
, "-isoc", sizeof(dep
->name
));
603 case USB_ENDPOINT_XFER_BULK
:
604 strlcat(dep
->name
, "-bulk", sizeof(dep
->name
));
606 case USB_ENDPOINT_XFER_INT
:
607 strlcat(dep
->name
, "-int", sizeof(dep
->name
));
610 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
616 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
617 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
619 struct dwc3_request
*req
;
621 if (!list_empty(&dep
->started_list
)) {
622 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
624 /* - giveback all requests to gadget driver */
625 while (!list_empty(&dep
->started_list
)) {
626 req
= next_request(&dep
->started_list
);
628 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
632 while (!list_empty(&dep
->pending_list
)) {
633 req
= next_request(&dep
->pending_list
);
635 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
640 * __dwc3_gadget_ep_disable - Disables a HW endpoint
641 * @dep: the endpoint to disable
643 * This function also removes requests which are currently processed ny the
644 * hardware and those which are not yet scheduled.
645 * Caller should take care of locking.
647 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
649 struct dwc3
*dwc
= dep
->dwc
;
652 dwc3_trace(trace_dwc3_gadget
, "Disabling %s", dep
->name
);
654 dwc3_remove_requests(dwc
, dep
);
656 /* make sure HW endpoint isn't stalled */
657 if (dep
->flags
& DWC3_EP_STALL
)
658 __dwc3_gadget_ep_set_halt(dep
, 0, false);
660 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
661 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
662 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
664 dep
->stream_capable
= false;
665 dep
->endpoint
.desc
= NULL
;
666 dep
->comp_desc
= NULL
;
670 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
672 (dep
->number
& 1) ? "in" : "out");
677 /* -------------------------------------------------------------------------- */
679 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
680 const struct usb_endpoint_descriptor
*desc
)
685 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
690 /* -------------------------------------------------------------------------- */
692 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
693 const struct usb_endpoint_descriptor
*desc
)
700 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
701 pr_debug("dwc3: invalid parameters\n");
705 if (!desc
->wMaxPacketSize
) {
706 pr_debug("dwc3: missing wMaxPacketSize\n");
710 dep
= to_dwc3_ep(ep
);
713 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
714 "%s is already enabled\n",
718 spin_lock_irqsave(&dwc
->lock
, flags
);
719 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false, false);
720 spin_unlock_irqrestore(&dwc
->lock
, flags
);
725 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
733 pr_debug("dwc3: invalid parameters\n");
737 dep
= to_dwc3_ep(ep
);
740 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
741 "%s is already disabled\n",
745 spin_lock_irqsave(&dwc
->lock
, flags
);
746 ret
= __dwc3_gadget_ep_disable(dep
);
747 spin_unlock_irqrestore(&dwc
->lock
, flags
);
752 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
755 struct dwc3_request
*req
;
756 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
758 req
= kzalloc(sizeof(*req
), gfp_flags
);
762 req
->epnum
= dep
->number
;
765 trace_dwc3_alloc_request(req
);
767 return &req
->request
;
770 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
771 struct usb_request
*request
)
773 struct dwc3_request
*req
= to_dwc3_request(request
);
775 trace_dwc3_free_request(req
);
780 * dwc3_prepare_one_trb - setup one TRB from one request
781 * @dep: endpoint for which this request is prepared
782 * @req: dwc3_request pointer
784 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
785 struct dwc3_request
*req
, dma_addr_t dma
,
786 unsigned length
, unsigned last
, unsigned chain
, unsigned node
)
788 struct dwc3_trb
*trb
;
790 dwc3_trace(trace_dwc3_gadget
, "%s: req %p dma %08llx length %d%s%s",
791 dep
->name
, req
, (unsigned long long) dma
,
792 length
, last
? " last" : "",
793 chain
? " chain" : "");
796 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
799 dwc3_gadget_move_started_request(req
);
801 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
802 req
->first_trb_index
= dep
->trb_enqueue
;
805 dwc3_ep_inc_enq(dep
);
806 /* Skip the LINK-TRB */
807 if (dwc3_ep_is_last_trb(dep
->trb_enqueue
))
808 dwc3_ep_inc_enq(dep
);
810 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
811 trb
->bpl
= lower_32_bits(dma
);
812 trb
->bph
= upper_32_bits(dma
);
814 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
815 case USB_ENDPOINT_XFER_CONTROL
:
816 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
819 case USB_ENDPOINT_XFER_ISOC
:
821 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
823 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
825 /* always enable Interrupt on Missed ISOC */
826 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
829 case USB_ENDPOINT_XFER_BULK
:
830 case USB_ENDPOINT_XFER_INT
:
831 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
835 * This is only possible with faulty memory because we
836 * checked it already :)
841 /* always enable Continue on Short Packet */
842 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
844 if (!req
->request
.no_interrupt
&& !chain
)
845 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_ISP_IMI
;
848 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
851 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
853 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
854 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
856 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
858 trace_dwc3_prepare_trb(dep
, trb
);
862 * dwc3_prepare_trbs - setup TRBs from requests
863 * @dep: endpoint for which requests are being prepared
864 * @starting: true if the endpoint is idle and no requests are queued.
866 * The function goes through the requests list and sets up TRBs for the
867 * transfers. The function returns once there are no more TRBs available or
868 * it runs out of requests.
870 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
, bool starting
)
872 struct dwc3_request
*req
, *n
;
874 unsigned int last_one
= 0;
876 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
878 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
881 * If enqueue & dequeue are equal than it is either full or empty. If we
882 * are starting to process requests then we are empty. Otherwise we are
883 * full and don't do anything
889 trbs_left
= DWC3_TRB_NUM
;
892 /* The last TRB is a link TRB, not used for xfer */
896 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
901 if (req
->request
.num_mapped_sgs
> 0) {
902 struct usb_request
*request
= &req
->request
;
903 struct scatterlist
*sg
= request
->sg
;
904 struct scatterlist
*s
;
907 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
908 unsigned chain
= true;
910 length
= sg_dma_len(s
);
911 dma
= sg_dma_address(s
);
913 if (i
== (request
->num_mapped_sgs
- 1) ||
915 if (list_empty(&dep
->pending_list
))
927 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
937 dma
= req
->request
.dma
;
938 length
= req
->request
.length
;
944 /* Is this the last request? */
945 if (list_is_last(&req
->list
, &dep
->pending_list
))
948 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
957 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
,
960 struct dwc3_gadget_ep_cmd_params params
;
961 struct dwc3_request
*req
;
962 struct dwc3
*dwc
= dep
->dwc
;
966 if (start_new
&& (dep
->flags
& DWC3_EP_BUSY
)) {
967 dwc3_trace(trace_dwc3_gadget
, "%s: endpoint busy", dep
->name
);
972 * If we are getting here after a short-out-packet we don't enqueue any
973 * new requests as we try to set the IOC bit only on the last request.
976 if (list_empty(&dep
->started_list
))
977 dwc3_prepare_trbs(dep
, start_new
);
979 /* req points to the first request which will be sent */
980 req
= next_request(&dep
->started_list
);
982 dwc3_prepare_trbs(dep
, start_new
);
985 * req points to the first request where HWO changed from 0 to 1
987 req
= next_request(&dep
->started_list
);
990 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
994 memset(¶ms
, 0, sizeof(params
));
997 params
.param0
= upper_32_bits(req
->trb_dma
);
998 params
.param1
= lower_32_bits(req
->trb_dma
);
999 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
1001 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
1004 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
1005 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
1008 * FIXME we need to iterate over the list of requests
1009 * here and stop, unmap, free and del each of the linked
1010 * requests instead of what we do now.
1012 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
1014 list_del(&req
->list
);
1018 dep
->flags
|= DWC3_EP_BUSY
;
1021 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dwc
,
1023 WARN_ON_ONCE(!dep
->resource_index
);
1029 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1030 struct dwc3_ep
*dep
, u32 cur_uf
)
1034 if (list_empty(&dep
->pending_list
)) {
1035 dwc3_trace(trace_dwc3_gadget
,
1036 "ISOC ep %s run out for requests",
1038 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1042 /* 4 micro frames in the future */
1043 uf
= cur_uf
+ dep
->interval
* 4;
1045 __dwc3_gadget_kick_transfer(dep
, uf
, 1);
1048 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1049 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1053 mask
= ~(dep
->interval
- 1);
1054 cur_uf
= event
->parameters
& mask
;
1056 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1059 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1061 struct dwc3
*dwc
= dep
->dwc
;
1064 if (!dep
->endpoint
.desc
) {
1065 dwc3_trace(trace_dwc3_gadget
,
1066 "trying to queue request %p to disabled %s\n",
1067 &req
->request
, dep
->endpoint
.name
);
1071 if (WARN(req
->dep
!= dep
, "request %p belongs to '%s'\n",
1072 &req
->request
, req
->dep
->name
)) {
1073 dwc3_trace(trace_dwc3_gadget
, "request %p belongs to '%s'\n",
1074 &req
->request
, req
->dep
->name
);
1078 req
->request
.actual
= 0;
1079 req
->request
.status
= -EINPROGRESS
;
1080 req
->direction
= dep
->direction
;
1081 req
->epnum
= dep
->number
;
1083 trace_dwc3_ep_queue(req
);
1086 * We only add to our list of requests now and
1087 * start consuming the list once we get XferNotReady
1090 * That way, we avoid doing anything that we don't need
1091 * to do now and defer it until the point we receive a
1092 * particular token from the Host side.
1094 * This will also avoid Host cancelling URBs due to too
1097 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1102 list_add_tail(&req
->list
, &dep
->pending_list
);
1105 * If there are no pending requests and the endpoint isn't already
1106 * busy, we will just start the request straight away.
1108 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1109 * little bit faster.
1111 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1112 !usb_endpoint_xfer_int(dep
->endpoint
.desc
) &&
1113 !(dep
->flags
& DWC3_EP_BUSY
)) {
1114 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1119 * There are a few special cases:
1121 * 1. XferNotReady with empty list of requests. We need to kick the
1122 * transfer here in that situation, otherwise we will be NAKing
1123 * forever. If we get XferNotReady before gadget driver has a
1124 * chance to queue a request, we will ACK the IRQ but won't be
1125 * able to receive the data until the next request is queued.
1126 * The following code is handling exactly that.
1129 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1131 * If xfernotready is already elapsed and it is a case
1132 * of isoc transfer, then issue END TRANSFER, so that
1133 * you can receive xfernotready again and can have
1134 * notion of current microframe.
1136 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1137 if (list_empty(&dep
->started_list
)) {
1138 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1139 dep
->flags
= DWC3_EP_ENABLED
;
1144 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1146 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
1152 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1153 * kick the transfer here after queuing a request, otherwise the
1154 * core may not see the modified TRB(s).
1156 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1157 (dep
->flags
& DWC3_EP_BUSY
) &&
1158 !(dep
->flags
& DWC3_EP_MISSED_ISOC
)) {
1159 WARN_ON_ONCE(!dep
->resource_index
);
1160 ret
= __dwc3_gadget_kick_transfer(dep
, dep
->resource_index
,
1166 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1167 * right away, otherwise host will not know we have streams to be
1170 if (dep
->stream_capable
)
1171 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1174 if (ret
&& ret
!= -EBUSY
)
1175 dwc3_trace(trace_dwc3_gadget
,
1176 "%s: failed to kick transfers\n",
1184 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep
*ep
,
1185 struct usb_request
*request
)
1187 dwc3_gadget_ep_free_request(ep
, request
);
1190 static int __dwc3_gadget_ep_queue_zlp(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1192 struct dwc3_request
*req
;
1193 struct usb_request
*request
;
1194 struct usb_ep
*ep
= &dep
->endpoint
;
1196 dwc3_trace(trace_dwc3_gadget
, "queueing ZLP\n");
1197 request
= dwc3_gadget_ep_alloc_request(ep
, GFP_ATOMIC
);
1201 request
->length
= 0;
1202 request
->buf
= dwc
->zlp_buf
;
1203 request
->complete
= __dwc3_gadget_ep_zlp_complete
;
1205 req
= to_dwc3_request(request
);
1207 return __dwc3_gadget_ep_queue(dep
, req
);
1210 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1213 struct dwc3_request
*req
= to_dwc3_request(request
);
1214 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1215 struct dwc3
*dwc
= dep
->dwc
;
1217 unsigned long flags
;
1221 spin_lock_irqsave(&dwc
->lock
, flags
);
1222 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1225 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1226 * setting request->zero, instead of doing magic, we will just queue an
1227 * extra usb_request ourselves so that it gets handled the same way as
1228 * any other request.
1230 if (ret
== 0 && request
->zero
&& request
->length
&&
1231 (request
->length
% ep
->maxpacket
== 0))
1232 ret
= __dwc3_gadget_ep_queue_zlp(dwc
, dep
);
1234 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1239 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1240 struct usb_request
*request
)
1242 struct dwc3_request
*req
= to_dwc3_request(request
);
1243 struct dwc3_request
*r
= NULL
;
1245 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1246 struct dwc3
*dwc
= dep
->dwc
;
1248 unsigned long flags
;
1251 trace_dwc3_ep_dequeue(req
);
1253 spin_lock_irqsave(&dwc
->lock
, flags
);
1255 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1261 list_for_each_entry(r
, &dep
->started_list
, list
) {
1266 /* wait until it is processed */
1267 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1270 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1277 /* giveback the request */
1278 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1281 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1286 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1288 struct dwc3_gadget_ep_cmd_params params
;
1289 struct dwc3
*dwc
= dep
->dwc
;
1292 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1293 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1297 memset(¶ms
, 0x00, sizeof(params
));
1300 if (!protocol
&& ((dep
->direction
&& dep
->flags
& DWC3_EP_BUSY
) ||
1301 (!list_empty(&dep
->started_list
) ||
1302 !list_empty(&dep
->pending_list
)))) {
1303 dwc3_trace(trace_dwc3_gadget
,
1304 "%s: pending request, cannot halt",
1309 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1310 DWC3_DEPCMD_SETSTALL
, ¶ms
);
1312 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1315 dep
->flags
|= DWC3_EP_STALL
;
1317 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1318 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1320 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1323 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1329 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1331 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1332 struct dwc3
*dwc
= dep
->dwc
;
1334 unsigned long flags
;
1338 spin_lock_irqsave(&dwc
->lock
, flags
);
1339 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1340 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1345 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1347 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1348 struct dwc3
*dwc
= dep
->dwc
;
1349 unsigned long flags
;
1352 spin_lock_irqsave(&dwc
->lock
, flags
);
1353 dep
->flags
|= DWC3_EP_WEDGE
;
1355 if (dep
->number
== 0 || dep
->number
== 1)
1356 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1358 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1359 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1364 /* -------------------------------------------------------------------------- */
1366 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1367 .bLength
= USB_DT_ENDPOINT_SIZE
,
1368 .bDescriptorType
= USB_DT_ENDPOINT
,
1369 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1372 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1373 .enable
= dwc3_gadget_ep0_enable
,
1374 .disable
= dwc3_gadget_ep0_disable
,
1375 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1376 .free_request
= dwc3_gadget_ep_free_request
,
1377 .queue
= dwc3_gadget_ep0_queue
,
1378 .dequeue
= dwc3_gadget_ep_dequeue
,
1379 .set_halt
= dwc3_gadget_ep0_set_halt
,
1380 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1383 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1384 .enable
= dwc3_gadget_ep_enable
,
1385 .disable
= dwc3_gadget_ep_disable
,
1386 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1387 .free_request
= dwc3_gadget_ep_free_request
,
1388 .queue
= dwc3_gadget_ep_queue
,
1389 .dequeue
= dwc3_gadget_ep_dequeue
,
1390 .set_halt
= dwc3_gadget_ep_set_halt
,
1391 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1394 /* -------------------------------------------------------------------------- */
1396 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1398 struct dwc3
*dwc
= gadget_to_dwc(g
);
1401 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1402 return DWC3_DSTS_SOFFN(reg
);
1405 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1407 unsigned long timeout
;
1416 * According to the Databook Remote wakeup request should
1417 * be issued only when the device is in early suspend state.
1419 * We can check that via USB Link State bits in DSTS register.
1421 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1423 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1424 if ((speed
== DWC3_DSTS_SUPERSPEED
) ||
1425 (speed
== DWC3_DSTS_SUPERSPEED_PLUS
)) {
1426 dwc3_trace(trace_dwc3_gadget
, "no wakeup on SuperSpeed\n");
1430 link_state
= DWC3_DSTS_USBLNKST(reg
);
1432 switch (link_state
) {
1433 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1434 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1437 dwc3_trace(trace_dwc3_gadget
,
1438 "can't wakeup from '%s'\n",
1439 dwc3_gadget_link_string(link_state
));
1443 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1445 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1449 /* Recent versions do this automatically */
1450 if (dwc
->revision
< DWC3_REVISION_194A
) {
1451 /* write zeroes to Link Change Request */
1452 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1453 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1454 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1457 /* poll until Link State changes to ON */
1458 timeout
= jiffies
+ msecs_to_jiffies(100);
1460 while (!time_after(jiffies
, timeout
)) {
1461 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1463 /* in HS, means ON */
1464 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1468 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1469 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1476 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1478 struct dwc3
*dwc
= gadget_to_dwc(g
);
1479 unsigned long flags
;
1482 spin_lock_irqsave(&dwc
->lock
, flags
);
1483 ret
= __dwc3_gadget_wakeup(dwc
);
1484 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1489 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1492 struct dwc3
*dwc
= gadget_to_dwc(g
);
1493 unsigned long flags
;
1495 spin_lock_irqsave(&dwc
->lock
, flags
);
1496 g
->is_selfpowered
= !!is_selfpowered
;
1497 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1502 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1507 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1509 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1510 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1511 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1514 if (dwc
->revision
>= DWC3_REVISION_194A
)
1515 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1516 reg
|= DWC3_DCTL_RUN_STOP
;
1518 if (dwc
->has_hibernation
)
1519 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1521 dwc
->pullups_connected
= true;
1523 reg
&= ~DWC3_DCTL_RUN_STOP
;
1525 if (dwc
->has_hibernation
&& !suspend
)
1526 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1528 dwc
->pullups_connected
= false;
1531 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1534 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1536 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1539 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1548 dwc3_trace(trace_dwc3_gadget
, "gadget %s data soft-%s",
1550 ? dwc
->gadget_driver
->function
: "no-function",
1551 is_on
? "connect" : "disconnect");
1556 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1558 struct dwc3
*dwc
= gadget_to_dwc(g
);
1559 unsigned long flags
;
1564 spin_lock_irqsave(&dwc
->lock
, flags
);
1565 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1566 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1571 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1575 /* Enable all but Start and End of Frame IRQs */
1576 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1577 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1578 DWC3_DEVTEN_CMDCMPLTEN
|
1579 DWC3_DEVTEN_ERRTICERREN
|
1580 DWC3_DEVTEN_WKUPEVTEN
|
1581 DWC3_DEVTEN_ULSTCNGEN
|
1582 DWC3_DEVTEN_CONNECTDONEEN
|
1583 DWC3_DEVTEN_USBRSTEN
|
1584 DWC3_DEVTEN_DISCONNEVTEN
);
1586 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1589 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1591 /* mask all interrupts */
1592 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1595 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1596 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1598 static int dwc3_gadget_start(struct usb_gadget
*g
,
1599 struct usb_gadget_driver
*driver
)
1601 struct dwc3
*dwc
= gadget_to_dwc(g
);
1602 struct dwc3_ep
*dep
;
1603 unsigned long flags
;
1608 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
1609 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1610 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
1612 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1617 spin_lock_irqsave(&dwc
->lock
, flags
);
1619 if (dwc
->gadget_driver
) {
1620 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1622 dwc
->gadget_driver
->driver
.name
);
1627 dwc
->gadget_driver
= driver
;
1629 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1630 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1633 * WORKAROUND: DWC3 revision < 2.20a have an issue
1634 * which would cause metastability state on Run/Stop
1635 * bit if we try to force the IP to USB2-only mode.
1637 * Because of that, we cannot configure the IP to any
1638 * speed other than the SuperSpeed
1642 * STAR#9000525659: Clock Domain Crossing on DCTL in
1645 if (dwc
->revision
< DWC3_REVISION_220A
) {
1646 reg
|= DWC3_DCFG_SUPERSPEED
;
1648 switch (dwc
->maximum_speed
) {
1650 reg
|= DWC3_DSTS_LOWSPEED
;
1652 case USB_SPEED_FULL
:
1653 reg
|= DWC3_DSTS_FULLSPEED1
;
1655 case USB_SPEED_HIGH
:
1656 reg
|= DWC3_DSTS_HIGHSPEED
;
1658 case USB_SPEED_SUPER_PLUS
:
1659 reg
|= DWC3_DSTS_SUPERSPEED_PLUS
;
1662 dev_err(dwc
->dev
, "invalid dwc->maximum_speed (%d)\n",
1663 dwc
->maximum_speed
);
1665 case USB_SPEED_SUPER
:
1666 reg
|= DWC3_DCFG_SUPERSPEED
;
1670 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1673 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1674 * field instead of letting dwc3 itself calculate that automatically.
1676 * This way, we maximize the chances that we'll be able to get several
1677 * bursts of data without going through any sort of endpoint throttling.
1679 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1680 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1681 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1683 /* Start with SuperSpeed Default */
1684 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1687 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1690 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1695 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1698 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1702 /* begin to receive SETUP packets */
1703 dwc
->ep0state
= EP0_SETUP_PHASE
;
1704 dwc3_ep0_out_start(dwc
);
1706 dwc3_gadget_enable_irq(dwc
);
1708 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1713 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1716 dwc
->gadget_driver
= NULL
;
1719 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1721 free_irq(irq
, dwc
->ev_buf
);
1727 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1729 struct dwc3
*dwc
= gadget_to_dwc(g
);
1730 unsigned long flags
;
1733 spin_lock_irqsave(&dwc
->lock
, flags
);
1735 dwc3_gadget_disable_irq(dwc
);
1736 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1737 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1739 dwc
->gadget_driver
= NULL
;
1741 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1743 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
1744 free_irq(irq
, dwc
->ev_buf
);
1749 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1750 .get_frame
= dwc3_gadget_get_frame
,
1751 .wakeup
= dwc3_gadget_wakeup
,
1752 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1753 .pullup
= dwc3_gadget_pullup
,
1754 .udc_start
= dwc3_gadget_start
,
1755 .udc_stop
= dwc3_gadget_stop
,
1758 /* -------------------------------------------------------------------------- */
1760 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1761 u8 num
, u32 direction
)
1763 struct dwc3_ep
*dep
;
1766 for (i
= 0; i
< num
; i
++) {
1767 u8 epnum
= (i
<< 1) | (!!direction
);
1769 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1774 dep
->number
= epnum
;
1775 dep
->direction
= !!direction
;
1776 dwc
->eps
[epnum
] = dep
;
1778 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1779 (epnum
& 1) ? "in" : "out");
1781 dep
->endpoint
.name
= dep
->name
;
1783 dwc3_trace(trace_dwc3_gadget
, "initializing %s", dep
->name
);
1785 if (epnum
== 0 || epnum
== 1) {
1786 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1787 dep
->endpoint
.maxburst
= 1;
1788 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1790 dwc
->gadget
.ep0
= &dep
->endpoint
;
1794 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1795 dep
->endpoint
.max_streams
= 15;
1796 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1797 list_add_tail(&dep
->endpoint
.ep_list
,
1798 &dwc
->gadget
.ep_list
);
1800 ret
= dwc3_alloc_trb_pool(dep
);
1805 if (epnum
== 0 || epnum
== 1) {
1806 dep
->endpoint
.caps
.type_control
= true;
1808 dep
->endpoint
.caps
.type_iso
= true;
1809 dep
->endpoint
.caps
.type_bulk
= true;
1810 dep
->endpoint
.caps
.type_int
= true;
1813 dep
->endpoint
.caps
.dir_in
= !!direction
;
1814 dep
->endpoint
.caps
.dir_out
= !direction
;
1816 INIT_LIST_HEAD(&dep
->pending_list
);
1817 INIT_LIST_HEAD(&dep
->started_list
);
1823 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1827 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1829 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1831 dwc3_trace(trace_dwc3_gadget
,
1832 "failed to allocate OUT endpoints");
1836 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1838 dwc3_trace(trace_dwc3_gadget
,
1839 "failed to allocate IN endpoints");
1846 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1848 struct dwc3_ep
*dep
;
1851 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1852 dep
= dwc
->eps
[epnum
];
1856 * Physical endpoints 0 and 1 are special; they form the
1857 * bi-directional USB endpoint 0.
1859 * For those two physical endpoints, we don't allocate a TRB
1860 * pool nor do we add them the endpoints list. Due to that, we
1861 * shouldn't do these two operations otherwise we would end up
1862 * with all sorts of bugs when removing dwc3.ko.
1864 if (epnum
!= 0 && epnum
!= 1) {
1865 dwc3_free_trb_pool(dep
);
1866 list_del(&dep
->endpoint
.ep_list
);
1873 /* -------------------------------------------------------------------------- */
1875 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1876 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
1877 const struct dwc3_event_depevt
*event
, int status
)
1880 unsigned int s_pkt
= 0;
1881 unsigned int trb_status
;
1883 trace_dwc3_complete_trb(dep
, trb
);
1885 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1887 * We continue despite the error. There is not much we
1888 * can do. If we don't clean it up we loop forever. If
1889 * we skip the TRB then it gets overwritten after a
1890 * while since we use them in a ring buffer. A BUG()
1891 * would help. Lets hope that if this occurs, someone
1892 * fixes the root cause instead of looking away :)
1894 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1896 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1898 if (dep
->direction
) {
1900 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1901 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1902 dwc3_trace(trace_dwc3_gadget
,
1903 "%s: incomplete IN transfer\n",
1906 * If missed isoc occurred and there is
1907 * no request queued then issue END
1908 * TRANSFER, so that core generates
1909 * next xfernotready and we will issue
1910 * a fresh START TRANSFER.
1911 * If there are still queued request
1912 * then wait, do not issue either END
1913 * or UPDATE TRANSFER, just attach next
1914 * request in pending_list during
1915 * giveback.If any future queued request
1916 * is successfully transferred then we
1917 * will issue UPDATE TRANSFER for all
1918 * request in the pending_list.
1920 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
1922 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1924 status
= -ECONNRESET
;
1927 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
1930 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1935 * We assume here we will always receive the entire data block
1936 * which we should receive. Meaning, if we program RX to
1937 * receive 4K but we receive only 2K, we assume that's all we
1938 * should receive and we simply bounce the request back to the
1939 * gadget driver for further processing.
1941 req
->request
.actual
+= req
->request
.length
- count
;
1944 if ((event
->status
& DEPEVT_STATUS_LST
) &&
1945 (trb
->ctrl
& (DWC3_TRB_CTRL_LST
|
1946 DWC3_TRB_CTRL_HWO
)))
1948 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1949 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1954 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1955 const struct dwc3_event_depevt
*event
, int status
)
1957 struct dwc3_request
*req
;
1958 struct dwc3_trb
*trb
;
1964 req
= next_request(&dep
->started_list
);
1965 if (WARN_ON_ONCE(!req
))
1970 slot
= req
->first_trb_index
+ i
;
1971 if (slot
== DWC3_TRB_NUM
- 1)
1973 slot
%= DWC3_TRB_NUM
;
1974 trb
= &dep
->trb_pool
[slot
];
1976 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
1980 } while (++i
< req
->request
.num_mapped_sgs
);
1982 dwc3_gadget_giveback(dep
, req
, status
);
1988 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1989 list_empty(&dep
->started_list
)) {
1990 if (list_empty(&dep
->pending_list
)) {
1992 * If there is no entry in request list then do
1993 * not issue END TRANSFER now. Just set PENDING
1994 * flag, so that END TRANSFER is issued when an
1995 * entry is added into request list.
1997 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
1999 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
2000 dep
->flags
= DWC3_EP_ENABLED
;
2008 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
2009 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
2011 unsigned status
= 0;
2013 u32 is_xfer_complete
;
2015 is_xfer_complete
= (event
->endpoint_event
== DWC3_DEPEVT_XFERCOMPLETE
);
2017 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2018 status
= -ECONNRESET
;
2020 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
2021 if (clean_busy
&& (is_xfer_complete
||
2022 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)))
2023 dep
->flags
&= ~DWC3_EP_BUSY
;
2026 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2027 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2029 if (dwc
->revision
< DWC3_REVISION_183A
) {
2033 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2036 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2039 if (!list_empty(&dep
->started_list
))
2043 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2045 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2050 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2053 ret
= __dwc3_gadget_kick_transfer(dep
, 0, is_xfer_complete
);
2054 if (!ret
|| ret
== -EBUSY
)
2059 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2060 const struct dwc3_event_depevt
*event
)
2062 struct dwc3_ep
*dep
;
2063 u8 epnum
= event
->endpoint_number
;
2065 dep
= dwc
->eps
[epnum
];
2067 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2070 if (epnum
== 0 || epnum
== 1) {
2071 dwc3_ep0_interrupt(dwc
, event
);
2075 switch (event
->endpoint_event
) {
2076 case DWC3_DEPEVT_XFERCOMPLETE
:
2077 dep
->resource_index
= 0;
2079 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2080 dwc3_trace(trace_dwc3_gadget
,
2081 "%s is an Isochronous endpoint\n",
2086 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2088 case DWC3_DEPEVT_XFERINPROGRESS
:
2089 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2091 case DWC3_DEPEVT_XFERNOTREADY
:
2092 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2093 dwc3_gadget_start_isoc(dwc
, dep
, event
);
2098 active
= event
->status
& DEPEVT_STATUS_TRANSFER_ACTIVE
;
2100 dwc3_trace(trace_dwc3_gadget
, "%s: reason %s",
2101 dep
->name
, active
? "Transfer Active"
2102 : "Transfer Not Active");
2104 ret
= __dwc3_gadget_kick_transfer(dep
, 0, !active
);
2105 if (!ret
|| ret
== -EBUSY
)
2108 dwc3_trace(trace_dwc3_gadget
,
2109 "%s: failed to kick transfers\n",
2114 case DWC3_DEPEVT_STREAMEVT
:
2115 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
2116 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
2121 switch (event
->status
) {
2122 case DEPEVT_STREAMEVT_FOUND
:
2123 dwc3_trace(trace_dwc3_gadget
,
2124 "Stream %d found and started",
2128 case DEPEVT_STREAMEVT_NOTFOUND
:
2131 dwc3_trace(trace_dwc3_gadget
,
2132 "unable to find suitable stream\n");
2135 case DWC3_DEPEVT_RXTXFIFOEVT
:
2136 dwc3_trace(trace_dwc3_gadget
, "%s FIFO Overrun\n", dep
->name
);
2138 case DWC3_DEPEVT_EPCMDCMPLT
:
2139 dwc3_trace(trace_dwc3_gadget
, "Endpoint Command Complete");
2144 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2146 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2147 spin_unlock(&dwc
->lock
);
2148 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2149 spin_lock(&dwc
->lock
);
2153 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2155 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2156 spin_unlock(&dwc
->lock
);
2157 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2158 spin_lock(&dwc
->lock
);
2162 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2164 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2165 spin_unlock(&dwc
->lock
);
2166 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2167 spin_lock(&dwc
->lock
);
2171 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2173 if (!dwc
->gadget_driver
)
2176 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2177 spin_unlock(&dwc
->lock
);
2178 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2179 spin_lock(&dwc
->lock
);
2183 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2185 struct dwc3_ep
*dep
;
2186 struct dwc3_gadget_ep_cmd_params params
;
2190 dep
= dwc
->eps
[epnum
];
2192 if (!dep
->resource_index
)
2196 * NOTICE: We are violating what the Databook says about the
2197 * EndTransfer command. Ideally we would _always_ wait for the
2198 * EndTransfer Command Completion IRQ, but that's causing too
2199 * much trouble synchronizing between us and gadget driver.
2201 * We have discussed this with the IP Provider and it was
2202 * suggested to giveback all requests here, but give HW some
2203 * extra time to synchronize with the interconnect. We're using
2204 * an arbitrary 100us delay for that.
2206 * Note also that a similar handling was tested by Synopsys
2207 * (thanks a lot Paul) and nothing bad has come out of it.
2208 * In short, what we're doing is:
2210 * - Issue EndTransfer WITH CMDIOC bit set
2214 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2215 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2216 cmd
|= DWC3_DEPCMD_CMDIOC
;
2217 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2218 memset(¶ms
, 0, sizeof(params
));
2219 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
2221 dep
->resource_index
= 0;
2222 dep
->flags
&= ~DWC3_EP_BUSY
;
2226 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
2230 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2231 struct dwc3_ep
*dep
;
2233 dep
= dwc
->eps
[epnum
];
2237 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2240 dwc3_remove_requests(dwc
, dep
);
2244 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2248 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2249 struct dwc3_ep
*dep
;
2250 struct dwc3_gadget_ep_cmd_params params
;
2253 dep
= dwc
->eps
[epnum
];
2257 if (!(dep
->flags
& DWC3_EP_STALL
))
2260 dep
->flags
&= ~DWC3_EP_STALL
;
2262 memset(¶ms
, 0, sizeof(params
));
2263 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
2264 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
2269 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2273 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2274 reg
&= ~DWC3_DCTL_INITU1ENA
;
2275 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2277 reg
&= ~DWC3_DCTL_INITU2ENA
;
2278 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2280 dwc3_disconnect_gadget(dwc
);
2282 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2283 dwc
->setup_packet_pending
= false;
2284 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2287 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2292 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2293 * would cause a missing Disconnect Event if there's a
2294 * pending Setup Packet in the FIFO.
2296 * There's no suggested workaround on the official Bug
2297 * report, which states that "unless the driver/application
2298 * is doing any special handling of a disconnect event,
2299 * there is no functional issue".
2301 * Unfortunately, it turns out that we _do_ some special
2302 * handling of a disconnect event, namely complete all
2303 * pending transfers, notify gadget driver of the
2304 * disconnection, and so on.
2306 * Our suggested workaround is to follow the Disconnect
2307 * Event steps here, instead, based on a setup_packet_pending
2308 * flag. Such flag gets set whenever we have a SETUP_PENDING
2309 * status for EP0 TRBs and gets cleared on XferComplete for the
2314 * STAR#9000466709: RTL: Device : Disconnect event not
2315 * generated if setup packet pending in FIFO
2317 if (dwc
->revision
< DWC3_REVISION_188A
) {
2318 if (dwc
->setup_packet_pending
)
2319 dwc3_gadget_disconnect_interrupt(dwc
);
2322 dwc3_reset_gadget(dwc
);
2324 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2325 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2326 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2327 dwc
->test_mode
= false;
2329 dwc3_stop_active_transfers(dwc
);
2330 dwc3_clear_stall_all_ep(dwc
);
2332 /* Reset device address to zero */
2333 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2334 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2335 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2338 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2341 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2344 * We change the clock only at SS but I dunno why I would want to do
2345 * this. Maybe it becomes part of the power saving plan.
2348 if ((speed
!= DWC3_DSTS_SUPERSPEED
) &&
2349 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
2353 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2354 * each time on Connect Done.
2359 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2360 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2361 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2364 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2366 struct dwc3_ep
*dep
;
2371 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2372 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2375 dwc3_update_ram_clk_sel(dwc
, speed
);
2378 case DWC3_DCFG_SUPERSPEED_PLUS
:
2379 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2380 dwc
->gadget
.ep0
->maxpacket
= 512;
2381 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2383 case DWC3_DCFG_SUPERSPEED
:
2385 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2386 * would cause a missing USB3 Reset event.
2388 * In such situations, we should force a USB3 Reset
2389 * event by calling our dwc3_gadget_reset_interrupt()
2394 * STAR#9000483510: RTL: SS : USB3 reset event may
2395 * not be generated always when the link enters poll
2397 if (dwc
->revision
< DWC3_REVISION_190A
)
2398 dwc3_gadget_reset_interrupt(dwc
);
2400 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2401 dwc
->gadget
.ep0
->maxpacket
= 512;
2402 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2404 case DWC3_DCFG_HIGHSPEED
:
2405 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2406 dwc
->gadget
.ep0
->maxpacket
= 64;
2407 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2409 case DWC3_DCFG_FULLSPEED2
:
2410 case DWC3_DCFG_FULLSPEED1
:
2411 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2412 dwc
->gadget
.ep0
->maxpacket
= 64;
2413 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2415 case DWC3_DCFG_LOWSPEED
:
2416 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2417 dwc
->gadget
.ep0
->maxpacket
= 8;
2418 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2422 /* Enable USB2 LPM Capability */
2424 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2425 (speed
!= DWC3_DCFG_SUPERSPEED
) &&
2426 (speed
!= DWC3_DCFG_SUPERSPEED_PLUS
)) {
2427 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2428 reg
|= DWC3_DCFG_LPM_CAP
;
2429 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2431 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2432 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2434 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2437 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2438 * DCFG.LPMCap is set, core responses with an ACK and the
2439 * BESL value in the LPM token is less than or equal to LPM
2442 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2443 && dwc
->has_lpm_erratum
,
2444 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2446 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2447 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2449 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2451 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2452 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2453 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2457 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2460 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2465 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2468 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2473 * Configure PHY via GUSB3PIPECTLn if required.
2475 * Update GTXFIFOSIZn
2477 * In both cases reset values should be sufficient.
2481 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2484 * TODO take core out of low power mode when that's
2488 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2489 spin_unlock(&dwc
->lock
);
2490 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2491 spin_lock(&dwc
->lock
);
2495 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2496 unsigned int evtinfo
)
2498 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2499 unsigned int pwropt
;
2502 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2503 * Hibernation mode enabled which would show up when device detects
2504 * host-initiated U3 exit.
2506 * In that case, device will generate a Link State Change Interrupt
2507 * from U3 to RESUME which is only necessary if Hibernation is
2510 * There are no functional changes due to such spurious event and we
2511 * just need to ignore it.
2515 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2518 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2519 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2520 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2521 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2522 (next
== DWC3_LINK_STATE_RESUME
)) {
2523 dwc3_trace(trace_dwc3_gadget
,
2524 "ignoring transition U3 -> Resume");
2530 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2531 * on the link partner, the USB session might do multiple entry/exit
2532 * of low power states before a transfer takes place.
2534 * Due to this problem, we might experience lower throughput. The
2535 * suggested workaround is to disable DCTL[12:9] bits if we're
2536 * transitioning from U1/U2 to U0 and enable those bits again
2537 * after a transfer completes and there are no pending transfers
2538 * on any of the enabled endpoints.
2540 * This is the first half of that workaround.
2544 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2545 * core send LGO_Ux entering U0
2547 if (dwc
->revision
< DWC3_REVISION_183A
) {
2548 if (next
== DWC3_LINK_STATE_U0
) {
2552 switch (dwc
->link_state
) {
2553 case DWC3_LINK_STATE_U1
:
2554 case DWC3_LINK_STATE_U2
:
2555 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2556 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2557 | DWC3_DCTL_ACCEPTU2ENA
2558 | DWC3_DCTL_INITU1ENA
2559 | DWC3_DCTL_ACCEPTU1ENA
);
2562 dwc
->u1u2
= reg
& u1u2
;
2566 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2576 case DWC3_LINK_STATE_U1
:
2577 if (dwc
->speed
== USB_SPEED_SUPER
)
2578 dwc3_suspend_gadget(dwc
);
2580 case DWC3_LINK_STATE_U2
:
2581 case DWC3_LINK_STATE_U3
:
2582 dwc3_suspend_gadget(dwc
);
2584 case DWC3_LINK_STATE_RESUME
:
2585 dwc3_resume_gadget(dwc
);
2592 dwc
->link_state
= next
;
2595 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2596 unsigned int evtinfo
)
2598 unsigned int is_ss
= evtinfo
& BIT(4);
2601 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2602 * have a known issue which can cause USB CV TD.9.23 to fail
2605 * Because of this issue, core could generate bogus hibernation
2606 * events which SW needs to ignore.
2610 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2611 * Device Fallback from SuperSpeed
2613 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2616 /* enter hibernation here */
2619 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2620 const struct dwc3_event_devt
*event
)
2622 switch (event
->type
) {
2623 case DWC3_DEVICE_EVENT_DISCONNECT
:
2624 dwc3_gadget_disconnect_interrupt(dwc
);
2626 case DWC3_DEVICE_EVENT_RESET
:
2627 dwc3_gadget_reset_interrupt(dwc
);
2629 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2630 dwc3_gadget_conndone_interrupt(dwc
);
2632 case DWC3_DEVICE_EVENT_WAKEUP
:
2633 dwc3_gadget_wakeup_interrupt(dwc
);
2635 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2636 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2637 "unexpected hibernation event\n"))
2640 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2642 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2643 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2645 case DWC3_DEVICE_EVENT_EOPF
:
2646 dwc3_trace(trace_dwc3_gadget
, "End of Periodic Frame");
2648 case DWC3_DEVICE_EVENT_SOF
:
2649 dwc3_trace(trace_dwc3_gadget
, "Start of Periodic Frame");
2651 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2652 dwc3_trace(trace_dwc3_gadget
, "Erratic Error");
2654 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2655 dwc3_trace(trace_dwc3_gadget
, "Command Complete");
2657 case DWC3_DEVICE_EVENT_OVERFLOW
:
2658 dwc3_trace(trace_dwc3_gadget
, "Overflow");
2661 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2665 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2666 const union dwc3_event
*event
)
2668 trace_dwc3_event(event
->raw
);
2670 /* Endpoint IRQ, handle it and return early */
2671 if (event
->type
.is_devspec
== 0) {
2673 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2676 switch (event
->type
.type
) {
2677 case DWC3_EVENT_TYPE_DEV
:
2678 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2680 /* REVISIT what to do with Carkit and I2C events ? */
2682 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2686 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
2688 struct dwc3
*dwc
= evt
->dwc
;
2689 irqreturn_t ret
= IRQ_NONE
;
2695 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2699 union dwc3_event event
;
2701 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2703 dwc3_process_event_entry(dwc
, &event
);
2706 * FIXME we wrap around correctly to the next entry as
2707 * almost all entries are 4 bytes in size. There is one
2708 * entry which has 12 bytes which is a regular entry
2709 * followed by 8 bytes data. ATM I don't know how
2710 * things are organized if we get next to the a
2711 * boundary so I worry about that once we try to handle
2714 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2717 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), 4);
2721 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2724 /* Unmask interrupt */
2725 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2726 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2727 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2732 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
2734 struct dwc3_event_buffer
*evt
= _evt
;
2735 struct dwc3
*dwc
= evt
->dwc
;
2736 unsigned long flags
;
2737 irqreturn_t ret
= IRQ_NONE
;
2739 spin_lock_irqsave(&dwc
->lock
, flags
);
2740 ret
= dwc3_process_event_buf(evt
);
2741 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2746 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
2748 struct dwc3
*dwc
= evt
->dwc
;
2752 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
2753 count
&= DWC3_GEVNTCOUNT_MASK
;
2758 evt
->flags
|= DWC3_EVENT_PENDING
;
2760 /* Mask interrupt */
2761 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2762 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2763 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2765 return IRQ_WAKE_THREAD
;
2768 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
2770 struct dwc3_event_buffer
*evt
= _evt
;
2772 return dwc3_check_event_buf(evt
);
2776 * dwc3_gadget_init - Initializes gadget related registers
2777 * @dwc: pointer to our controller context structure
2779 * Returns 0 on success otherwise negative errno.
2781 int dwc3_gadget_init(struct dwc3
*dwc
)
2785 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2786 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2787 if (!dwc
->ctrl_req
) {
2788 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2793 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
) * 2,
2794 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2795 if (!dwc
->ep0_trb
) {
2796 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2801 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2802 if (!dwc
->setup_buf
) {
2807 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2808 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2810 if (!dwc
->ep0_bounce
) {
2811 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2816 dwc
->zlp_buf
= kzalloc(DWC3_ZLP_BUF_SIZE
, GFP_KERNEL
);
2817 if (!dwc
->zlp_buf
) {
2822 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2823 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2824 dwc
->gadget
.sg_supported
= true;
2825 dwc
->gadget
.name
= "dwc3-gadget";
2826 dwc
->gadget
.is_otg
= dwc
->dr_mode
== USB_DR_MODE_OTG
;
2829 * FIXME We might be setting max_speed to <SUPER, however versions
2830 * <2.20a of dwc3 have an issue with metastability (documented
2831 * elsewhere in this driver) which tells us we can't set max speed to
2832 * anything lower than SUPER.
2834 * Because gadget.max_speed is only used by composite.c and function
2835 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2836 * to happen so we avoid sending SuperSpeed Capability descriptor
2837 * together with our BOS descriptor as that could confuse host into
2838 * thinking we can handle super speed.
2840 * Note that, in fact, we won't even support GetBOS requests when speed
2841 * is less than super speed because we don't have means, yet, to tell
2842 * composite.c that we are USB 2.0 + LPM ECN.
2844 if (dwc
->revision
< DWC3_REVISION_220A
)
2845 dwc3_trace(trace_dwc3_gadget
,
2846 "Changing max_speed on rev %08x\n",
2849 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
2852 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2855 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
2858 * REVISIT: Here we should clear all pending IRQs to be
2859 * sure we're starting from a well known location.
2862 ret
= dwc3_gadget_init_endpoints(dwc
);
2866 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2868 dev_err(dwc
->dev
, "failed to register udc\n");
2875 kfree(dwc
->zlp_buf
);
2878 dwc3_gadget_free_endpoints(dwc
);
2879 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2880 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2883 kfree(dwc
->setup_buf
);
2886 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2887 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2890 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2891 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2897 /* -------------------------------------------------------------------------- */
2899 void dwc3_gadget_exit(struct dwc3
*dwc
)
2901 usb_del_gadget_udc(&dwc
->gadget
);
2903 dwc3_gadget_free_endpoints(dwc
);
2905 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2906 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2908 kfree(dwc
->setup_buf
);
2909 kfree(dwc
->zlp_buf
);
2911 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2912 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2914 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2915 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2918 int dwc3_gadget_suspend(struct dwc3
*dwc
)
2920 if (!dwc
->gadget_driver
)
2923 if (dwc
->pullups_connected
) {
2924 dwc3_gadget_disable_irq(dwc
);
2925 dwc3_gadget_run_stop(dwc
, true, true);
2928 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2929 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
2931 dwc
->dcfg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2936 int dwc3_gadget_resume(struct dwc3
*dwc
)
2938 struct dwc3_ep
*dep
;
2941 if (!dwc
->gadget_driver
)
2944 /* Start with SuperSpeed Default */
2945 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2948 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
2954 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
2959 /* begin to receive SETUP packets */
2960 dwc
->ep0state
= EP0_SETUP_PHASE
;
2961 dwc3_ep0_out_start(dwc
);
2963 dwc3_writel(dwc
->regs
, DWC3_DCFG
, dwc
->dcfg
);
2965 if (dwc
->pullups_connected
) {
2966 dwc3_gadget_enable_irq(dwc
);
2967 dwc3_gadget_run_stop(dwc
, true, false);
2973 __dwc3_gadget_ep_disable(dwc
->eps
[0]);