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Merge branches 'pm-core', 'pm-clk', 'pm-domains' and 'pm-pci'
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102 #include <linux/usb.h>
103
104 #include "musb_core.h"
105
106 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
107
108
109 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111
112 #define MUSB_VERSION "6.0"
113
114 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115
116 #define MUSB_DRIVER_NAME "musb-hdrc"
117 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118
119 MODULE_DESCRIPTION(DRIVER_INFO);
120 MODULE_AUTHOR(DRIVER_AUTHOR);
121 MODULE_LICENSE("GPL");
122 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
123
124
125 /*-------------------------------------------------------------------------*/
126
127 static inline struct musb *dev_to_musb(struct device *dev)
128 {
129 return dev_get_drvdata(dev);
130 }
131
132 /*-------------------------------------------------------------------------*/
133
134 #ifndef CONFIG_BLACKFIN
135 static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
136 {
137 void __iomem *addr = phy->io_priv;
138 int i = 0;
139 u8 r;
140 u8 power;
141 int ret;
142
143 pm_runtime_get_sync(phy->io_dev);
144
145 /* Make sure the transceiver is not in low power mode */
146 power = musb_readb(addr, MUSB_POWER);
147 power &= ~MUSB_POWER_SUSPENDM;
148 musb_writeb(addr, MUSB_POWER, power);
149
150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
152 */
153
154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157
158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
159 & MUSB_ULPI_REG_CMPLT)) {
160 i++;
161 if (i == 10000) {
162 ret = -ETIMEDOUT;
163 goto out;
164 }
165
166 }
167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
168 r &= ~MUSB_ULPI_REG_CMPLT;
169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170
171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
172
173 out:
174 pm_runtime_put(phy->io_dev);
175
176 return ret;
177 }
178
179 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
180 {
181 void __iomem *addr = phy->io_priv;
182 int i = 0;
183 u8 r = 0;
184 u8 power;
185 int ret = 0;
186
187 pm_runtime_get_sync(phy->io_dev);
188
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
193
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
197
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
200 i++;
201 if (i == 10000) {
202 ret = -ETIMEDOUT;
203 goto out;
204 }
205 }
206
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
210
211 out:
212 pm_runtime_put(phy->io_dev);
213
214 return ret;
215 }
216 #else
217 #define musb_ulpi_read NULL
218 #define musb_ulpi_write NULL
219 #endif
220
221 static struct usb_phy_io_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
224 };
225
226 /*-------------------------------------------------------------------------*/
227
228 static u32 musb_default_fifo_offset(u8 epnum)
229 {
230 return 0x20 + (epnum * 4);
231 }
232
233 /* "flat" mapping: each endpoint has its own i/o address */
234 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
235 {
236 }
237
238 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
239 {
240 return 0x100 + (0x10 * epnum) + offset;
241 }
242
243 /* "indexed" mapping: INDEX register controls register bank select */
244 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
245 {
246 musb_writeb(mbase, MUSB_INDEX, epnum);
247 }
248
249 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
250 {
251 return 0x10 + offset;
252 }
253
254 static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
255 {
256 return 0x80 + (0x08 * epnum) + offset;
257 }
258
259 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
260 {
261 return __raw_readb(addr + offset);
262 }
263
264 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
265 {
266 __raw_writeb(data, addr + offset);
267 }
268
269 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
270 {
271 return __raw_readw(addr + offset);
272 }
273
274 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
275 {
276 __raw_writew(data, addr + offset);
277 }
278
279 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
280 {
281 return __raw_readl(addr + offset);
282 }
283
284 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
285 {
286 __raw_writel(data, addr + offset);
287 }
288
289 /*
290 * Load an endpoint's FIFO
291 */
292 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
293 const u8 *src)
294 {
295 struct musb *musb = hw_ep->musb;
296 void __iomem *fifo = hw_ep->fifo;
297
298 if (unlikely(len == 0))
299 return;
300
301 prefetch((u8 *)src);
302
303 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
304 'T', hw_ep->epnum, fifo, len, src);
305
306 /* we can't assume unaligned reads work */
307 if (likely((0x01 & (unsigned long) src) == 0)) {
308 u16 index = 0;
309
310 /* best case is 32bit-aligned source address */
311 if ((0x02 & (unsigned long) src) == 0) {
312 if (len >= 4) {
313 iowrite32_rep(fifo, src + index, len >> 2);
314 index += len & ~0x03;
315 }
316 if (len & 0x02) {
317 __raw_writew(*(u16 *)&src[index], fifo);
318 index += 2;
319 }
320 } else {
321 if (len >= 2) {
322 iowrite16_rep(fifo, src + index, len >> 1);
323 index += len & ~0x01;
324 }
325 }
326 if (len & 0x01)
327 __raw_writeb(src[index], fifo);
328 } else {
329 /* byte aligned */
330 iowrite8_rep(fifo, src, len);
331 }
332 }
333
334 /*
335 * Unload an endpoint's FIFO
336 */
337 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
338 {
339 struct musb *musb = hw_ep->musb;
340 void __iomem *fifo = hw_ep->fifo;
341
342 if (unlikely(len == 0))
343 return;
344
345 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
346 'R', hw_ep->epnum, fifo, len, dst);
347
348 /* we can't assume unaligned writes work */
349 if (likely((0x01 & (unsigned long) dst) == 0)) {
350 u16 index = 0;
351
352 /* best case is 32bit-aligned destination address */
353 if ((0x02 & (unsigned long) dst) == 0) {
354 if (len >= 4) {
355 ioread32_rep(fifo, dst, len >> 2);
356 index = len & ~0x03;
357 }
358 if (len & 0x02) {
359 *(u16 *)&dst[index] = __raw_readw(fifo);
360 index += 2;
361 }
362 } else {
363 if (len >= 2) {
364 ioread16_rep(fifo, dst, len >> 1);
365 index = len & ~0x01;
366 }
367 }
368 if (len & 0x01)
369 dst[index] = __raw_readb(fifo);
370 } else {
371 /* byte aligned */
372 ioread8_rep(fifo, dst, len);
373 }
374 }
375
376 /*
377 * Old style IO functions
378 */
379 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readb);
381
382 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
383 EXPORT_SYMBOL_GPL(musb_writeb);
384
385 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readw);
387
388 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
389 EXPORT_SYMBOL_GPL(musb_writew);
390
391 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
392 EXPORT_SYMBOL_GPL(musb_readl);
393
394 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
395 EXPORT_SYMBOL_GPL(musb_writel);
396
397 #ifndef CONFIG_MUSB_PIO_ONLY
398 struct dma_controller *
399 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
400 EXPORT_SYMBOL(musb_dma_controller_create);
401
402 void (*musb_dma_controller_destroy)(struct dma_controller *c);
403 EXPORT_SYMBOL(musb_dma_controller_destroy);
404 #endif
405
406 /*
407 * New style IO functions
408 */
409 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
410 {
411 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
412 }
413
414 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
415 {
416 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
417 }
418
419 /*-------------------------------------------------------------------------*/
420
421 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
422 static const u8 musb_test_packet[53] = {
423 /* implicit SYNC then DATA0 to start */
424
425 /* JKJKJKJK x9 */
426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
427 /* JJKKJJKK x8 */
428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
429 /* JJJJKKKK x8 */
430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431 /* JJJJJJJKKKKKKK x8 */
432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
433 /* JJJJJJJK x8 */
434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435 /* JKKKKKKK x10, JK */
436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
437
438 /* implicit CRC16 then EOP to end */
439 };
440
441 void musb_load_testpacket(struct musb *musb)
442 {
443 void __iomem *regs = musb->endpoints[0].regs;
444
445 musb_ep_select(musb->mregs, 0);
446 musb_write_fifo(musb->control_ep,
447 sizeof(musb_test_packet), musb_test_packet);
448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
449 }
450
451 /*-------------------------------------------------------------------------*/
452
453 /*
454 * Handles OTG hnp timeouts, such as b_ase0_brst
455 */
456 static void musb_otg_timer_func(unsigned long data)
457 {
458 struct musb *musb = (struct musb *)data;
459 unsigned long flags;
460
461 spin_lock_irqsave(&musb->lock, flags);
462 switch (musb->xceiv->otg->state) {
463 case OTG_STATE_B_WAIT_ACON:
464 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
465 musb_g_disconnect(musb);
466 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
467 musb->is_active = 0;
468 break;
469 case OTG_STATE_A_SUSPEND:
470 case OTG_STATE_A_WAIT_BCON:
471 dev_dbg(musb->controller, "HNP: %s timeout\n",
472 usb_otg_state_string(musb->xceiv->otg->state));
473 musb_platform_set_vbus(musb, 0);
474 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
475 break;
476 default:
477 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
479 }
480 spin_unlock_irqrestore(&musb->lock, flags);
481 }
482
483 /*
484 * Stops the HNP transition. Caller must take care of locking.
485 */
486 void musb_hnp_stop(struct musb *musb)
487 {
488 struct usb_hcd *hcd = musb->hcd;
489 void __iomem *mbase = musb->mregs;
490 u8 reg;
491
492 dev_dbg(musb->controller, "HNP: stop from %s\n",
493 usb_otg_state_string(musb->xceiv->otg->state));
494
495 switch (musb->xceiv->otg->state) {
496 case OTG_STATE_A_PERIPHERAL:
497 musb_g_disconnect(musb);
498 dev_dbg(musb->controller, "HNP: back to %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
500 break;
501 case OTG_STATE_B_HOST:
502 dev_dbg(musb->controller, "HNP: Disabling HR\n");
503 if (hcd)
504 hcd->self.is_b_host = 0;
505 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
506 MUSB_DEV_MODE(musb);
507 reg = musb_readb(mbase, MUSB_POWER);
508 reg |= MUSB_POWER_SUSPENDM;
509 musb_writeb(mbase, MUSB_POWER, reg);
510 /* REVISIT: Start SESSION_REQUEST here? */
511 break;
512 default:
513 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
514 usb_otg_state_string(musb->xceiv->otg->state));
515 }
516
517 /*
518 * When returning to A state after HNP, avoid hub_port_rebounce(),
519 * which cause occasional OPT A "Did not receive reset after connect"
520 * errors.
521 */
522 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
523 }
524
525 static void musb_recover_from_babble(struct musb *musb);
526
527 /*
528 * Interrupt Service Routine to record USB "global" interrupts.
529 * Since these do not happen often and signify things of
530 * paramount importance, it seems OK to check them individually;
531 * the order of the tests is specified in the manual
532 *
533 * @param musb instance pointer
534 * @param int_usb register contents
535 * @param devctl
536 * @param power
537 */
538
539 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
540 u8 devctl)
541 {
542 irqreturn_t handled = IRQ_NONE;
543
544 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
545 int_usb);
546
547 /* in host mode, the peripheral may issue remote wakeup.
548 * in peripheral mode, the host may resume the link.
549 * spurious RESUME irqs happen too, paired with SUSPEND.
550 */
551 if (int_usb & MUSB_INTR_RESUME) {
552 handled = IRQ_HANDLED;
553 dev_dbg(musb->controller, "RESUME (%s)\n",
554 usb_otg_state_string(musb->xceiv->otg->state));
555
556 if (devctl & MUSB_DEVCTL_HM) {
557 switch (musb->xceiv->otg->state) {
558 case OTG_STATE_A_SUSPEND:
559 /* remote wakeup? later, GetPortStatus
560 * will stop RESUME signaling
561 */
562
563 musb->port1_status |=
564 (USB_PORT_STAT_C_SUSPEND << 16)
565 | MUSB_PORT_STAT_RESUME;
566 musb->rh_timer = jiffies
567 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
568 musb->need_finish_resume = 1;
569
570 musb->xceiv->otg->state = OTG_STATE_A_HOST;
571 musb->is_active = 1;
572 musb_host_resume_root_hub(musb);
573 break;
574 case OTG_STATE_B_WAIT_ACON:
575 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
576 musb->is_active = 1;
577 MUSB_DEV_MODE(musb);
578 break;
579 default:
580 WARNING("bogus %s RESUME (%s)\n",
581 "host",
582 usb_otg_state_string(musb->xceiv->otg->state));
583 }
584 } else {
585 switch (musb->xceiv->otg->state) {
586 case OTG_STATE_A_SUSPEND:
587 /* possibly DISCONNECT is upcoming */
588 musb->xceiv->otg->state = OTG_STATE_A_HOST;
589 musb_host_resume_root_hub(musb);
590 break;
591 case OTG_STATE_B_WAIT_ACON:
592 case OTG_STATE_B_PERIPHERAL:
593 /* disconnect while suspended? we may
594 * not get a disconnect irq...
595 */
596 if ((devctl & MUSB_DEVCTL_VBUS)
597 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
598 ) {
599 musb->int_usb |= MUSB_INTR_DISCONNECT;
600 musb->int_usb &= ~MUSB_INTR_SUSPEND;
601 break;
602 }
603 musb_g_resume(musb);
604 break;
605 case OTG_STATE_B_IDLE:
606 musb->int_usb &= ~MUSB_INTR_SUSPEND;
607 break;
608 default:
609 WARNING("bogus %s RESUME (%s)\n",
610 "peripheral",
611 usb_otg_state_string(musb->xceiv->otg->state));
612 }
613 }
614 }
615
616 /* see manual for the order of the tests */
617 if (int_usb & MUSB_INTR_SESSREQ) {
618 void __iomem *mbase = musb->mregs;
619
620 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
621 && (devctl & MUSB_DEVCTL_BDEVICE)) {
622 dev_dbg(musb->controller, "SessReq while on B state\n");
623 return IRQ_HANDLED;
624 }
625
626 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
627 usb_otg_state_string(musb->xceiv->otg->state));
628
629 /* IRQ arrives from ID pin sense or (later, if VBUS power
630 * is removed) SRP. responses are time critical:
631 * - turn on VBUS (with silicon-specific mechanism)
632 * - go through A_WAIT_VRISE
633 * - ... to A_WAIT_BCON.
634 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
635 */
636 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
637 musb->ep0_stage = MUSB_EP0_START;
638 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
639 MUSB_HST_MODE(musb);
640 musb_platform_set_vbus(musb, 1);
641
642 handled = IRQ_HANDLED;
643 }
644
645 if (int_usb & MUSB_INTR_VBUSERROR) {
646 int ignore = 0;
647
648 /* During connection as an A-Device, we may see a short
649 * current spikes causing voltage drop, because of cable
650 * and peripheral capacitance combined with vbus draw.
651 * (So: less common with truly self-powered devices, where
652 * vbus doesn't act like a power supply.)
653 *
654 * Such spikes are short; usually less than ~500 usec, max
655 * of ~2 msec. That is, they're not sustained overcurrent
656 * errors, though they're reported using VBUSERROR irqs.
657 *
658 * Workarounds: (a) hardware: use self powered devices.
659 * (b) software: ignore non-repeated VBUS errors.
660 *
661 * REVISIT: do delays from lots of DEBUG_KERNEL checks
662 * make trouble here, keeping VBUS < 4.4V ?
663 */
664 switch (musb->xceiv->otg->state) {
665 case OTG_STATE_A_HOST:
666 /* recovery is dicey once we've gotten past the
667 * initial stages of enumeration, but if VBUS
668 * stayed ok at the other end of the link, and
669 * another reset is due (at least for high speed,
670 * to redo the chirp etc), it might work OK...
671 */
672 case OTG_STATE_A_WAIT_BCON:
673 case OTG_STATE_A_WAIT_VRISE:
674 if (musb->vbuserr_retry) {
675 void __iomem *mbase = musb->mregs;
676
677 musb->vbuserr_retry--;
678 ignore = 1;
679 devctl |= MUSB_DEVCTL_SESSION;
680 musb_writeb(mbase, MUSB_DEVCTL, devctl);
681 } else {
682 musb->port1_status |=
683 USB_PORT_STAT_OVERCURRENT
684 | (USB_PORT_STAT_C_OVERCURRENT << 16);
685 }
686 break;
687 default:
688 break;
689 }
690
691 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
692 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
693 usb_otg_state_string(musb->xceiv->otg->state),
694 devctl,
695 ({ char *s;
696 switch (devctl & MUSB_DEVCTL_VBUS) {
697 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<SessEnd"; break;
699 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<AValid"; break;
701 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
702 s = "<VBusValid"; break;
703 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
704 default:
705 s = "VALID"; break;
706 } s; }),
707 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
708 musb->port1_status);
709
710 /* go through A_WAIT_VFALL then start a new session */
711 if (!ignore)
712 musb_platform_set_vbus(musb, 0);
713 handled = IRQ_HANDLED;
714 }
715
716 if (int_usb & MUSB_INTR_SUSPEND) {
717 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
718 usb_otg_state_string(musb->xceiv->otg->state), devctl);
719 handled = IRQ_HANDLED;
720
721 switch (musb->xceiv->otg->state) {
722 case OTG_STATE_A_PERIPHERAL:
723 /* We also come here if the cable is removed, since
724 * this silicon doesn't report ID-no-longer-grounded.
725 *
726 * We depend on T(a_wait_bcon) to shut us down, and
727 * hope users don't do anything dicey during this
728 * undesired detour through A_WAIT_BCON.
729 */
730 musb_hnp_stop(musb);
731 musb_host_resume_root_hub(musb);
732 musb_root_disconnect(musb);
733 musb_platform_try_idle(musb, jiffies
734 + msecs_to_jiffies(musb->a_wait_bcon
735 ? : OTG_TIME_A_WAIT_BCON));
736
737 break;
738 case OTG_STATE_B_IDLE:
739 if (!musb->is_active)
740 break;
741 case OTG_STATE_B_PERIPHERAL:
742 musb_g_suspend(musb);
743 musb->is_active = musb->g.b_hnp_enable;
744 if (musb->is_active) {
745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
746 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
747 mod_timer(&musb->otg_timer, jiffies
748 + msecs_to_jiffies(
749 OTG_TIME_B_ASE0_BRST));
750 }
751 break;
752 case OTG_STATE_A_WAIT_BCON:
753 if (musb->a_wait_bcon != 0)
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
756 break;
757 case OTG_STATE_A_HOST:
758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
759 musb->is_active = musb->hcd->self.b_hnp_enable;
760 break;
761 case OTG_STATE_B_HOST:
762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
763 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
764 break;
765 default:
766 /* "should not happen" */
767 musb->is_active = 0;
768 break;
769 }
770 }
771
772 if (int_usb & MUSB_INTR_CONNECT) {
773 struct usb_hcd *hcd = musb->hcd;
774
775 handled = IRQ_HANDLED;
776 musb->is_active = 1;
777
778 musb->ep0_stage = MUSB_EP0_START;
779
780 musb->intrtxe = musb->epmask;
781 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
782 musb->intrrxe = musb->epmask & 0xfffe;
783 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
784 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
785 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
786 |USB_PORT_STAT_HIGH_SPEED
787 |USB_PORT_STAT_ENABLE
788 );
789 musb->port1_status |= USB_PORT_STAT_CONNECTION
790 |(USB_PORT_STAT_C_CONNECTION << 16);
791
792 /* high vs full speed is just a guess until after reset */
793 if (devctl & MUSB_DEVCTL_LSDEV)
794 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
795
796 /* indicate new connection to OTG machine */
797 switch (musb->xceiv->otg->state) {
798 case OTG_STATE_B_PERIPHERAL:
799 if (int_usb & MUSB_INTR_SUSPEND) {
800 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
801 int_usb &= ~MUSB_INTR_SUSPEND;
802 goto b_host;
803 } else
804 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
805 break;
806 case OTG_STATE_B_WAIT_ACON:
807 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
808 b_host:
809 musb->xceiv->otg->state = OTG_STATE_B_HOST;
810 if (musb->hcd)
811 musb->hcd->self.is_b_host = 1;
812 del_timer(&musb->otg_timer);
813 break;
814 default:
815 if ((devctl & MUSB_DEVCTL_VBUS)
816 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
817 musb->xceiv->otg->state = OTG_STATE_A_HOST;
818 if (hcd)
819 hcd->self.is_b_host = 0;
820 }
821 break;
822 }
823
824 musb_host_poke_root_hub(musb);
825
826 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
827 usb_otg_state_string(musb->xceiv->otg->state), devctl);
828 }
829
830 if (int_usb & MUSB_INTR_DISCONNECT) {
831 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
832 usb_otg_state_string(musb->xceiv->otg->state),
833 MUSB_MODE(musb), devctl);
834 handled = IRQ_HANDLED;
835
836 switch (musb->xceiv->otg->state) {
837 case OTG_STATE_A_HOST:
838 case OTG_STATE_A_SUSPEND:
839 musb_host_resume_root_hub(musb);
840 musb_root_disconnect(musb);
841 if (musb->a_wait_bcon != 0)
842 musb_platform_try_idle(musb, jiffies
843 + msecs_to_jiffies(musb->a_wait_bcon));
844 break;
845 case OTG_STATE_B_HOST:
846 /* REVISIT this behaves for "real disconnect"
847 * cases; make sure the other transitions from
848 * from B_HOST act right too. The B_HOST code
849 * in hnp_stop() is currently not used...
850 */
851 musb_root_disconnect(musb);
852 if (musb->hcd)
853 musb->hcd->self.is_b_host = 0;
854 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
855 MUSB_DEV_MODE(musb);
856 musb_g_disconnect(musb);
857 break;
858 case OTG_STATE_A_PERIPHERAL:
859 musb_hnp_stop(musb);
860 musb_root_disconnect(musb);
861 /* FALLTHROUGH */
862 case OTG_STATE_B_WAIT_ACON:
863 /* FALLTHROUGH */
864 case OTG_STATE_B_PERIPHERAL:
865 case OTG_STATE_B_IDLE:
866 musb_g_disconnect(musb);
867 break;
868 default:
869 WARNING("unhandled DISCONNECT transition (%s)\n",
870 usb_otg_state_string(musb->xceiv->otg->state));
871 break;
872 }
873 }
874
875 /* mentor saves a bit: bus reset and babble share the same irq.
876 * only host sees babble; only peripheral sees bus reset.
877 */
878 if (int_usb & MUSB_INTR_RESET) {
879 handled = IRQ_HANDLED;
880 if (devctl & MUSB_DEVCTL_HM) {
881 /*
882 * When BABBLE happens what we can depends on which
883 * platform MUSB is running, because some platforms
884 * implemented proprietary means for 'recovering' from
885 * Babble conditions. One such platform is AM335x. In
886 * most cases, however, the only thing we can do is
887 * drop the session.
888 */
889 dev_err(musb->controller, "Babble\n");
890
891 if (is_host_active(musb))
892 musb_recover_from_babble(musb);
893 } else {
894 dev_dbg(musb->controller, "BUS RESET as %s\n",
895 usb_otg_state_string(musb->xceiv->otg->state));
896 switch (musb->xceiv->otg->state) {
897 case OTG_STATE_A_SUSPEND:
898 musb_g_reset(musb);
899 /* FALLTHROUGH */
900 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
901 /* never use invalid T(a_wait_bcon) */
902 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
903 usb_otg_state_string(musb->xceiv->otg->state),
904 TA_WAIT_BCON(musb));
905 mod_timer(&musb->otg_timer, jiffies
906 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
907 break;
908 case OTG_STATE_A_PERIPHERAL:
909 del_timer(&musb->otg_timer);
910 musb_g_reset(musb);
911 break;
912 case OTG_STATE_B_WAIT_ACON:
913 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
914 usb_otg_state_string(musb->xceiv->otg->state));
915 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
916 musb_g_reset(musb);
917 break;
918 case OTG_STATE_B_IDLE:
919 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
920 /* FALLTHROUGH */
921 case OTG_STATE_B_PERIPHERAL:
922 musb_g_reset(musb);
923 break;
924 default:
925 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
926 usb_otg_state_string(musb->xceiv->otg->state));
927 }
928 }
929 }
930
931 #if 0
932 /* REVISIT ... this would be for multiplexing periodic endpoints, or
933 * supporting transfer phasing to prevent exceeding ISO bandwidth
934 * limits of a given frame or microframe.
935 *
936 * It's not needed for peripheral side, which dedicates endpoints;
937 * though it _might_ use SOF irqs for other purposes.
938 *
939 * And it's not currently needed for host side, which also dedicates
940 * endpoints, relies on TX/RX interval registers, and isn't claimed
941 * to support ISO transfers yet.
942 */
943 if (int_usb & MUSB_INTR_SOF) {
944 void __iomem *mbase = musb->mregs;
945 struct musb_hw_ep *ep;
946 u8 epnum;
947 u16 frame;
948
949 dev_dbg(musb->controller, "START_OF_FRAME\n");
950 handled = IRQ_HANDLED;
951
952 /* start any periodic Tx transfers waiting for current frame */
953 frame = musb_readw(mbase, MUSB_FRAME);
954 ep = musb->endpoints;
955 for (epnum = 1; (epnum < musb->nr_endpoints)
956 && (musb->epmask >= (1 << epnum));
957 epnum++, ep++) {
958 /*
959 * FIXME handle framecounter wraps (12 bits)
960 * eliminate duplicated StartUrb logic
961 */
962 if (ep->dwWaitFrame >= frame) {
963 ep->dwWaitFrame = 0;
964 pr_debug("SOF --> periodic TX%s on %d\n",
965 ep->tx_channel ? " DMA" : "",
966 epnum);
967 if (!ep->tx_channel)
968 musb_h_tx_start(musb, epnum);
969 else
970 cppi_hostdma_start(musb, epnum);
971 }
972 } /* end of for loop */
973 }
974 #endif
975
976 schedule_work(&musb->irq_work);
977
978 return handled;
979 }
980
981 /*-------------------------------------------------------------------------*/
982
983 static void musb_disable_interrupts(struct musb *musb)
984 {
985 void __iomem *mbase = musb->mregs;
986 u16 temp;
987
988 /* disable interrupts */
989 musb_writeb(mbase, MUSB_INTRUSBE, 0);
990 musb->intrtxe = 0;
991 musb_writew(mbase, MUSB_INTRTXE, 0);
992 musb->intrrxe = 0;
993 musb_writew(mbase, MUSB_INTRRXE, 0);
994
995 /* flush pending interrupts */
996 temp = musb_readb(mbase, MUSB_INTRUSB);
997 temp = musb_readw(mbase, MUSB_INTRTX);
998 temp = musb_readw(mbase, MUSB_INTRRX);
999 }
1000
1001 static void musb_enable_interrupts(struct musb *musb)
1002 {
1003 void __iomem *regs = musb->mregs;
1004
1005 /* Set INT enable registers, enable interrupts */
1006 musb->intrtxe = musb->epmask;
1007 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1008 musb->intrrxe = musb->epmask & 0xfffe;
1009 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1010 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1011
1012 }
1013
1014 static void musb_generic_disable(struct musb *musb)
1015 {
1016 void __iomem *mbase = musb->mregs;
1017
1018 musb_disable_interrupts(musb);
1019
1020 /* off */
1021 musb_writeb(mbase, MUSB_DEVCTL, 0);
1022 }
1023
1024 /*
1025 * Program the HDRC to start (enable interrupts, dma, etc.).
1026 */
1027 void musb_start(struct musb *musb)
1028 {
1029 void __iomem *regs = musb->mregs;
1030 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1031 u8 power;
1032
1033 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1034
1035 musb_enable_interrupts(musb);
1036 musb_writeb(regs, MUSB_TESTMODE, 0);
1037
1038 power = MUSB_POWER_ISOUPDATE;
1039 /*
1040 * treating UNKNOWN as unspecified maximum speed, in which case
1041 * we will default to high-speed.
1042 */
1043 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1044 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1045 power |= MUSB_POWER_HSENAB;
1046 musb_writeb(regs, MUSB_POWER, power);
1047
1048 musb->is_active = 0;
1049 devctl = musb_readb(regs, MUSB_DEVCTL);
1050 devctl &= ~MUSB_DEVCTL_SESSION;
1051
1052 /* session started after:
1053 * (a) ID-grounded irq, host mode;
1054 * (b) vbus present/connect IRQ, peripheral mode;
1055 * (c) peripheral initiates, using SRP
1056 */
1057 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1058 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1059 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1060 musb->is_active = 1;
1061 } else {
1062 devctl |= MUSB_DEVCTL_SESSION;
1063 }
1064
1065 musb_platform_enable(musb);
1066 musb_writeb(regs, MUSB_DEVCTL, devctl);
1067 }
1068
1069 /*
1070 * Make the HDRC stop (disable interrupts, etc.);
1071 * reversible by musb_start
1072 * called on gadget driver unregister
1073 * with controller locked, irqs blocked
1074 * acts as a NOP unless some role activated the hardware
1075 */
1076 void musb_stop(struct musb *musb)
1077 {
1078 /* stop IRQs, timers, ... */
1079 musb_platform_disable(musb);
1080 musb_generic_disable(musb);
1081 dev_dbg(musb->controller, "HDRC disabled\n");
1082
1083 /* FIXME
1084 * - mark host and/or peripheral drivers unusable/inactive
1085 * - disable DMA (and enable it in HdrcStart)
1086 * - make sure we can musb_start() after musb_stop(); with
1087 * OTG mode, gadget driver module rmmod/modprobe cycles that
1088 * - ...
1089 */
1090 musb_platform_try_idle(musb, 0);
1091 }
1092
1093 /*-------------------------------------------------------------------------*/
1094
1095 /*
1096 * The silicon either has hard-wired endpoint configurations, or else
1097 * "dynamic fifo" sizing. The driver has support for both, though at this
1098 * writing only the dynamic sizing is very well tested. Since we switched
1099 * away from compile-time hardware parameters, we can no longer rely on
1100 * dead code elimination to leave only the relevant one in the object file.
1101 *
1102 * We don't currently use dynamic fifo setup capability to do anything
1103 * more than selecting one of a bunch of predefined configurations.
1104 */
1105 static ushort fifo_mode;
1106
1107 /* "modprobe ... fifo_mode=1" etc */
1108 module_param(fifo_mode, ushort, 0);
1109 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1110
1111 /*
1112 * tables defining fifo_mode values. define more if you like.
1113 * for host side, make sure both halves of ep1 are set up.
1114 */
1115
1116 /* mode 0 - fits in 2KB */
1117 static struct musb_fifo_cfg mode_0_cfg[] = {
1118 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1119 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1120 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1121 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1122 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1123 };
1124
1125 /* mode 1 - fits in 4KB */
1126 static struct musb_fifo_cfg mode_1_cfg[] = {
1127 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1128 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1129 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1130 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1131 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1132 };
1133
1134 /* mode 2 - fits in 4KB */
1135 static struct musb_fifo_cfg mode_2_cfg[] = {
1136 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1137 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1138 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1139 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1140 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1141 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1142 };
1143
1144 /* mode 3 - fits in 4KB */
1145 static struct musb_fifo_cfg mode_3_cfg[] = {
1146 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1147 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1148 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1149 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1150 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1151 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1152 };
1153
1154 /* mode 4 - fits in 16KB */
1155 static struct musb_fifo_cfg mode_4_cfg[] = {
1156 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1157 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1158 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1159 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1160 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1161 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1162 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1163 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1164 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1165 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1166 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1167 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1168 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1169 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1170 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1171 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1172 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1173 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1174 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1175 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1176 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1177 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1178 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1179 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1180 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1181 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1182 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1183 };
1184
1185 /* mode 5 - fits in 8KB */
1186 static struct musb_fifo_cfg mode_5_cfg[] = {
1187 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1188 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1189 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1190 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1191 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1192 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1193 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1194 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1195 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1196 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1197 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1198 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1199 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1200 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1201 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1202 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1203 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1204 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1205 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1206 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1207 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1208 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1209 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1210 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1211 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1212 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1213 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1214 };
1215
1216 /*
1217 * configure a fifo; for non-shared endpoints, this may be called
1218 * once for a tx fifo and once for an rx fifo.
1219 *
1220 * returns negative errno or offset for next fifo.
1221 */
1222 static int
1223 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1224 const struct musb_fifo_cfg *cfg, u16 offset)
1225 {
1226 void __iomem *mbase = musb->mregs;
1227 int size = 0;
1228 u16 maxpacket = cfg->maxpacket;
1229 u16 c_off = offset >> 3;
1230 u8 c_size;
1231
1232 /* expect hw_ep has already been zero-initialized */
1233
1234 size = ffs(max(maxpacket, (u16) 8)) - 1;
1235 maxpacket = 1 << size;
1236
1237 c_size = size - 3;
1238 if (cfg->mode == BUF_DOUBLE) {
1239 if ((offset + (maxpacket << 1)) >
1240 (1 << (musb->config->ram_bits + 2)))
1241 return -EMSGSIZE;
1242 c_size |= MUSB_FIFOSZ_DPB;
1243 } else {
1244 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1245 return -EMSGSIZE;
1246 }
1247
1248 /* configure the FIFO */
1249 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1250
1251 /* EP0 reserved endpoint for control, bidirectional;
1252 * EP1 reserved for bulk, two unidirectional halves.
1253 */
1254 if (hw_ep->epnum == 1)
1255 musb->bulk_ep = hw_ep;
1256 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1257 switch (cfg->style) {
1258 case FIFO_TX:
1259 musb_write_txfifosz(mbase, c_size);
1260 musb_write_txfifoadd(mbase, c_off);
1261 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1262 hw_ep->max_packet_sz_tx = maxpacket;
1263 break;
1264 case FIFO_RX:
1265 musb_write_rxfifosz(mbase, c_size);
1266 musb_write_rxfifoadd(mbase, c_off);
1267 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1268 hw_ep->max_packet_sz_rx = maxpacket;
1269 break;
1270 case FIFO_RXTX:
1271 musb_write_txfifosz(mbase, c_size);
1272 musb_write_txfifoadd(mbase, c_off);
1273 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1274 hw_ep->max_packet_sz_rx = maxpacket;
1275
1276 musb_write_rxfifosz(mbase, c_size);
1277 musb_write_rxfifoadd(mbase, c_off);
1278 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1279 hw_ep->max_packet_sz_tx = maxpacket;
1280
1281 hw_ep->is_shared_fifo = true;
1282 break;
1283 }
1284
1285 /* NOTE rx and tx endpoint irqs aren't managed separately,
1286 * which happens to be ok
1287 */
1288 musb->epmask |= (1 << hw_ep->epnum);
1289
1290 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1291 }
1292
1293 static struct musb_fifo_cfg ep0_cfg = {
1294 .style = FIFO_RXTX, .maxpacket = 64,
1295 };
1296
1297 static int ep_config_from_table(struct musb *musb)
1298 {
1299 const struct musb_fifo_cfg *cfg;
1300 unsigned i, n;
1301 int offset;
1302 struct musb_hw_ep *hw_ep = musb->endpoints;
1303
1304 if (musb->config->fifo_cfg) {
1305 cfg = musb->config->fifo_cfg;
1306 n = musb->config->fifo_cfg_size;
1307 goto done;
1308 }
1309
1310 switch (fifo_mode) {
1311 default:
1312 fifo_mode = 0;
1313 /* FALLTHROUGH */
1314 case 0:
1315 cfg = mode_0_cfg;
1316 n = ARRAY_SIZE(mode_0_cfg);
1317 break;
1318 case 1:
1319 cfg = mode_1_cfg;
1320 n = ARRAY_SIZE(mode_1_cfg);
1321 break;
1322 case 2:
1323 cfg = mode_2_cfg;
1324 n = ARRAY_SIZE(mode_2_cfg);
1325 break;
1326 case 3:
1327 cfg = mode_3_cfg;
1328 n = ARRAY_SIZE(mode_3_cfg);
1329 break;
1330 case 4:
1331 cfg = mode_4_cfg;
1332 n = ARRAY_SIZE(mode_4_cfg);
1333 break;
1334 case 5:
1335 cfg = mode_5_cfg;
1336 n = ARRAY_SIZE(mode_5_cfg);
1337 break;
1338 }
1339
1340 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1341
1342
1343 done:
1344 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1345 /* assert(offset > 0) */
1346
1347 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1348 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1349 */
1350
1351 for (i = 0; i < n; i++) {
1352 u8 epn = cfg->hw_ep_num;
1353
1354 if (epn >= musb->config->num_eps) {
1355 pr_debug("%s: invalid ep %d\n",
1356 musb_driver_name, epn);
1357 return -EINVAL;
1358 }
1359 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1360 if (offset < 0) {
1361 pr_debug("%s: mem overrun, ep %d\n",
1362 musb_driver_name, epn);
1363 return offset;
1364 }
1365 epn++;
1366 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1367 }
1368
1369 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1370 musb_driver_name,
1371 n + 1, musb->config->num_eps * 2 - 1,
1372 offset, (1 << (musb->config->ram_bits + 2)));
1373
1374 if (!musb->bulk_ep) {
1375 pr_debug("%s: missing bulk\n", musb_driver_name);
1376 return -EINVAL;
1377 }
1378
1379 return 0;
1380 }
1381
1382
1383 /*
1384 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1385 * @param musb the controller
1386 */
1387 static int ep_config_from_hw(struct musb *musb)
1388 {
1389 u8 epnum = 0;
1390 struct musb_hw_ep *hw_ep;
1391 void __iomem *mbase = musb->mregs;
1392 int ret = 0;
1393
1394 dev_dbg(musb->controller, "<== static silicon ep config\n");
1395
1396 /* FIXME pick up ep0 maxpacket size */
1397
1398 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1399 musb_ep_select(mbase, epnum);
1400 hw_ep = musb->endpoints + epnum;
1401
1402 ret = musb_read_fifosize(musb, hw_ep, epnum);
1403 if (ret < 0)
1404 break;
1405
1406 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1407
1408 /* pick an RX/TX endpoint for bulk */
1409 if (hw_ep->max_packet_sz_tx < 512
1410 || hw_ep->max_packet_sz_rx < 512)
1411 continue;
1412
1413 /* REVISIT: this algorithm is lazy, we should at least
1414 * try to pick a double buffered endpoint.
1415 */
1416 if (musb->bulk_ep)
1417 continue;
1418 musb->bulk_ep = hw_ep;
1419 }
1420
1421 if (!musb->bulk_ep) {
1422 pr_debug("%s: missing bulk\n", musb_driver_name);
1423 return -EINVAL;
1424 }
1425
1426 return 0;
1427 }
1428
1429 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1430
1431 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1432 * configure endpoints, or take their config from silicon
1433 */
1434 static int musb_core_init(u16 musb_type, struct musb *musb)
1435 {
1436 u8 reg;
1437 char *type;
1438 char aInfo[90], aRevision[32], aDate[12];
1439 void __iomem *mbase = musb->mregs;
1440 int status = 0;
1441 int i;
1442
1443 /* log core options (read using indexed model) */
1444 reg = musb_read_configdata(mbase);
1445
1446 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1447 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1448 strcat(aInfo, ", dyn FIFOs");
1449 musb->dyn_fifo = true;
1450 }
1451 if (reg & MUSB_CONFIGDATA_MPRXE) {
1452 strcat(aInfo, ", bulk combine");
1453 musb->bulk_combine = true;
1454 }
1455 if (reg & MUSB_CONFIGDATA_MPTXE) {
1456 strcat(aInfo, ", bulk split");
1457 musb->bulk_split = true;
1458 }
1459 if (reg & MUSB_CONFIGDATA_HBRXE) {
1460 strcat(aInfo, ", HB-ISO Rx");
1461 musb->hb_iso_rx = true;
1462 }
1463 if (reg & MUSB_CONFIGDATA_HBTXE) {
1464 strcat(aInfo, ", HB-ISO Tx");
1465 musb->hb_iso_tx = true;
1466 }
1467 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1468 strcat(aInfo, ", SoftConn");
1469
1470 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1471
1472 aDate[0] = 0;
1473 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1474 musb->is_multipoint = 1;
1475 type = "M";
1476 } else {
1477 musb->is_multipoint = 0;
1478 type = "";
1479 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1480 pr_err("%s: kernel must blacklist external hubs\n",
1481 musb_driver_name);
1482 #endif
1483 }
1484
1485 /* log release info */
1486 musb->hwvers = musb_read_hwvers(mbase);
1487 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1488 MUSB_HWVERS_MINOR(musb->hwvers),
1489 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1490 pr_debug("%s: %sHDRC RTL version %s %s\n",
1491 musb_driver_name, type, aRevision, aDate);
1492
1493 /* configure ep0 */
1494 musb_configure_ep0(musb);
1495
1496 /* discover endpoint configuration */
1497 musb->nr_endpoints = 1;
1498 musb->epmask = 1;
1499
1500 if (musb->dyn_fifo)
1501 status = ep_config_from_table(musb);
1502 else
1503 status = ep_config_from_hw(musb);
1504
1505 if (status < 0)
1506 return status;
1507
1508 /* finish init, and print endpoint config */
1509 for (i = 0; i < musb->nr_endpoints; i++) {
1510 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1511
1512 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1513 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1514 if (musb->io.quirks & MUSB_IN_TUSB) {
1515 hw_ep->fifo_async = musb->async + 0x400 +
1516 musb->io.fifo_offset(i);
1517 hw_ep->fifo_sync = musb->sync + 0x400 +
1518 musb->io.fifo_offset(i);
1519 hw_ep->fifo_sync_va =
1520 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1521
1522 if (i == 0)
1523 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1524 else
1525 hw_ep->conf = mbase + 0x400 +
1526 (((i - 1) & 0xf) << 2);
1527 }
1528 #endif
1529
1530 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1531 hw_ep->rx_reinit = 1;
1532 hw_ep->tx_reinit = 1;
1533
1534 if (hw_ep->max_packet_sz_tx) {
1535 dev_dbg(musb->controller,
1536 "%s: hw_ep %d%s, %smax %d\n",
1537 musb_driver_name, i,
1538 hw_ep->is_shared_fifo ? "shared" : "tx",
1539 hw_ep->tx_double_buffered
1540 ? "doublebuffer, " : "",
1541 hw_ep->max_packet_sz_tx);
1542 }
1543 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1544 dev_dbg(musb->controller,
1545 "%s: hw_ep %d%s, %smax %d\n",
1546 musb_driver_name, i,
1547 "rx",
1548 hw_ep->rx_double_buffered
1549 ? "doublebuffer, " : "",
1550 hw_ep->max_packet_sz_rx);
1551 }
1552 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1553 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1554 }
1555
1556 return 0;
1557 }
1558
1559 /*-------------------------------------------------------------------------*/
1560
1561 /*
1562 * handle all the irqs defined by the HDRC core. for now we expect: other
1563 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1564 * will be assigned, and the irq will already have been acked.
1565 *
1566 * called in irq context with spinlock held, irqs blocked
1567 */
1568 irqreturn_t musb_interrupt(struct musb *musb)
1569 {
1570 irqreturn_t retval = IRQ_NONE;
1571 unsigned long status;
1572 unsigned long epnum;
1573 u8 devctl;
1574
1575 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1576 return IRQ_NONE;
1577
1578 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1579
1580 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1581 is_host_active(musb) ? "host" : "peripheral",
1582 musb->int_usb, musb->int_tx, musb->int_rx);
1583
1584 /**
1585 * According to Mentor Graphics' documentation, flowchart on page 98,
1586 * IRQ should be handled as follows:
1587 *
1588 * . Resume IRQ
1589 * . Session Request IRQ
1590 * . VBUS Error IRQ
1591 * . Suspend IRQ
1592 * . Connect IRQ
1593 * . Disconnect IRQ
1594 * . Reset/Babble IRQ
1595 * . SOF IRQ (we're not using this one)
1596 * . Endpoint 0 IRQ
1597 * . TX Endpoints
1598 * . RX Endpoints
1599 *
1600 * We will be following that flowchart in order to avoid any problems
1601 * that might arise with internal Finite State Machine.
1602 */
1603
1604 if (musb->int_usb)
1605 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1606
1607 if (musb->int_tx & 1) {
1608 if (is_host_active(musb))
1609 retval |= musb_h_ep0_irq(musb);
1610 else
1611 retval |= musb_g_ep0_irq(musb);
1612
1613 /* we have just handled endpoint 0 IRQ, clear it */
1614 musb->int_tx &= ~BIT(0);
1615 }
1616
1617 status = musb->int_tx;
1618
1619 for_each_set_bit(epnum, &status, 16) {
1620 retval = IRQ_HANDLED;
1621 if (is_host_active(musb))
1622 musb_host_tx(musb, epnum);
1623 else
1624 musb_g_tx(musb, epnum);
1625 }
1626
1627 status = musb->int_rx;
1628
1629 for_each_set_bit(epnum, &status, 16) {
1630 retval = IRQ_HANDLED;
1631 if (is_host_active(musb))
1632 musb_host_rx(musb, epnum);
1633 else
1634 musb_g_rx(musb, epnum);
1635 }
1636
1637 return retval;
1638 }
1639 EXPORT_SYMBOL_GPL(musb_interrupt);
1640
1641 #ifndef CONFIG_MUSB_PIO_ONLY
1642 static bool use_dma = 1;
1643
1644 /* "modprobe ... use_dma=0" etc */
1645 module_param(use_dma, bool, 0644);
1646 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1647
1648 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1649 {
1650 /* called with controller lock already held */
1651
1652 if (!epnum) {
1653 if (!is_cppi_enabled(musb)) {
1654 /* endpoint 0 */
1655 if (is_host_active(musb))
1656 musb_h_ep0_irq(musb);
1657 else
1658 musb_g_ep0_irq(musb);
1659 }
1660 } else {
1661 /* endpoints 1..15 */
1662 if (transmit) {
1663 if (is_host_active(musb))
1664 musb_host_tx(musb, epnum);
1665 else
1666 musb_g_tx(musb, epnum);
1667 } else {
1668 /* receive */
1669 if (is_host_active(musb))
1670 musb_host_rx(musb, epnum);
1671 else
1672 musb_g_rx(musb, epnum);
1673 }
1674 }
1675 }
1676 EXPORT_SYMBOL_GPL(musb_dma_completion);
1677
1678 #else
1679 #define use_dma 0
1680 #endif
1681
1682 static int (*musb_phy_callback)(enum musb_vbus_id_status status);
1683
1684 /*
1685 * musb_mailbox - optional phy notifier function
1686 * @status phy state change
1687 *
1688 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1689 * disabled at the point the phy_callback is registered or unregistered.
1690 */
1691 int musb_mailbox(enum musb_vbus_id_status status)
1692 {
1693 if (musb_phy_callback)
1694 return musb_phy_callback(status);
1695
1696 return -ENODEV;
1697 };
1698 EXPORT_SYMBOL_GPL(musb_mailbox);
1699
1700 /*-------------------------------------------------------------------------*/
1701
1702 static ssize_t
1703 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1704 {
1705 struct musb *musb = dev_to_musb(dev);
1706 unsigned long flags;
1707 int ret = -EINVAL;
1708
1709 spin_lock_irqsave(&musb->lock, flags);
1710 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1711 spin_unlock_irqrestore(&musb->lock, flags);
1712
1713 return ret;
1714 }
1715
1716 static ssize_t
1717 musb_mode_store(struct device *dev, struct device_attribute *attr,
1718 const char *buf, size_t n)
1719 {
1720 struct musb *musb = dev_to_musb(dev);
1721 unsigned long flags;
1722 int status;
1723
1724 spin_lock_irqsave(&musb->lock, flags);
1725 if (sysfs_streq(buf, "host"))
1726 status = musb_platform_set_mode(musb, MUSB_HOST);
1727 else if (sysfs_streq(buf, "peripheral"))
1728 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1729 else if (sysfs_streq(buf, "otg"))
1730 status = musb_platform_set_mode(musb, MUSB_OTG);
1731 else
1732 status = -EINVAL;
1733 spin_unlock_irqrestore(&musb->lock, flags);
1734
1735 return (status == 0) ? n : status;
1736 }
1737 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1738
1739 static ssize_t
1740 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1741 const char *buf, size_t n)
1742 {
1743 struct musb *musb = dev_to_musb(dev);
1744 unsigned long flags;
1745 unsigned long val;
1746
1747 if (sscanf(buf, "%lu", &val) < 1) {
1748 dev_err(dev, "Invalid VBUS timeout ms value\n");
1749 return -EINVAL;
1750 }
1751
1752 spin_lock_irqsave(&musb->lock, flags);
1753 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1754 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1755 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1756 musb->is_active = 0;
1757 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1758 spin_unlock_irqrestore(&musb->lock, flags);
1759
1760 return n;
1761 }
1762
1763 static ssize_t
1764 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1765 {
1766 struct musb *musb = dev_to_musb(dev);
1767 unsigned long flags;
1768 unsigned long val;
1769 int vbus;
1770 u8 devctl;
1771
1772 spin_lock_irqsave(&musb->lock, flags);
1773 val = musb->a_wait_bcon;
1774 vbus = musb_platform_get_vbus_status(musb);
1775 if (vbus < 0) {
1776 /* Use default MUSB method by means of DEVCTL register */
1777 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1778 if ((devctl & MUSB_DEVCTL_VBUS)
1779 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1780 vbus = 1;
1781 else
1782 vbus = 0;
1783 }
1784 spin_unlock_irqrestore(&musb->lock, flags);
1785
1786 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1787 vbus ? "on" : "off", val);
1788 }
1789 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1790
1791 /* Gadget drivers can't know that a host is connected so they might want
1792 * to start SRP, but users can. This allows userspace to trigger SRP.
1793 */
1794 static ssize_t
1795 musb_srp_store(struct device *dev, struct device_attribute *attr,
1796 const char *buf, size_t n)
1797 {
1798 struct musb *musb = dev_to_musb(dev);
1799 unsigned short srp;
1800
1801 if (sscanf(buf, "%hu", &srp) != 1
1802 || (srp != 1)) {
1803 dev_err(dev, "SRP: Value must be 1\n");
1804 return -EINVAL;
1805 }
1806
1807 if (srp == 1)
1808 musb_g_wakeup(musb);
1809
1810 return n;
1811 }
1812 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1813
1814 static struct attribute *musb_attributes[] = {
1815 &dev_attr_mode.attr,
1816 &dev_attr_vbus.attr,
1817 &dev_attr_srp.attr,
1818 NULL
1819 };
1820
1821 static const struct attribute_group musb_attr_group = {
1822 .attrs = musb_attributes,
1823 };
1824
1825 /* Only used to provide driver mode change events */
1826 static void musb_irq_work(struct work_struct *data)
1827 {
1828 struct musb *musb = container_of(data, struct musb, irq_work);
1829
1830 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1831 musb->xceiv_old_state = musb->xceiv->otg->state;
1832 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1833 }
1834 }
1835
1836 static void musb_recover_from_babble(struct musb *musb)
1837 {
1838 int ret;
1839 u8 devctl;
1840
1841 musb_disable_interrupts(musb);
1842
1843 /*
1844 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1845 * it some slack and wait for 10us.
1846 */
1847 udelay(10);
1848
1849 ret = musb_platform_recover(musb);
1850 if (ret) {
1851 musb_enable_interrupts(musb);
1852 return;
1853 }
1854
1855 /* drop session bit */
1856 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1857 devctl &= ~MUSB_DEVCTL_SESSION;
1858 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1859
1860 /* tell usbcore about it */
1861 musb_root_disconnect(musb);
1862
1863 /*
1864 * When a babble condition occurs, the musb controller
1865 * removes the session bit and the endpoint config is lost.
1866 */
1867 if (musb->dyn_fifo)
1868 ret = ep_config_from_table(musb);
1869 else
1870 ret = ep_config_from_hw(musb);
1871
1872 /* restart session */
1873 if (ret == 0)
1874 musb_start(musb);
1875 }
1876
1877 /* --------------------------------------------------------------------------
1878 * Init support
1879 */
1880
1881 static struct musb *allocate_instance(struct device *dev,
1882 const struct musb_hdrc_config *config, void __iomem *mbase)
1883 {
1884 struct musb *musb;
1885 struct musb_hw_ep *ep;
1886 int epnum;
1887 int ret;
1888
1889 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1890 if (!musb)
1891 return NULL;
1892
1893 INIT_LIST_HEAD(&musb->control);
1894 INIT_LIST_HEAD(&musb->in_bulk);
1895 INIT_LIST_HEAD(&musb->out_bulk);
1896
1897 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1898 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1899 musb->mregs = mbase;
1900 musb->ctrl_base = mbase;
1901 musb->nIrq = -ENODEV;
1902 musb->config = config;
1903 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1904 for (epnum = 0, ep = musb->endpoints;
1905 epnum < musb->config->num_eps;
1906 epnum++, ep++) {
1907 ep->musb = musb;
1908 ep->epnum = epnum;
1909 }
1910
1911 musb->controller = dev;
1912
1913 ret = musb_host_alloc(musb);
1914 if (ret < 0)
1915 goto err_free;
1916
1917 dev_set_drvdata(dev, musb);
1918
1919 return musb;
1920
1921 err_free:
1922 return NULL;
1923 }
1924
1925 static void musb_free(struct musb *musb)
1926 {
1927 /* this has multiple entry modes. it handles fault cleanup after
1928 * probe(), where things may be partially set up, as well as rmmod
1929 * cleanup after everything's been de-activated.
1930 */
1931
1932 #ifdef CONFIG_SYSFS
1933 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1934 #endif
1935
1936 if (musb->nIrq >= 0) {
1937 if (musb->irq_wake)
1938 disable_irq_wake(musb->nIrq);
1939 free_irq(musb->nIrq, musb);
1940 }
1941
1942 musb_host_free(musb);
1943 }
1944
1945 static void musb_deassert_reset(struct work_struct *work)
1946 {
1947 struct musb *musb;
1948 unsigned long flags;
1949
1950 musb = container_of(work, struct musb, deassert_reset_work.work);
1951
1952 spin_lock_irqsave(&musb->lock, flags);
1953
1954 if (musb->port1_status & USB_PORT_STAT_RESET)
1955 musb_port_reset(musb, false);
1956
1957 spin_unlock_irqrestore(&musb->lock, flags);
1958 }
1959
1960 /*
1961 * Perform generic per-controller initialization.
1962 *
1963 * @dev: the controller (already clocked, etc)
1964 * @nIrq: IRQ number
1965 * @ctrl: virtual address of controller registers,
1966 * not yet corrected for platform-specific offsets
1967 */
1968 static int
1969 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1970 {
1971 int status;
1972 struct musb *musb;
1973 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1974
1975 /* The driver might handle more features than the board; OK.
1976 * Fail when the board needs a feature that's not enabled.
1977 */
1978 if (!plat) {
1979 dev_dbg(dev, "no platform_data?\n");
1980 status = -ENODEV;
1981 goto fail0;
1982 }
1983
1984 /* allocate */
1985 musb = allocate_instance(dev, plat->config, ctrl);
1986 if (!musb) {
1987 status = -ENOMEM;
1988 goto fail0;
1989 }
1990
1991 spin_lock_init(&musb->lock);
1992 musb->board_set_power = plat->set_power;
1993 musb->min_power = plat->min_power;
1994 musb->ops = plat->platform_ops;
1995 musb->port_mode = plat->mode;
1996
1997 /*
1998 * Initialize the default IO functions. At least omap2430 needs
1999 * these early. We initialize the platform specific IO functions
2000 * later on.
2001 */
2002 musb_readb = musb_default_readb;
2003 musb_writeb = musb_default_writeb;
2004 musb_readw = musb_default_readw;
2005 musb_writew = musb_default_writew;
2006 musb_readl = musb_default_readl;
2007 musb_writel = musb_default_writel;
2008
2009 /* The musb_platform_init() call:
2010 * - adjusts musb->mregs
2011 * - sets the musb->isr
2012 * - may initialize an integrated transceiver
2013 * - initializes musb->xceiv, usually by otg_get_phy()
2014 * - stops powering VBUS
2015 *
2016 * There are various transceiver configurations. Blackfin,
2017 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2018 * external/discrete ones in various flavors (twl4030 family,
2019 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2020 */
2021 status = musb_platform_init(musb);
2022 if (status < 0)
2023 goto fail1;
2024
2025 if (!musb->isr) {
2026 status = -ENODEV;
2027 goto fail2;
2028 }
2029
2030 if (musb->ops->quirks)
2031 musb->io.quirks = musb->ops->quirks;
2032
2033 /* Most devices use indexed offset or flat offset */
2034 if (musb->io.quirks & MUSB_INDEXED_EP) {
2035 musb->io.ep_offset = musb_indexed_ep_offset;
2036 musb->io.ep_select = musb_indexed_ep_select;
2037 } else {
2038 musb->io.ep_offset = musb_flat_ep_offset;
2039 musb->io.ep_select = musb_flat_ep_select;
2040 }
2041 /* And override them with platform specific ops if specified. */
2042 if (musb->ops->ep_offset)
2043 musb->io.ep_offset = musb->ops->ep_offset;
2044 if (musb->ops->ep_select)
2045 musb->io.ep_select = musb->ops->ep_select;
2046
2047 /* At least tusb6010 has its own offsets */
2048 if (musb->ops->ep_offset)
2049 musb->io.ep_offset = musb->ops->ep_offset;
2050 if (musb->ops->ep_select)
2051 musb->io.ep_select = musb->ops->ep_select;
2052
2053 if (musb->ops->fifo_mode)
2054 fifo_mode = musb->ops->fifo_mode;
2055 else
2056 fifo_mode = 4;
2057
2058 if (musb->ops->fifo_offset)
2059 musb->io.fifo_offset = musb->ops->fifo_offset;
2060 else
2061 musb->io.fifo_offset = musb_default_fifo_offset;
2062
2063 if (musb->ops->busctl_offset)
2064 musb->io.busctl_offset = musb->ops->busctl_offset;
2065 else
2066 musb->io.busctl_offset = musb_default_busctl_offset;
2067
2068 if (musb->ops->readb)
2069 musb_readb = musb->ops->readb;
2070 if (musb->ops->writeb)
2071 musb_writeb = musb->ops->writeb;
2072 if (musb->ops->readw)
2073 musb_readw = musb->ops->readw;
2074 if (musb->ops->writew)
2075 musb_writew = musb->ops->writew;
2076 if (musb->ops->readl)
2077 musb_readl = musb->ops->readl;
2078 if (musb->ops->writel)
2079 musb_writel = musb->ops->writel;
2080
2081 #ifndef CONFIG_MUSB_PIO_ONLY
2082 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2083 dev_err(dev, "DMA controller not set\n");
2084 status = -ENODEV;
2085 goto fail2;
2086 }
2087 musb_dma_controller_create = musb->ops->dma_init;
2088 musb_dma_controller_destroy = musb->ops->dma_exit;
2089 #endif
2090
2091 if (musb->ops->read_fifo)
2092 musb->io.read_fifo = musb->ops->read_fifo;
2093 else
2094 musb->io.read_fifo = musb_default_read_fifo;
2095
2096 if (musb->ops->write_fifo)
2097 musb->io.write_fifo = musb->ops->write_fifo;
2098 else
2099 musb->io.write_fifo = musb_default_write_fifo;
2100
2101 if (!musb->xceiv->io_ops) {
2102 musb->xceiv->io_dev = musb->controller;
2103 musb->xceiv->io_priv = musb->mregs;
2104 musb->xceiv->io_ops = &musb_ulpi_access;
2105 }
2106
2107 if (musb->ops->phy_callback)
2108 musb_phy_callback = musb->ops->phy_callback;
2109
2110 /*
2111 * We need musb_read/write functions initialized for PM.
2112 * Note that at least 2430 glue needs autosuspend delay
2113 * somewhere above 300 ms for the hardware to idle properly
2114 * after disconnecting the cable in host mode. Let's use
2115 * 500 ms for some margin.
2116 */
2117 pm_runtime_use_autosuspend(musb->controller);
2118 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2119 pm_runtime_enable(musb->controller);
2120 pm_runtime_get_sync(musb->controller);
2121
2122 status = usb_phy_init(musb->xceiv);
2123 if (status < 0)
2124 goto err_usb_phy_init;
2125
2126 if (use_dma && dev->dma_mask) {
2127 musb->dma_controller =
2128 musb_dma_controller_create(musb, musb->mregs);
2129 if (IS_ERR(musb->dma_controller)) {
2130 status = PTR_ERR(musb->dma_controller);
2131 goto fail2_5;
2132 }
2133 }
2134
2135 /* be sure interrupts are disabled before connecting ISR */
2136 musb_platform_disable(musb);
2137 musb_generic_disable(musb);
2138
2139 /* Init IRQ workqueue before request_irq */
2140 INIT_WORK(&musb->irq_work, musb_irq_work);
2141 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2142 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2143
2144 /* setup musb parts of the core (especially endpoints) */
2145 status = musb_core_init(plat->config->multipoint
2146 ? MUSB_CONTROLLER_MHDRC
2147 : MUSB_CONTROLLER_HDRC, musb);
2148 if (status < 0)
2149 goto fail3;
2150
2151 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2152
2153 /* attach to the IRQ */
2154 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2155 dev_err(dev, "request_irq %d failed!\n", nIrq);
2156 status = -ENODEV;
2157 goto fail3;
2158 }
2159 musb->nIrq = nIrq;
2160 /* FIXME this handles wakeup irqs wrong */
2161 if (enable_irq_wake(nIrq) == 0) {
2162 musb->irq_wake = 1;
2163 device_init_wakeup(dev, 1);
2164 } else {
2165 musb->irq_wake = 0;
2166 }
2167
2168 /* program PHY to use external vBus if required */
2169 if (plat->extvbus) {
2170 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2171 busctl |= MUSB_ULPI_USE_EXTVBUS;
2172 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2173 }
2174
2175 if (musb->xceiv->otg->default_a) {
2176 MUSB_HST_MODE(musb);
2177 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2178 } else {
2179 MUSB_DEV_MODE(musb);
2180 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2181 }
2182
2183 switch (musb->port_mode) {
2184 case MUSB_PORT_MODE_HOST:
2185 status = musb_host_setup(musb, plat->power);
2186 if (status < 0)
2187 goto fail3;
2188 status = musb_platform_set_mode(musb, MUSB_HOST);
2189 break;
2190 case MUSB_PORT_MODE_GADGET:
2191 status = musb_gadget_setup(musb);
2192 if (status < 0)
2193 goto fail3;
2194 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2195 break;
2196 case MUSB_PORT_MODE_DUAL_ROLE:
2197 status = musb_host_setup(musb, plat->power);
2198 if (status < 0)
2199 goto fail3;
2200 status = musb_gadget_setup(musb);
2201 if (status) {
2202 musb_host_cleanup(musb);
2203 goto fail3;
2204 }
2205 status = musb_platform_set_mode(musb, MUSB_OTG);
2206 break;
2207 default:
2208 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2209 break;
2210 }
2211
2212 if (status < 0)
2213 goto fail3;
2214
2215 status = musb_init_debugfs(musb);
2216 if (status < 0)
2217 goto fail4;
2218
2219 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2220 if (status)
2221 goto fail5;
2222
2223 pm_runtime_mark_last_busy(musb->controller);
2224 pm_runtime_put_autosuspend(musb->controller);
2225
2226 return 0;
2227
2228 fail5:
2229 musb_exit_debugfs(musb);
2230
2231 fail4:
2232 musb_gadget_cleanup(musb);
2233 musb_host_cleanup(musb);
2234
2235 fail3:
2236 cancel_work_sync(&musb->irq_work);
2237 cancel_delayed_work_sync(&musb->finish_resume_work);
2238 cancel_delayed_work_sync(&musb->deassert_reset_work);
2239 if (musb->dma_controller)
2240 musb_dma_controller_destroy(musb->dma_controller);
2241
2242 fail2_5:
2243 usb_phy_shutdown(musb->xceiv);
2244
2245 err_usb_phy_init:
2246 pm_runtime_dont_use_autosuspend(musb->controller);
2247 pm_runtime_put_sync(musb->controller);
2248 pm_runtime_disable(musb->controller);
2249
2250 fail2:
2251 if (musb->irq_wake)
2252 device_init_wakeup(dev, 0);
2253 musb_platform_exit(musb);
2254
2255 fail1:
2256 dev_err(musb->controller,
2257 "musb_init_controller failed with status %d\n", status);
2258
2259 musb_free(musb);
2260
2261 fail0:
2262
2263 return status;
2264
2265 }
2266
2267 /*-------------------------------------------------------------------------*/
2268
2269 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2270 * bridge to a platform device; this driver then suffices.
2271 */
2272 static int musb_probe(struct platform_device *pdev)
2273 {
2274 struct device *dev = &pdev->dev;
2275 int irq = platform_get_irq_byname(pdev, "mc");
2276 struct resource *iomem;
2277 void __iomem *base;
2278
2279 if (irq <= 0)
2280 return -ENODEV;
2281
2282 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2283 base = devm_ioremap_resource(dev, iomem);
2284 if (IS_ERR(base))
2285 return PTR_ERR(base);
2286
2287 return musb_init_controller(dev, irq, base);
2288 }
2289
2290 static int musb_remove(struct platform_device *pdev)
2291 {
2292 struct device *dev = &pdev->dev;
2293 struct musb *musb = dev_to_musb(dev);
2294 unsigned long flags;
2295
2296 /* this gets called on rmmod.
2297 * - Host mode: host may still be active
2298 * - Peripheral mode: peripheral is deactivated (or never-activated)
2299 * - OTG mode: both roles are deactivated (or never-activated)
2300 */
2301 musb_exit_debugfs(musb);
2302
2303 cancel_work_sync(&musb->irq_work);
2304 cancel_delayed_work_sync(&musb->finish_resume_work);
2305 cancel_delayed_work_sync(&musb->deassert_reset_work);
2306 pm_runtime_get_sync(musb->controller);
2307 musb_host_cleanup(musb);
2308 musb_gadget_cleanup(musb);
2309 spin_lock_irqsave(&musb->lock, flags);
2310 musb_platform_disable(musb);
2311 musb_generic_disable(musb);
2312 spin_unlock_irqrestore(&musb->lock, flags);
2313 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2314 pm_runtime_dont_use_autosuspend(musb->controller);
2315 pm_runtime_put_sync(musb->controller);
2316 pm_runtime_disable(musb->controller);
2317 musb_platform_exit(musb);
2318 musb_phy_callback = NULL;
2319 if (musb->dma_controller)
2320 musb_dma_controller_destroy(musb->dma_controller);
2321 usb_phy_shutdown(musb->xceiv);
2322 musb_free(musb);
2323 device_init_wakeup(dev, 0);
2324 return 0;
2325 }
2326
2327 #ifdef CONFIG_PM
2328
2329 static void musb_save_context(struct musb *musb)
2330 {
2331 int i;
2332 void __iomem *musb_base = musb->mregs;
2333 void __iomem *epio;
2334
2335 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2336 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2337 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2338 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2339 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2340 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2341 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2342
2343 for (i = 0; i < musb->config->num_eps; ++i) {
2344 struct musb_hw_ep *hw_ep;
2345
2346 hw_ep = &musb->endpoints[i];
2347 if (!hw_ep)
2348 continue;
2349
2350 epio = hw_ep->regs;
2351 if (!epio)
2352 continue;
2353
2354 musb_writeb(musb_base, MUSB_INDEX, i);
2355 musb->context.index_regs[i].txmaxp =
2356 musb_readw(epio, MUSB_TXMAXP);
2357 musb->context.index_regs[i].txcsr =
2358 musb_readw(epio, MUSB_TXCSR);
2359 musb->context.index_regs[i].rxmaxp =
2360 musb_readw(epio, MUSB_RXMAXP);
2361 musb->context.index_regs[i].rxcsr =
2362 musb_readw(epio, MUSB_RXCSR);
2363
2364 if (musb->dyn_fifo) {
2365 musb->context.index_regs[i].txfifoadd =
2366 musb_read_txfifoadd(musb_base);
2367 musb->context.index_regs[i].rxfifoadd =
2368 musb_read_rxfifoadd(musb_base);
2369 musb->context.index_regs[i].txfifosz =
2370 musb_read_txfifosz(musb_base);
2371 musb->context.index_regs[i].rxfifosz =
2372 musb_read_rxfifosz(musb_base);
2373 }
2374
2375 musb->context.index_regs[i].txtype =
2376 musb_readb(epio, MUSB_TXTYPE);
2377 musb->context.index_regs[i].txinterval =
2378 musb_readb(epio, MUSB_TXINTERVAL);
2379 musb->context.index_regs[i].rxtype =
2380 musb_readb(epio, MUSB_RXTYPE);
2381 musb->context.index_regs[i].rxinterval =
2382 musb_readb(epio, MUSB_RXINTERVAL);
2383
2384 musb->context.index_regs[i].txfunaddr =
2385 musb_read_txfunaddr(musb, i);
2386 musb->context.index_regs[i].txhubaddr =
2387 musb_read_txhubaddr(musb, i);
2388 musb->context.index_regs[i].txhubport =
2389 musb_read_txhubport(musb, i);
2390
2391 musb->context.index_regs[i].rxfunaddr =
2392 musb_read_rxfunaddr(musb, i);
2393 musb->context.index_regs[i].rxhubaddr =
2394 musb_read_rxhubaddr(musb, i);
2395 musb->context.index_regs[i].rxhubport =
2396 musb_read_rxhubport(musb, i);
2397 }
2398 }
2399
2400 static void musb_restore_context(struct musb *musb)
2401 {
2402 int i;
2403 void __iomem *musb_base = musb->mregs;
2404 void __iomem *epio;
2405 u8 power;
2406
2407 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2408 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2409 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2410
2411 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2412 power = musb_readb(musb_base, MUSB_POWER);
2413 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2414 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2415 power |= musb->context.power;
2416 musb_writeb(musb_base, MUSB_POWER, power);
2417
2418 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2419 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2420 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2421 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2422 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2423
2424 for (i = 0; i < musb->config->num_eps; ++i) {
2425 struct musb_hw_ep *hw_ep;
2426
2427 hw_ep = &musb->endpoints[i];
2428 if (!hw_ep)
2429 continue;
2430
2431 epio = hw_ep->regs;
2432 if (!epio)
2433 continue;
2434
2435 musb_writeb(musb_base, MUSB_INDEX, i);
2436 musb_writew(epio, MUSB_TXMAXP,
2437 musb->context.index_regs[i].txmaxp);
2438 musb_writew(epio, MUSB_TXCSR,
2439 musb->context.index_regs[i].txcsr);
2440 musb_writew(epio, MUSB_RXMAXP,
2441 musb->context.index_regs[i].rxmaxp);
2442 musb_writew(epio, MUSB_RXCSR,
2443 musb->context.index_regs[i].rxcsr);
2444
2445 if (musb->dyn_fifo) {
2446 musb_write_txfifosz(musb_base,
2447 musb->context.index_regs[i].txfifosz);
2448 musb_write_rxfifosz(musb_base,
2449 musb->context.index_regs[i].rxfifosz);
2450 musb_write_txfifoadd(musb_base,
2451 musb->context.index_regs[i].txfifoadd);
2452 musb_write_rxfifoadd(musb_base,
2453 musb->context.index_regs[i].rxfifoadd);
2454 }
2455
2456 musb_writeb(epio, MUSB_TXTYPE,
2457 musb->context.index_regs[i].txtype);
2458 musb_writeb(epio, MUSB_TXINTERVAL,
2459 musb->context.index_regs[i].txinterval);
2460 musb_writeb(epio, MUSB_RXTYPE,
2461 musb->context.index_regs[i].rxtype);
2462 musb_writeb(epio, MUSB_RXINTERVAL,
2463
2464 musb->context.index_regs[i].rxinterval);
2465 musb_write_txfunaddr(musb, i,
2466 musb->context.index_regs[i].txfunaddr);
2467 musb_write_txhubaddr(musb, i,
2468 musb->context.index_regs[i].txhubaddr);
2469 musb_write_txhubport(musb, i,
2470 musb->context.index_regs[i].txhubport);
2471
2472 musb_write_rxfunaddr(musb, i,
2473 musb->context.index_regs[i].rxfunaddr);
2474 musb_write_rxhubaddr(musb, i,
2475 musb->context.index_regs[i].rxhubaddr);
2476 musb_write_rxhubport(musb, i,
2477 musb->context.index_regs[i].rxhubport);
2478 }
2479 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2480 }
2481
2482 static int musb_suspend(struct device *dev)
2483 {
2484 struct musb *musb = dev_to_musb(dev);
2485 unsigned long flags;
2486
2487 musb_platform_disable(musb);
2488 musb_generic_disable(musb);
2489
2490 spin_lock_irqsave(&musb->lock, flags);
2491
2492 if (is_peripheral_active(musb)) {
2493 /* FIXME force disconnect unless we know USB will wake
2494 * the system up quickly enough to respond ...
2495 */
2496 } else if (is_host_active(musb)) {
2497 /* we know all the children are suspended; sometimes
2498 * they will even be wakeup-enabled.
2499 */
2500 }
2501
2502 musb_save_context(musb);
2503
2504 spin_unlock_irqrestore(&musb->lock, flags);
2505 return 0;
2506 }
2507
2508 static int musb_resume(struct device *dev)
2509 {
2510 struct musb *musb = dev_to_musb(dev);
2511 u8 devctl;
2512 u8 mask;
2513
2514 /*
2515 * For static cmos like DaVinci, register values were preserved
2516 * unless for some reason the whole soc powered down or the USB
2517 * module got reset through the PSC (vs just being disabled).
2518 *
2519 * For the DSPS glue layer though, a full register restore has to
2520 * be done. As it shouldn't harm other platforms, we do it
2521 * unconditionally.
2522 */
2523
2524 musb_restore_context(musb);
2525
2526 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2527 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2528 if ((devctl & mask) != (musb->context.devctl & mask))
2529 musb->port1_status = 0;
2530 if (musb->need_finish_resume) {
2531 musb->need_finish_resume = 0;
2532 schedule_delayed_work(&musb->finish_resume_work,
2533 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2534 }
2535
2536 /*
2537 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2538 * out of suspend
2539 */
2540 pm_runtime_disable(dev);
2541 pm_runtime_set_active(dev);
2542 pm_runtime_enable(dev);
2543
2544 musb_start(musb);
2545
2546 return 0;
2547 }
2548
2549 static int musb_runtime_suspend(struct device *dev)
2550 {
2551 struct musb *musb = dev_to_musb(dev);
2552
2553 musb_save_context(musb);
2554
2555 return 0;
2556 }
2557
2558 static int musb_runtime_resume(struct device *dev)
2559 {
2560 struct musb *musb = dev_to_musb(dev);
2561 static int first = 1;
2562
2563 /*
2564 * When pm_runtime_get_sync called for the first time in driver
2565 * init, some of the structure is still not initialized which is
2566 * used in restore function. But clock needs to be
2567 * enabled before any register access, so
2568 * pm_runtime_get_sync has to be called.
2569 * Also context restore without save does not make
2570 * any sense
2571 */
2572 if (!first)
2573 musb_restore_context(musb);
2574 first = 0;
2575
2576 if (musb->need_finish_resume) {
2577 musb->need_finish_resume = 0;
2578 schedule_delayed_work(&musb->finish_resume_work,
2579 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2580 }
2581
2582 return 0;
2583 }
2584
2585 static const struct dev_pm_ops musb_dev_pm_ops = {
2586 .suspend = musb_suspend,
2587 .resume = musb_resume,
2588 .runtime_suspend = musb_runtime_suspend,
2589 .runtime_resume = musb_runtime_resume,
2590 };
2591
2592 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2593 #else
2594 #define MUSB_DEV_PM_OPS NULL
2595 #endif
2596
2597 static struct platform_driver musb_driver = {
2598 .driver = {
2599 .name = (char *)musb_driver_name,
2600 .bus = &platform_bus_type,
2601 .pm = MUSB_DEV_PM_OPS,
2602 },
2603 .probe = musb_probe,
2604 .remove = musb_remove,
2605 };
2606
2607 module_platform_driver(musb_driver);
Linux kernel - Deliverables
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