1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 /* Default to compress debug sections for Linux. */
38 enum compressed_debug_section_type flag_compress_debug
39 = COMPRESS_DEBUG_ZLIB
;
42 #ifndef REGISTER_WARNINGS
43 #define REGISTER_WARNINGS 1
46 #ifndef INFER_ADDR_PREFIX
47 #define INFER_ADDR_PREFIX 1
51 #define DEFAULT_ARCH "i386"
56 #define INLINE __inline__
62 /* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
72 #define HLE_PREFIX REP_PREFIX
73 #define BND_PREFIX REP_PREFIX
75 #define REX_PREFIX 6 /* must come last. */
76 #define MAX_PREFIXES 7 /* max prefixes per opcode */
78 /* we define the syntax here (modulo base,index,scale syntax) */
79 #define REGISTER_PREFIX '%'
80 #define IMMEDIATE_PREFIX '$'
81 #define ABSOLUTE_PREFIX '*'
83 /* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85 #define WORD_MNEM_SUFFIX 'w'
86 #define BYTE_MNEM_SUFFIX 'b'
87 #define SHORT_MNEM_SUFFIX 's'
88 #define LONG_MNEM_SUFFIX 'l'
89 #define QWORD_MNEM_SUFFIX 'q'
90 #define XMMWORD_MNEM_SUFFIX 'x'
91 #define YMMWORD_MNEM_SUFFIX 'y'
92 #define ZMMWORD_MNEM_SUFFIX 'z'
93 /* Intel Syntax. Use a non-ascii letter since since it never appears
95 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
97 #define END_OF_INSN '\0'
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
108 const insn_template
*start
;
109 const insn_template
*end
;
113 /* 386 operand encoding bytes: see 386 book for details of this. */
116 unsigned int regmem
; /* codes register or memory operand */
117 unsigned int reg
; /* codes register operand (or extended opcode) */
118 unsigned int mode
; /* how to interpret regmem & reg */
122 /* x86-64 extension prefix. */
123 typedef int rex_byte
;
125 /* 386 opcode byte to code indirect addressing. */
134 /* x86 arch names, types and features */
137 const char *name
; /* arch name */
138 unsigned int len
; /* arch string length */
139 enum processor_type type
; /* arch type */
140 i386_cpu_flags flags
; /* cpu feature flags */
141 unsigned int skip
; /* show_arch should skip this. */
142 unsigned int negated
; /* turn off indicated flags. */
146 static void update_code_flag (int, int);
147 static void set_code_flag (int);
148 static void set_16bit_gcc_code_flag (int);
149 static void set_intel_syntax (int);
150 static void set_intel_mnemonic (int);
151 static void set_allow_index_reg (int);
152 static void set_check (int);
153 static void set_cpu_arch (int);
155 static void pe_directive_secrel (int);
157 static void signed_cons (int);
158 static char *output_invalid (int c
);
159 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
161 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
163 static int i386_att_operand (char *);
164 static int i386_intel_operand (char *, int);
165 static int i386_intel_simplify (expressionS
*);
166 static int i386_intel_parse_name (const char *, expressionS
*);
167 static const reg_entry
*parse_register (char *, char **);
168 static char *parse_insn (char *, char *);
169 static char *parse_operands (char *, const char *);
170 static void swap_operands (void);
171 static void swap_2_operands (int, int);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (void);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const seg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
194 static const char *default_arch
= DEFAULT_ARCH
;
196 /* This struct describes rounding control and SAE in the instruction. */
210 static struct RC_Operation rc_op
;
212 /* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215 struct Mask_Operation
217 const reg_entry
*mask
;
218 unsigned int zeroing
;
219 /* The operand where this operation is associated. */
223 static struct Mask_Operation mask_op
;
225 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
227 struct Broadcast_Operation
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 /* Index of broadcasted operand. */
236 static struct Broadcast_Operation broadcast_op
;
241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes
[4];
244 /* Destination or source register specifier. */
245 const reg_entry
*register_specifier
;
248 /* 'md_assemble ()' gathers together information and puts it into a
255 const reg_entry
*regs
;
260 operand_size_mismatch
,
261 operand_type_mismatch
,
262 register_type_mismatch
,
263 number_of_operands_mismatch
,
264 invalid_instruction_suffix
,
267 unsupported_with_intel_mnemonic
,
270 invalid_vsib_address
,
271 invalid_vector_register_set
,
272 unsupported_vector_index_register
,
273 unsupported_broadcast
,
274 broadcast_not_on_src_operand
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
287 /* TM holds the template for the insn were currently assembling. */
290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
294 /* OPERANDS gives the number of given operands. */
295 unsigned int operands
;
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
300 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
302 /* TYPES [i] is the type (see above #defines) which tells us how to
303 use OP[i] for the corresponding operand. */
304 i386_operand_type types
[MAX_OPERANDS
];
306 /* Displacement expression, immediate expression, or register for each
308 union i386_op op
[MAX_OPERANDS
];
310 /* Flags for operands. */
311 unsigned int flags
[MAX_OPERANDS
];
312 #define Operand_PCrel 1
314 /* Relocation type for operand */
315 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry
*base_reg
;
320 const reg_entry
*index_reg
;
321 unsigned int log2_scale_factor
;
323 /* SEG gives the seg_entries of this insn. They are zero unless
324 explicit segment overrides are given. */
325 const seg_entry
*seg
[2];
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Swap operand in encoding. */
353 unsigned int swap_operand
;
355 /* Prefer 8bit or 32bit displacement in encoding. */
358 disp_encoding_default
= 0,
364 const char *rep_prefix
;
367 const char *hle_prefix
;
369 /* Have BND prefix. */
370 const char *bnd_prefix
;
372 /* Need VREX to support upper 16 registers. */
376 enum i386_error error
;
379 typedef struct _i386_insn i386_insn
;
381 /* Link RC type with corresponding string, that'll be looked for in
390 static const struct RC_name RC_NamesTable
[] =
392 { rne
, STRING_COMMA_LEN ("rn-sae") },
393 { rd
, STRING_COMMA_LEN ("rd-sae") },
394 { ru
, STRING_COMMA_LEN ("ru-sae") },
395 { rz
, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly
, STRING_COMMA_LEN ("sae") },
399 /* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
401 const char extra_symbol_chars
[] = "*%-([{"
410 #if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
412 && !defined (TE_GNU) \
413 && !defined (TE_LINUX) \
414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
416 && !defined (TE_FreeBSD) \
417 && !defined (TE_DragonFly) \
418 && !defined (TE_NetBSD)))
419 /* This array holds the chars that always start a comment. If the
420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422 const char *i386_comment_chars
= "#/";
423 #define SVR4_COMMENT_CHARS 1
424 #define PREFIX_SEPARATOR '\\'
427 const char *i386_comment_chars
= "#";
428 #define PREFIX_SEPARATOR '/'
431 /* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
435 first line of the input file. This is because the compiler outputs
436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
438 '/' isn't otherwise defined. */
439 const char line_comment_chars
[] = "#/";
441 const char line_separator_chars
[] = ";";
443 /* Chars that can be used to separate mant from exp in floating point
445 const char EXP_CHARS
[] = "eE";
447 /* Chars that mean this number is a floating point constant
450 const char FLT_CHARS
[] = "fFdDxX";
452 /* Tables for lexical analysis. */
453 static char mnemonic_chars
[256];
454 static char register_chars
[256];
455 static char operand_chars
[256];
456 static char identifier_chars
[256];
457 static char digit_chars
[256];
459 /* Lexical macros. */
460 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461 #define is_operand_char(x) (operand_chars[(unsigned char) x])
462 #define is_register_char(x) (register_chars[(unsigned char) x])
463 #define is_space_char(x) ((x) == ' ')
464 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465 #define is_digit_char(x) (digit_chars[(unsigned char) x])
467 /* All non-digit non-letter characters that may occur in an operand. */
468 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
470 /* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
473 assembler instruction). */
474 static char save_stack
[32];
475 static char *save_stack_p
;
476 #define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478 #define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
481 /* The instruction we're assembling. */
484 /* Possible templates for current insn. */
485 static const templates
*current_templates
;
487 /* Per instruction expressionS buffers: max displacements & immediates. */
488 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
489 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
491 /* Current operand we are working on. */
492 static int this_operand
= -1;
494 /* We support four different modes. FLAG_CODE variable is used to distinguish
502 static enum flag_code flag_code
;
503 static unsigned int object_64bit
;
504 static unsigned int disallow_64bit_reloc
;
505 static int use_rela_relocations
= 0;
507 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
511 /* The ELF ABI to use. */
519 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
522 #if defined (TE_PE) || defined (TE_PEP)
523 /* Use big object file format. */
524 static int use_big_obj
= 0;
527 /* 1 for intel syntax,
529 static int intel_syntax
= 0;
531 /* 1 for intel mnemonic,
532 0 if att mnemonic. */
533 static int intel_mnemonic
= !SYSV386_COMPAT
;
535 /* 1 if support old (<= 2.8.1) versions of gcc. */
536 static int old_gcc
= OLDGCC_COMPAT
;
538 /* 1 if pseudo registers are permitted. */
539 static int allow_pseudo_reg
= 0;
541 /* 1 if register prefix % not required. */
542 static int allow_naked_reg
= 0;
544 /* 1 if the assembler should add BND prefix for all control-tranferring
545 instructions supporting it, even if this prefix wasn't specified
547 static int add_bnd_prefix
= 0;
549 /* 1 if pseudo index register, eiz/riz, is allowed . */
550 static int allow_index_reg
= 0;
552 /* 1 if the assembler should ignore LOCK prefix, even if it was
553 specified explicitly. */
554 static int omit_lock_prefix
= 0;
556 static enum check_kind
562 sse_check
, operand_check
= check_warning
;
564 /* Register prefix used for error message. */
565 static const char *register_prefix
= "%";
567 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
568 leave, push, and pop instructions so that gcc has the same stack
569 frame as in 32 bit mode. */
570 static char stackop_size
= '\0';
572 /* Non-zero to optimize code alignment. */
573 int optimize_align_code
= 1;
575 /* Non-zero to quieten some warnings. */
576 static int quiet_warnings
= 0;
579 static const char *cpu_arch_name
= NULL
;
580 static char *cpu_sub_arch_name
= NULL
;
582 /* CPU feature flags. */
583 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
585 /* If we have selected a cpu we are generating instructions for. */
586 static int cpu_arch_tune_set
= 0;
588 /* Cpu we are generating instructions for. */
589 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of cpu we are generating instructions for. */
592 static i386_cpu_flags cpu_arch_tune_flags
;
594 /* CPU instruction set architecture used. */
595 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
597 /* CPU feature flags of instruction set architecture used. */
598 i386_cpu_flags cpu_arch_isa_flags
;
600 /* If set, conditional jumps are not automatically promoted to handle
601 larger than a byte offset. */
602 static unsigned int no_cond_jump_promotion
= 0;
604 /* Encode SSE instructions with VEX prefix. */
605 static unsigned int sse2avx
;
607 /* Encode scalar AVX instructions with specific vector length. */
614 /* Encode scalar EVEX LIG instructions with specific vector length. */
622 /* Encode EVEX WIG instructions with specific evex.w. */
629 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
630 static enum rc_type evexrcig
= rne
;
632 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
633 static symbolS
*GOT_symbol
;
635 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
636 unsigned int x86_dwarf2_return_column
;
638 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
639 int x86_cie_data_alignment
;
641 /* Interface to relax_segment.
642 There are 3 major relax states for 386 jump insns because the
643 different types of jumps add different sizes to frags when we're
644 figuring out what sort of jump to choose to reach a given label. */
647 #define UNCOND_JUMP 0
649 #define COND_JUMP86 2
654 #define SMALL16 (SMALL | CODE16)
656 #define BIG16 (BIG | CODE16)
660 #define INLINE __inline__
666 #define ENCODE_RELAX_STATE(type, size) \
667 ((relax_substateT) (((type) << 2) | (size)))
668 #define TYPE_FROM_RELAX_STATE(s) \
670 #define DISP_SIZE_FROM_RELAX_STATE(s) \
671 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
673 /* This table is used by relax_frag to promote short jumps to long
674 ones where necessary. SMALL (short) jumps may be promoted to BIG
675 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
676 don't allow a short jump in a 32 bit code segment to be promoted to
677 a 16 bit offset jump because it's slower (requires data size
678 prefix), and doesn't work, unless the destination is in the bottom
679 64k of the code segment (The top 16 bits of eip are zeroed). */
681 const relax_typeS md_relax_table
[] =
684 1) most positive reach of this state,
685 2) most negative reach of this state,
686 3) how many bytes this mode will have in the variable part of the frag
687 4) which index into the table to try if we can't fit into this one. */
689 /* UNCOND_JUMP states. */
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
691 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
692 /* dword jmp adds 4 bytes to frag:
693 0 extra opcode bytes, 4 displacement bytes. */
695 /* word jmp adds 2 byte2 to frag:
696 0 extra opcode bytes, 2 displacement bytes. */
699 /* COND_JUMP states. */
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
701 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
702 /* dword conditionals adds 5 bytes to frag:
703 1 extra opcode byte, 4 displacement bytes. */
705 /* word conditionals add 3 bytes to frag:
706 1 extra opcode byte, 2 displacement bytes. */
709 /* COND_JUMP86 states. */
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
712 /* dword conditionals adds 5 bytes to frag:
713 1 extra opcode byte, 4 displacement bytes. */
715 /* word conditionals add 4 bytes to frag:
716 1 displacement byte and a 3 byte long branch insn. */
720 static const arch_entry cpu_arch
[] =
722 /* Do not replace the first two entries - i386_target_format()
723 relies on them being there in this order. */
724 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
725 CPU_GENERIC32_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
727 CPU_GENERIC64_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
729 CPU_NONE_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
731 CPU_I186_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
733 CPU_I286_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
735 CPU_I386_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
737 CPU_I486_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
739 CPU_I586_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
741 CPU_I686_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
743 CPU_I586_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
745 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
747 CPU_P2_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
749 CPU_P3_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
751 CPU_P4_FLAGS
, 0, 0 },
752 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
753 CPU_CORE_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
755 CPU_NOCONA_FLAGS
, 0, 0 },
756 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
757 CPU_CORE_FLAGS
, 1, 0 },
758 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
759 CPU_CORE_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
761 CPU_CORE2_FLAGS
, 1, 0 },
762 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
763 CPU_CORE2_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
765 CPU_COREI7_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
767 CPU_L1OM_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
769 CPU_K1OM_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
771 CPU_K6_FLAGS
, 0, 0 },
772 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
773 CPU_K6_2_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
775 CPU_ATHLON_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
777 CPU_K8_FLAGS
, 1, 0 },
778 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
779 CPU_K8_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
781 CPU_K8_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
783 CPU_AMDFAM10_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
785 CPU_BDVER1_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
787 CPU_BDVER2_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
789 CPU_BDVER3_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
791 CPU_BDVER4_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
793 CPU_ZNVER1_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
795 CPU_BTVER1_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
797 CPU_BTVER2_FLAGS
, 0, 0 },
798 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
799 CPU_8087_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
801 CPU_287_FLAGS
, 0, 0 },
802 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
803 CPU_387_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
805 CPU_ANY87_FLAGS
, 0, 1 },
806 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
807 CPU_MMX_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
809 CPU_3DNOWA_FLAGS
, 0, 1 },
810 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
811 CPU_SSE_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
813 CPU_SSE2_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
815 CPU_SSE3_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
817 CPU_SSSE3_FLAGS
, 0, 0 },
818 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
819 CPU_SSE4_1_FLAGS
, 0, 0 },
820 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
821 CPU_SSE4_2_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
823 CPU_SSE4_2_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
825 CPU_ANY_SSE_FLAGS
, 0, 1 },
826 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
827 CPU_AVX_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
829 CPU_AVX2_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
831 CPU_AVX512F_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
833 CPU_AVX512CD_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
835 CPU_AVX512ER_FLAGS
, 0, 0 },
836 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
837 CPU_AVX512PF_FLAGS
, 0, 0 },
838 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
839 CPU_AVX512DQ_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
841 CPU_AVX512BW_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
843 CPU_AVX512VL_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
845 CPU_ANY_AVX_FLAGS
, 0, 1 },
846 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
847 CPU_VMX_FLAGS
, 0, 0 },
848 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
849 CPU_VMFUNC_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
851 CPU_SMX_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
853 CPU_XSAVE_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
855 CPU_XSAVEOPT_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
857 CPU_XSAVEC_FLAGS
, 0, 0 },
858 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
859 CPU_XSAVES_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
861 CPU_AES_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
863 CPU_PCLMUL_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
865 CPU_PCLMUL_FLAGS
, 1, 0 },
866 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
867 CPU_FSGSBASE_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
869 CPU_RDRND_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
871 CPU_F16C_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
873 CPU_BMI2_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
875 CPU_FMA_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
877 CPU_FMA4_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
879 CPU_XOP_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
881 CPU_LWP_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
883 CPU_MOVBE_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
885 CPU_CX16_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
887 CPU_EPT_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
889 CPU_LZCNT_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
891 CPU_HLE_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
893 CPU_RTM_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
895 CPU_INVPCID_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
897 CPU_CLFLUSH_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
899 CPU_NOP_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
901 CPU_SYSCALL_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
903 CPU_RDTSCP_FLAGS
, 0, 0 },
904 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
905 CPU_3DNOW_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
907 CPU_3DNOWA_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
909 CPU_PADLOCK_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
911 CPU_SVME_FLAGS
, 1, 0 },
912 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
913 CPU_SVME_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
915 CPU_SSE4A_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
917 CPU_ABM_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
919 CPU_BMI_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
921 CPU_TBM_FLAGS
, 0, 0 },
922 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
923 CPU_ADX_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
925 CPU_RDSEED_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
927 CPU_PRFCHW_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
929 CPU_SMAP_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
931 CPU_MPX_FLAGS
, 0, 0 },
932 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
933 CPU_SHA_FLAGS
, 0, 0 },
934 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
935 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
936 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
937 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
938 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
939 CPU_SE1_FLAGS
, 0, 0 },
940 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
941 CPU_CLWB_FLAGS
, 0, 0 },
942 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
943 CPU_PCOMMIT_FLAGS
, 0, 0 },
944 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
945 CPU_AVX512IFMA_FLAGS
, 0, 0 },
946 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
947 CPU_AVX512VBMI_FLAGS
, 0, 0 },
948 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
949 CPU_CLZERO_FLAGS
, 0, 0 },
953 /* Like s_lcomm_internal in gas/read.c but the alignment string
954 is allowed to be optional. */
957 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
964 && *input_line_pointer
== ',')
966 align
= parse_align (needs_align
- 1);
968 if (align
== (addressT
) -1)
983 bss_alloc (symbolP
, size
, align
);
988 pe_lcomm (int needs_align
)
990 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
994 const pseudo_typeS md_pseudo_table
[] =
996 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
997 {"align", s_align_bytes
, 0},
999 {"align", s_align_ptwo
, 0},
1001 {"arch", set_cpu_arch
, 0},
1005 {"lcomm", pe_lcomm
, 1},
1007 {"ffloat", float_cons
, 'f'},
1008 {"dfloat", float_cons
, 'd'},
1009 {"tfloat", float_cons
, 'x'},
1011 {"slong", signed_cons
, 4},
1012 {"noopt", s_ignore
, 0},
1013 {"optim", s_ignore
, 0},
1014 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1015 {"code16", set_code_flag
, CODE_16BIT
},
1016 {"code32", set_code_flag
, CODE_32BIT
},
1017 {"code64", set_code_flag
, CODE_64BIT
},
1018 {"intel_syntax", set_intel_syntax
, 1},
1019 {"att_syntax", set_intel_syntax
, 0},
1020 {"intel_mnemonic", set_intel_mnemonic
, 1},
1021 {"att_mnemonic", set_intel_mnemonic
, 0},
1022 {"allow_index_reg", set_allow_index_reg
, 1},
1023 {"disallow_index_reg", set_allow_index_reg
, 0},
1024 {"sse_check", set_check
, 0},
1025 {"operand_check", set_check
, 1},
1026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1027 {"largecomm", handle_large_common
, 0},
1029 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1030 {"loc", dwarf2_directive_loc
, 0},
1031 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1034 {"secrel32", pe_directive_secrel
, 0},
1039 /* For interface with expression (). */
1040 extern char *input_line_pointer
;
1042 /* Hash table for instruction mnemonic lookup. */
1043 static struct hash_control
*op_hash
;
1045 /* Hash table for register lookup. */
1046 static struct hash_control
*reg_hash
;
1049 i386_align_code (fragS
*fragP
, int count
)
1051 /* Various efficient no-op patterns for aligning code labels.
1052 Note: Don't try to assemble the instructions in the comments.
1053 0L and 0w are not legal. */
1054 static const char f32_1
[] =
1056 static const char f32_2
[] =
1057 {0x66,0x90}; /* xchg %ax,%ax */
1058 static const char f32_3
[] =
1059 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1060 static const char f32_4
[] =
1061 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1062 static const char f32_5
[] =
1064 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1065 static const char f32_6
[] =
1066 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1067 static const char f32_7
[] =
1068 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1069 static const char f32_8
[] =
1071 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1072 static const char f32_9
[] =
1073 {0x89,0xf6, /* movl %esi,%esi */
1074 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1075 static const char f32_10
[] =
1076 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f32_11
[] =
1079 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1080 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1081 static const char f32_12
[] =
1082 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1083 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1084 static const char f32_13
[] =
1085 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1086 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1087 static const char f32_14
[] =
1088 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f16_3
[] =
1091 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1092 static const char f16_4
[] =
1093 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1094 static const char f16_5
[] =
1096 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1097 static const char f16_6
[] =
1098 {0x89,0xf6, /* mov %si,%si */
1099 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1100 static const char f16_7
[] =
1101 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1102 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1103 static const char f16_8
[] =
1104 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1105 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1106 static const char jump_31
[] =
1107 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1108 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1109 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1110 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1111 static const char *const f32_patt
[] = {
1112 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1113 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1115 static const char *const f16_patt
[] = {
1116 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1118 /* nopl (%[re]ax) */
1119 static const char alt_3
[] =
1121 /* nopl 0(%[re]ax) */
1122 static const char alt_4
[] =
1123 {0x0f,0x1f,0x40,0x00};
1124 /* nopl 0(%[re]ax,%[re]ax,1) */
1125 static const char alt_5
[] =
1126 {0x0f,0x1f,0x44,0x00,0x00};
1127 /* nopw 0(%[re]ax,%[re]ax,1) */
1128 static const char alt_6
[] =
1129 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1130 /* nopl 0L(%[re]ax) */
1131 static const char alt_7
[] =
1132 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1133 /* nopl 0L(%[re]ax,%[re]ax,1) */
1134 static const char alt_8
[] =
1135 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 /* nopw 0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_9
[] =
1138 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_10
[] =
1141 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 static const char *const alt_patt
[] = {
1143 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1147 /* Only align for at least a positive non-zero boundary. */
1148 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1151 /* We need to decide which NOP sequence to use for 32bit and
1152 64bit. When -mtune= is used:
1154 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1155 PROCESSOR_GENERIC32, f32_patt will be used.
1156 2. For the rest, alt_patt will be used.
1158 When -mtune= isn't used, alt_patt will be used if
1159 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1162 When -march= or .arch is used, we can't use anything beyond
1163 cpu_arch_isa_flags. */
1165 if (flag_code
== CODE_16BIT
)
1169 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1171 /* Adjust jump offset. */
1172 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1175 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1176 f16_patt
[count
- 1], count
);
1180 const char *const *patt
= NULL
;
1182 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1184 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1185 switch (cpu_arch_tune
)
1187 case PROCESSOR_UNKNOWN
:
1188 /* We use cpu_arch_isa_flags to check if we SHOULD
1189 optimize with nops. */
1190 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1195 case PROCESSOR_PENTIUM4
:
1196 case PROCESSOR_NOCONA
:
1197 case PROCESSOR_CORE
:
1198 case PROCESSOR_CORE2
:
1199 case PROCESSOR_COREI7
:
1200 case PROCESSOR_L1OM
:
1201 case PROCESSOR_K1OM
:
1202 case PROCESSOR_GENERIC64
:
1204 case PROCESSOR_ATHLON
:
1206 case PROCESSOR_AMDFAM10
:
1208 case PROCESSOR_ZNVER
:
1212 case PROCESSOR_I386
:
1213 case PROCESSOR_I486
:
1214 case PROCESSOR_PENTIUM
:
1215 case PROCESSOR_PENTIUMPRO
:
1216 case PROCESSOR_GENERIC32
:
1223 switch (fragP
->tc_frag_data
.tune
)
1225 case PROCESSOR_UNKNOWN
:
1226 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1227 PROCESSOR_UNKNOWN. */
1231 case PROCESSOR_I386
:
1232 case PROCESSOR_I486
:
1233 case PROCESSOR_PENTIUM
:
1235 case PROCESSOR_ATHLON
:
1237 case PROCESSOR_AMDFAM10
:
1239 case PROCESSOR_ZNVER
:
1241 case PROCESSOR_GENERIC32
:
1242 /* We use cpu_arch_isa_flags to check if we CAN optimize
1244 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1249 case PROCESSOR_PENTIUMPRO
:
1250 case PROCESSOR_PENTIUM4
:
1251 case PROCESSOR_NOCONA
:
1252 case PROCESSOR_CORE
:
1253 case PROCESSOR_CORE2
:
1254 case PROCESSOR_COREI7
:
1255 case PROCESSOR_L1OM
:
1256 case PROCESSOR_K1OM
:
1257 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1262 case PROCESSOR_GENERIC64
:
1268 if (patt
== f32_patt
)
1270 /* If the padding is less than 15 bytes, we use the normal
1271 ones. Otherwise, we use a jump instruction and adjust
1275 /* For 64bit, the limit is 3 bytes. */
1276 if (flag_code
== CODE_64BIT
1277 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1282 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1283 patt
[count
- 1], count
);
1286 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1288 /* Adjust jump offset. */
1289 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1294 /* Maximum length of an instruction is 10 byte. If the
1295 padding is greater than 10 bytes and we don't use jump,
1296 we have to break it into smaller pieces. */
1297 int padding
= count
;
1298 while (padding
> 10)
1301 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1306 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1307 patt
[padding
- 1], padding
);
1310 fragP
->fr_var
= count
;
1314 operand_type_all_zero (const union i386_operand_type
*x
)
1316 switch (ARRAY_SIZE(x
->array
))
1325 return !x
->array
[0];
1332 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1334 switch (ARRAY_SIZE(x
->array
))
1349 operand_type_equal (const union i386_operand_type
*x
,
1350 const union i386_operand_type
*y
)
1352 switch (ARRAY_SIZE(x
->array
))
1355 if (x
->array
[2] != y
->array
[2])
1358 if (x
->array
[1] != y
->array
[1])
1361 return x
->array
[0] == y
->array
[0];
1369 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1371 switch (ARRAY_SIZE(x
->array
))
1380 return !x
->array
[0];
1387 cpu_flags_equal (const union i386_cpu_flags
*x
,
1388 const union i386_cpu_flags
*y
)
1390 switch (ARRAY_SIZE(x
->array
))
1393 if (x
->array
[2] != y
->array
[2])
1396 if (x
->array
[1] != y
->array
[1])
1399 return x
->array
[0] == y
->array
[0];
1407 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1409 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1410 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1413 static INLINE i386_cpu_flags
1414 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1416 switch (ARRAY_SIZE (x
.array
))
1419 x
.array
[2] &= y
.array
[2];
1421 x
.array
[1] &= y
.array
[1];
1423 x
.array
[0] &= y
.array
[0];
1431 static INLINE i386_cpu_flags
1432 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1434 switch (ARRAY_SIZE (x
.array
))
1437 x
.array
[2] |= y
.array
[2];
1439 x
.array
[1] |= y
.array
[1];
1441 x
.array
[0] |= y
.array
[0];
1449 static INLINE i386_cpu_flags
1450 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1452 switch (ARRAY_SIZE (x
.array
))
1455 x
.array
[2] &= ~y
.array
[2];
1457 x
.array
[1] &= ~y
.array
[1];
1459 x
.array
[0] &= ~y
.array
[0];
1467 #define CPU_FLAGS_ARCH_MATCH 0x1
1468 #define CPU_FLAGS_64BIT_MATCH 0x2
1469 #define CPU_FLAGS_AES_MATCH 0x4
1470 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1471 #define CPU_FLAGS_AVX_MATCH 0x10
1473 #define CPU_FLAGS_32BIT_MATCH \
1474 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1475 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1476 #define CPU_FLAGS_PERFECT_MATCH \
1477 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1479 /* Return CPU flags match bits. */
1482 cpu_flags_match (const insn_template
*t
)
1484 i386_cpu_flags x
= t
->cpu_flags
;
1485 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1487 x
.bitfield
.cpu64
= 0;
1488 x
.bitfield
.cpuno64
= 0;
1490 if (cpu_flags_all_zero (&x
))
1492 /* This instruction is available on all archs. */
1493 match
|= CPU_FLAGS_32BIT_MATCH
;
1497 /* This instruction is available only on some archs. */
1498 i386_cpu_flags cpu
= cpu_arch_flags
;
1500 cpu
.bitfield
.cpu64
= 0;
1501 cpu
.bitfield
.cpuno64
= 0;
1502 cpu
= cpu_flags_and (x
, cpu
);
1503 if (!cpu_flags_all_zero (&cpu
))
1505 if (x
.bitfield
.cpuavx
)
1507 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1508 if (cpu
.bitfield
.cpuavx
)
1510 /* Check SSE2AVX. */
1511 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1513 match
|= (CPU_FLAGS_ARCH_MATCH
1514 | CPU_FLAGS_AVX_MATCH
);
1516 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1517 match
|= CPU_FLAGS_AES_MATCH
;
1519 if (!x
.bitfield
.cpupclmul
1520 || cpu
.bitfield
.cpupclmul
)
1521 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1525 match
|= CPU_FLAGS_ARCH_MATCH
;
1528 match
|= CPU_FLAGS_32BIT_MATCH
;
1534 static INLINE i386_operand_type
1535 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1537 switch (ARRAY_SIZE (x
.array
))
1540 x
.array
[2] &= y
.array
[2];
1542 x
.array
[1] &= y
.array
[1];
1544 x
.array
[0] &= y
.array
[0];
1552 static INLINE i386_operand_type
1553 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1555 switch (ARRAY_SIZE (x
.array
))
1558 x
.array
[2] |= y
.array
[2];
1560 x
.array
[1] |= y
.array
[1];
1562 x
.array
[0] |= y
.array
[0];
1570 static INLINE i386_operand_type
1571 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1573 switch (ARRAY_SIZE (x
.array
))
1576 x
.array
[2] ^= y
.array
[2];
1578 x
.array
[1] ^= y
.array
[1];
1580 x
.array
[0] ^= y
.array
[0];
1588 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1589 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1590 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1591 static const i386_operand_type inoutportreg
1592 = OPERAND_TYPE_INOUTPORTREG
;
1593 static const i386_operand_type reg16_inoutportreg
1594 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1595 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1596 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1597 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1598 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1599 static const i386_operand_type anydisp
1600 = OPERAND_TYPE_ANYDISP
;
1601 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1602 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1603 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1604 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1605 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1606 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1607 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1608 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1609 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1610 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1611 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1612 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1613 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1614 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1625 operand_type_check (i386_operand_type t
, enum operand_type c
)
1630 return (t
.bitfield
.reg8
1633 || t
.bitfield
.reg64
);
1636 return (t
.bitfield
.imm8
1640 || t
.bitfield
.imm32s
1641 || t
.bitfield
.imm64
);
1644 return (t
.bitfield
.disp8
1645 || t
.bitfield
.disp16
1646 || t
.bitfield
.disp32
1647 || t
.bitfield
.disp32s
1648 || t
.bitfield
.disp64
);
1651 return (t
.bitfield
.disp8
1652 || t
.bitfield
.disp16
1653 || t
.bitfield
.disp32
1654 || t
.bitfield
.disp32s
1655 || t
.bitfield
.disp64
1656 || t
.bitfield
.baseindex
);
1665 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1666 operand J for instruction template T. */
1669 match_reg_size (const insn_template
*t
, unsigned int j
)
1671 return !((i
.types
[j
].bitfield
.byte
1672 && !t
->operand_types
[j
].bitfield
.byte
)
1673 || (i
.types
[j
].bitfield
.word
1674 && !t
->operand_types
[j
].bitfield
.word
)
1675 || (i
.types
[j
].bitfield
.dword
1676 && !t
->operand_types
[j
].bitfield
.dword
)
1677 || (i
.types
[j
].bitfield
.qword
1678 && !t
->operand_types
[j
].bitfield
.qword
));
1681 /* Return 1 if there is no conflict in any size on operand J for
1682 instruction template T. */
1685 match_mem_size (const insn_template
*t
, unsigned int j
)
1687 return (match_reg_size (t
, j
)
1688 && !((i
.types
[j
].bitfield
.unspecified
1690 && !t
->operand_types
[j
].bitfield
.unspecified
)
1691 || (i
.types
[j
].bitfield
.fword
1692 && !t
->operand_types
[j
].bitfield
.fword
)
1693 || (i
.types
[j
].bitfield
.tbyte
1694 && !t
->operand_types
[j
].bitfield
.tbyte
)
1695 || (i
.types
[j
].bitfield
.xmmword
1696 && !t
->operand_types
[j
].bitfield
.xmmword
)
1697 || (i
.types
[j
].bitfield
.ymmword
1698 && !t
->operand_types
[j
].bitfield
.ymmword
)
1699 || (i
.types
[j
].bitfield
.zmmword
1700 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1703 /* Return 1 if there is no size conflict on any operands for
1704 instruction template T. */
1707 operand_size_match (const insn_template
*t
)
1712 /* Don't check jump instructions. */
1713 if (t
->opcode_modifier
.jump
1714 || t
->opcode_modifier
.jumpbyte
1715 || t
->opcode_modifier
.jumpdword
1716 || t
->opcode_modifier
.jumpintersegment
)
1719 /* Check memory and accumulator operand size. */
1720 for (j
= 0; j
< i
.operands
; j
++)
1722 if (t
->operand_types
[j
].bitfield
.anysize
)
1725 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1731 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1740 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1743 i
.error
= operand_size_mismatch
;
1747 /* Check reverse. */
1748 gas_assert (i
.operands
== 2);
1751 for (j
= 0; j
< 2; j
++)
1753 if (t
->operand_types
[j
].bitfield
.acc
1754 && !match_reg_size (t
, j
? 0 : 1))
1757 if (i
.types
[j
].bitfield
.mem
1758 && !match_mem_size (t
, j
? 0 : 1))
1766 operand_type_match (i386_operand_type overlap
,
1767 i386_operand_type given
)
1769 i386_operand_type temp
= overlap
;
1771 temp
.bitfield
.jumpabsolute
= 0;
1772 temp
.bitfield
.unspecified
= 0;
1773 temp
.bitfield
.byte
= 0;
1774 temp
.bitfield
.word
= 0;
1775 temp
.bitfield
.dword
= 0;
1776 temp
.bitfield
.fword
= 0;
1777 temp
.bitfield
.qword
= 0;
1778 temp
.bitfield
.tbyte
= 0;
1779 temp
.bitfield
.xmmword
= 0;
1780 temp
.bitfield
.ymmword
= 0;
1781 temp
.bitfield
.zmmword
= 0;
1782 if (operand_type_all_zero (&temp
))
1785 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1786 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1790 i
.error
= operand_type_mismatch
;
1794 /* If given types g0 and g1 are registers they must be of the same type
1795 unless the expected operand type register overlap is null.
1796 Note that Acc in a template matches every size of reg. */
1799 operand_type_register_match (i386_operand_type m0
,
1800 i386_operand_type g0
,
1801 i386_operand_type t0
,
1802 i386_operand_type m1
,
1803 i386_operand_type g1
,
1804 i386_operand_type t1
)
1806 if (!operand_type_check (g0
, reg
))
1809 if (!operand_type_check (g1
, reg
))
1812 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1813 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1814 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1815 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1818 if (m0
.bitfield
.acc
)
1820 t0
.bitfield
.reg8
= 1;
1821 t0
.bitfield
.reg16
= 1;
1822 t0
.bitfield
.reg32
= 1;
1823 t0
.bitfield
.reg64
= 1;
1826 if (m1
.bitfield
.acc
)
1828 t1
.bitfield
.reg8
= 1;
1829 t1
.bitfield
.reg16
= 1;
1830 t1
.bitfield
.reg32
= 1;
1831 t1
.bitfield
.reg64
= 1;
1834 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1835 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1836 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1837 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1840 i
.error
= register_type_mismatch
;
1845 static INLINE
unsigned int
1846 register_number (const reg_entry
*r
)
1848 unsigned int nr
= r
->reg_num
;
1850 if (r
->reg_flags
& RegRex
)
1856 static INLINE
unsigned int
1857 mode_from_disp_size (i386_operand_type t
)
1859 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1861 else if (t
.bitfield
.disp16
1862 || t
.bitfield
.disp32
1863 || t
.bitfield
.disp32s
)
1870 fits_in_signed_byte (addressT num
)
1872 return num
+ 0x80 <= 0xff;
1876 fits_in_unsigned_byte (addressT num
)
1882 fits_in_unsigned_word (addressT num
)
1884 return num
<= 0xffff;
1888 fits_in_signed_word (addressT num
)
1890 return num
+ 0x8000 <= 0xffff;
1894 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1899 return num
+ 0x80000000 <= 0xffffffff;
1901 } /* fits_in_signed_long() */
1904 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1909 return num
<= 0xffffffff;
1911 } /* fits_in_unsigned_long() */
1914 fits_in_vec_disp8 (offsetT num
)
1916 int shift
= i
.memshift
;
1922 mask
= (1 << shift
) - 1;
1924 /* Return 0 if NUM isn't properly aligned. */
1928 /* Check if NUM will fit in 8bit after shift. */
1929 return fits_in_signed_byte (num
>> shift
);
1933 fits_in_imm4 (offsetT num
)
1935 return (num
& 0xf) == num
;
1938 static i386_operand_type
1939 smallest_imm_type (offsetT num
)
1941 i386_operand_type t
;
1943 operand_type_set (&t
, 0);
1944 t
.bitfield
.imm64
= 1;
1946 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1948 /* This code is disabled on the 486 because all the Imm1 forms
1949 in the opcode table are slower on the i486. They're the
1950 versions with the implicitly specified single-position
1951 displacement, which has another syntax if you really want to
1953 t
.bitfield
.imm1
= 1;
1954 t
.bitfield
.imm8
= 1;
1955 t
.bitfield
.imm8s
= 1;
1956 t
.bitfield
.imm16
= 1;
1957 t
.bitfield
.imm32
= 1;
1958 t
.bitfield
.imm32s
= 1;
1960 else if (fits_in_signed_byte (num
))
1962 t
.bitfield
.imm8
= 1;
1963 t
.bitfield
.imm8s
= 1;
1964 t
.bitfield
.imm16
= 1;
1965 t
.bitfield
.imm32
= 1;
1966 t
.bitfield
.imm32s
= 1;
1968 else if (fits_in_unsigned_byte (num
))
1970 t
.bitfield
.imm8
= 1;
1971 t
.bitfield
.imm16
= 1;
1972 t
.bitfield
.imm32
= 1;
1973 t
.bitfield
.imm32s
= 1;
1975 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1977 t
.bitfield
.imm16
= 1;
1978 t
.bitfield
.imm32
= 1;
1979 t
.bitfield
.imm32s
= 1;
1981 else if (fits_in_signed_long (num
))
1983 t
.bitfield
.imm32
= 1;
1984 t
.bitfield
.imm32s
= 1;
1986 else if (fits_in_unsigned_long (num
))
1987 t
.bitfield
.imm32
= 1;
1993 offset_in_range (offsetT val
, int size
)
1999 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2000 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2001 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2003 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2009 /* If BFD64, sign extend val for 32bit address mode. */
2010 if (flag_code
!= CODE_64BIT
2011 || i
.prefix
[ADDR_PREFIX
])
2012 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2013 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2016 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2018 char buf1
[40], buf2
[40];
2020 sprint_value (buf1
, val
);
2021 sprint_value (buf2
, val
& mask
);
2022 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2036 a. PREFIX_EXIST if attempting to add a prefix where one from the
2037 same class already exists.
2038 b. PREFIX_LOCK if lock prefix is added.
2039 c. PREFIX_REP if rep/repne prefix is added.
2040 d. PREFIX_OTHER if other prefix is added.
2043 static enum PREFIX_GROUP
2044 add_prefix (unsigned int prefix
)
2046 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2049 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2050 && flag_code
== CODE_64BIT
)
2052 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2053 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2054 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2065 case CS_PREFIX_OPCODE
:
2066 case DS_PREFIX_OPCODE
:
2067 case ES_PREFIX_OPCODE
:
2068 case FS_PREFIX_OPCODE
:
2069 case GS_PREFIX_OPCODE
:
2070 case SS_PREFIX_OPCODE
:
2074 case REPNE_PREFIX_OPCODE
:
2075 case REPE_PREFIX_OPCODE
:
2080 case LOCK_PREFIX_OPCODE
:
2089 case ADDR_PREFIX_OPCODE
:
2093 case DATA_PREFIX_OPCODE
:
2097 if (i
.prefix
[q
] != 0)
2105 i
.prefix
[q
] |= prefix
;
2108 as_bad (_("same type of prefix used twice"));
2114 update_code_flag (int value
, int check
)
2116 PRINTF_LIKE ((*as_error
));
2118 flag_code
= (enum flag_code
) value
;
2119 if (flag_code
== CODE_64BIT
)
2121 cpu_arch_flags
.bitfield
.cpu64
= 1;
2122 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2126 cpu_arch_flags
.bitfield
.cpu64
= 0;
2127 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2129 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2132 as_error
= as_fatal
;
2135 (*as_error
) (_("64bit mode not supported on `%s'."),
2136 cpu_arch_name
? cpu_arch_name
: default_arch
);
2138 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2141 as_error
= as_fatal
;
2144 (*as_error
) (_("32bit mode not supported on `%s'."),
2145 cpu_arch_name
? cpu_arch_name
: default_arch
);
2147 stackop_size
= '\0';
2151 set_code_flag (int value
)
2153 update_code_flag (value
, 0);
2157 set_16bit_gcc_code_flag (int new_code_flag
)
2159 flag_code
= (enum flag_code
) new_code_flag
;
2160 if (flag_code
!= CODE_16BIT
)
2162 cpu_arch_flags
.bitfield
.cpu64
= 0;
2163 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2164 stackop_size
= LONG_MNEM_SUFFIX
;
2168 set_intel_syntax (int syntax_flag
)
2170 /* Find out if register prefixing is specified. */
2171 int ask_naked_reg
= 0;
2174 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2176 char *string
= input_line_pointer
;
2177 int e
= get_symbol_end ();
2179 if (strcmp (string
, "prefix") == 0)
2181 else if (strcmp (string
, "noprefix") == 0)
2184 as_bad (_("bad argument to syntax directive."));
2185 *input_line_pointer
= e
;
2187 demand_empty_rest_of_line ();
2189 intel_syntax
= syntax_flag
;
2191 if (ask_naked_reg
== 0)
2192 allow_naked_reg
= (intel_syntax
2193 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2195 allow_naked_reg
= (ask_naked_reg
< 0);
2197 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2199 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2200 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2201 register_prefix
= allow_naked_reg
? "" : "%";
2205 set_intel_mnemonic (int mnemonic_flag
)
2207 intel_mnemonic
= mnemonic_flag
;
2211 set_allow_index_reg (int flag
)
2213 allow_index_reg
= flag
;
2217 set_check (int what
)
2219 enum check_kind
*kind
;
2224 kind
= &operand_check
;
2235 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2237 char *string
= input_line_pointer
;
2238 int e
= get_symbol_end ();
2240 if (strcmp (string
, "none") == 0)
2242 else if (strcmp (string
, "warning") == 0)
2243 *kind
= check_warning
;
2244 else if (strcmp (string
, "error") == 0)
2245 *kind
= check_error
;
2247 as_bad (_("bad argument to %s_check directive."), str
);
2248 *input_line_pointer
= e
;
2251 as_bad (_("missing argument for %s_check directive"), str
);
2253 demand_empty_rest_of_line ();
2257 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2258 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2261 static const char *arch
;
2263 /* Intel LIOM is only supported on ELF. */
2269 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2270 use default_arch. */
2271 arch
= cpu_arch_name
;
2273 arch
= default_arch
;
2276 /* If we are targeting Intel L1OM, we must enable it. */
2277 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2278 || new_flag
.bitfield
.cpul1om
)
2281 /* If we are targeting Intel K1OM, we must enable it. */
2282 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2283 || new_flag
.bitfield
.cpuk1om
)
2286 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2291 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2295 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2297 char *string
= input_line_pointer
;
2298 int e
= get_symbol_end ();
2300 i386_cpu_flags flags
;
2302 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2304 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2306 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2310 cpu_arch_name
= cpu_arch
[j
].name
;
2311 cpu_sub_arch_name
= NULL
;
2312 cpu_arch_flags
= cpu_arch
[j
].flags
;
2313 if (flag_code
== CODE_64BIT
)
2315 cpu_arch_flags
.bitfield
.cpu64
= 1;
2316 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2320 cpu_arch_flags
.bitfield
.cpu64
= 0;
2321 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2323 cpu_arch_isa
= cpu_arch
[j
].type
;
2324 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2325 if (!cpu_arch_tune_set
)
2327 cpu_arch_tune
= cpu_arch_isa
;
2328 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2333 if (!cpu_arch
[j
].negated
)
2334 flags
= cpu_flags_or (cpu_arch_flags
,
2337 flags
= cpu_flags_and_not (cpu_arch_flags
,
2339 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2341 if (cpu_sub_arch_name
)
2343 char *name
= cpu_sub_arch_name
;
2344 cpu_sub_arch_name
= concat (name
,
2346 (const char *) NULL
);
2350 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2351 cpu_arch_flags
= flags
;
2352 cpu_arch_isa_flags
= flags
;
2354 *input_line_pointer
= e
;
2355 demand_empty_rest_of_line ();
2359 if (j
>= ARRAY_SIZE (cpu_arch
))
2360 as_bad (_("no such architecture: `%s'"), string
);
2362 *input_line_pointer
= e
;
2365 as_bad (_("missing cpu architecture"));
2367 no_cond_jump_promotion
= 0;
2368 if (*input_line_pointer
== ','
2369 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2371 char *string
= ++input_line_pointer
;
2372 int e
= get_symbol_end ();
2374 if (strcmp (string
, "nojumps") == 0)
2375 no_cond_jump_promotion
= 1;
2376 else if (strcmp (string
, "jumps") == 0)
2379 as_bad (_("no such architecture modifier: `%s'"), string
);
2381 *input_line_pointer
= e
;
2384 demand_empty_rest_of_line ();
2387 enum bfd_architecture
2390 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2392 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2393 || flag_code
!= CODE_64BIT
)
2394 as_fatal (_("Intel L1OM is 64bit ELF only"));
2395 return bfd_arch_l1om
;
2397 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2399 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2400 || flag_code
!= CODE_64BIT
)
2401 as_fatal (_("Intel K1OM is 64bit ELF only"));
2402 return bfd_arch_k1om
;
2405 return bfd_arch_i386
;
2411 if (!strncmp (default_arch
, "x86_64", 6))
2413 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2415 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2416 || default_arch
[6] != '\0')
2417 as_fatal (_("Intel L1OM is 64bit ELF only"));
2418 return bfd_mach_l1om
;
2420 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2422 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2423 || default_arch
[6] != '\0')
2424 as_fatal (_("Intel K1OM is 64bit ELF only"));
2425 return bfd_mach_k1om
;
2427 else if (default_arch
[6] == '\0')
2428 return bfd_mach_x86_64
;
2430 return bfd_mach_x64_32
;
2432 else if (!strcmp (default_arch
, "i386"))
2433 return bfd_mach_i386_i386
;
2435 as_fatal (_("unknown architecture"));
2441 const char *hash_err
;
2443 /* Initialize op_hash hash table. */
2444 op_hash
= hash_new ();
2447 const insn_template
*optab
;
2448 templates
*core_optab
;
2450 /* Setup for loop. */
2452 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2453 core_optab
->start
= optab
;
2458 if (optab
->name
== NULL
2459 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2461 /* different name --> ship out current template list;
2462 add to hash table; & begin anew. */
2463 core_optab
->end
= optab
;
2464 hash_err
= hash_insert (op_hash
,
2466 (void *) core_optab
);
2469 as_fatal (_("can't hash %s: %s"),
2473 if (optab
->name
== NULL
)
2475 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2476 core_optab
->start
= optab
;
2481 /* Initialize reg_hash hash table. */
2482 reg_hash
= hash_new ();
2484 const reg_entry
*regtab
;
2485 unsigned int regtab_size
= i386_regtab_size
;
2487 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2489 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2491 as_fatal (_("can't hash %s: %s"),
2497 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2502 for (c
= 0; c
< 256; c
++)
2507 mnemonic_chars
[c
] = c
;
2508 register_chars
[c
] = c
;
2509 operand_chars
[c
] = c
;
2511 else if (ISLOWER (c
))
2513 mnemonic_chars
[c
] = c
;
2514 register_chars
[c
] = c
;
2515 operand_chars
[c
] = c
;
2517 else if (ISUPPER (c
))
2519 mnemonic_chars
[c
] = TOLOWER (c
);
2520 register_chars
[c
] = mnemonic_chars
[c
];
2521 operand_chars
[c
] = c
;
2523 else if (c
== '{' || c
== '}')
2524 operand_chars
[c
] = c
;
2526 if (ISALPHA (c
) || ISDIGIT (c
))
2527 identifier_chars
[c
] = c
;
2530 identifier_chars
[c
] = c
;
2531 operand_chars
[c
] = c
;
2536 identifier_chars
['@'] = '@';
2539 identifier_chars
['?'] = '?';
2540 operand_chars
['?'] = '?';
2542 digit_chars
['-'] = '-';
2543 mnemonic_chars
['_'] = '_';
2544 mnemonic_chars
['-'] = '-';
2545 mnemonic_chars
['.'] = '.';
2546 identifier_chars
['_'] = '_';
2547 identifier_chars
['.'] = '.';
2549 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2550 operand_chars
[(unsigned char) *p
] = *p
;
2553 if (flag_code
== CODE_64BIT
)
2555 #if defined (OBJ_COFF) && defined (TE_PE)
2556 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2559 x86_dwarf2_return_column
= 16;
2561 x86_cie_data_alignment
= -8;
2565 x86_dwarf2_return_column
= 8;
2566 x86_cie_data_alignment
= -4;
2571 i386_print_statistics (FILE *file
)
2573 hash_print_statistics (file
, "i386 opcode", op_hash
);
2574 hash_print_statistics (file
, "i386 register", reg_hash
);
2579 /* Debugging routines for md_assemble. */
2580 static void pte (insn_template
*);
2581 static void pt (i386_operand_type
);
2582 static void pe (expressionS
*);
2583 static void ps (symbolS
*);
2586 pi (char *line
, i386_insn
*x
)
2590 fprintf (stdout
, "%s: template ", line
);
2592 fprintf (stdout
, " address: base %s index %s scale %x\n",
2593 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2594 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2595 x
->log2_scale_factor
);
2596 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2597 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2598 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2599 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2600 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2601 (x
->rex
& REX_W
) != 0,
2602 (x
->rex
& REX_R
) != 0,
2603 (x
->rex
& REX_X
) != 0,
2604 (x
->rex
& REX_B
) != 0);
2605 for (j
= 0; j
< x
->operands
; j
++)
2607 fprintf (stdout
, " #%d: ", j
+ 1);
2609 fprintf (stdout
, "\n");
2610 if (x
->types
[j
].bitfield
.reg8
2611 || x
->types
[j
].bitfield
.reg16
2612 || x
->types
[j
].bitfield
.reg32
2613 || x
->types
[j
].bitfield
.reg64
2614 || x
->types
[j
].bitfield
.regmmx
2615 || x
->types
[j
].bitfield
.regxmm
2616 || x
->types
[j
].bitfield
.regymm
2617 || x
->types
[j
].bitfield
.regzmm
2618 || x
->types
[j
].bitfield
.sreg2
2619 || x
->types
[j
].bitfield
.sreg3
2620 || x
->types
[j
].bitfield
.control
2621 || x
->types
[j
].bitfield
.debug
2622 || x
->types
[j
].bitfield
.test
)
2623 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2624 if (operand_type_check (x
->types
[j
], imm
))
2626 if (operand_type_check (x
->types
[j
], disp
))
2627 pe (x
->op
[j
].disps
);
2632 pte (insn_template
*t
)
2635 fprintf (stdout
, " %d operands ", t
->operands
);
2636 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2637 if (t
->extension_opcode
!= None
)
2638 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2639 if (t
->opcode_modifier
.d
)
2640 fprintf (stdout
, "D");
2641 if (t
->opcode_modifier
.w
)
2642 fprintf (stdout
, "W");
2643 fprintf (stdout
, "\n");
2644 for (j
= 0; j
< t
->operands
; j
++)
2646 fprintf (stdout
, " #%d type ", j
+ 1);
2647 pt (t
->operand_types
[j
]);
2648 fprintf (stdout
, "\n");
2655 fprintf (stdout
, " operation %d\n", e
->X_op
);
2656 fprintf (stdout
, " add_number %ld (%lx)\n",
2657 (long) e
->X_add_number
, (long) e
->X_add_number
);
2658 if (e
->X_add_symbol
)
2660 fprintf (stdout
, " add_symbol ");
2661 ps (e
->X_add_symbol
);
2662 fprintf (stdout
, "\n");
2666 fprintf (stdout
, " op_symbol ");
2667 ps (e
->X_op_symbol
);
2668 fprintf (stdout
, "\n");
2675 fprintf (stdout
, "%s type %s%s",
2677 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2678 segment_name (S_GET_SEGMENT (s
)));
2681 static struct type_name
2683 i386_operand_type mask
;
2686 const type_names
[] =
2688 { OPERAND_TYPE_REG8
, "r8" },
2689 { OPERAND_TYPE_REG16
, "r16" },
2690 { OPERAND_TYPE_REG32
, "r32" },
2691 { OPERAND_TYPE_REG64
, "r64" },
2692 { OPERAND_TYPE_IMM8
, "i8" },
2693 { OPERAND_TYPE_IMM8
, "i8s" },
2694 { OPERAND_TYPE_IMM16
, "i16" },
2695 { OPERAND_TYPE_IMM32
, "i32" },
2696 { OPERAND_TYPE_IMM32S
, "i32s" },
2697 { OPERAND_TYPE_IMM64
, "i64" },
2698 { OPERAND_TYPE_IMM1
, "i1" },
2699 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2700 { OPERAND_TYPE_DISP8
, "d8" },
2701 { OPERAND_TYPE_DISP16
, "d16" },
2702 { OPERAND_TYPE_DISP32
, "d32" },
2703 { OPERAND_TYPE_DISP32S
, "d32s" },
2704 { OPERAND_TYPE_DISP64
, "d64" },
2705 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2706 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2707 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2708 { OPERAND_TYPE_CONTROL
, "control reg" },
2709 { OPERAND_TYPE_TEST
, "test reg" },
2710 { OPERAND_TYPE_DEBUG
, "debug reg" },
2711 { OPERAND_TYPE_FLOATREG
, "FReg" },
2712 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2713 { OPERAND_TYPE_SREG2
, "SReg2" },
2714 { OPERAND_TYPE_SREG3
, "SReg3" },
2715 { OPERAND_TYPE_ACC
, "Acc" },
2716 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2717 { OPERAND_TYPE_REGMMX
, "rMMX" },
2718 { OPERAND_TYPE_REGXMM
, "rXMM" },
2719 { OPERAND_TYPE_REGYMM
, "rYMM" },
2720 { OPERAND_TYPE_REGZMM
, "rZMM" },
2721 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2722 { OPERAND_TYPE_ESSEG
, "es" },
2726 pt (i386_operand_type t
)
2729 i386_operand_type a
;
2731 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2733 a
= operand_type_and (t
, type_names
[j
].mask
);
2734 if (!operand_type_all_zero (&a
))
2735 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2740 #endif /* DEBUG386 */
2742 static bfd_reloc_code_real_type
2743 reloc (unsigned int size
,
2746 bfd_reloc_code_real_type other
)
2748 if (other
!= NO_RELOC
)
2750 reloc_howto_type
*rel
;
2755 case BFD_RELOC_X86_64_GOT32
:
2756 return BFD_RELOC_X86_64_GOT64
;
2758 case BFD_RELOC_X86_64_GOTPLT64
:
2759 return BFD_RELOC_X86_64_GOTPLT64
;
2761 case BFD_RELOC_X86_64_PLTOFF64
:
2762 return BFD_RELOC_X86_64_PLTOFF64
;
2764 case BFD_RELOC_X86_64_GOTPC32
:
2765 other
= BFD_RELOC_X86_64_GOTPC64
;
2767 case BFD_RELOC_X86_64_GOTPCREL
:
2768 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2770 case BFD_RELOC_X86_64_TPOFF32
:
2771 other
= BFD_RELOC_X86_64_TPOFF64
;
2773 case BFD_RELOC_X86_64_DTPOFF32
:
2774 other
= BFD_RELOC_X86_64_DTPOFF64
;
2780 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2781 if (other
== BFD_RELOC_SIZE32
)
2784 other
= BFD_RELOC_SIZE64
;
2787 as_bad (_("there are no pc-relative size relocations"));
2793 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2794 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2797 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2799 as_bad (_("unknown relocation (%u)"), other
);
2800 else if (size
!= bfd_get_reloc_size (rel
))
2801 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2802 bfd_get_reloc_size (rel
),
2804 else if (pcrel
&& !rel
->pc_relative
)
2805 as_bad (_("non-pc-relative relocation for pc-relative field"));
2806 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2808 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2810 as_bad (_("relocated field and relocation type differ in signedness"));
2819 as_bad (_("there are no unsigned pc-relative relocations"));
2822 case 1: return BFD_RELOC_8_PCREL
;
2823 case 2: return BFD_RELOC_16_PCREL
;
2824 case 4: return BFD_RELOC_32_PCREL
;
2825 case 8: return BFD_RELOC_64_PCREL
;
2827 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2834 case 4: return BFD_RELOC_X86_64_32S
;
2839 case 1: return BFD_RELOC_8
;
2840 case 2: return BFD_RELOC_16
;
2841 case 4: return BFD_RELOC_32
;
2842 case 8: return BFD_RELOC_64
;
2844 as_bad (_("cannot do %s %u byte relocation"),
2845 sign
> 0 ? "signed" : "unsigned", size
);
2851 /* Here we decide which fixups can be adjusted to make them relative to
2852 the beginning of the section instead of the symbol. Basically we need
2853 to make sure that the dynamic relocations are done correctly, so in
2854 some cases we force the original symbol to be used. */
2857 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2863 /* Don't adjust pc-relative references to merge sections in 64-bit
2865 if (use_rela_relocations
2866 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2870 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2871 and changed later by validate_fix. */
2872 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2873 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2876 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2877 for size relocations. */
2878 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2879 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2880 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2881 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2882 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2883 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2884 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2885 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2886 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2887 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2888 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2889 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2890 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2891 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2892 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2893 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2894 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2895 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2896 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2897 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2898 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2899 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2900 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2901 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2902 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2903 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2904 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2905 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2906 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2907 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2914 intel_float_operand (const char *mnemonic
)
2916 /* Note that the value returned is meaningful only for opcodes with (memory)
2917 operands, hence the code here is free to improperly handle opcodes that
2918 have no operands (for better performance and smaller code). */
2920 if (mnemonic
[0] != 'f')
2921 return 0; /* non-math */
2923 switch (mnemonic
[1])
2925 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2926 the fs segment override prefix not currently handled because no
2927 call path can make opcodes without operands get here */
2929 return 2 /* integer op */;
2931 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2932 return 3; /* fldcw/fldenv */
2935 if (mnemonic
[2] != 'o' /* fnop */)
2936 return 3; /* non-waiting control op */
2939 if (mnemonic
[2] == 's')
2940 return 3; /* frstor/frstpm */
2943 if (mnemonic
[2] == 'a')
2944 return 3; /* fsave */
2945 if (mnemonic
[2] == 't')
2947 switch (mnemonic
[3])
2949 case 'c': /* fstcw */
2950 case 'd': /* fstdw */
2951 case 'e': /* fstenv */
2952 case 's': /* fsts[gw] */
2958 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2959 return 0; /* fxsave/fxrstor are not really math ops */
2966 /* Build the VEX prefix. */
2969 build_vex_prefix (const insn_template
*t
)
2971 unsigned int register_specifier
;
2972 unsigned int implied_prefix
;
2973 unsigned int vector_length
;
2975 /* Check register specifier. */
2976 if (i
.vex
.register_specifier
)
2978 register_specifier
=
2979 ~register_number (i
.vex
.register_specifier
) & 0xf;
2980 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
2983 register_specifier
= 0xf;
2985 /* Use 2-byte VEX prefix by swappping destination and source
2988 && i
.operands
== i
.reg_operands
2989 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2990 && i
.tm
.opcode_modifier
.s
2993 unsigned int xchg
= i
.operands
- 1;
2994 union i386_op temp_op
;
2995 i386_operand_type temp_type
;
2997 temp_type
= i
.types
[xchg
];
2998 i
.types
[xchg
] = i
.types
[0];
2999 i
.types
[0] = temp_type
;
3000 temp_op
= i
.op
[xchg
];
3001 i
.op
[xchg
] = i
.op
[0];
3004 gas_assert (i
.rm
.mode
== 3);
3008 i
.rm
.regmem
= i
.rm
.reg
;
3011 /* Use the next insn. */
3015 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3016 vector_length
= avxscalar
;
3018 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3020 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3025 case DATA_PREFIX_OPCODE
:
3028 case REPE_PREFIX_OPCODE
:
3031 case REPNE_PREFIX_OPCODE
:
3038 /* Use 2-byte VEX prefix if possible. */
3039 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3040 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3041 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3043 /* 2-byte VEX prefix. */
3047 i
.vex
.bytes
[0] = 0xc5;
3049 /* Check the REX.R bit. */
3050 r
= (i
.rex
& REX_R
) ? 0 : 1;
3051 i
.vex
.bytes
[1] = (r
<< 7
3052 | register_specifier
<< 3
3053 | vector_length
<< 2
3058 /* 3-byte VEX prefix. */
3063 switch (i
.tm
.opcode_modifier
.vexopcode
)
3067 i
.vex
.bytes
[0] = 0xc4;
3071 i
.vex
.bytes
[0] = 0xc4;
3075 i
.vex
.bytes
[0] = 0xc4;
3079 i
.vex
.bytes
[0] = 0x8f;
3083 i
.vex
.bytes
[0] = 0x8f;
3087 i
.vex
.bytes
[0] = 0x8f;
3093 /* The high 3 bits of the second VEX byte are 1's compliment
3094 of RXB bits from REX. */
3095 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3097 /* Check the REX.W bit. */
3098 w
= (i
.rex
& REX_W
) ? 1 : 0;
3099 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3102 i
.vex
.bytes
[2] = (w
<< 7
3103 | register_specifier
<< 3
3104 | vector_length
<< 2
3109 /* Build the EVEX prefix. */
3112 build_evex_prefix (void)
3114 unsigned int register_specifier
;
3115 unsigned int implied_prefix
;
3117 rex_byte vrex_used
= 0;
3119 /* Check register specifier. */
3120 if (i
.vex
.register_specifier
)
3122 gas_assert ((i
.vrex
& REX_X
) == 0);
3124 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3125 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3126 register_specifier
+= 8;
3127 /* The upper 16 registers are encoded in the fourth byte of the
3129 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3130 i
.vex
.bytes
[3] = 0x8;
3131 register_specifier
= ~register_specifier
& 0xf;
3135 register_specifier
= 0xf;
3137 /* Encode upper 16 vector index register in the fourth byte of
3139 if (!(i
.vrex
& REX_X
))
3140 i
.vex
.bytes
[3] = 0x8;
3145 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3150 case DATA_PREFIX_OPCODE
:
3153 case REPE_PREFIX_OPCODE
:
3156 case REPNE_PREFIX_OPCODE
:
3163 /* 4 byte EVEX prefix. */
3165 i
.vex
.bytes
[0] = 0x62;
3168 switch (i
.tm
.opcode_modifier
.vexopcode
)
3184 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3186 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3188 /* The fifth bit of the second EVEX byte is 1's compliment of the
3189 REX_R bit in VREX. */
3190 if (!(i
.vrex
& REX_R
))
3191 i
.vex
.bytes
[1] |= 0x10;
3195 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3197 /* When all operands are registers, the REX_X bit in REX is not
3198 used. We reuse it to encode the upper 16 registers, which is
3199 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3200 as 1's compliment. */
3201 if ((i
.vrex
& REX_B
))
3204 i
.vex
.bytes
[1] &= ~0x40;
3208 /* EVEX instructions shouldn't need the REX prefix. */
3209 i
.vrex
&= ~vrex_used
;
3210 gas_assert (i
.vrex
== 0);
3212 /* Check the REX.W bit. */
3213 w
= (i
.rex
& REX_W
) ? 1 : 0;
3214 if (i
.tm
.opcode_modifier
.vexw
)
3216 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3219 /* If w is not set it means we are dealing with WIG instruction. */
3222 if (evexwig
== evexw1
)
3226 /* Encode the U bit. */
3227 implied_prefix
|= 0x4;
3229 /* The third byte of the EVEX prefix. */
3230 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3232 /* The fourth byte of the EVEX prefix. */
3233 /* The zeroing-masking bit. */
3234 if (i
.mask
&& i
.mask
->zeroing
)
3235 i
.vex
.bytes
[3] |= 0x80;
3237 /* Don't always set the broadcast bit if there is no RC. */
3240 /* Encode the vector length. */
3241 unsigned int vec_length
;
3243 switch (i
.tm
.opcode_modifier
.evex
)
3245 case EVEXLIG
: /* LL' is ignored */
3246 vec_length
= evexlig
<< 5;
3249 vec_length
= 0 << 5;
3252 vec_length
= 1 << 5;
3255 vec_length
= 2 << 5;
3261 i
.vex
.bytes
[3] |= vec_length
;
3262 /* Encode the broadcast bit. */
3264 i
.vex
.bytes
[3] |= 0x10;
3268 if (i
.rounding
->type
!= saeonly
)
3269 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3271 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3274 if (i
.mask
&& i
.mask
->mask
)
3275 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3279 process_immext (void)
3283 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3286 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3287 with an opcode suffix which is coded in the same place as an
3288 8-bit immediate field would be.
3289 Here we check those operands and remove them afterwards. */
3292 for (x
= 0; x
< i
.operands
; x
++)
3293 if (register_number (i
.op
[x
].regs
) != x
)
3294 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3295 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3301 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3302 which is coded in the same place as an 8-bit immediate field
3303 would be. Here we fake an 8-bit immediate operand from the
3304 opcode suffix stored in tm.extension_opcode.
3306 AVX instructions also use this encoding, for some of
3307 3 argument instructions. */
3309 gas_assert (i
.imm_operands
<= 1
3311 || ((i
.tm
.opcode_modifier
.vex
3312 || i
.tm
.opcode_modifier
.evex
)
3313 && i
.operands
<= 4)));
3315 exp
= &im_expressions
[i
.imm_operands
++];
3316 i
.op
[i
.operands
].imms
= exp
;
3317 i
.types
[i
.operands
] = imm8
;
3319 exp
->X_op
= O_constant
;
3320 exp
->X_add_number
= i
.tm
.extension_opcode
;
3321 i
.tm
.extension_opcode
= None
;
3328 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3333 as_bad (_("invalid instruction `%s' after `%s'"),
3334 i
.tm
.name
, i
.hle_prefix
);
3337 if (i
.prefix
[LOCK_PREFIX
])
3339 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3343 case HLEPrefixRelease
:
3344 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3346 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3350 if (i
.mem_operands
== 0
3351 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3353 as_bad (_("memory destination needed for instruction `%s'"
3354 " after `xrelease'"), i
.tm
.name
);
3361 /* This is the guts of the machine-dependent assembler. LINE points to a
3362 machine dependent instruction. This function is supposed to emit
3363 the frags/bytes it assembles to. */
3366 md_assemble (char *line
)
3369 char mnemonic
[MAX_MNEM_SIZE
];
3370 const insn_template
*t
;
3372 /* Initialize globals. */
3373 memset (&i
, '\0', sizeof (i
));
3374 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3375 i
.reloc
[j
] = NO_RELOC
;
3376 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3377 memset (im_expressions
, '\0', sizeof (im_expressions
));
3378 save_stack_p
= save_stack
;
3380 /* First parse an instruction mnemonic & call i386_operand for the operands.
3381 We assume that the scrubber has arranged it so that line[0] is the valid
3382 start of a (possibly prefixed) mnemonic. */
3384 line
= parse_insn (line
, mnemonic
);
3388 line
= parse_operands (line
, mnemonic
);
3393 /* Now we've parsed the mnemonic into a set of templates, and have the
3394 operands at hand. */
3396 /* All intel opcodes have reversed operands except for "bound" and
3397 "enter". We also don't reverse intersegment "jmp" and "call"
3398 instructions with 2 immediate operands so that the immediate segment
3399 precedes the offset, as it does when in AT&T mode. */
3402 && (strcmp (mnemonic
, "bound") != 0)
3403 && (strcmp (mnemonic
, "invlpga") != 0)
3404 && !(operand_type_check (i
.types
[0], imm
)
3405 && operand_type_check (i
.types
[1], imm
)))
3408 /* The order of the immediates should be reversed
3409 for 2 immediates extrq and insertq instructions */
3410 if (i
.imm_operands
== 2
3411 && (strcmp (mnemonic
, "extrq") == 0
3412 || strcmp (mnemonic
, "insertq") == 0))
3413 swap_2_operands (0, 1);
3418 /* Don't optimize displacement for movabs since it only takes 64bit
3421 && i
.disp_encoding
!= disp_encoding_32bit
3422 && (flag_code
!= CODE_64BIT
3423 || strcmp (mnemonic
, "movabs") != 0))
3426 /* Next, we find a template that matches the given insn,
3427 making sure the overlap of the given operands types is consistent
3428 with the template operand types. */
3430 if (!(t
= match_template ()))
3433 if (sse_check
!= check_none
3434 && !i
.tm
.opcode_modifier
.noavx
3435 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3436 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3437 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3438 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3439 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3440 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3442 (sse_check
== check_warning
3444 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3447 /* Zap movzx and movsx suffix. The suffix has been set from
3448 "word ptr" or "byte ptr" on the source operand in Intel syntax
3449 or extracted from mnemonic in AT&T syntax. But we'll use
3450 the destination register to choose the suffix for encoding. */
3451 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3453 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3454 there is no suffix, the default will be byte extension. */
3455 if (i
.reg_operands
!= 2
3458 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3463 if (i
.tm
.opcode_modifier
.fwait
)
3464 if (!add_prefix (FWAIT_OPCODE
))
3467 /* Check if REP prefix is OK. */
3468 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3470 as_bad (_("invalid instruction `%s' after `%s'"),
3471 i
.tm
.name
, i
.rep_prefix
);
3475 /* Check for lock without a lockable instruction. Destination operand
3476 must be memory unless it is xchg (0x86). */
3477 if (i
.prefix
[LOCK_PREFIX
]
3478 && (!i
.tm
.opcode_modifier
.islockable
3479 || i
.mem_operands
== 0
3480 || (i
.tm
.base_opcode
!= 0x86
3481 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3483 as_bad (_("expecting lockable instruction after `lock'"));
3487 /* Check if HLE prefix is OK. */
3488 if (i
.hle_prefix
&& !check_hle ())
3491 /* Check BND prefix. */
3492 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3493 as_bad (_("expecting valid branch instruction after `bnd'"));
3495 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3496 && flag_code
== CODE_64BIT
3497 && i
.prefix
[ADDR_PREFIX
])
3498 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3500 /* Insert BND prefix. */
3502 && i
.tm
.opcode_modifier
.bndprefixok
3503 && !i
.prefix
[BND_PREFIX
])
3504 add_prefix (BND_PREFIX_OPCODE
);
3506 /* Check string instruction segment overrides. */
3507 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3509 if (!check_string ())
3511 i
.disp_operands
= 0;
3514 if (!process_suffix ())
3517 /* Update operand types. */
3518 for (j
= 0; j
< i
.operands
; j
++)
3519 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3521 /* Make still unresolved immediate matches conform to size of immediate
3522 given in i.suffix. */
3523 if (!finalize_imm ())
3526 if (i
.types
[0].bitfield
.imm1
)
3527 i
.imm_operands
= 0; /* kludge for shift insns. */
3529 /* We only need to check those implicit registers for instructions
3530 with 3 operands or less. */
3531 if (i
.operands
<= 3)
3532 for (j
= 0; j
< i
.operands
; j
++)
3533 if (i
.types
[j
].bitfield
.inoutportreg
3534 || i
.types
[j
].bitfield
.shiftcount
3535 || i
.types
[j
].bitfield
.acc
3536 || i
.types
[j
].bitfield
.floatacc
)
3539 /* ImmExt should be processed after SSE2AVX. */
3540 if (!i
.tm
.opcode_modifier
.sse2avx
3541 && i
.tm
.opcode_modifier
.immext
)
3544 /* For insns with operands there are more diddles to do to the opcode. */
3547 if (!process_operands ())
3550 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3552 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3553 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3556 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3558 if (flag_code
== CODE_16BIT
)
3560 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3565 if (i
.tm
.opcode_modifier
.vex
)
3566 build_vex_prefix (t
);
3568 build_evex_prefix ();
3571 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3572 instructions may define INT_OPCODE as well, so avoid this corner
3573 case for those instructions that use MODRM. */
3574 if (i
.tm
.base_opcode
== INT_OPCODE
3575 && !i
.tm
.opcode_modifier
.modrm
3576 && i
.op
[0].imms
->X_add_number
== 3)
3578 i
.tm
.base_opcode
= INT3_OPCODE
;
3582 if ((i
.tm
.opcode_modifier
.jump
3583 || i
.tm
.opcode_modifier
.jumpbyte
3584 || i
.tm
.opcode_modifier
.jumpdword
)
3585 && i
.op
[0].disps
->X_op
== O_constant
)
3587 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3588 the absolute address given by the constant. Since ix86 jumps and
3589 calls are pc relative, we need to generate a reloc. */
3590 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3591 i
.op
[0].disps
->X_op
= O_symbol
;
3594 if (i
.tm
.opcode_modifier
.rex64
)
3597 /* For 8 bit registers we need an empty rex prefix. Also if the
3598 instruction already has a prefix, we need to convert old
3599 registers to new ones. */
3601 if ((i
.types
[0].bitfield
.reg8
3602 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3603 || (i
.types
[1].bitfield
.reg8
3604 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3605 || ((i
.types
[0].bitfield
.reg8
3606 || i
.types
[1].bitfield
.reg8
)
3611 i
.rex
|= REX_OPCODE
;
3612 for (x
= 0; x
< 2; x
++)
3614 /* Look for 8 bit operand that uses old registers. */
3615 if (i
.types
[x
].bitfield
.reg8
3616 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3618 /* In case it is "hi" register, give up. */
3619 if (i
.op
[x
].regs
->reg_num
> 3)
3620 as_bad (_("can't encode register '%s%s' in an "
3621 "instruction requiring REX prefix."),
3622 register_prefix
, i
.op
[x
].regs
->reg_name
);
3624 /* Otherwise it is equivalent to the extended register.
3625 Since the encoding doesn't change this is merely
3626 cosmetic cleanup for debug output. */
3628 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3634 add_prefix (REX_OPCODE
| i
.rex
);
3636 /* We are ready to output the insn. */
3641 parse_insn (char *line
, char *mnemonic
)
3644 char *token_start
= l
;
3647 const insn_template
*t
;
3653 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3658 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3660 as_bad (_("no such instruction: `%s'"), token_start
);
3665 if (!is_space_char (*l
)
3666 && *l
!= END_OF_INSN
3668 || (*l
!= PREFIX_SEPARATOR
3671 as_bad (_("invalid character %s in mnemonic"),
3672 output_invalid (*l
));
3675 if (token_start
== l
)
3677 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3678 as_bad (_("expecting prefix; got nothing"));
3680 as_bad (_("expecting mnemonic; got nothing"));
3684 /* Look up instruction (or prefix) via hash table. */
3685 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3687 if (*l
!= END_OF_INSN
3688 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3689 && current_templates
3690 && current_templates
->start
->opcode_modifier
.isprefix
)
3692 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3694 as_bad ((flag_code
!= CODE_64BIT
3695 ? _("`%s' is only supported in 64-bit mode")
3696 : _("`%s' is not supported in 64-bit mode")),
3697 current_templates
->start
->name
);
3700 /* If we are in 16-bit mode, do not allow addr16 or data16.
3701 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3702 if ((current_templates
->start
->opcode_modifier
.size16
3703 || current_templates
->start
->opcode_modifier
.size32
)
3704 && flag_code
!= CODE_64BIT
3705 && (current_templates
->start
->opcode_modifier
.size32
3706 ^ (flag_code
== CODE_16BIT
)))
3708 as_bad (_("redundant %s prefix"),
3709 current_templates
->start
->name
);
3712 /* Add prefix, checking for repeated prefixes. */
3713 switch (add_prefix (current_templates
->start
->base_opcode
))
3718 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3719 i
.hle_prefix
= current_templates
->start
->name
;
3720 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3721 i
.bnd_prefix
= current_templates
->start
->name
;
3723 i
.rep_prefix
= current_templates
->start
->name
;
3728 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3735 if (!current_templates
)
3737 /* Check if we should swap operand or force 32bit displacement in
3739 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3741 else if (mnem_p
- 3 == dot_p
3744 i
.disp_encoding
= disp_encoding_8bit
;
3745 else if (mnem_p
- 4 == dot_p
3749 i
.disp_encoding
= disp_encoding_32bit
;
3754 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3757 if (!current_templates
)
3760 /* See if we can get a match by trimming off a suffix. */
3763 case WORD_MNEM_SUFFIX
:
3764 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3765 i
.suffix
= SHORT_MNEM_SUFFIX
;
3767 case BYTE_MNEM_SUFFIX
:
3768 case QWORD_MNEM_SUFFIX
:
3769 i
.suffix
= mnem_p
[-1];
3771 current_templates
= (const templates
*) hash_find (op_hash
,
3774 case SHORT_MNEM_SUFFIX
:
3775 case LONG_MNEM_SUFFIX
:
3778 i
.suffix
= mnem_p
[-1];
3780 current_templates
= (const templates
*) hash_find (op_hash
,
3789 if (intel_float_operand (mnemonic
) == 1)
3790 i
.suffix
= SHORT_MNEM_SUFFIX
;
3792 i
.suffix
= LONG_MNEM_SUFFIX
;
3794 current_templates
= (const templates
*) hash_find (op_hash
,
3799 if (!current_templates
)
3801 as_bad (_("no such instruction: `%s'"), token_start
);
3806 if (current_templates
->start
->opcode_modifier
.jump
3807 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3809 /* Check for a branch hint. We allow ",pt" and ",pn" for
3810 predict taken and predict not taken respectively.
3811 I'm not sure that branch hints actually do anything on loop
3812 and jcxz insns (JumpByte) for current Pentium4 chips. They
3813 may work in the future and it doesn't hurt to accept them
3815 if (l
[0] == ',' && l
[1] == 'p')
3819 if (!add_prefix (DS_PREFIX_OPCODE
))
3823 else if (l
[2] == 'n')
3825 if (!add_prefix (CS_PREFIX_OPCODE
))
3831 /* Any other comma loses. */
3834 as_bad (_("invalid character %s in mnemonic"),
3835 output_invalid (*l
));
3839 /* Check if instruction is supported on specified architecture. */
3841 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3843 supported
|= cpu_flags_match (t
);
3844 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3848 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3850 as_bad (flag_code
== CODE_64BIT
3851 ? _("`%s' is not supported in 64-bit mode")
3852 : _("`%s' is only supported in 64-bit mode"),
3853 current_templates
->start
->name
);
3856 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3858 as_bad (_("`%s' is not supported on `%s%s'"),
3859 current_templates
->start
->name
,
3860 cpu_arch_name
? cpu_arch_name
: default_arch
,
3861 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3866 if (!cpu_arch_flags
.bitfield
.cpui386
3867 && (flag_code
!= CODE_16BIT
))
3869 as_warn (_("use .code16 to ensure correct addressing mode"));
3876 parse_operands (char *l
, const char *mnemonic
)
3880 /* 1 if operand is pending after ','. */
3881 unsigned int expecting_operand
= 0;
3883 /* Non-zero if operand parens not balanced. */
3884 unsigned int paren_not_balanced
;
3886 while (*l
!= END_OF_INSN
)
3888 /* Skip optional white space before operand. */
3889 if (is_space_char (*l
))
3891 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3893 as_bad (_("invalid character %s before operand %d"),
3894 output_invalid (*l
),
3898 token_start
= l
; /* after white space */
3899 paren_not_balanced
= 0;
3900 while (paren_not_balanced
|| *l
!= ',')
3902 if (*l
== END_OF_INSN
)
3904 if (paren_not_balanced
)
3907 as_bad (_("unbalanced parenthesis in operand %d."),
3910 as_bad (_("unbalanced brackets in operand %d."),
3915 break; /* we are done */
3917 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3919 as_bad (_("invalid character %s in operand %d"),
3920 output_invalid (*l
),
3927 ++paren_not_balanced
;
3929 --paren_not_balanced
;
3934 ++paren_not_balanced
;
3936 --paren_not_balanced
;
3940 if (l
!= token_start
)
3941 { /* Yes, we've read in another operand. */
3942 unsigned int operand_ok
;
3943 this_operand
= i
.operands
++;
3944 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3945 if (i
.operands
> MAX_OPERANDS
)
3947 as_bad (_("spurious operands; (%d operands/instruction max)"),
3951 /* Now parse operand adding info to 'i' as we go along. */
3952 END_STRING_AND_SAVE (l
);
3956 i386_intel_operand (token_start
,
3957 intel_float_operand (mnemonic
));
3959 operand_ok
= i386_att_operand (token_start
);
3961 RESTORE_END_STRING (l
);
3967 if (expecting_operand
)
3969 expecting_operand_after_comma
:
3970 as_bad (_("expecting operand after ','; got nothing"));
3975 as_bad (_("expecting operand before ','; got nothing"));
3980 /* Now *l must be either ',' or END_OF_INSN. */
3983 if (*++l
== END_OF_INSN
)
3985 /* Just skip it, if it's \n complain. */
3986 goto expecting_operand_after_comma
;
3988 expecting_operand
= 1;
3995 swap_2_operands (int xchg1
, int xchg2
)
3997 union i386_op temp_op
;
3998 i386_operand_type temp_type
;
3999 enum bfd_reloc_code_real temp_reloc
;
4001 temp_type
= i
.types
[xchg2
];
4002 i
.types
[xchg2
] = i
.types
[xchg1
];
4003 i
.types
[xchg1
] = temp_type
;
4004 temp_op
= i
.op
[xchg2
];
4005 i
.op
[xchg2
] = i
.op
[xchg1
];
4006 i
.op
[xchg1
] = temp_op
;
4007 temp_reloc
= i
.reloc
[xchg2
];
4008 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4009 i
.reloc
[xchg1
] = temp_reloc
;
4013 if (i
.mask
->operand
== xchg1
)
4014 i
.mask
->operand
= xchg2
;
4015 else if (i
.mask
->operand
== xchg2
)
4016 i
.mask
->operand
= xchg1
;
4020 if (i
.broadcast
->operand
== xchg1
)
4021 i
.broadcast
->operand
= xchg2
;
4022 else if (i
.broadcast
->operand
== xchg2
)
4023 i
.broadcast
->operand
= xchg1
;
4027 if (i
.rounding
->operand
== xchg1
)
4028 i
.rounding
->operand
= xchg2
;
4029 else if (i
.rounding
->operand
== xchg2
)
4030 i
.rounding
->operand
= xchg1
;
4035 swap_operands (void)
4041 swap_2_operands (1, i
.operands
- 2);
4044 swap_2_operands (0, i
.operands
- 1);
4050 if (i
.mem_operands
== 2)
4052 const seg_entry
*temp_seg
;
4053 temp_seg
= i
.seg
[0];
4054 i
.seg
[0] = i
.seg
[1];
4055 i
.seg
[1] = temp_seg
;
4059 /* Try to ensure constant immediates are represented in the smallest
4064 char guess_suffix
= 0;
4068 guess_suffix
= i
.suffix
;
4069 else if (i
.reg_operands
)
4071 /* Figure out a suffix from the last register operand specified.
4072 We can't do this properly yet, ie. excluding InOutPortReg,
4073 but the following works for instructions with immediates.
4074 In any case, we can't set i.suffix yet. */
4075 for (op
= i
.operands
; --op
>= 0;)
4076 if (i
.types
[op
].bitfield
.reg8
)
4078 guess_suffix
= BYTE_MNEM_SUFFIX
;
4081 else if (i
.types
[op
].bitfield
.reg16
)
4083 guess_suffix
= WORD_MNEM_SUFFIX
;
4086 else if (i
.types
[op
].bitfield
.reg32
)
4088 guess_suffix
= LONG_MNEM_SUFFIX
;
4091 else if (i
.types
[op
].bitfield
.reg64
)
4093 guess_suffix
= QWORD_MNEM_SUFFIX
;
4097 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4098 guess_suffix
= WORD_MNEM_SUFFIX
;
4100 for (op
= i
.operands
; --op
>= 0;)
4101 if (operand_type_check (i
.types
[op
], imm
))
4103 switch (i
.op
[op
].imms
->X_op
)
4106 /* If a suffix is given, this operand may be shortened. */
4107 switch (guess_suffix
)
4109 case LONG_MNEM_SUFFIX
:
4110 i
.types
[op
].bitfield
.imm32
= 1;
4111 i
.types
[op
].bitfield
.imm64
= 1;
4113 case WORD_MNEM_SUFFIX
:
4114 i
.types
[op
].bitfield
.imm16
= 1;
4115 i
.types
[op
].bitfield
.imm32
= 1;
4116 i
.types
[op
].bitfield
.imm32s
= 1;
4117 i
.types
[op
].bitfield
.imm64
= 1;
4119 case BYTE_MNEM_SUFFIX
:
4120 i
.types
[op
].bitfield
.imm8
= 1;
4121 i
.types
[op
].bitfield
.imm8s
= 1;
4122 i
.types
[op
].bitfield
.imm16
= 1;
4123 i
.types
[op
].bitfield
.imm32
= 1;
4124 i
.types
[op
].bitfield
.imm32s
= 1;
4125 i
.types
[op
].bitfield
.imm64
= 1;
4129 /* If this operand is at most 16 bits, convert it
4130 to a signed 16 bit number before trying to see
4131 whether it will fit in an even smaller size.
4132 This allows a 16-bit operand such as $0xffe0 to
4133 be recognised as within Imm8S range. */
4134 if ((i
.types
[op
].bitfield
.imm16
)
4135 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4137 i
.op
[op
].imms
->X_add_number
=
4138 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4140 if ((i
.types
[op
].bitfield
.imm32
)
4141 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4144 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4145 ^ ((offsetT
) 1 << 31))
4146 - ((offsetT
) 1 << 31));
4149 = operand_type_or (i
.types
[op
],
4150 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4152 /* We must avoid matching of Imm32 templates when 64bit
4153 only immediate is available. */
4154 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4155 i
.types
[op
].bitfield
.imm32
= 0;
4162 /* Symbols and expressions. */
4164 /* Convert symbolic operand to proper sizes for matching, but don't
4165 prevent matching a set of insns that only supports sizes other
4166 than those matching the insn suffix. */
4168 i386_operand_type mask
, allowed
;
4169 const insn_template
*t
;
4171 operand_type_set (&mask
, 0);
4172 operand_type_set (&allowed
, 0);
4174 for (t
= current_templates
->start
;
4175 t
< current_templates
->end
;
4177 allowed
= operand_type_or (allowed
,
4178 t
->operand_types
[op
]);
4179 switch (guess_suffix
)
4181 case QWORD_MNEM_SUFFIX
:
4182 mask
.bitfield
.imm64
= 1;
4183 mask
.bitfield
.imm32s
= 1;
4185 case LONG_MNEM_SUFFIX
:
4186 mask
.bitfield
.imm32
= 1;
4188 case WORD_MNEM_SUFFIX
:
4189 mask
.bitfield
.imm16
= 1;
4191 case BYTE_MNEM_SUFFIX
:
4192 mask
.bitfield
.imm8
= 1;
4197 allowed
= operand_type_and (mask
, allowed
);
4198 if (!operand_type_all_zero (&allowed
))
4199 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4206 /* Try to use the smallest displacement type too. */
4208 optimize_disp (void)
4212 for (op
= i
.operands
; --op
>= 0;)
4213 if (operand_type_check (i
.types
[op
], disp
))
4215 if (i
.op
[op
].disps
->X_op
== O_constant
)
4217 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4219 if (i
.types
[op
].bitfield
.disp16
4220 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4222 /* If this operand is at most 16 bits, convert
4223 to a signed 16 bit number and don't use 64bit
4225 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4226 i
.types
[op
].bitfield
.disp64
= 0;
4228 if (i
.types
[op
].bitfield
.disp32
4229 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4231 /* If this operand is at most 32 bits, convert
4232 to a signed 32 bit number and don't use 64bit
4234 op_disp
&= (((offsetT
) 2 << 31) - 1);
4235 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4236 i
.types
[op
].bitfield
.disp64
= 0;
4238 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4240 i
.types
[op
].bitfield
.disp8
= 0;
4241 i
.types
[op
].bitfield
.disp16
= 0;
4242 i
.types
[op
].bitfield
.disp32
= 0;
4243 i
.types
[op
].bitfield
.disp32s
= 0;
4244 i
.types
[op
].bitfield
.disp64
= 0;
4248 else if (flag_code
== CODE_64BIT
)
4250 if (fits_in_signed_long (op_disp
))
4252 i
.types
[op
].bitfield
.disp64
= 0;
4253 i
.types
[op
].bitfield
.disp32s
= 1;
4255 if (i
.prefix
[ADDR_PREFIX
]
4256 && fits_in_unsigned_long (op_disp
))
4257 i
.types
[op
].bitfield
.disp32
= 1;
4259 if ((i
.types
[op
].bitfield
.disp32
4260 || i
.types
[op
].bitfield
.disp32s
4261 || i
.types
[op
].bitfield
.disp16
)
4262 && fits_in_signed_byte (op_disp
))
4263 i
.types
[op
].bitfield
.disp8
= 1;
4265 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4266 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4268 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4269 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4270 i
.types
[op
].bitfield
.disp8
= 0;
4271 i
.types
[op
].bitfield
.disp16
= 0;
4272 i
.types
[op
].bitfield
.disp32
= 0;
4273 i
.types
[op
].bitfield
.disp32s
= 0;
4274 i
.types
[op
].bitfield
.disp64
= 0;
4277 /* We only support 64bit displacement on constants. */
4278 i
.types
[op
].bitfield
.disp64
= 0;
4282 /* Check if operands are valid for the instruction. */
4285 check_VecOperands (const insn_template
*t
)
4289 /* Without VSIB byte, we can't have a vector register for index. */
4290 if (!t
->opcode_modifier
.vecsib
4292 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4293 || i
.index_reg
->reg_type
.bitfield
.regymm
4294 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4296 i
.error
= unsupported_vector_index_register
;
4300 /* Check if default mask is allowed. */
4301 if (t
->opcode_modifier
.nodefmask
4302 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4304 i
.error
= no_default_mask
;
4308 /* For VSIB byte, we need a vector register for index, and all vector
4309 registers must be distinct. */
4310 if (t
->opcode_modifier
.vecsib
)
4313 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4314 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4315 || (t
->opcode_modifier
.vecsib
== VecSIB256
4316 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4317 || (t
->opcode_modifier
.vecsib
== VecSIB512
4318 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4320 i
.error
= invalid_vsib_address
;
4324 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4325 if (i
.reg_operands
== 2 && !i
.mask
)
4327 gas_assert (i
.types
[0].bitfield
.regxmm
4328 || i
.types
[0].bitfield
.regymm
);
4329 gas_assert (i
.types
[2].bitfield
.regxmm
4330 || i
.types
[2].bitfield
.regymm
);
4331 if (operand_check
== check_none
)
4333 if (register_number (i
.op
[0].regs
)
4334 != register_number (i
.index_reg
)
4335 && register_number (i
.op
[2].regs
)
4336 != register_number (i
.index_reg
)
4337 && register_number (i
.op
[0].regs
)
4338 != register_number (i
.op
[2].regs
))
4340 if (operand_check
== check_error
)
4342 i
.error
= invalid_vector_register_set
;
4345 as_warn (_("mask, index, and destination registers should be distinct"));
4347 else if (i
.reg_operands
== 1 && i
.mask
)
4349 if ((i
.types
[1].bitfield
.regymm
4350 || i
.types
[1].bitfield
.regzmm
)
4351 && (register_number (i
.op
[1].regs
)
4352 == register_number (i
.index_reg
)))
4354 if (operand_check
== check_error
)
4356 i
.error
= invalid_vector_register_set
;
4359 if (operand_check
!= check_none
)
4360 as_warn (_("index and destination registers should be distinct"));
4365 /* Check if broadcast is supported by the instruction and is applied
4366 to the memory operand. */
4369 int broadcasted_opnd_size
;
4371 /* Check if specified broadcast is supported in this instruction,
4372 and it's applied to memory operand of DWORD or QWORD type,
4373 depending on VecESize. */
4374 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4375 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4376 || (t
->opcode_modifier
.vecesize
== 0
4377 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4378 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4379 || (t
->opcode_modifier
.vecesize
== 1
4380 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4381 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4384 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4385 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4386 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4387 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4388 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4389 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4390 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4391 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4392 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4396 if ((broadcasted_opnd_size
== 256
4397 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4398 || (broadcasted_opnd_size
== 512
4399 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4402 i
.error
= unsupported_broadcast
;
4406 /* If broadcast is supported in this instruction, we need to check if
4407 operand of one-element size isn't specified without broadcast. */
4408 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4410 /* Find memory operand. */
4411 for (op
= 0; op
< i
.operands
; op
++)
4412 if (operand_type_check (i
.types
[op
], anymem
))
4414 gas_assert (op
< i
.operands
);
4415 /* Check size of the memory operand. */
4416 if ((t
->opcode_modifier
.vecesize
== 0
4417 && i
.types
[op
].bitfield
.dword
)
4418 || (t
->opcode_modifier
.vecesize
== 1
4419 && i
.types
[op
].bitfield
.qword
))
4421 i
.error
= broadcast_needed
;
4426 /* Check if requested masking is supported. */
4428 && (!t
->opcode_modifier
.masking
4430 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4432 i
.error
= unsupported_masking
;
4436 /* Check if masking is applied to dest operand. */
4437 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4439 i
.error
= mask_not_on_destination
;
4446 if ((i
.rounding
->type
!= saeonly
4447 && !t
->opcode_modifier
.staticrounding
)
4448 || (i
.rounding
->type
== saeonly
4449 && (t
->opcode_modifier
.staticrounding
4450 || !t
->opcode_modifier
.sae
)))
4452 i
.error
= unsupported_rc_sae
;
4455 /* If the instruction has several immediate operands and one of
4456 them is rounding, the rounding operand should be the last
4457 immediate operand. */
4458 if (i
.imm_operands
> 1
4459 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4461 i
.error
= rc_sae_operand_not_last_imm
;
4466 /* Check vector Disp8 operand. */
4467 if (t
->opcode_modifier
.disp8memshift
)
4470 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4472 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4474 for (op
= 0; op
< i
.operands
; op
++)
4475 if (operand_type_check (i
.types
[op
], disp
)
4476 && i
.op
[op
].disps
->X_op
== O_constant
)
4478 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4479 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4480 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4483 i
.types
[op
].bitfield
.vec_disp8
= 1;
4486 /* Vector insn can only have Vec_Disp8/Disp32 in
4487 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4489 i
.types
[op
].bitfield
.disp8
= 0;
4490 if (flag_code
!= CODE_16BIT
)
4491 i
.types
[op
].bitfield
.disp16
= 0;
4494 else if (flag_code
!= CODE_16BIT
)
4496 /* One form of this instruction supports vector Disp8.
4497 Try vector Disp8 if we need to use Disp32. */
4498 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4500 i
.error
= try_vector_disp8
;
4512 /* Check if operands are valid for the instruction. Update VEX
4516 VEX_check_operands (const insn_template
*t
)
4518 /* VREX is only valid with EVEX prefix. */
4519 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4521 i
.error
= invalid_register_operand
;
4525 if (!t
->opcode_modifier
.vex
)
4528 /* Only check VEX_Imm4, which must be the first operand. */
4529 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4531 if (i
.op
[0].imms
->X_op
!= O_constant
4532 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4538 /* Turn off Imm8 so that update_imm won't complain. */
4539 i
.types
[0] = vec_imm4
;
4545 static const insn_template
*
4546 match_template (void)
4548 /* Points to template once we've found it. */
4549 const insn_template
*t
;
4550 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4551 i386_operand_type overlap4
;
4552 unsigned int found_reverse_match
;
4553 i386_opcode_modifier suffix_check
;
4554 i386_operand_type operand_types
[MAX_OPERANDS
];
4555 int addr_prefix_disp
;
4557 unsigned int found_cpu_match
;
4558 unsigned int check_register
;
4559 enum i386_error specific_error
= 0;
4561 #if MAX_OPERANDS != 5
4562 # error "MAX_OPERANDS must be 5."
4565 found_reverse_match
= 0;
4566 addr_prefix_disp
= -1;
4568 memset (&suffix_check
, 0, sizeof (suffix_check
));
4569 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4570 suffix_check
.no_bsuf
= 1;
4571 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4572 suffix_check
.no_wsuf
= 1;
4573 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4574 suffix_check
.no_ssuf
= 1;
4575 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4576 suffix_check
.no_lsuf
= 1;
4577 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4578 suffix_check
.no_qsuf
= 1;
4579 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4580 suffix_check
.no_ldsuf
= 1;
4582 /* Must have right number of operands. */
4583 i
.error
= number_of_operands_mismatch
;
4585 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4587 addr_prefix_disp
= -1;
4589 if (i
.operands
!= t
->operands
)
4592 /* Check processor support. */
4593 i
.error
= unsupported
;
4594 found_cpu_match
= (cpu_flags_match (t
)
4595 == CPU_FLAGS_PERFECT_MATCH
);
4596 if (!found_cpu_match
)
4599 /* Check old gcc support. */
4600 i
.error
= old_gcc_only
;
4601 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4604 /* Check AT&T mnemonic. */
4605 i
.error
= unsupported_with_intel_mnemonic
;
4606 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4609 /* Check AT&T/Intel syntax. */
4610 i
.error
= unsupported_syntax
;
4611 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4612 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4615 /* Check the suffix, except for some instructions in intel mode. */
4616 i
.error
= invalid_instruction_suffix
;
4617 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4618 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4619 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4620 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4621 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4622 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4623 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4626 if (!operand_size_match (t
))
4629 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4630 operand_types
[j
] = t
->operand_types
[j
];
4632 /* In general, don't allow 64-bit operands in 32-bit mode. */
4633 if (i
.suffix
== QWORD_MNEM_SUFFIX
4634 && flag_code
!= CODE_64BIT
4636 ? (!t
->opcode_modifier
.ignoresize
4637 && !intel_float_operand (t
->name
))
4638 : intel_float_operand (t
->name
) != 2)
4639 && ((!operand_types
[0].bitfield
.regmmx
4640 && !operand_types
[0].bitfield
.regxmm
4641 && !operand_types
[0].bitfield
.regymm
4642 && !operand_types
[0].bitfield
.regzmm
)
4643 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4644 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4645 && operand_types
[t
->operands
> 1].bitfield
.regymm
4646 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4647 && (t
->base_opcode
!= 0x0fc7
4648 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4651 /* In general, don't allow 32-bit operands on pre-386. */
4652 else if (i
.suffix
== LONG_MNEM_SUFFIX
4653 && !cpu_arch_flags
.bitfield
.cpui386
4655 ? (!t
->opcode_modifier
.ignoresize
4656 && !intel_float_operand (t
->name
))
4657 : intel_float_operand (t
->name
) != 2)
4658 && ((!operand_types
[0].bitfield
.regmmx
4659 && !operand_types
[0].bitfield
.regxmm
)
4660 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4661 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4664 /* Do not verify operands when there are none. */
4668 /* We've found a match; break out of loop. */
4672 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4673 into Disp32/Disp16/Disp32 operand. */
4674 if (i
.prefix
[ADDR_PREFIX
] != 0)
4676 /* There should be only one Disp operand. */
4680 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4682 if (operand_types
[j
].bitfield
.disp16
)
4684 addr_prefix_disp
= j
;
4685 operand_types
[j
].bitfield
.disp32
= 1;
4686 operand_types
[j
].bitfield
.disp16
= 0;
4692 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4694 if (operand_types
[j
].bitfield
.disp32
)
4696 addr_prefix_disp
= j
;
4697 operand_types
[j
].bitfield
.disp32
= 0;
4698 operand_types
[j
].bitfield
.disp16
= 1;
4704 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4706 if (operand_types
[j
].bitfield
.disp64
)
4708 addr_prefix_disp
= j
;
4709 operand_types
[j
].bitfield
.disp64
= 0;
4710 operand_types
[j
].bitfield
.disp32
= 1;
4718 /* We check register size if needed. */
4719 check_register
= t
->opcode_modifier
.checkregsize
;
4720 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4721 switch (t
->operands
)
4724 if (!operand_type_match (overlap0
, i
.types
[0]))
4728 /* xchg %eax, %eax is a special case. It is an aliase for nop
4729 only in 32bit mode and we can use opcode 0x90. In 64bit
4730 mode, we can't use 0x90 for xchg %eax, %eax since it should
4731 zero-extend %eax to %rax. */
4732 if (flag_code
== CODE_64BIT
4733 && t
->base_opcode
== 0x90
4734 && operand_type_equal (&i
.types
[0], &acc32
)
4735 && operand_type_equal (&i
.types
[1], &acc32
))
4739 /* If we swap operand in encoding, we either match
4740 the next one or reverse direction of operands. */
4741 if (t
->opcode_modifier
.s
)
4743 else if (t
->opcode_modifier
.d
)
4748 /* If we swap operand in encoding, we match the next one. */
4749 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4753 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4754 if (!operand_type_match (overlap0
, i
.types
[0])
4755 || !operand_type_match (overlap1
, i
.types
[1])
4757 && !operand_type_register_match (overlap0
, i
.types
[0],
4759 overlap1
, i
.types
[1],
4762 /* Check if other direction is valid ... */
4763 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4767 /* Try reversing direction of operands. */
4768 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4769 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4770 if (!operand_type_match (overlap0
, i
.types
[0])
4771 || !operand_type_match (overlap1
, i
.types
[1])
4773 && !operand_type_register_match (overlap0
,
4780 /* Does not match either direction. */
4783 /* found_reverse_match holds which of D or FloatDR
4785 if (t
->opcode_modifier
.d
)
4786 found_reverse_match
= Opcode_D
;
4787 else if (t
->opcode_modifier
.floatd
)
4788 found_reverse_match
= Opcode_FloatD
;
4790 found_reverse_match
= 0;
4791 if (t
->opcode_modifier
.floatr
)
4792 found_reverse_match
|= Opcode_FloatR
;
4796 /* Found a forward 2 operand match here. */
4797 switch (t
->operands
)
4800 overlap4
= operand_type_and (i
.types
[4],
4803 overlap3
= operand_type_and (i
.types
[3],
4806 overlap2
= operand_type_and (i
.types
[2],
4811 switch (t
->operands
)
4814 if (!operand_type_match (overlap4
, i
.types
[4])
4815 || !operand_type_register_match (overlap3
,
4823 if (!operand_type_match (overlap3
, i
.types
[3])
4825 && !operand_type_register_match (overlap2
,
4833 /* Here we make use of the fact that there are no
4834 reverse match 3 operand instructions, and all 3
4835 operand instructions only need to be checked for
4836 register consistency between operands 2 and 3. */
4837 if (!operand_type_match (overlap2
, i
.types
[2])
4839 && !operand_type_register_match (overlap1
,
4849 /* Found either forward/reverse 2, 3 or 4 operand match here:
4850 slip through to break. */
4852 if (!found_cpu_match
)
4854 found_reverse_match
= 0;
4858 /* Check if vector and VEX operands are valid. */
4859 if (check_VecOperands (t
) || VEX_check_operands (t
))
4861 specific_error
= i
.error
;
4865 /* We've found a match; break out of loop. */
4869 if (t
== current_templates
->end
)
4871 /* We found no match. */
4872 const char *err_msg
;
4873 switch (specific_error
? specific_error
: i
.error
)
4877 case operand_size_mismatch
:
4878 err_msg
= _("operand size mismatch");
4880 case operand_type_mismatch
:
4881 err_msg
= _("operand type mismatch");
4883 case register_type_mismatch
:
4884 err_msg
= _("register type mismatch");
4886 case number_of_operands_mismatch
:
4887 err_msg
= _("number of operands mismatch");
4889 case invalid_instruction_suffix
:
4890 err_msg
= _("invalid instruction suffix");
4893 err_msg
= _("constant doesn't fit in 4 bits");
4896 err_msg
= _("only supported with old gcc");
4898 case unsupported_with_intel_mnemonic
:
4899 err_msg
= _("unsupported with Intel mnemonic");
4901 case unsupported_syntax
:
4902 err_msg
= _("unsupported syntax");
4905 as_bad (_("unsupported instruction `%s'"),
4906 current_templates
->start
->name
);
4908 case invalid_vsib_address
:
4909 err_msg
= _("invalid VSIB address");
4911 case invalid_vector_register_set
:
4912 err_msg
= _("mask, index, and destination registers must be distinct");
4914 case unsupported_vector_index_register
:
4915 err_msg
= _("unsupported vector index register");
4917 case unsupported_broadcast
:
4918 err_msg
= _("unsupported broadcast");
4920 case broadcast_not_on_src_operand
:
4921 err_msg
= _("broadcast not on source memory operand");
4923 case broadcast_needed
:
4924 err_msg
= _("broadcast is needed for operand of such type");
4926 case unsupported_masking
:
4927 err_msg
= _("unsupported masking");
4929 case mask_not_on_destination
:
4930 err_msg
= _("mask not on destination operand");
4932 case no_default_mask
:
4933 err_msg
= _("default mask isn't allowed");
4935 case unsupported_rc_sae
:
4936 err_msg
= _("unsupported static rounding/sae");
4938 case rc_sae_operand_not_last_imm
:
4940 err_msg
= _("RC/SAE operand must precede immediate operands");
4942 err_msg
= _("RC/SAE operand must follow immediate operands");
4944 case invalid_register_operand
:
4945 err_msg
= _("invalid register operand");
4948 as_bad (_("%s for `%s'"), err_msg
,
4949 current_templates
->start
->name
);
4953 if (!quiet_warnings
)
4956 && (i
.types
[0].bitfield
.jumpabsolute
4957 != operand_types
[0].bitfield
.jumpabsolute
))
4959 as_warn (_("indirect %s without `*'"), t
->name
);
4962 if (t
->opcode_modifier
.isprefix
4963 && t
->opcode_modifier
.ignoresize
)
4965 /* Warn them that a data or address size prefix doesn't
4966 affect assembly of the next line of code. */
4967 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4971 /* Copy the template we found. */
4974 if (addr_prefix_disp
!= -1)
4975 i
.tm
.operand_types
[addr_prefix_disp
]
4976 = operand_types
[addr_prefix_disp
];
4978 if (found_reverse_match
)
4980 /* If we found a reverse match we must alter the opcode
4981 direction bit. found_reverse_match holds bits to change
4982 (different for int & float insns). */
4984 i
.tm
.base_opcode
^= found_reverse_match
;
4986 i
.tm
.operand_types
[0] = operand_types
[1];
4987 i
.tm
.operand_types
[1] = operand_types
[0];
4996 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4997 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4999 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5001 as_bad (_("`%s' operand %d must use `%ses' segment"),
5007 /* There's only ever one segment override allowed per instruction.
5008 This instruction possibly has a legal segment override on the
5009 second operand, so copy the segment to where non-string
5010 instructions store it, allowing common code. */
5011 i
.seg
[0] = i
.seg
[1];
5013 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5015 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5017 as_bad (_("`%s' operand %d must use `%ses' segment"),
5028 process_suffix (void)
5030 /* If matched instruction specifies an explicit instruction mnemonic
5032 if (i
.tm
.opcode_modifier
.size16
)
5033 i
.suffix
= WORD_MNEM_SUFFIX
;
5034 else if (i
.tm
.opcode_modifier
.size32
)
5035 i
.suffix
= LONG_MNEM_SUFFIX
;
5036 else if (i
.tm
.opcode_modifier
.size64
)
5037 i
.suffix
= QWORD_MNEM_SUFFIX
;
5038 else if (i
.reg_operands
)
5040 /* If there's no instruction mnemonic suffix we try to invent one
5041 based on register operands. */
5044 /* We take i.suffix from the last register operand specified,
5045 Destination register type is more significant than source
5046 register type. crc32 in SSE4.2 prefers source register
5048 if (i
.tm
.base_opcode
== 0xf20f38f1)
5050 if (i
.types
[0].bitfield
.reg16
)
5051 i
.suffix
= WORD_MNEM_SUFFIX
;
5052 else if (i
.types
[0].bitfield
.reg32
)
5053 i
.suffix
= LONG_MNEM_SUFFIX
;
5054 else if (i
.types
[0].bitfield
.reg64
)
5055 i
.suffix
= QWORD_MNEM_SUFFIX
;
5057 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5059 if (i
.types
[0].bitfield
.reg8
)
5060 i
.suffix
= BYTE_MNEM_SUFFIX
;
5067 if (i
.tm
.base_opcode
== 0xf20f38f1
5068 || i
.tm
.base_opcode
== 0xf20f38f0)
5070 /* We have to know the operand size for crc32. */
5071 as_bad (_("ambiguous memory operand size for `%s`"),
5076 for (op
= i
.operands
; --op
>= 0;)
5077 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5079 if (i
.types
[op
].bitfield
.reg8
)
5081 i
.suffix
= BYTE_MNEM_SUFFIX
;
5084 else if (i
.types
[op
].bitfield
.reg16
)
5086 i
.suffix
= WORD_MNEM_SUFFIX
;
5089 else if (i
.types
[op
].bitfield
.reg32
)
5091 i
.suffix
= LONG_MNEM_SUFFIX
;
5094 else if (i
.types
[op
].bitfield
.reg64
)
5096 i
.suffix
= QWORD_MNEM_SUFFIX
;
5102 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5105 && i
.tm
.opcode_modifier
.ignoresize
5106 && i
.tm
.opcode_modifier
.no_bsuf
)
5108 else if (!check_byte_reg ())
5111 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5114 && i
.tm
.opcode_modifier
.ignoresize
5115 && i
.tm
.opcode_modifier
.no_lsuf
)
5117 else if (!check_long_reg ())
5120 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5123 && i
.tm
.opcode_modifier
.ignoresize
5124 && i
.tm
.opcode_modifier
.no_qsuf
)
5126 else if (!check_qword_reg ())
5129 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5132 && i
.tm
.opcode_modifier
.ignoresize
5133 && i
.tm
.opcode_modifier
.no_wsuf
)
5135 else if (!check_word_reg ())
5138 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5139 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5140 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5142 /* Skip if the instruction has x/y/z suffix. match_template
5143 should check if it is a valid suffix. */
5145 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5146 /* Do nothing if the instruction is going to ignore the prefix. */
5151 else if (i
.tm
.opcode_modifier
.defaultsize
5153 /* exclude fldenv/frstor/fsave/fstenv */
5154 && i
.tm
.opcode_modifier
.no_ssuf
)
5156 i
.suffix
= stackop_size
;
5158 else if (intel_syntax
5160 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5161 || i
.tm
.opcode_modifier
.jumpbyte
5162 || i
.tm
.opcode_modifier
.jumpintersegment
5163 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5164 && i
.tm
.extension_opcode
<= 3)))
5169 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5171 i
.suffix
= QWORD_MNEM_SUFFIX
;
5175 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5176 i
.suffix
= LONG_MNEM_SUFFIX
;
5179 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5180 i
.suffix
= WORD_MNEM_SUFFIX
;
5189 if (i
.tm
.opcode_modifier
.w
)
5191 as_bad (_("no instruction mnemonic suffix given and "
5192 "no register operands; can't size instruction"));
5198 unsigned int suffixes
;
5200 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5201 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5203 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5205 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5207 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5209 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5212 /* There are more than suffix matches. */
5213 if (i
.tm
.opcode_modifier
.w
5214 || ((suffixes
& (suffixes
- 1))
5215 && !i
.tm
.opcode_modifier
.defaultsize
5216 && !i
.tm
.opcode_modifier
.ignoresize
))
5218 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5224 /* Change the opcode based on the operand size given by i.suffix;
5225 We don't need to change things for byte insns. */
5228 && i
.suffix
!= BYTE_MNEM_SUFFIX
5229 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5230 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5231 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5233 /* It's not a byte, select word/dword operation. */
5234 if (i
.tm
.opcode_modifier
.w
)
5236 if (i
.tm
.opcode_modifier
.shortform
)
5237 i
.tm
.base_opcode
|= 8;
5239 i
.tm
.base_opcode
|= 1;
5242 /* Now select between word & dword operations via the operand
5243 size prefix, except for instructions that will ignore this
5245 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5247 /* The address size override prefix changes the size of the
5249 if ((flag_code
== CODE_32BIT
5250 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5251 || (flag_code
!= CODE_32BIT
5252 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5253 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5256 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5257 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5258 && !i
.tm
.opcode_modifier
.ignoresize
5259 && !i
.tm
.opcode_modifier
.floatmf
5260 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5261 || (flag_code
== CODE_64BIT
5262 && i
.tm
.opcode_modifier
.jumpbyte
)))
5264 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5266 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5267 prefix
= ADDR_PREFIX_OPCODE
;
5269 if (!add_prefix (prefix
))
5273 /* Set mode64 for an operand. */
5274 if (i
.suffix
== QWORD_MNEM_SUFFIX
5275 && flag_code
== CODE_64BIT
5276 && !i
.tm
.opcode_modifier
.norex64
)
5278 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5279 need rex64. cmpxchg8b is also a special case. */
5280 if (! (i
.operands
== 2
5281 && i
.tm
.base_opcode
== 0x90
5282 && i
.tm
.extension_opcode
== None
5283 && operand_type_equal (&i
.types
[0], &acc64
)
5284 && operand_type_equal (&i
.types
[1], &acc64
))
5285 && ! (i
.operands
== 1
5286 && i
.tm
.base_opcode
== 0xfc7
5287 && i
.tm
.extension_opcode
== 1
5288 && !operand_type_check (i
.types
[0], reg
)
5289 && operand_type_check (i
.types
[0], anymem
)))
5293 /* Size floating point instruction. */
5294 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5295 if (i
.tm
.opcode_modifier
.floatmf
)
5296 i
.tm
.base_opcode
^= 4;
5303 check_byte_reg (void)
5307 for (op
= i
.operands
; --op
>= 0;)
5309 /* If this is an eight bit register, it's OK. If it's the 16 or
5310 32 bit version of an eight bit register, we will just use the
5311 low portion, and that's OK too. */
5312 if (i
.types
[op
].bitfield
.reg8
)
5315 /* I/O port address operands are OK too. */
5316 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5319 /* crc32 doesn't generate this warning. */
5320 if (i
.tm
.base_opcode
== 0xf20f38f0)
5323 if ((i
.types
[op
].bitfield
.reg16
5324 || i
.types
[op
].bitfield
.reg32
5325 || i
.types
[op
].bitfield
.reg64
)
5326 && i
.op
[op
].regs
->reg_num
< 4
5327 /* Prohibit these changes in 64bit mode, since the lowering
5328 would be more complicated. */
5329 && flag_code
!= CODE_64BIT
)
5331 #if REGISTER_WARNINGS
5332 if (!quiet_warnings
)
5333 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5335 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5336 ? REGNAM_AL
- REGNAM_AX
5337 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5339 i
.op
[op
].regs
->reg_name
,
5344 /* Any other register is bad. */
5345 if (i
.types
[op
].bitfield
.reg16
5346 || i
.types
[op
].bitfield
.reg32
5347 || i
.types
[op
].bitfield
.reg64
5348 || i
.types
[op
].bitfield
.regmmx
5349 || i
.types
[op
].bitfield
.regxmm
5350 || i
.types
[op
].bitfield
.regymm
5351 || i
.types
[op
].bitfield
.regzmm
5352 || i
.types
[op
].bitfield
.sreg2
5353 || i
.types
[op
].bitfield
.sreg3
5354 || i
.types
[op
].bitfield
.control
5355 || i
.types
[op
].bitfield
.debug
5356 || i
.types
[op
].bitfield
.test
5357 || i
.types
[op
].bitfield
.floatreg
5358 || i
.types
[op
].bitfield
.floatacc
)
5360 as_bad (_("`%s%s' not allowed with `%s%c'"),
5362 i
.op
[op
].regs
->reg_name
,
5372 check_long_reg (void)
5376 for (op
= i
.operands
; --op
>= 0;)
5377 /* Reject eight bit registers, except where the template requires
5378 them. (eg. movzb) */
5379 if (i
.types
[op
].bitfield
.reg8
5380 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5381 || i
.tm
.operand_types
[op
].bitfield
.reg32
5382 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5384 as_bad (_("`%s%s' not allowed with `%s%c'"),
5386 i
.op
[op
].regs
->reg_name
,
5391 /* Warn if the e prefix on a general reg is missing. */
5392 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5393 && i
.types
[op
].bitfield
.reg16
5394 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5395 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5397 /* Prohibit these changes in the 64bit mode, since the
5398 lowering is more complicated. */
5399 if (flag_code
== CODE_64BIT
)
5401 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5402 register_prefix
, i
.op
[op
].regs
->reg_name
,
5406 #if REGISTER_WARNINGS
5407 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5409 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5410 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5413 /* Warn if the r prefix on a general reg is present. */
5414 else if (i
.types
[op
].bitfield
.reg64
5415 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5416 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5419 && i
.tm
.opcode_modifier
.toqword
5420 && !i
.types
[0].bitfield
.regxmm
)
5422 /* Convert to QWORD. We want REX byte. */
5423 i
.suffix
= QWORD_MNEM_SUFFIX
;
5427 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5428 register_prefix
, i
.op
[op
].regs
->reg_name
,
5437 check_qword_reg (void)
5441 for (op
= i
.operands
; --op
>= 0; )
5442 /* Reject eight bit registers, except where the template requires
5443 them. (eg. movzb) */
5444 if (i
.types
[op
].bitfield
.reg8
5445 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5446 || i
.tm
.operand_types
[op
].bitfield
.reg32
5447 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5449 as_bad (_("`%s%s' not allowed with `%s%c'"),
5451 i
.op
[op
].regs
->reg_name
,
5456 /* Warn if the r prefix on a general reg is missing. */
5457 else if ((i
.types
[op
].bitfield
.reg16
5458 || i
.types
[op
].bitfield
.reg32
)
5459 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5460 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5462 /* Prohibit these changes in the 64bit mode, since the
5463 lowering is more complicated. */
5465 && i
.tm
.opcode_modifier
.todword
5466 && !i
.types
[0].bitfield
.regxmm
)
5468 /* Convert to DWORD. We don't want REX byte. */
5469 i
.suffix
= LONG_MNEM_SUFFIX
;
5473 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5474 register_prefix
, i
.op
[op
].regs
->reg_name
,
5483 check_word_reg (void)
5486 for (op
= i
.operands
; --op
>= 0;)
5487 /* Reject eight bit registers, except where the template requires
5488 them. (eg. movzb) */
5489 if (i
.types
[op
].bitfield
.reg8
5490 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5491 || i
.tm
.operand_types
[op
].bitfield
.reg32
5492 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5494 as_bad (_("`%s%s' not allowed with `%s%c'"),
5496 i
.op
[op
].regs
->reg_name
,
5501 /* Warn if the e or r prefix on a general reg is present. */
5502 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5503 && (i
.types
[op
].bitfield
.reg32
5504 || i
.types
[op
].bitfield
.reg64
)
5505 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5506 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5508 /* Prohibit these changes in the 64bit mode, since the
5509 lowering is more complicated. */
5510 if (flag_code
== CODE_64BIT
)
5512 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5513 register_prefix
, i
.op
[op
].regs
->reg_name
,
5517 #if REGISTER_WARNINGS
5518 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5520 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5521 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5528 update_imm (unsigned int j
)
5530 i386_operand_type overlap
= i
.types
[j
];
5531 if ((overlap
.bitfield
.imm8
5532 || overlap
.bitfield
.imm8s
5533 || overlap
.bitfield
.imm16
5534 || overlap
.bitfield
.imm32
5535 || overlap
.bitfield
.imm32s
5536 || overlap
.bitfield
.imm64
)
5537 && !operand_type_equal (&overlap
, &imm8
)
5538 && !operand_type_equal (&overlap
, &imm8s
)
5539 && !operand_type_equal (&overlap
, &imm16
)
5540 && !operand_type_equal (&overlap
, &imm32
)
5541 && !operand_type_equal (&overlap
, &imm32s
)
5542 && !operand_type_equal (&overlap
, &imm64
))
5546 i386_operand_type temp
;
5548 operand_type_set (&temp
, 0);
5549 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5551 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5552 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5554 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5555 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5556 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5558 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5559 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5562 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5565 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5566 || operand_type_equal (&overlap
, &imm16_32
)
5567 || operand_type_equal (&overlap
, &imm16_32s
))
5569 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5574 if (!operand_type_equal (&overlap
, &imm8
)
5575 && !operand_type_equal (&overlap
, &imm8s
)
5576 && !operand_type_equal (&overlap
, &imm16
)
5577 && !operand_type_equal (&overlap
, &imm32
)
5578 && !operand_type_equal (&overlap
, &imm32s
)
5579 && !operand_type_equal (&overlap
, &imm64
))
5581 as_bad (_("no instruction mnemonic suffix given; "
5582 "can't determine immediate size"));
5586 i
.types
[j
] = overlap
;
5596 /* Update the first 2 immediate operands. */
5597 n
= i
.operands
> 2 ? 2 : i
.operands
;
5600 for (j
= 0; j
< n
; j
++)
5601 if (update_imm (j
) == 0)
5604 /* The 3rd operand can't be immediate operand. */
5605 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5612 bad_implicit_operand (int xmm
)
5614 const char *ireg
= xmm
? "xmm0" : "ymm0";
5617 as_bad (_("the last operand of `%s' must be `%s%s'"),
5618 i
.tm
.name
, register_prefix
, ireg
);
5620 as_bad (_("the first operand of `%s' must be `%s%s'"),
5621 i
.tm
.name
, register_prefix
, ireg
);
5626 process_operands (void)
5628 /* Default segment register this instruction will use for memory
5629 accesses. 0 means unknown. This is only for optimizing out
5630 unnecessary segment overrides. */
5631 const seg_entry
*default_seg
= 0;
5633 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5635 unsigned int dupl
= i
.operands
;
5636 unsigned int dest
= dupl
- 1;
5639 /* The destination must be an xmm register. */
5640 gas_assert (i
.reg_operands
5641 && MAX_OPERANDS
> dupl
5642 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5644 if (i
.tm
.opcode_modifier
.firstxmm0
)
5646 /* The first operand is implicit and must be xmm0. */
5647 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5648 if (register_number (i
.op
[0].regs
) != 0)
5649 return bad_implicit_operand (1);
5651 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5653 /* Keep xmm0 for instructions with VEX prefix and 3
5659 /* We remove the first xmm0 and keep the number of
5660 operands unchanged, which in fact duplicates the
5662 for (j
= 1; j
< i
.operands
; j
++)
5664 i
.op
[j
- 1] = i
.op
[j
];
5665 i
.types
[j
- 1] = i
.types
[j
];
5666 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5670 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5672 gas_assert ((MAX_OPERANDS
- 1) > dupl
5673 && (i
.tm
.opcode_modifier
.vexsources
5676 /* Add the implicit xmm0 for instructions with VEX prefix
5678 for (j
= i
.operands
; j
> 0; j
--)
5680 i
.op
[j
] = i
.op
[j
- 1];
5681 i
.types
[j
] = i
.types
[j
- 1];
5682 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5685 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5686 i
.types
[0] = regxmm
;
5687 i
.tm
.operand_types
[0] = regxmm
;
5690 i
.reg_operands
+= 2;
5695 i
.op
[dupl
] = i
.op
[dest
];
5696 i
.types
[dupl
] = i
.types
[dest
];
5697 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5706 i
.op
[dupl
] = i
.op
[dest
];
5707 i
.types
[dupl
] = i
.types
[dest
];
5708 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5711 if (i
.tm
.opcode_modifier
.immext
)
5714 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5718 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5719 gas_assert (i
.reg_operands
5720 && (operand_type_equal (&i
.types
[0], ®xmm
)
5721 || operand_type_equal (&i
.types
[0], ®ymm
)
5722 || operand_type_equal (&i
.types
[0], ®zmm
)));
5723 if (register_number (i
.op
[0].regs
) != 0)
5724 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5726 for (j
= 1; j
< i
.operands
; j
++)
5728 i
.op
[j
- 1] = i
.op
[j
];
5729 i
.types
[j
- 1] = i
.types
[j
];
5731 /* We need to adjust fields in i.tm since they are used by
5732 build_modrm_byte. */
5733 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5740 else if (i
.tm
.opcode_modifier
.regkludge
)
5742 /* The imul $imm, %reg instruction is converted into
5743 imul $imm, %reg, %reg, and the clr %reg instruction
5744 is converted into xor %reg, %reg. */
5746 unsigned int first_reg_op
;
5748 if (operand_type_check (i
.types
[0], reg
))
5752 /* Pretend we saw the extra register operand. */
5753 gas_assert (i
.reg_operands
== 1
5754 && i
.op
[first_reg_op
+ 1].regs
== 0);
5755 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5756 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5761 if (i
.tm
.opcode_modifier
.shortform
)
5763 if (i
.types
[0].bitfield
.sreg2
5764 || i
.types
[0].bitfield
.sreg3
)
5766 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5767 && i
.op
[0].regs
->reg_num
== 1)
5769 as_bad (_("you can't `pop %scs'"), register_prefix
);
5772 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5773 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5778 /* The register or float register operand is in operand
5782 if (i
.types
[0].bitfield
.floatreg
5783 || operand_type_check (i
.types
[0], reg
))
5787 /* Register goes in low 3 bits of opcode. */
5788 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5789 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5791 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5793 /* Warn about some common errors, but press on regardless.
5794 The first case can be generated by gcc (<= 2.8.1). */
5795 if (i
.operands
== 2)
5797 /* Reversed arguments on faddp, fsubp, etc. */
5798 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5799 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5800 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5804 /* Extraneous `l' suffix on fp insn. */
5805 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5806 register_prefix
, i
.op
[0].regs
->reg_name
);
5811 else if (i
.tm
.opcode_modifier
.modrm
)
5813 /* The opcode is completed (modulo i.tm.extension_opcode which
5814 must be put into the modrm byte). Now, we make the modrm and
5815 index base bytes based on all the info we've collected. */
5817 default_seg
= build_modrm_byte ();
5819 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5823 else if (i
.tm
.opcode_modifier
.isstring
)
5825 /* For the string instructions that allow a segment override
5826 on one of their operands, the default segment is ds. */
5830 if (i
.tm
.base_opcode
== 0x8d /* lea */
5833 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5835 /* If a segment was explicitly specified, and the specified segment
5836 is not the default, use an opcode prefix to select it. If we
5837 never figured out what the default segment is, then default_seg
5838 will be zero at this point, and the specified segment prefix will
5840 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5842 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5848 static const seg_entry
*
5849 build_modrm_byte (void)
5851 const seg_entry
*default_seg
= 0;
5852 unsigned int source
, dest
;
5855 /* The first operand of instructions with VEX prefix and 3 sources
5856 must be VEX_Imm4. */
5857 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5860 unsigned int nds
, reg_slot
;
5863 if (i
.tm
.opcode_modifier
.veximmext
5864 && i
.tm
.opcode_modifier
.immext
)
5866 dest
= i
.operands
- 2;
5867 gas_assert (dest
== 3);
5870 dest
= i
.operands
- 1;
5873 /* There are 2 kinds of instructions:
5874 1. 5 operands: 4 register operands or 3 register operands
5875 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5876 VexW0 or VexW1. The destination must be either XMM, YMM or
5878 2. 4 operands: 4 register operands or 3 register operands
5879 plus 1 memory operand, VexXDS, and VexImmExt */
5880 gas_assert ((i
.reg_operands
== 4
5881 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5882 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5883 && (i
.tm
.opcode_modifier
.veximmext
5884 || (i
.imm_operands
== 1
5885 && i
.types
[0].bitfield
.vec_imm4
5886 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5887 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5888 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5889 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5890 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5892 if (i
.imm_operands
== 0)
5894 /* When there is no immediate operand, generate an 8bit
5895 immediate operand to encode the first operand. */
5896 exp
= &im_expressions
[i
.imm_operands
++];
5897 i
.op
[i
.operands
].imms
= exp
;
5898 i
.types
[i
.operands
] = imm8
;
5900 /* If VexW1 is set, the first operand is the source and
5901 the second operand is encoded in the immediate operand. */
5902 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5913 /* FMA swaps REG and NDS. */
5914 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5922 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5924 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5926 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5928 exp
->X_op
= O_constant
;
5929 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5930 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5934 unsigned int imm_slot
;
5936 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5938 /* If VexW0 is set, the third operand is the source and
5939 the second operand is encoded in the immediate
5946 /* VexW1 is set, the second operand is the source and
5947 the third operand is encoded in the immediate
5953 if (i
.tm
.opcode_modifier
.immext
)
5955 /* When ImmExt is set, the immdiate byte is the last
5957 imm_slot
= i
.operands
- 1;
5965 /* Turn on Imm8 so that output_imm will generate it. */
5966 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5969 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5971 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5973 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5975 i
.op
[imm_slot
].imms
->X_add_number
5976 |= register_number (i
.op
[reg_slot
].regs
) << 4;
5977 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5980 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5981 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5983 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5985 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5990 /* i.reg_operands MUST be the number of real register operands;
5991 implicit registers do not count. If there are 3 register
5992 operands, it must be a instruction with VexNDS. For a
5993 instruction with VexNDD, the destination register is encoded
5994 in VEX prefix. If there are 4 register operands, it must be
5995 a instruction with VEX prefix and 3 sources. */
5996 if (i
.mem_operands
== 0
5997 && ((i
.reg_operands
== 2
5998 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5999 || (i
.reg_operands
== 3
6000 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6001 || (i
.reg_operands
== 4 && vex_3_sources
)))
6009 /* When there are 3 operands, one of them may be immediate,
6010 which may be the first or the last operand. Otherwise,
6011 the first operand must be shift count register (cl) or it
6012 is an instruction with VexNDS. */
6013 gas_assert (i
.imm_operands
== 1
6014 || (i
.imm_operands
== 0
6015 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6016 || i
.types
[0].bitfield
.shiftcount
)));
6017 if (operand_type_check (i
.types
[0], imm
)
6018 || i
.types
[0].bitfield
.shiftcount
)
6024 /* When there are 4 operands, the first two must be 8bit
6025 immediate operands. The source operand will be the 3rd
6028 For instructions with VexNDS, if the first operand
6029 an imm8, the source operand is the 2nd one. If the last
6030 operand is imm8, the source operand is the first one. */
6031 gas_assert ((i
.imm_operands
== 2
6032 && i
.types
[0].bitfield
.imm8
6033 && i
.types
[1].bitfield
.imm8
)
6034 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6035 && i
.imm_operands
== 1
6036 && (i
.types
[0].bitfield
.imm8
6037 || i
.types
[i
.operands
- 1].bitfield
.imm8
6039 if (i
.imm_operands
== 2)
6043 if (i
.types
[0].bitfield
.imm8
)
6050 if (i
.tm
.opcode_modifier
.evex
)
6052 /* For EVEX instructions, when there are 5 operands, the
6053 first one must be immediate operand. If the second one
6054 is immediate operand, the source operand is the 3th
6055 one. If the last one is immediate operand, the source
6056 operand is the 2nd one. */
6057 gas_assert (i
.imm_operands
== 2
6058 && i
.tm
.opcode_modifier
.sae
6059 && operand_type_check (i
.types
[0], imm
));
6060 if (operand_type_check (i
.types
[1], imm
))
6062 else if (operand_type_check (i
.types
[4], imm
))
6076 /* RC/SAE operand could be between DEST and SRC. That happens
6077 when one operand is GPR and the other one is XMM/YMM/ZMM
6079 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6082 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6084 /* For instructions with VexNDS, the register-only source
6085 operand must be 32/64bit integer, XMM, YMM or ZMM
6086 register. It is encoded in VEX prefix. We need to
6087 clear RegMem bit before calling operand_type_equal. */
6089 i386_operand_type op
;
6092 /* Check register-only source operand when two source
6093 operands are swapped. */
6094 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6095 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6103 op
= i
.tm
.operand_types
[vvvv
];
6104 op
.bitfield
.regmem
= 0;
6105 if ((dest
+ 1) >= i
.operands
6106 || (!op
.bitfield
.reg32
6107 && op
.bitfield
.reg64
6108 && !operand_type_equal (&op
, ®xmm
)
6109 && !operand_type_equal (&op
, ®ymm
)
6110 && !operand_type_equal (&op
, ®zmm
)
6111 && !operand_type_equal (&op
, ®mask
)))
6113 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6119 /* One of the register operands will be encoded in the i.tm.reg
6120 field, the other in the combined i.tm.mode and i.tm.regmem
6121 fields. If no form of this instruction supports a memory
6122 destination operand, then we assume the source operand may
6123 sometimes be a memory operand and so we need to store the
6124 destination in the i.rm.reg field. */
6125 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6126 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6128 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6129 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6130 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6132 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6134 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6136 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6141 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6142 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6143 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6145 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6147 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6149 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6152 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6154 if (!i
.types
[0].bitfield
.control
6155 && !i
.types
[1].bitfield
.control
)
6157 i
.rex
&= ~(REX_R
| REX_B
);
6158 add_prefix (LOCK_PREFIX_OPCODE
);
6162 { /* If it's not 2 reg operands... */
6167 unsigned int fake_zero_displacement
= 0;
6170 for (op
= 0; op
< i
.operands
; op
++)
6171 if (operand_type_check (i
.types
[op
], anymem
))
6173 gas_assert (op
< i
.operands
);
6175 if (i
.tm
.opcode_modifier
.vecsib
)
6177 if (i
.index_reg
->reg_num
== RegEiz
6178 || i
.index_reg
->reg_num
== RegRiz
)
6181 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6184 i
.sib
.base
= NO_BASE_REGISTER
;
6185 i
.sib
.scale
= i
.log2_scale_factor
;
6186 /* No Vec_Disp8 if there is no base. */
6187 i
.types
[op
].bitfield
.vec_disp8
= 0;
6188 i
.types
[op
].bitfield
.disp8
= 0;
6189 i
.types
[op
].bitfield
.disp16
= 0;
6190 i
.types
[op
].bitfield
.disp64
= 0;
6191 if (flag_code
!= CODE_64BIT
)
6193 /* Must be 32 bit */
6194 i
.types
[op
].bitfield
.disp32
= 1;
6195 i
.types
[op
].bitfield
.disp32s
= 0;
6199 i
.types
[op
].bitfield
.disp32
= 0;
6200 i
.types
[op
].bitfield
.disp32s
= 1;
6203 i
.sib
.index
= i
.index_reg
->reg_num
;
6204 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6206 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6212 if (i
.base_reg
== 0)
6215 if (!i
.disp_operands
)
6217 fake_zero_displacement
= 1;
6218 /* Instructions with VSIB byte need 32bit displacement
6219 if there is no base register. */
6220 if (i
.tm
.opcode_modifier
.vecsib
)
6221 i
.types
[op
].bitfield
.disp32
= 1;
6223 if (i
.index_reg
== 0)
6225 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6226 /* Operand is just <disp> */
6227 if (flag_code
== CODE_64BIT
)
6229 /* 64bit mode overwrites the 32bit absolute
6230 addressing by RIP relative addressing and
6231 absolute addressing is encoded by one of the
6232 redundant SIB forms. */
6233 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6234 i
.sib
.base
= NO_BASE_REGISTER
;
6235 i
.sib
.index
= NO_INDEX_REGISTER
;
6236 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6237 ? disp32s
: disp32
);
6239 else if ((flag_code
== CODE_16BIT
)
6240 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6242 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6243 i
.types
[op
] = disp16
;
6247 i
.rm
.regmem
= NO_BASE_REGISTER
;
6248 i
.types
[op
] = disp32
;
6251 else if (!i
.tm
.opcode_modifier
.vecsib
)
6253 /* !i.base_reg && i.index_reg */
6254 if (i
.index_reg
->reg_num
== RegEiz
6255 || i
.index_reg
->reg_num
== RegRiz
)
6256 i
.sib
.index
= NO_INDEX_REGISTER
;
6258 i
.sib
.index
= i
.index_reg
->reg_num
;
6259 i
.sib
.base
= NO_BASE_REGISTER
;
6260 i
.sib
.scale
= i
.log2_scale_factor
;
6261 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6262 /* No Vec_Disp8 if there is no base. */
6263 i
.types
[op
].bitfield
.vec_disp8
= 0;
6264 i
.types
[op
].bitfield
.disp8
= 0;
6265 i
.types
[op
].bitfield
.disp16
= 0;
6266 i
.types
[op
].bitfield
.disp64
= 0;
6267 if (flag_code
!= CODE_64BIT
)
6269 /* Must be 32 bit */
6270 i
.types
[op
].bitfield
.disp32
= 1;
6271 i
.types
[op
].bitfield
.disp32s
= 0;
6275 i
.types
[op
].bitfield
.disp32
= 0;
6276 i
.types
[op
].bitfield
.disp32s
= 1;
6278 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6282 /* RIP addressing for 64bit mode. */
6283 else if (i
.base_reg
->reg_num
== RegRip
||
6284 i
.base_reg
->reg_num
== RegEip
)
6286 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6287 i
.rm
.regmem
= NO_BASE_REGISTER
;
6288 i
.types
[op
].bitfield
.disp8
= 0;
6289 i
.types
[op
].bitfield
.disp16
= 0;
6290 i
.types
[op
].bitfield
.disp32
= 0;
6291 i
.types
[op
].bitfield
.disp32s
= 1;
6292 i
.types
[op
].bitfield
.disp64
= 0;
6293 i
.types
[op
].bitfield
.vec_disp8
= 0;
6294 i
.flags
[op
] |= Operand_PCrel
;
6295 if (! i
.disp_operands
)
6296 fake_zero_displacement
= 1;
6298 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6300 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6301 switch (i
.base_reg
->reg_num
)
6304 if (i
.index_reg
== 0)
6306 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6307 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6311 if (i
.index_reg
== 0)
6314 if (operand_type_check (i
.types
[op
], disp
) == 0)
6316 /* fake (%bp) into 0(%bp) */
6317 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6318 i
.types
[op
].bitfield
.vec_disp8
= 1;
6320 i
.types
[op
].bitfield
.disp8
= 1;
6321 fake_zero_displacement
= 1;
6324 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6325 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6327 default: /* (%si) -> 4 or (%di) -> 5 */
6328 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6330 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6332 else /* i.base_reg and 32/64 bit mode */
6334 if (flag_code
== CODE_64BIT
6335 && operand_type_check (i
.types
[op
], disp
))
6337 i386_operand_type temp
;
6338 operand_type_set (&temp
, 0);
6339 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6340 temp
.bitfield
.vec_disp8
6341 = i
.types
[op
].bitfield
.vec_disp8
;
6343 if (i
.prefix
[ADDR_PREFIX
] == 0)
6344 i
.types
[op
].bitfield
.disp32s
= 1;
6346 i
.types
[op
].bitfield
.disp32
= 1;
6349 if (!i
.tm
.opcode_modifier
.vecsib
)
6350 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6351 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6353 i
.sib
.base
= i
.base_reg
->reg_num
;
6354 /* x86-64 ignores REX prefix bit here to avoid decoder
6356 if (!(i
.base_reg
->reg_flags
& RegRex
)
6357 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6358 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6360 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6362 fake_zero_displacement
= 1;
6363 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6364 i
.types
[op
].bitfield
.vec_disp8
= 1;
6366 i
.types
[op
].bitfield
.disp8
= 1;
6368 i
.sib
.scale
= i
.log2_scale_factor
;
6369 if (i
.index_reg
== 0)
6371 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6372 /* <disp>(%esp) becomes two byte modrm with no index
6373 register. We've already stored the code for esp
6374 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6375 Any base register besides %esp will not use the
6376 extra modrm byte. */
6377 i
.sib
.index
= NO_INDEX_REGISTER
;
6379 else if (!i
.tm
.opcode_modifier
.vecsib
)
6381 if (i
.index_reg
->reg_num
== RegEiz
6382 || i
.index_reg
->reg_num
== RegRiz
)
6383 i
.sib
.index
= NO_INDEX_REGISTER
;
6385 i
.sib
.index
= i
.index_reg
->reg_num
;
6386 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6387 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6392 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6393 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6397 if (!fake_zero_displacement
6401 fake_zero_displacement
= 1;
6402 if (i
.disp_encoding
== disp_encoding_8bit
)
6403 i
.types
[op
].bitfield
.disp8
= 1;
6405 i
.types
[op
].bitfield
.disp32
= 1;
6407 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6411 if (fake_zero_displacement
)
6413 /* Fakes a zero displacement assuming that i.types[op]
6414 holds the correct displacement size. */
6417 gas_assert (i
.op
[op
].disps
== 0);
6418 exp
= &disp_expressions
[i
.disp_operands
++];
6419 i
.op
[op
].disps
= exp
;
6420 exp
->X_op
= O_constant
;
6421 exp
->X_add_number
= 0;
6422 exp
->X_add_symbol
= (symbolS
*) 0;
6423 exp
->X_op_symbol
= (symbolS
*) 0;
6431 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6433 if (operand_type_check (i
.types
[0], imm
))
6434 i
.vex
.register_specifier
= NULL
;
6437 /* VEX.vvvv encodes one of the sources when the first
6438 operand is not an immediate. */
6439 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6440 i
.vex
.register_specifier
= i
.op
[0].regs
;
6442 i
.vex
.register_specifier
= i
.op
[1].regs
;
6445 /* Destination is a XMM register encoded in the ModRM.reg
6447 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6448 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6451 /* ModRM.rm and VEX.B encodes the other source. */
6452 if (!i
.mem_operands
)
6456 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6457 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6459 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6461 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6465 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6467 i
.vex
.register_specifier
= i
.op
[2].regs
;
6468 if (!i
.mem_operands
)
6471 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6472 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6476 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6477 (if any) based on i.tm.extension_opcode. Again, we must be
6478 careful to make sure that segment/control/debug/test/MMX
6479 registers are coded into the i.rm.reg field. */
6480 else if (i
.reg_operands
)
6483 unsigned int vex_reg
= ~0;
6485 for (op
= 0; op
< i
.operands
; op
++)
6486 if (i
.types
[op
].bitfield
.reg8
6487 || i
.types
[op
].bitfield
.reg16
6488 || i
.types
[op
].bitfield
.reg32
6489 || i
.types
[op
].bitfield
.reg64
6490 || i
.types
[op
].bitfield
.regmmx
6491 || i
.types
[op
].bitfield
.regxmm
6492 || i
.types
[op
].bitfield
.regymm
6493 || i
.types
[op
].bitfield
.regbnd
6494 || i
.types
[op
].bitfield
.regzmm
6495 || i
.types
[op
].bitfield
.regmask
6496 || i
.types
[op
].bitfield
.sreg2
6497 || i
.types
[op
].bitfield
.sreg3
6498 || i
.types
[op
].bitfield
.control
6499 || i
.types
[op
].bitfield
.debug
6500 || i
.types
[op
].bitfield
.test
)
6505 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6507 /* For instructions with VexNDS, the register-only
6508 source operand is encoded in VEX prefix. */
6509 gas_assert (mem
!= (unsigned int) ~0);
6514 gas_assert (op
< i
.operands
);
6518 /* Check register-only source operand when two source
6519 operands are swapped. */
6520 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6521 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6525 gas_assert (mem
== (vex_reg
+ 1)
6526 && op
< i
.operands
);
6531 gas_assert (vex_reg
< i
.operands
);
6535 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6537 /* For instructions with VexNDD, the register destination
6538 is encoded in VEX prefix. */
6539 if (i
.mem_operands
== 0)
6541 /* There is no memory operand. */
6542 gas_assert ((op
+ 2) == i
.operands
);
6547 /* There are only 2 operands. */
6548 gas_assert (op
< 2 && i
.operands
== 2);
6553 gas_assert (op
< i
.operands
);
6555 if (vex_reg
!= (unsigned int) ~0)
6557 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6559 if (type
->bitfield
.reg32
!= 1
6560 && type
->bitfield
.reg64
!= 1
6561 && !operand_type_equal (type
, ®xmm
)
6562 && !operand_type_equal (type
, ®ymm
)
6563 && !operand_type_equal (type
, ®zmm
)
6564 && !operand_type_equal (type
, ®mask
))
6567 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6570 /* Don't set OP operand twice. */
6573 /* If there is an extension opcode to put here, the
6574 register number must be put into the regmem field. */
6575 if (i
.tm
.extension_opcode
!= None
)
6577 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6578 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6580 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6585 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6586 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6588 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6593 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6594 must set it to 3 to indicate this is a register operand
6595 in the regmem field. */
6596 if (!i
.mem_operands
)
6600 /* Fill in i.rm.reg field with extension opcode (if any). */
6601 if (i
.tm
.extension_opcode
!= None
)
6602 i
.rm
.reg
= i
.tm
.extension_opcode
;
6608 output_branch (void)
6614 relax_substateT subtype
;
6618 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6619 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6622 if (i
.prefix
[DATA_PREFIX
] != 0)
6628 /* Pentium4 branch hints. */
6629 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6630 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6635 if (i
.prefix
[REX_PREFIX
] != 0)
6641 /* BND prefixed jump. */
6642 if (i
.prefix
[BND_PREFIX
] != 0)
6644 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6648 if (i
.prefixes
!= 0 && !intel_syntax
)
6649 as_warn (_("skipping prefixes on this instruction"));
6651 /* It's always a symbol; End frag & setup for relax.
6652 Make sure there is enough room in this frag for the largest
6653 instruction we may generate in md_convert_frag. This is 2
6654 bytes for the opcode and room for the prefix and largest
6656 frag_grow (prefix
+ 2 + 4);
6657 /* Prefix and 1 opcode byte go in fr_fix. */
6658 p
= frag_more (prefix
+ 1);
6659 if (i
.prefix
[DATA_PREFIX
] != 0)
6660 *p
++ = DATA_PREFIX_OPCODE
;
6661 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6662 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6663 *p
++ = i
.prefix
[SEG_PREFIX
];
6664 if (i
.prefix
[REX_PREFIX
] != 0)
6665 *p
++ = i
.prefix
[REX_PREFIX
];
6666 *p
= i
.tm
.base_opcode
;
6668 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6669 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6670 else if (cpu_arch_flags
.bitfield
.cpui386
)
6671 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6673 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6676 sym
= i
.op
[0].disps
->X_add_symbol
;
6677 off
= i
.op
[0].disps
->X_add_number
;
6679 if (i
.op
[0].disps
->X_op
!= O_constant
6680 && i
.op
[0].disps
->X_op
!= O_symbol
)
6682 /* Handle complex expressions. */
6683 sym
= make_expr_symbol (i
.op
[0].disps
);
6687 /* 1 possible extra opcode + 4 byte displacement go in var part.
6688 Pass reloc in fr_var. */
6689 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6699 if (i
.tm
.opcode_modifier
.jumpbyte
)
6701 /* This is a loop or jecxz type instruction. */
6703 if (i
.prefix
[ADDR_PREFIX
] != 0)
6705 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6708 /* Pentium4 branch hints. */
6709 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6710 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6712 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6721 if (flag_code
== CODE_16BIT
)
6724 if (i
.prefix
[DATA_PREFIX
] != 0)
6726 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6736 if (i
.prefix
[REX_PREFIX
] != 0)
6738 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6742 /* BND prefixed jump. */
6743 if (i
.prefix
[BND_PREFIX
] != 0)
6745 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6749 if (i
.prefixes
!= 0 && !intel_syntax
)
6750 as_warn (_("skipping prefixes on this instruction"));
6752 p
= frag_more (i
.tm
.opcode_length
+ size
);
6753 switch (i
.tm
.opcode_length
)
6756 *p
++ = i
.tm
.base_opcode
>> 8;
6758 *p
++ = i
.tm
.base_opcode
;
6764 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6765 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6767 /* All jumps handled here are signed, but don't use a signed limit
6768 check for 32 and 16 bit jumps as we want to allow wrap around at
6769 4G and 64k respectively. */
6771 fixP
->fx_signed
= 1;
6775 output_interseg_jump (void)
6783 if (flag_code
== CODE_16BIT
)
6787 if (i
.prefix
[DATA_PREFIX
] != 0)
6793 if (i
.prefix
[REX_PREFIX
] != 0)
6803 if (i
.prefixes
!= 0 && !intel_syntax
)
6804 as_warn (_("skipping prefixes on this instruction"));
6806 /* 1 opcode; 2 segment; offset */
6807 p
= frag_more (prefix
+ 1 + 2 + size
);
6809 if (i
.prefix
[DATA_PREFIX
] != 0)
6810 *p
++ = DATA_PREFIX_OPCODE
;
6812 if (i
.prefix
[REX_PREFIX
] != 0)
6813 *p
++ = i
.prefix
[REX_PREFIX
];
6815 *p
++ = i
.tm
.base_opcode
;
6816 if (i
.op
[1].imms
->X_op
== O_constant
)
6818 offsetT n
= i
.op
[1].imms
->X_add_number
;
6821 && !fits_in_unsigned_word (n
)
6822 && !fits_in_signed_word (n
))
6824 as_bad (_("16-bit jump out of range"));
6827 md_number_to_chars (p
, n
, size
);
6830 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6831 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6832 if (i
.op
[0].imms
->X_op
!= O_constant
)
6833 as_bad (_("can't handle non absolute segment in `%s'"),
6835 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6841 fragS
*insn_start_frag
;
6842 offsetT insn_start_off
;
6844 /* Tie dwarf2 debug info to the address at the start of the insn.
6845 We can't do this after the insn has been output as the current
6846 frag may have been closed off. eg. by frag_var. */
6847 dwarf2_emit_insn (0);
6849 insn_start_frag
= frag_now
;
6850 insn_start_off
= frag_now_fix ();
6853 if (i
.tm
.opcode_modifier
.jump
)
6855 else if (i
.tm
.opcode_modifier
.jumpbyte
6856 || i
.tm
.opcode_modifier
.jumpdword
)
6858 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6859 output_interseg_jump ();
6862 /* Output normal instructions here. */
6866 unsigned int prefix
;
6868 /* Some processors fail on LOCK prefix. This options makes
6869 assembler ignore LOCK prefix and serves as a workaround. */
6870 if (omit_lock_prefix
)
6872 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6874 i
.prefix
[LOCK_PREFIX
] = 0;
6877 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6878 don't need the explicit prefix. */
6879 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6881 switch (i
.tm
.opcode_length
)
6884 if (i
.tm
.base_opcode
& 0xff000000)
6886 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6891 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6893 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6894 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6897 if (prefix
!= REPE_PREFIX_OPCODE
6898 || (i
.prefix
[REP_PREFIX
]
6899 != REPE_PREFIX_OPCODE
))
6900 add_prefix (prefix
);
6903 add_prefix (prefix
);
6912 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6913 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6914 R_X86_64_GOTTPOFF relocation so that linker can safely
6915 perform IE->LE optimization. */
6916 if (x86_elf_abi
== X86_64_X32_ABI
6918 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
6919 && i
.prefix
[REX_PREFIX
] == 0)
6920 add_prefix (REX_OPCODE
);
6923 /* The prefix bytes. */
6924 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6926 FRAG_APPEND_1_CHAR (*q
);
6930 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6935 /* REX byte is encoded in VEX prefix. */
6939 FRAG_APPEND_1_CHAR (*q
);
6942 /* There should be no other prefixes for instructions
6947 /* For EVEX instructions i.vrex should become 0 after
6948 build_evex_prefix. For VEX instructions upper 16 registers
6949 aren't available, so VREX should be 0. */
6952 /* Now the VEX prefix. */
6953 p
= frag_more (i
.vex
.length
);
6954 for (j
= 0; j
< i
.vex
.length
; j
++)
6955 p
[j
] = i
.vex
.bytes
[j
];
6958 /* Now the opcode; be careful about word order here! */
6959 if (i
.tm
.opcode_length
== 1)
6961 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6965 switch (i
.tm
.opcode_length
)
6969 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
6970 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6974 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6984 /* Put out high byte first: can't use md_number_to_chars! */
6985 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6986 *p
= i
.tm
.base_opcode
& 0xff;
6989 /* Now the modrm byte and sib byte (if present). */
6990 if (i
.tm
.opcode_modifier
.modrm
)
6992 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6995 /* If i.rm.regmem == ESP (4)
6996 && i.rm.mode != (Register mode)
6998 ==> need second modrm byte. */
6999 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7001 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7002 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7004 | i
.sib
.scale
<< 6));
7007 if (i
.disp_operands
)
7008 output_disp (insn_start_frag
, insn_start_off
);
7011 output_imm (insn_start_frag
, insn_start_off
);
7017 pi ("" /*line*/, &i
);
7019 #endif /* DEBUG386 */
7022 /* Return the size of the displacement operand N. */
7025 disp_size (unsigned int n
)
7029 /* Vec_Disp8 has to be 8bit. */
7030 if (i
.types
[n
].bitfield
.vec_disp8
)
7032 else if (i
.types
[n
].bitfield
.disp64
)
7034 else if (i
.types
[n
].bitfield
.disp8
)
7036 else if (i
.types
[n
].bitfield
.disp16
)
7041 /* Return the size of the immediate operand N. */
7044 imm_size (unsigned int n
)
7047 if (i
.types
[n
].bitfield
.imm64
)
7049 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7051 else if (i
.types
[n
].bitfield
.imm16
)
7057 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7062 for (n
= 0; n
< i
.operands
; n
++)
7064 if (i
.types
[n
].bitfield
.vec_disp8
7065 || operand_type_check (i
.types
[n
], disp
))
7067 if (i
.op
[n
].disps
->X_op
== O_constant
)
7069 int size
= disp_size (n
);
7070 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7072 if (i
.types
[n
].bitfield
.vec_disp8
)
7074 val
= offset_in_range (val
, size
);
7075 p
= frag_more (size
);
7076 md_number_to_chars (p
, val
, size
);
7080 enum bfd_reloc_code_real reloc_type
;
7081 int size
= disp_size (n
);
7082 int sign
= i
.types
[n
].bitfield
.disp32s
;
7083 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7085 /* We can't have 8 bit displacement here. */
7086 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7088 /* The PC relative address is computed relative
7089 to the instruction boundary, so in case immediate
7090 fields follows, we need to adjust the value. */
7091 if (pcrel
&& i
.imm_operands
)
7096 for (n1
= 0; n1
< i
.operands
; n1
++)
7097 if (operand_type_check (i
.types
[n1
], imm
))
7099 /* Only one immediate is allowed for PC
7100 relative address. */
7101 gas_assert (sz
== 0);
7103 i
.op
[n
].disps
->X_add_number
-= sz
;
7105 /* We should find the immediate. */
7106 gas_assert (sz
!= 0);
7109 p
= frag_more (size
);
7110 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7112 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7113 && (((reloc_type
== BFD_RELOC_32
7114 || reloc_type
== BFD_RELOC_X86_64_32S
7115 || (reloc_type
== BFD_RELOC_64
7117 && (i
.op
[n
].disps
->X_op
== O_symbol
7118 || (i
.op
[n
].disps
->X_op
== O_add
7119 && ((symbol_get_value_expression
7120 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7122 || reloc_type
== BFD_RELOC_32_PCREL
))
7126 if (insn_start_frag
== frag_now
)
7127 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7132 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7133 for (fr
= insn_start_frag
->fr_next
;
7134 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7136 add
+= p
- frag_now
->fr_literal
;
7141 reloc_type
= BFD_RELOC_386_GOTPC
;
7142 i
.op
[n
].imms
->X_add_number
+= add
;
7144 else if (reloc_type
== BFD_RELOC_64
)
7145 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7147 /* Don't do the adjustment for x86-64, as there
7148 the pcrel addressing is relative to the _next_
7149 insn, and that is taken care of in other code. */
7150 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7152 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7153 i
.op
[n
].disps
, pcrel
, reloc_type
);
7160 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7165 for (n
= 0; n
< i
.operands
; n
++)
7167 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7168 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7171 if (operand_type_check (i
.types
[n
], imm
))
7173 if (i
.op
[n
].imms
->X_op
== O_constant
)
7175 int size
= imm_size (n
);
7178 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7180 p
= frag_more (size
);
7181 md_number_to_chars (p
, val
, size
);
7185 /* Not absolute_section.
7186 Need a 32-bit fixup (don't support 8bit
7187 non-absolute imms). Try to support other
7189 enum bfd_reloc_code_real reloc_type
;
7190 int size
= imm_size (n
);
7193 if (i
.types
[n
].bitfield
.imm32s
7194 && (i
.suffix
== QWORD_MNEM_SUFFIX
7195 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7200 p
= frag_more (size
);
7201 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7203 /* This is tough to explain. We end up with this one if we
7204 * have operands that look like
7205 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7206 * obtain the absolute address of the GOT, and it is strongly
7207 * preferable from a performance point of view to avoid using
7208 * a runtime relocation for this. The actual sequence of
7209 * instructions often look something like:
7214 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7216 * The call and pop essentially return the absolute address
7217 * of the label .L66 and store it in %ebx. The linker itself
7218 * will ultimately change the first operand of the addl so
7219 * that %ebx points to the GOT, but to keep things simple, the
7220 * .o file must have this operand set so that it generates not
7221 * the absolute address of .L66, but the absolute address of
7222 * itself. This allows the linker itself simply treat a GOTPC
7223 * relocation as asking for a pcrel offset to the GOT to be
7224 * added in, and the addend of the relocation is stored in the
7225 * operand field for the instruction itself.
7227 * Our job here is to fix the operand so that it would add
7228 * the correct offset so that %ebx would point to itself. The
7229 * thing that is tricky is that .-.L66 will point to the
7230 * beginning of the instruction, so we need to further modify
7231 * the operand so that it will point to itself. There are
7232 * other cases where you have something like:
7234 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7236 * and here no correction would be required. Internally in
7237 * the assembler we treat operands of this form as not being
7238 * pcrel since the '.' is explicitly mentioned, and I wonder
7239 * whether it would simplify matters to do it this way. Who
7240 * knows. In earlier versions of the PIC patches, the
7241 * pcrel_adjust field was used to store the correction, but
7242 * since the expression is not pcrel, I felt it would be
7243 * confusing to do it this way. */
7245 if ((reloc_type
== BFD_RELOC_32
7246 || reloc_type
== BFD_RELOC_X86_64_32S
7247 || reloc_type
== BFD_RELOC_64
)
7249 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7250 && (i
.op
[n
].imms
->X_op
== O_symbol
7251 || (i
.op
[n
].imms
->X_op
== O_add
7252 && ((symbol_get_value_expression
7253 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7258 if (insn_start_frag
== frag_now
)
7259 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7264 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7265 for (fr
= insn_start_frag
->fr_next
;
7266 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7268 add
+= p
- frag_now
->fr_literal
;
7272 reloc_type
= BFD_RELOC_386_GOTPC
;
7274 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7276 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7277 i
.op
[n
].imms
->X_add_number
+= add
;
7279 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7280 i
.op
[n
].imms
, 0, reloc_type
);
7286 /* x86_cons_fix_new is called via the expression parsing code when a
7287 reloc is needed. We use this hook to get the correct .got reloc. */
7288 static int cons_sign
= -1;
7291 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7292 expressionS
*exp
, bfd_reloc_code_real_type r
)
7294 r
= reloc (len
, 0, cons_sign
, r
);
7297 if (exp
->X_op
== O_secrel
)
7299 exp
->X_op
= O_symbol
;
7300 r
= BFD_RELOC_32_SECREL
;
7304 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7307 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7308 purpose of the `.dc.a' internal pseudo-op. */
7311 x86_address_bytes (void)
7313 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7315 return stdoutput
->arch_info
->bits_per_address
/ 8;
7318 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7320 # define lex_got(reloc, adjust, types) NULL
7322 /* Parse operands of the form
7323 <symbol>@GOTOFF+<nnn>
7324 and similar .plt or .got references.
7326 If we find one, set up the correct relocation in RELOC and copy the
7327 input string, minus the `@GOTOFF' into a malloc'd buffer for
7328 parsing by the calling routine. Return this buffer, and if ADJUST
7329 is non-null set it to the length of the string we removed from the
7330 input line. Otherwise return NULL. */
7332 lex_got (enum bfd_reloc_code_real
*rel
,
7334 i386_operand_type
*types
)
7336 /* Some of the relocations depend on the size of what field is to
7337 be relocated. But in our callers i386_immediate and i386_displacement
7338 we don't yet know the operand size (this will be set by insn
7339 matching). Hence we record the word32 relocation here,
7340 and adjust the reloc according to the real size in reloc(). */
7341 static const struct {
7344 const enum bfd_reloc_code_real rel
[2];
7345 const i386_operand_type types64
;
7347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7348 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7350 OPERAND_TYPE_IMM32_64
},
7352 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7353 BFD_RELOC_X86_64_PLTOFF64
},
7354 OPERAND_TYPE_IMM64
},
7355 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7356 BFD_RELOC_X86_64_PLT32
},
7357 OPERAND_TYPE_IMM32_32S_DISP32
},
7358 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7359 BFD_RELOC_X86_64_GOTPLT64
},
7360 OPERAND_TYPE_IMM64_DISP64
},
7361 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7362 BFD_RELOC_X86_64_GOTOFF64
},
7363 OPERAND_TYPE_IMM64_DISP64
},
7364 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7365 BFD_RELOC_X86_64_GOTPCREL
},
7366 OPERAND_TYPE_IMM32_32S_DISP32
},
7367 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7368 BFD_RELOC_X86_64_TLSGD
},
7369 OPERAND_TYPE_IMM32_32S_DISP32
},
7370 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7371 _dummy_first_bfd_reloc_code_real
},
7372 OPERAND_TYPE_NONE
},
7373 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7374 BFD_RELOC_X86_64_TLSLD
},
7375 OPERAND_TYPE_IMM32_32S_DISP32
},
7376 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7377 BFD_RELOC_X86_64_GOTTPOFF
},
7378 OPERAND_TYPE_IMM32_32S_DISP32
},
7379 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7380 BFD_RELOC_X86_64_TPOFF32
},
7381 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7382 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7383 _dummy_first_bfd_reloc_code_real
},
7384 OPERAND_TYPE_NONE
},
7385 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7386 BFD_RELOC_X86_64_DTPOFF32
},
7387 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7388 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7389 _dummy_first_bfd_reloc_code_real
},
7390 OPERAND_TYPE_NONE
},
7391 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7392 _dummy_first_bfd_reloc_code_real
},
7393 OPERAND_TYPE_NONE
},
7394 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7395 BFD_RELOC_X86_64_GOT32
},
7396 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7397 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7398 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7399 OPERAND_TYPE_IMM32_32S_DISP32
},
7400 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7401 BFD_RELOC_X86_64_TLSDESC_CALL
},
7402 OPERAND_TYPE_IMM32_32S_DISP32
},
7407 #if defined (OBJ_MAYBE_ELF)
7412 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7413 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7416 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7418 int len
= gotrel
[j
].len
;
7419 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7421 if (gotrel
[j
].rel
[object_64bit
] != 0)
7424 char *tmpbuf
, *past_reloc
;
7426 *rel
= gotrel
[j
].rel
[object_64bit
];
7430 if (flag_code
!= CODE_64BIT
)
7432 types
->bitfield
.imm32
= 1;
7433 types
->bitfield
.disp32
= 1;
7436 *types
= gotrel
[j
].types64
;
7439 if (j
!= 0 && GOT_symbol
== NULL
)
7440 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7442 /* The length of the first part of our input line. */
7443 first
= cp
- input_line_pointer
;
7445 /* The second part goes from after the reloc token until
7446 (and including) an end_of_line char or comma. */
7447 past_reloc
= cp
+ 1 + len
;
7449 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7451 second
= cp
+ 1 - past_reloc
;
7453 /* Allocate and copy string. The trailing NUL shouldn't
7454 be necessary, but be safe. */
7455 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7456 memcpy (tmpbuf
, input_line_pointer
, first
);
7457 if (second
!= 0 && *past_reloc
!= ' ')
7458 /* Replace the relocation token with ' ', so that
7459 errors like foo@GOTOFF1 will be detected. */
7460 tmpbuf
[first
++] = ' ';
7462 /* Increment length by 1 if the relocation token is
7467 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7468 tmpbuf
[first
+ second
] = '\0';
7472 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7473 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7478 /* Might be a symbol version string. Don't as_bad here. */
7487 /* Parse operands of the form
7488 <symbol>@SECREL32+<nnn>
7490 If we find one, set up the correct relocation in RELOC and copy the
7491 input string, minus the `@SECREL32' into a malloc'd buffer for
7492 parsing by the calling routine. Return this buffer, and if ADJUST
7493 is non-null set it to the length of the string we removed from the
7494 input line. Otherwise return NULL.
7496 This function is copied from the ELF version above adjusted for PE targets. */
7499 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7500 int *adjust ATTRIBUTE_UNUSED
,
7501 i386_operand_type
*types
)
7507 const enum bfd_reloc_code_real rel
[2];
7508 const i386_operand_type types64
;
7512 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7513 BFD_RELOC_32_SECREL
},
7514 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7520 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7521 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7524 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7526 int len
= gotrel
[j
].len
;
7528 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7530 if (gotrel
[j
].rel
[object_64bit
] != 0)
7533 char *tmpbuf
, *past_reloc
;
7535 *rel
= gotrel
[j
].rel
[object_64bit
];
7541 if (flag_code
!= CODE_64BIT
)
7543 types
->bitfield
.imm32
= 1;
7544 types
->bitfield
.disp32
= 1;
7547 *types
= gotrel
[j
].types64
;
7550 /* The length of the first part of our input line. */
7551 first
= cp
- input_line_pointer
;
7553 /* The second part goes from after the reloc token until
7554 (and including) an end_of_line char or comma. */
7555 past_reloc
= cp
+ 1 + len
;
7557 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7559 second
= cp
+ 1 - past_reloc
;
7561 /* Allocate and copy string. The trailing NUL shouldn't
7562 be necessary, but be safe. */
7563 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7564 memcpy (tmpbuf
, input_line_pointer
, first
);
7565 if (second
!= 0 && *past_reloc
!= ' ')
7566 /* Replace the relocation token with ' ', so that
7567 errors like foo@SECLREL321 will be detected. */
7568 tmpbuf
[first
++] = ' ';
7569 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7570 tmpbuf
[first
+ second
] = '\0';
7574 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7575 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7580 /* Might be a symbol version string. Don't as_bad here. */
7586 bfd_reloc_code_real_type
7587 x86_cons (expressionS
*exp
, int size
)
7589 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7591 intel_syntax
= -intel_syntax
;
7594 if (size
== 4 || (object_64bit
&& size
== 8))
7596 /* Handle @GOTOFF and the like in an expression. */
7598 char *gotfree_input_line
;
7601 save
= input_line_pointer
;
7602 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7603 if (gotfree_input_line
)
7604 input_line_pointer
= gotfree_input_line
;
7608 if (gotfree_input_line
)
7610 /* expression () has merrily parsed up to the end of line,
7611 or a comma - in the wrong buffer. Transfer how far
7612 input_line_pointer has moved to the right buffer. */
7613 input_line_pointer
= (save
7614 + (input_line_pointer
- gotfree_input_line
)
7616 free (gotfree_input_line
);
7617 if (exp
->X_op
== O_constant
7618 || exp
->X_op
== O_absent
7619 || exp
->X_op
== O_illegal
7620 || exp
->X_op
== O_register
7621 || exp
->X_op
== O_big
)
7623 char c
= *input_line_pointer
;
7624 *input_line_pointer
= 0;
7625 as_bad (_("missing or invalid expression `%s'"), save
);
7626 *input_line_pointer
= c
;
7633 intel_syntax
= -intel_syntax
;
7636 i386_intel_simplify (exp
);
7642 signed_cons (int size
)
7644 if (flag_code
== CODE_64BIT
)
7652 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7659 if (exp
.X_op
== O_symbol
)
7660 exp
.X_op
= O_secrel
;
7662 emit_expr (&exp
, 4);
7664 while (*input_line_pointer
++ == ',');
7666 input_line_pointer
--;
7667 demand_empty_rest_of_line ();
7671 /* Handle Vector operations. */
7674 check_VecOperations (char *op_string
, char *op_end
)
7676 const reg_entry
*mask
;
7681 && (op_end
== NULL
|| op_string
< op_end
))
7684 if (*op_string
== '{')
7688 /* Check broadcasts. */
7689 if (strncmp (op_string
, "1to", 3) == 0)
7694 goto duplicated_vec_op
;
7697 if (*op_string
== '8')
7698 bcst_type
= BROADCAST_1TO8
;
7699 else if (*op_string
== '4')
7700 bcst_type
= BROADCAST_1TO4
;
7701 else if (*op_string
== '2')
7702 bcst_type
= BROADCAST_1TO2
;
7703 else if (*op_string
== '1'
7704 && *(op_string
+1) == '6')
7706 bcst_type
= BROADCAST_1TO16
;
7711 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7716 broadcast_op
.type
= bcst_type
;
7717 broadcast_op
.operand
= this_operand
;
7718 i
.broadcast
= &broadcast_op
;
7720 /* Check masking operation. */
7721 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7723 /* k0 can't be used for write mask. */
7724 if (mask
->reg_num
== 0)
7726 as_bad (_("`%s' can't be used for write mask"),
7733 mask_op
.mask
= mask
;
7734 mask_op
.zeroing
= 0;
7735 mask_op
.operand
= this_operand
;
7741 goto duplicated_vec_op
;
7743 i
.mask
->mask
= mask
;
7745 /* Only "{z}" is allowed here. No need to check
7746 zeroing mask explicitly. */
7747 if (i
.mask
->operand
!= this_operand
)
7749 as_bad (_("invalid write mask `%s'"), saved
);
7756 /* Check zeroing-flag for masking operation. */
7757 else if (*op_string
== 'z')
7761 mask_op
.mask
= NULL
;
7762 mask_op
.zeroing
= 1;
7763 mask_op
.operand
= this_operand
;
7768 if (i
.mask
->zeroing
)
7771 as_bad (_("duplicated `%s'"), saved
);
7775 i
.mask
->zeroing
= 1;
7777 /* Only "{%k}" is allowed here. No need to check mask
7778 register explicitly. */
7779 if (i
.mask
->operand
!= this_operand
)
7781 as_bad (_("invalid zeroing-masking `%s'"),
7790 goto unknown_vec_op
;
7792 if (*op_string
!= '}')
7794 as_bad (_("missing `}' in `%s'"), saved
);
7801 /* We don't know this one. */
7802 as_bad (_("unknown vector operation: `%s'"), saved
);
7810 i386_immediate (char *imm_start
)
7812 char *save_input_line_pointer
;
7813 char *gotfree_input_line
;
7816 i386_operand_type types
;
7818 operand_type_set (&types
, ~0);
7820 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7822 as_bad (_("at most %d immediate operands are allowed"),
7823 MAX_IMMEDIATE_OPERANDS
);
7827 exp
= &im_expressions
[i
.imm_operands
++];
7828 i
.op
[this_operand
].imms
= exp
;
7830 if (is_space_char (*imm_start
))
7833 save_input_line_pointer
= input_line_pointer
;
7834 input_line_pointer
= imm_start
;
7836 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7837 if (gotfree_input_line
)
7838 input_line_pointer
= gotfree_input_line
;
7840 exp_seg
= expression (exp
);
7844 /* Handle vector operations. */
7845 if (*input_line_pointer
== '{')
7847 input_line_pointer
= check_VecOperations (input_line_pointer
,
7849 if (input_line_pointer
== NULL
)
7853 if (*input_line_pointer
)
7854 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7856 input_line_pointer
= save_input_line_pointer
;
7857 if (gotfree_input_line
)
7859 free (gotfree_input_line
);
7861 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7862 exp
->X_op
= O_illegal
;
7865 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7869 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7870 i386_operand_type types
, const char *imm_start
)
7872 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7875 as_bad (_("missing or invalid immediate expression `%s'"),
7879 else if (exp
->X_op
== O_constant
)
7881 /* Size it properly later. */
7882 i
.types
[this_operand
].bitfield
.imm64
= 1;
7883 /* If not 64bit, sign extend val. */
7884 if (flag_code
!= CODE_64BIT
7885 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7887 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7889 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7890 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7891 && exp_seg
!= absolute_section
7892 && exp_seg
!= text_section
7893 && exp_seg
!= data_section
7894 && exp_seg
!= bss_section
7895 && exp_seg
!= undefined_section
7896 && !bfd_is_com_section (exp_seg
))
7898 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7902 else if (!intel_syntax
&& exp_seg
== reg_section
)
7905 as_bad (_("illegal immediate register operand %s"), imm_start
);
7910 /* This is an address. The size of the address will be
7911 determined later, depending on destination register,
7912 suffix, or the default for the section. */
7913 i
.types
[this_operand
].bitfield
.imm8
= 1;
7914 i
.types
[this_operand
].bitfield
.imm16
= 1;
7915 i
.types
[this_operand
].bitfield
.imm32
= 1;
7916 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7917 i
.types
[this_operand
].bitfield
.imm64
= 1;
7918 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7926 i386_scale (char *scale
)
7929 char *save
= input_line_pointer
;
7931 input_line_pointer
= scale
;
7932 val
= get_absolute_expression ();
7937 i
.log2_scale_factor
= 0;
7940 i
.log2_scale_factor
= 1;
7943 i
.log2_scale_factor
= 2;
7946 i
.log2_scale_factor
= 3;
7950 char sep
= *input_line_pointer
;
7952 *input_line_pointer
= '\0';
7953 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7955 *input_line_pointer
= sep
;
7956 input_line_pointer
= save
;
7960 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7962 as_warn (_("scale factor of %d without an index register"),
7963 1 << i
.log2_scale_factor
);
7964 i
.log2_scale_factor
= 0;
7966 scale
= input_line_pointer
;
7967 input_line_pointer
= save
;
7972 i386_displacement (char *disp_start
, char *disp_end
)
7976 char *save_input_line_pointer
;
7977 char *gotfree_input_line
;
7979 i386_operand_type bigdisp
, types
= anydisp
;
7982 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7984 as_bad (_("at most %d displacement operands are allowed"),
7985 MAX_MEMORY_OPERANDS
);
7989 operand_type_set (&bigdisp
, 0);
7990 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7991 || (!current_templates
->start
->opcode_modifier
.jump
7992 && !current_templates
->start
->opcode_modifier
.jumpdword
))
7994 bigdisp
.bitfield
.disp32
= 1;
7995 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7996 if (flag_code
== CODE_64BIT
)
8000 bigdisp
.bitfield
.disp32s
= 1;
8001 bigdisp
.bitfield
.disp64
= 1;
8004 else if ((flag_code
== CODE_16BIT
) ^ override
)
8006 bigdisp
.bitfield
.disp32
= 0;
8007 bigdisp
.bitfield
.disp16
= 1;
8012 /* For PC-relative branches, the width of the displacement
8013 is dependent upon data size, not address size. */
8014 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8015 if (flag_code
== CODE_64BIT
)
8017 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8018 bigdisp
.bitfield
.disp16
= 1;
8021 bigdisp
.bitfield
.disp32
= 1;
8022 bigdisp
.bitfield
.disp32s
= 1;
8028 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8030 : LONG_MNEM_SUFFIX
));
8031 bigdisp
.bitfield
.disp32
= 1;
8032 if ((flag_code
== CODE_16BIT
) ^ override
)
8034 bigdisp
.bitfield
.disp32
= 0;
8035 bigdisp
.bitfield
.disp16
= 1;
8039 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8042 exp
= &disp_expressions
[i
.disp_operands
];
8043 i
.op
[this_operand
].disps
= exp
;
8045 save_input_line_pointer
= input_line_pointer
;
8046 input_line_pointer
= disp_start
;
8047 END_STRING_AND_SAVE (disp_end
);
8049 #ifndef GCC_ASM_O_HACK
8050 #define GCC_ASM_O_HACK 0
8053 END_STRING_AND_SAVE (disp_end
+ 1);
8054 if (i
.types
[this_operand
].bitfield
.baseIndex
8055 && displacement_string_end
[-1] == '+')
8057 /* This hack is to avoid a warning when using the "o"
8058 constraint within gcc asm statements.
8061 #define _set_tssldt_desc(n,addr,limit,type) \
8062 __asm__ __volatile__ ( \
8064 "movw %w1,2+%0\n\t" \
8066 "movb %b1,4+%0\n\t" \
8067 "movb %4,5+%0\n\t" \
8068 "movb $0,6+%0\n\t" \
8069 "movb %h1,7+%0\n\t" \
8071 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8073 This works great except that the output assembler ends
8074 up looking a bit weird if it turns out that there is
8075 no offset. You end up producing code that looks like:
8088 So here we provide the missing zero. */
8090 *displacement_string_end
= '0';
8093 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8094 if (gotfree_input_line
)
8095 input_line_pointer
= gotfree_input_line
;
8097 exp_seg
= expression (exp
);
8100 if (*input_line_pointer
)
8101 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8103 RESTORE_END_STRING (disp_end
+ 1);
8105 input_line_pointer
= save_input_line_pointer
;
8106 if (gotfree_input_line
)
8108 free (gotfree_input_line
);
8110 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8111 exp
->X_op
= O_illegal
;
8114 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8116 RESTORE_END_STRING (disp_end
);
8122 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8123 i386_operand_type types
, const char *disp_start
)
8125 i386_operand_type bigdisp
;
8128 /* We do this to make sure that the section symbol is in
8129 the symbol table. We will ultimately change the relocation
8130 to be relative to the beginning of the section. */
8131 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8132 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8133 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8135 if (exp
->X_op
!= O_symbol
)
8138 if (S_IS_LOCAL (exp
->X_add_symbol
)
8139 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8140 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8141 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8142 exp
->X_op
= O_subtract
;
8143 exp
->X_op_symbol
= GOT_symbol
;
8144 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8145 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8146 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8147 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8149 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8152 else if (exp
->X_op
== O_absent
8153 || exp
->X_op
== O_illegal
8154 || exp
->X_op
== O_big
)
8157 as_bad (_("missing or invalid displacement expression `%s'"),
8162 else if (flag_code
== CODE_64BIT
8163 && !i
.prefix
[ADDR_PREFIX
]
8164 && exp
->X_op
== O_constant
)
8166 /* Since displacement is signed extended to 64bit, don't allow
8167 disp32 and turn off disp32s if they are out of range. */
8168 i
.types
[this_operand
].bitfield
.disp32
= 0;
8169 if (!fits_in_signed_long (exp
->X_add_number
))
8171 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8172 if (i
.types
[this_operand
].bitfield
.baseindex
)
8174 as_bad (_("0x%lx out range of signed 32bit displacement"),
8175 (long) exp
->X_add_number
);
8181 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8182 else if (exp
->X_op
!= O_constant
8183 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8184 && exp_seg
!= absolute_section
8185 && exp_seg
!= text_section
8186 && exp_seg
!= data_section
8187 && exp_seg
!= bss_section
8188 && exp_seg
!= undefined_section
8189 && !bfd_is_com_section (exp_seg
))
8191 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8196 /* Check if this is a displacement only operand. */
8197 bigdisp
= i
.types
[this_operand
];
8198 bigdisp
.bitfield
.disp8
= 0;
8199 bigdisp
.bitfield
.disp16
= 0;
8200 bigdisp
.bitfield
.disp32
= 0;
8201 bigdisp
.bitfield
.disp32s
= 0;
8202 bigdisp
.bitfield
.disp64
= 0;
8203 if (operand_type_all_zero (&bigdisp
))
8204 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8210 /* Make sure the memory operand we've been dealt is valid.
8211 Return 1 on success, 0 on a failure. */
8214 i386_index_check (const char *operand_string
)
8216 const char *kind
= "base/index";
8217 enum flag_code addr_mode
;
8219 if (i
.prefix
[ADDR_PREFIX
])
8220 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8223 addr_mode
= flag_code
;
8225 #if INFER_ADDR_PREFIX
8226 if (i
.mem_operands
== 0)
8228 /* Infer address prefix from the first memory operand. */
8229 const reg_entry
*addr_reg
= i
.base_reg
;
8231 if (addr_reg
== NULL
)
8232 addr_reg
= i
.index_reg
;
8236 if (addr_reg
->reg_num
== RegEip
8237 || addr_reg
->reg_num
== RegEiz
8238 || addr_reg
->reg_type
.bitfield
.reg32
)
8239 addr_mode
= CODE_32BIT
;
8240 else if (flag_code
!= CODE_64BIT
8241 && addr_reg
->reg_type
.bitfield
.reg16
)
8242 addr_mode
= CODE_16BIT
;
8244 if (addr_mode
!= flag_code
)
8246 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8248 /* Change the size of any displacement too. At most one
8249 of Disp16 or Disp32 is set.
8250 FIXME. There doesn't seem to be any real need for
8251 separate Disp16 and Disp32 flags. The same goes for
8252 Imm16 and Imm32. Removing them would probably clean
8253 up the code quite a lot. */
8254 if (flag_code
!= CODE_64BIT
8255 && (i
.types
[this_operand
].bitfield
.disp16
8256 || i
.types
[this_operand
].bitfield
.disp32
))
8257 i
.types
[this_operand
]
8258 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8265 if (current_templates
->start
->opcode_modifier
.isstring
8266 && !current_templates
->start
->opcode_modifier
.immext
8267 && (current_templates
->end
[-1].opcode_modifier
.isstring
8270 /* Memory operands of string insns are special in that they only allow
8271 a single register (rDI, rSI, or rBX) as their memory address. */
8272 const reg_entry
*expected_reg
;
8273 static const char *di_si
[][2] =
8279 static const char *bx
[] = { "ebx", "bx", "rbx" };
8281 kind
= "string address";
8283 if (current_templates
->start
->opcode_modifier
.w
)
8285 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8287 if (!type
.bitfield
.baseindex
8288 || ((!i
.mem_operands
!= !intel_syntax
)
8289 && current_templates
->end
[-1].operand_types
[1]
8290 .bitfield
.baseindex
))
8291 type
= current_templates
->end
[-1].operand_types
[1];
8292 expected_reg
= hash_find (reg_hash
,
8293 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8297 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8299 if (i
.base_reg
!= expected_reg
8301 || operand_type_check (i
.types
[this_operand
], disp
))
8303 /* The second memory operand must have the same size as
8307 && !((addr_mode
== CODE_64BIT
8308 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8309 || (addr_mode
== CODE_32BIT
8310 ? i
.base_reg
->reg_type
.bitfield
.reg32
8311 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8314 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8316 intel_syntax
? '[' : '(',
8318 expected_reg
->reg_name
,
8319 intel_syntax
? ']' : ')');
8326 as_bad (_("`%s' is not a valid %s expression"),
8327 operand_string
, kind
);
8332 if (addr_mode
!= CODE_16BIT
)
8334 /* 32-bit/64-bit checks. */
8336 && (addr_mode
== CODE_64BIT
8337 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8338 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8340 || (i
.base_reg
->reg_num
8341 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8343 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8344 && !i
.index_reg
->reg_type
.bitfield
.regymm
8345 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8346 && ((addr_mode
== CODE_64BIT
8347 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8348 || i
.index_reg
->reg_num
== RegRiz
)
8349 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8350 || i
.index_reg
->reg_num
== RegEiz
))
8351 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8356 /* 16-bit checks. */
8358 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8359 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8361 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8362 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8364 && i
.base_reg
->reg_num
< 6
8365 && i
.index_reg
->reg_num
>= 6
8366 && i
.log2_scale_factor
== 0))))
8373 /* Handle vector immediates. */
8376 RC_SAE_immediate (const char *imm_start
)
8378 unsigned int match_found
, j
;
8379 const char *pstr
= imm_start
;
8387 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8389 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8393 rc_op
.type
= RC_NamesTable
[j
].type
;
8394 rc_op
.operand
= this_operand
;
8395 i
.rounding
= &rc_op
;
8399 as_bad (_("duplicated `%s'"), imm_start
);
8402 pstr
+= RC_NamesTable
[j
].len
;
8412 as_bad (_("Missing '}': '%s'"), imm_start
);
8415 /* RC/SAE immediate string should contain nothing more. */;
8418 as_bad (_("Junk after '}': '%s'"), imm_start
);
8422 exp
= &im_expressions
[i
.imm_operands
++];
8423 i
.op
[this_operand
].imms
= exp
;
8425 exp
->X_op
= O_constant
;
8426 exp
->X_add_number
= 0;
8427 exp
->X_add_symbol
= (symbolS
*) 0;
8428 exp
->X_op_symbol
= (symbolS
*) 0;
8430 i
.types
[this_operand
].bitfield
.imm8
= 1;
8434 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8438 i386_att_operand (char *operand_string
)
8442 char *op_string
= operand_string
;
8444 if (is_space_char (*op_string
))
8447 /* We check for an absolute prefix (differentiating,
8448 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8449 if (*op_string
== ABSOLUTE_PREFIX
)
8452 if (is_space_char (*op_string
))
8454 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8457 /* Check if operand is a register. */
8458 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8460 i386_operand_type temp
;
8462 /* Check for a segment override by searching for ':' after a
8463 segment register. */
8465 if (is_space_char (*op_string
))
8467 if (*op_string
== ':'
8468 && (r
->reg_type
.bitfield
.sreg2
8469 || r
->reg_type
.bitfield
.sreg3
))
8474 i
.seg
[i
.mem_operands
] = &es
;
8477 i
.seg
[i
.mem_operands
] = &cs
;
8480 i
.seg
[i
.mem_operands
] = &ss
;
8483 i
.seg
[i
.mem_operands
] = &ds
;
8486 i
.seg
[i
.mem_operands
] = &fs
;
8489 i
.seg
[i
.mem_operands
] = &gs
;
8493 /* Skip the ':' and whitespace. */
8495 if (is_space_char (*op_string
))
8498 if (!is_digit_char (*op_string
)
8499 && !is_identifier_char (*op_string
)
8500 && *op_string
!= '('
8501 && *op_string
!= ABSOLUTE_PREFIX
)
8503 as_bad (_("bad memory operand `%s'"), op_string
);
8506 /* Handle case of %es:*foo. */
8507 if (*op_string
== ABSOLUTE_PREFIX
)
8510 if (is_space_char (*op_string
))
8512 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8514 goto do_memory_reference
;
8517 /* Handle vector operations. */
8518 if (*op_string
== '{')
8520 op_string
= check_VecOperations (op_string
, NULL
);
8521 if (op_string
== NULL
)
8527 as_bad (_("junk `%s' after register"), op_string
);
8531 temp
.bitfield
.baseindex
= 0;
8532 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8534 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8535 i
.op
[this_operand
].regs
= r
;
8538 else if (*op_string
== REGISTER_PREFIX
)
8540 as_bad (_("bad register name `%s'"), op_string
);
8543 else if (*op_string
== IMMEDIATE_PREFIX
)
8546 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8548 as_bad (_("immediate operand illegal with absolute jump"));
8551 if (!i386_immediate (op_string
))
8554 else if (RC_SAE_immediate (operand_string
))
8556 /* If it is a RC or SAE immediate, do nothing. */
8559 else if (is_digit_char (*op_string
)
8560 || is_identifier_char (*op_string
)
8561 || *op_string
== '(')
8563 /* This is a memory reference of some sort. */
8566 /* Start and end of displacement string expression (if found). */
8567 char *displacement_string_start
;
8568 char *displacement_string_end
;
8571 do_memory_reference
:
8572 if ((i
.mem_operands
== 1
8573 && !current_templates
->start
->opcode_modifier
.isstring
)
8574 || i
.mem_operands
== 2)
8576 as_bad (_("too many memory references for `%s'"),
8577 current_templates
->start
->name
);
8581 /* Check for base index form. We detect the base index form by
8582 looking for an ')' at the end of the operand, searching
8583 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8585 base_string
= op_string
+ strlen (op_string
);
8587 /* Handle vector operations. */
8588 vop_start
= strchr (op_string
, '{');
8589 if (vop_start
&& vop_start
< base_string
)
8591 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8593 base_string
= vop_start
;
8597 if (is_space_char (*base_string
))
8600 /* If we only have a displacement, set-up for it to be parsed later. */
8601 displacement_string_start
= op_string
;
8602 displacement_string_end
= base_string
+ 1;
8604 if (*base_string
== ')')
8607 unsigned int parens_balanced
= 1;
8608 /* We've already checked that the number of left & right ()'s are
8609 equal, so this loop will not be infinite. */
8613 if (*base_string
== ')')
8615 if (*base_string
== '(')
8618 while (parens_balanced
);
8620 temp_string
= base_string
;
8622 /* Skip past '(' and whitespace. */
8624 if (is_space_char (*base_string
))
8627 if (*base_string
== ','
8628 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8631 displacement_string_end
= temp_string
;
8633 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8637 base_string
= end_op
;
8638 if (is_space_char (*base_string
))
8642 /* There may be an index reg or scale factor here. */
8643 if (*base_string
== ',')
8646 if (is_space_char (*base_string
))
8649 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8652 base_string
= end_op
;
8653 if (is_space_char (*base_string
))
8655 if (*base_string
== ',')
8658 if (is_space_char (*base_string
))
8661 else if (*base_string
!= ')')
8663 as_bad (_("expecting `,' or `)' "
8664 "after index register in `%s'"),
8669 else if (*base_string
== REGISTER_PREFIX
)
8671 end_op
= strchr (base_string
, ',');
8674 as_bad (_("bad register name `%s'"), base_string
);
8678 /* Check for scale factor. */
8679 if (*base_string
!= ')')
8681 char *end_scale
= i386_scale (base_string
);
8686 base_string
= end_scale
;
8687 if (is_space_char (*base_string
))
8689 if (*base_string
!= ')')
8691 as_bad (_("expecting `)' "
8692 "after scale factor in `%s'"),
8697 else if (!i
.index_reg
)
8699 as_bad (_("expecting index register or scale factor "
8700 "after `,'; got '%c'"),
8705 else if (*base_string
!= ')')
8707 as_bad (_("expecting `,' or `)' "
8708 "after base register in `%s'"),
8713 else if (*base_string
== REGISTER_PREFIX
)
8715 end_op
= strchr (base_string
, ',');
8718 as_bad (_("bad register name `%s'"), base_string
);
8723 /* If there's an expression beginning the operand, parse it,
8724 assuming displacement_string_start and
8725 displacement_string_end are meaningful. */
8726 if (displacement_string_start
!= displacement_string_end
)
8728 if (!i386_displacement (displacement_string_start
,
8729 displacement_string_end
))
8733 /* Special case for (%dx) while doing input/output op. */
8735 && operand_type_equal (&i
.base_reg
->reg_type
,
8736 ®16_inoutportreg
)
8738 && i
.log2_scale_factor
== 0
8739 && i
.seg
[i
.mem_operands
] == 0
8740 && !operand_type_check (i
.types
[this_operand
], disp
))
8742 i
.types
[this_operand
] = inoutportreg
;
8746 if (i386_index_check (operand_string
) == 0)
8748 i
.types
[this_operand
].bitfield
.mem
= 1;
8753 /* It's not a memory operand; argh! */
8754 as_bad (_("invalid char %s beginning operand %d `%s'"),
8755 output_invalid (*op_string
),
8760 return 1; /* Normal return. */
8763 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8764 that an rs_machine_dependent frag may reach. */
8767 i386_frag_max_var (fragS
*frag
)
8769 /* The only relaxable frags are for jumps.
8770 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8771 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8772 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8775 /* md_estimate_size_before_relax()
8777 Called just before relax() for rs_machine_dependent frags. The x86
8778 assembler uses these frags to handle variable size jump
8781 Any symbol that is now undefined will not become defined.
8782 Return the correct fr_subtype in the frag.
8783 Return the initial "guess for variable size of frag" to caller.
8784 The guess is actually the growth beyond the fixed part. Whatever
8785 we do to grow the fixed or variable part contributes to our
8789 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8791 /* We've already got fragP->fr_subtype right; all we have to do is
8792 check for un-relaxable symbols. On an ELF system, we can't relax
8793 an externally visible symbol, because it may be overridden by a
8795 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8796 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8798 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8799 || S_IS_WEAK (fragP
->fr_symbol
)
8800 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8801 & BSF_GNU_INDIRECT_FUNCTION
))))
8803 #if defined (OBJ_COFF) && defined (TE_PE)
8804 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8805 && S_IS_WEAK (fragP
->fr_symbol
))
8809 /* Symbol is undefined in this segment, or we need to keep a
8810 reloc so that weak symbols can be overridden. */
8811 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8812 enum bfd_reloc_code_real reloc_type
;
8813 unsigned char *opcode
;
8816 if (fragP
->fr_var
!= NO_RELOC
)
8817 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8819 reloc_type
= BFD_RELOC_16_PCREL
;
8821 reloc_type
= BFD_RELOC_32_PCREL
;
8823 old_fr_fix
= fragP
->fr_fix
;
8824 opcode
= (unsigned char *) fragP
->fr_opcode
;
8826 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8829 /* Make jmp (0xeb) a (d)word displacement jump. */
8831 fragP
->fr_fix
+= size
;
8832 fix_new (fragP
, old_fr_fix
, size
,
8834 fragP
->fr_offset
, 1,
8840 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8842 /* Negate the condition, and branch past an
8843 unconditional jump. */
8846 /* Insert an unconditional jump. */
8848 /* We added two extra opcode bytes, and have a two byte
8850 fragP
->fr_fix
+= 2 + 2;
8851 fix_new (fragP
, old_fr_fix
+ 2, 2,
8853 fragP
->fr_offset
, 1,
8860 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8865 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8867 fragP
->fr_offset
, 1,
8869 fixP
->fx_signed
= 1;
8873 /* This changes the byte-displacement jump 0x7N
8874 to the (d)word-displacement jump 0x0f,0x8N. */
8875 opcode
[1] = opcode
[0] + 0x10;
8876 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8877 /* We've added an opcode byte. */
8878 fragP
->fr_fix
+= 1 + size
;
8879 fix_new (fragP
, old_fr_fix
+ 1, size
,
8881 fragP
->fr_offset
, 1,
8886 BAD_CASE (fragP
->fr_subtype
);
8890 return fragP
->fr_fix
- old_fr_fix
;
8893 /* Guess size depending on current relax state. Initially the relax
8894 state will correspond to a short jump and we return 1, because
8895 the variable part of the frag (the branch offset) is one byte
8896 long. However, we can relax a section more than once and in that
8897 case we must either set fr_subtype back to the unrelaxed state,
8898 or return the value for the appropriate branch. */
8899 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8902 /* Called after relax() is finished.
8904 In: Address of frag.
8905 fr_type == rs_machine_dependent.
8906 fr_subtype is what the address relaxed to.
8908 Out: Any fixSs and constants are set up.
8909 Caller will turn frag into a ".space 0". */
8912 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8915 unsigned char *opcode
;
8916 unsigned char *where_to_put_displacement
= NULL
;
8917 offsetT target_address
;
8918 offsetT opcode_address
;
8919 unsigned int extension
= 0;
8920 offsetT displacement_from_opcode_start
;
8922 opcode
= (unsigned char *) fragP
->fr_opcode
;
8924 /* Address we want to reach in file space. */
8925 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8927 /* Address opcode resides at in file space. */
8928 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8930 /* Displacement from opcode start to fill into instruction. */
8931 displacement_from_opcode_start
= target_address
- opcode_address
;
8933 if ((fragP
->fr_subtype
& BIG
) == 0)
8935 /* Don't have to change opcode. */
8936 extension
= 1; /* 1 opcode + 1 displacement */
8937 where_to_put_displacement
= &opcode
[1];
8941 if (no_cond_jump_promotion
8942 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8943 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8944 _("long jump required"));
8946 switch (fragP
->fr_subtype
)
8948 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8949 extension
= 4; /* 1 opcode + 4 displacement */
8951 where_to_put_displacement
= &opcode
[1];
8954 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8955 extension
= 2; /* 1 opcode + 2 displacement */
8957 where_to_put_displacement
= &opcode
[1];
8960 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8961 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8962 extension
= 5; /* 2 opcode + 4 displacement */
8963 opcode
[1] = opcode
[0] + 0x10;
8964 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8965 where_to_put_displacement
= &opcode
[2];
8968 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8969 extension
= 3; /* 2 opcode + 2 displacement */
8970 opcode
[1] = opcode
[0] + 0x10;
8971 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8972 where_to_put_displacement
= &opcode
[2];
8975 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8980 where_to_put_displacement
= &opcode
[3];
8984 BAD_CASE (fragP
->fr_subtype
);
8989 /* If size if less then four we are sure that the operand fits,
8990 but if it's 4, then it could be that the displacement is larger
8992 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
8994 && ((addressT
) (displacement_from_opcode_start
- extension
8995 + ((addressT
) 1 << 31))
8996 > (((addressT
) 2 << 31) - 1)))
8998 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
8999 _("jump target out of range"));
9000 /* Make us emit 0. */
9001 displacement_from_opcode_start
= extension
;
9003 /* Now put displacement after opcode. */
9004 md_number_to_chars ((char *) where_to_put_displacement
,
9005 (valueT
) (displacement_from_opcode_start
- extension
),
9006 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9007 fragP
->fr_fix
+= extension
;
9010 /* Apply a fixup (fixP) to segment data, once it has been determined
9011 by our caller that we have all the info we need to fix it up.
9013 Parameter valP is the pointer to the value of the bits.
9015 On the 386, immediates, displacements, and data pointers are all in
9016 the same (little-endian) format, so we don't need to care about which
9020 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9022 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9023 valueT value
= *valP
;
9025 #if !defined (TE_Mach)
9028 switch (fixP
->fx_r_type
)
9034 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9037 case BFD_RELOC_X86_64_32S
:
9038 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9041 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9044 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9049 if (fixP
->fx_addsy
!= NULL
9050 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9051 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9052 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9053 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9054 && !use_rela_relocations
)
9056 /* This is a hack. There should be a better way to handle this.
9057 This covers for the fact that bfd_install_relocation will
9058 subtract the current location (for partial_inplace, PC relative
9059 relocations); see more below. */
9063 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9066 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9068 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9071 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9074 || (symbol_section_p (fixP
->fx_addsy
)
9075 && sym_seg
!= absolute_section
))
9076 && !generic_force_reloc (fixP
))
9078 /* Yes, we add the values in twice. This is because
9079 bfd_install_relocation subtracts them out again. I think
9080 bfd_install_relocation is broken, but I don't dare change
9082 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9086 #if defined (OBJ_COFF) && defined (TE_PE)
9087 /* For some reason, the PE format does not store a
9088 section address offset for a PC relative symbol. */
9089 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9090 || S_IS_WEAK (fixP
->fx_addsy
))
9091 value
+= md_pcrel_from (fixP
);
9094 #if defined (OBJ_COFF) && defined (TE_PE)
9095 if (fixP
->fx_addsy
!= NULL
9096 && S_IS_WEAK (fixP
->fx_addsy
)
9097 /* PR 16858: Do not modify weak function references. */
9098 && ! fixP
->fx_pcrel
)
9100 #if !defined (TE_PEP)
9101 /* For x86 PE weak function symbols are neither PC-relative
9102 nor do they set S_IS_FUNCTION. So the only reliable way
9103 to detect them is to check the flags of their containing
9105 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9106 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9110 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9114 /* Fix a few things - the dynamic linker expects certain values here,
9115 and we must not disappoint it. */
9116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9117 if (IS_ELF
&& fixP
->fx_addsy
)
9118 switch (fixP
->fx_r_type
)
9120 case BFD_RELOC_386_PLT32
:
9121 case BFD_RELOC_X86_64_PLT32
:
9122 /* Make the jump instruction point to the address of the operand. At
9123 runtime we merely add the offset to the actual PLT entry. */
9127 case BFD_RELOC_386_TLS_GD
:
9128 case BFD_RELOC_386_TLS_LDM
:
9129 case BFD_RELOC_386_TLS_IE_32
:
9130 case BFD_RELOC_386_TLS_IE
:
9131 case BFD_RELOC_386_TLS_GOTIE
:
9132 case BFD_RELOC_386_TLS_GOTDESC
:
9133 case BFD_RELOC_X86_64_TLSGD
:
9134 case BFD_RELOC_X86_64_TLSLD
:
9135 case BFD_RELOC_X86_64_GOTTPOFF
:
9136 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9137 value
= 0; /* Fully resolved at runtime. No addend. */
9139 case BFD_RELOC_386_TLS_LE
:
9140 case BFD_RELOC_386_TLS_LDO_32
:
9141 case BFD_RELOC_386_TLS_LE_32
:
9142 case BFD_RELOC_X86_64_DTPOFF32
:
9143 case BFD_RELOC_X86_64_DTPOFF64
:
9144 case BFD_RELOC_X86_64_TPOFF32
:
9145 case BFD_RELOC_X86_64_TPOFF64
:
9146 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9149 case BFD_RELOC_386_TLS_DESC_CALL
:
9150 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9151 value
= 0; /* Fully resolved at runtime. No addend. */
9152 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9156 case BFD_RELOC_386_GOT32
:
9157 case BFD_RELOC_X86_64_GOT32
:
9158 value
= 0; /* Fully resolved at runtime. No addend. */
9161 case BFD_RELOC_VTABLE_INHERIT
:
9162 case BFD_RELOC_VTABLE_ENTRY
:
9169 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9171 #endif /* !defined (TE_Mach) */
9173 /* Are we finished with this relocation now? */
9174 if (fixP
->fx_addsy
== NULL
)
9176 #if defined (OBJ_COFF) && defined (TE_PE)
9177 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9180 /* Remember value for tc_gen_reloc. */
9181 fixP
->fx_addnumber
= value
;
9182 /* Clear out the frag for now. */
9186 else if (use_rela_relocations
)
9188 fixP
->fx_no_overflow
= 1;
9189 /* Remember value for tc_gen_reloc. */
9190 fixP
->fx_addnumber
= value
;
9194 md_number_to_chars (p
, value
, fixP
->fx_size
);
9198 md_atof (int type
, char *litP
, int *sizeP
)
9200 /* This outputs the LITTLENUMs in REVERSE order;
9201 in accord with the bigendian 386. */
9202 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9205 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9208 output_invalid (int c
)
9211 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9214 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9215 "(0x%x)", (unsigned char) c
);
9216 return output_invalid_buf
;
9219 /* REG_STRING starts *before* REGISTER_PREFIX. */
9221 static const reg_entry
*
9222 parse_real_register (char *reg_string
, char **end_op
)
9224 char *s
= reg_string
;
9226 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9229 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9230 if (*s
== REGISTER_PREFIX
)
9233 if (is_space_char (*s
))
9237 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9239 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9240 return (const reg_entry
*) NULL
;
9244 /* For naked regs, make sure that we are not dealing with an identifier.
9245 This prevents confusing an identifier like `eax_var' with register
9247 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9248 return (const reg_entry
*) NULL
;
9252 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9254 /* Handle floating point regs, allowing spaces in the (i) part. */
9255 if (r
== i386_regtab
/* %st is first entry of table */)
9257 if (is_space_char (*s
))
9262 if (is_space_char (*s
))
9264 if (*s
>= '0' && *s
<= '7')
9268 if (is_space_char (*s
))
9273 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9278 /* We have "%st(" then garbage. */
9279 return (const reg_entry
*) NULL
;
9283 if (r
== NULL
|| allow_pseudo_reg
)
9286 if (operand_type_all_zero (&r
->reg_type
))
9287 return (const reg_entry
*) NULL
;
9289 if ((r
->reg_type
.bitfield
.reg32
9290 || r
->reg_type
.bitfield
.sreg3
9291 || r
->reg_type
.bitfield
.control
9292 || r
->reg_type
.bitfield
.debug
9293 || r
->reg_type
.bitfield
.test
)
9294 && !cpu_arch_flags
.bitfield
.cpui386
)
9295 return (const reg_entry
*) NULL
;
9297 if (r
->reg_type
.bitfield
.floatreg
9298 && !cpu_arch_flags
.bitfield
.cpu8087
9299 && !cpu_arch_flags
.bitfield
.cpu287
9300 && !cpu_arch_flags
.bitfield
.cpu387
)
9301 return (const reg_entry
*) NULL
;
9303 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9304 return (const reg_entry
*) NULL
;
9306 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9307 return (const reg_entry
*) NULL
;
9309 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9310 return (const reg_entry
*) NULL
;
9312 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9313 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9314 return (const reg_entry
*) NULL
;
9316 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9317 if (!allow_index_reg
9318 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9319 return (const reg_entry
*) NULL
;
9321 /* Upper 16 vector register is only available with VREX in 64bit
9323 if ((r
->reg_flags
& RegVRex
))
9325 if (!cpu_arch_flags
.bitfield
.cpuvrex
9326 || flag_code
!= CODE_64BIT
)
9327 return (const reg_entry
*) NULL
;
9332 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9333 || r
->reg_type
.bitfield
.reg64
)
9334 && (!cpu_arch_flags
.bitfield
.cpulm
9335 || !operand_type_equal (&r
->reg_type
, &control
))
9336 && flag_code
!= CODE_64BIT
)
9337 return (const reg_entry
*) NULL
;
9339 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9340 return (const reg_entry
*) NULL
;
9345 /* REG_STRING starts *before* REGISTER_PREFIX. */
9347 static const reg_entry
*
9348 parse_register (char *reg_string
, char **end_op
)
9352 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9353 r
= parse_real_register (reg_string
, end_op
);
9358 char *save
= input_line_pointer
;
9362 input_line_pointer
= reg_string
;
9363 c
= get_symbol_end ();
9364 symbolP
= symbol_find (reg_string
);
9365 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9367 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9369 know (e
->X_op
== O_register
);
9370 know (e
->X_add_number
>= 0
9371 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9372 r
= i386_regtab
+ e
->X_add_number
;
9373 if ((r
->reg_flags
& RegVRex
))
9375 *end_op
= input_line_pointer
;
9377 *input_line_pointer
= c
;
9378 input_line_pointer
= save
;
9384 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9387 char *end
= input_line_pointer
;
9390 r
= parse_register (name
, &input_line_pointer
);
9391 if (r
&& end
<= input_line_pointer
)
9393 *nextcharP
= *input_line_pointer
;
9394 *input_line_pointer
= 0;
9395 e
->X_op
= O_register
;
9396 e
->X_add_number
= r
- i386_regtab
;
9399 input_line_pointer
= end
;
9401 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9405 md_operand (expressionS
*e
)
9410 switch (*input_line_pointer
)
9412 case REGISTER_PREFIX
:
9413 r
= parse_real_register (input_line_pointer
, &end
);
9416 e
->X_op
= O_register
;
9417 e
->X_add_number
= r
- i386_regtab
;
9418 input_line_pointer
= end
;
9423 gas_assert (intel_syntax
);
9424 end
= input_line_pointer
++;
9426 if (*input_line_pointer
== ']')
9428 ++input_line_pointer
;
9429 e
->X_op_symbol
= make_expr_symbol (e
);
9430 e
->X_add_symbol
= NULL
;
9431 e
->X_add_number
= 0;
9437 input_line_pointer
= end
;
9444 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9445 const char *md_shortopts
= "kVQ:sqn";
9447 const char *md_shortopts
= "qn";
9450 #define OPTION_32 (OPTION_MD_BASE + 0)
9451 #define OPTION_64 (OPTION_MD_BASE + 1)
9452 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9453 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9454 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9455 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9456 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9457 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9458 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9459 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9460 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9461 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9462 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9463 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9464 #define OPTION_X32 (OPTION_MD_BASE + 14)
9465 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9466 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9467 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9468 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9469 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9470 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9472 struct option md_longopts
[] =
9474 {"32", no_argument
, NULL
, OPTION_32
},
9475 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9476 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9477 {"64", no_argument
, NULL
, OPTION_64
},
9479 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9480 {"x32", no_argument
, NULL
, OPTION_X32
},
9482 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9483 {"march", required_argument
, NULL
, OPTION_MARCH
},
9484 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9485 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9486 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9487 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9488 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9489 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9490 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9491 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9492 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9493 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9494 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9495 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9496 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9497 # if defined (TE_PE) || defined (TE_PEP)
9498 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9500 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9501 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9502 {NULL
, no_argument
, NULL
, 0}
9504 size_t md_longopts_size
= sizeof (md_longopts
);
9507 md_parse_option (int c
, char *arg
)
9515 optimize_align_code
= 0;
9522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9523 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9524 should be emitted or not. FIXME: Not implemented. */
9528 /* -V: SVR4 argument to print version ID. */
9530 print_version_id ();
9533 /* -k: Ignore for FreeBSD compatibility. */
9538 /* -s: On i386 Solaris, this tells the native assembler to use
9539 .stab instead of .stab.excl. We always use .stab anyhow. */
9542 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9543 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9546 const char **list
, **l
;
9548 list
= bfd_target_list ();
9549 for (l
= list
; *l
!= NULL
; l
++)
9550 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9551 || strcmp (*l
, "coff-x86-64") == 0
9552 || strcmp (*l
, "pe-x86-64") == 0
9553 || strcmp (*l
, "pei-x86-64") == 0
9554 || strcmp (*l
, "mach-o-x86-64") == 0)
9556 default_arch
= "x86_64";
9560 as_fatal (_("no compiled in support for x86_64"));
9566 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9570 const char **list
, **l
;
9572 list
= bfd_target_list ();
9573 for (l
= list
; *l
!= NULL
; l
++)
9574 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9576 default_arch
= "x86_64:32";
9580 as_fatal (_("no compiled in support for 32bit x86_64"));
9584 as_fatal (_("32bit x86_64 is only supported for ELF"));
9589 default_arch
= "i386";
9593 #ifdef SVR4_COMMENT_CHARS
9598 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9600 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9604 i386_comment_chars
= n
;
9610 arch
= xstrdup (arg
);
9614 as_fatal (_("invalid -march= option: `%s'"), arg
);
9615 next
= strchr (arch
, '+');
9618 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9620 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9623 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9626 cpu_arch_name
= cpu_arch
[j
].name
;
9627 cpu_sub_arch_name
= NULL
;
9628 cpu_arch_flags
= cpu_arch
[j
].flags
;
9629 cpu_arch_isa
= cpu_arch
[j
].type
;
9630 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9631 if (!cpu_arch_tune_set
)
9633 cpu_arch_tune
= cpu_arch_isa
;
9634 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9638 else if (*cpu_arch
[j
].name
== '.'
9639 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9641 /* ISA entension. */
9642 i386_cpu_flags flags
;
9644 if (!cpu_arch
[j
].negated
)
9645 flags
= cpu_flags_or (cpu_arch_flags
,
9648 flags
= cpu_flags_and_not (cpu_arch_flags
,
9650 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9652 if (cpu_sub_arch_name
)
9654 char *name
= cpu_sub_arch_name
;
9655 cpu_sub_arch_name
= concat (name
,
9657 (const char *) NULL
);
9661 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9662 cpu_arch_flags
= flags
;
9663 cpu_arch_isa_flags
= flags
;
9669 if (j
>= ARRAY_SIZE (cpu_arch
))
9670 as_fatal (_("invalid -march= option: `%s'"), arg
);
9674 while (next
!= NULL
);
9679 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9680 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9682 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9684 cpu_arch_tune_set
= 1;
9685 cpu_arch_tune
= cpu_arch
[j
].type
;
9686 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9690 if (j
>= ARRAY_SIZE (cpu_arch
))
9691 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9694 case OPTION_MMNEMONIC
:
9695 if (strcasecmp (arg
, "att") == 0)
9697 else if (strcasecmp (arg
, "intel") == 0)
9700 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9703 case OPTION_MSYNTAX
:
9704 if (strcasecmp (arg
, "att") == 0)
9706 else if (strcasecmp (arg
, "intel") == 0)
9709 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9712 case OPTION_MINDEX_REG
:
9713 allow_index_reg
= 1;
9716 case OPTION_MNAKED_REG
:
9717 allow_naked_reg
= 1;
9720 case OPTION_MOLD_GCC
:
9724 case OPTION_MSSE2AVX
:
9728 case OPTION_MSSE_CHECK
:
9729 if (strcasecmp (arg
, "error") == 0)
9730 sse_check
= check_error
;
9731 else if (strcasecmp (arg
, "warning") == 0)
9732 sse_check
= check_warning
;
9733 else if (strcasecmp (arg
, "none") == 0)
9734 sse_check
= check_none
;
9736 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9739 case OPTION_MOPERAND_CHECK
:
9740 if (strcasecmp (arg
, "error") == 0)
9741 operand_check
= check_error
;
9742 else if (strcasecmp (arg
, "warning") == 0)
9743 operand_check
= check_warning
;
9744 else if (strcasecmp (arg
, "none") == 0)
9745 operand_check
= check_none
;
9747 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9750 case OPTION_MAVXSCALAR
:
9751 if (strcasecmp (arg
, "128") == 0)
9753 else if (strcasecmp (arg
, "256") == 0)
9756 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9759 case OPTION_MADD_BND_PREFIX
:
9763 case OPTION_MEVEXLIG
:
9764 if (strcmp (arg
, "128") == 0)
9766 else if (strcmp (arg
, "256") == 0)
9768 else if (strcmp (arg
, "512") == 0)
9771 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9774 case OPTION_MEVEXRCIG
:
9775 if (strcmp (arg
, "rne") == 0)
9777 else if (strcmp (arg
, "rd") == 0)
9779 else if (strcmp (arg
, "ru") == 0)
9781 else if (strcmp (arg
, "rz") == 0)
9784 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9787 case OPTION_MEVEXWIG
:
9788 if (strcmp (arg
, "0") == 0)
9790 else if (strcmp (arg
, "1") == 0)
9793 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9796 # if defined (TE_PE) || defined (TE_PEP)
9797 case OPTION_MBIG_OBJ
:
9802 case OPTION_OMIT_LOCK_PREFIX
:
9803 if (strcasecmp (arg
, "yes") == 0)
9804 omit_lock_prefix
= 1;
9805 else if (strcasecmp (arg
, "no") == 0)
9806 omit_lock_prefix
= 0;
9808 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9817 #define MESSAGE_TEMPLATE \
9821 show_arch (FILE *stream
, int ext
, int check
)
9823 static char message
[] = MESSAGE_TEMPLATE
;
9824 char *start
= message
+ 27;
9826 int size
= sizeof (MESSAGE_TEMPLATE
);
9833 left
= size
- (start
- message
);
9834 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9836 /* Should it be skipped? */
9837 if (cpu_arch
[j
].skip
)
9840 name
= cpu_arch
[j
].name
;
9841 len
= cpu_arch
[j
].len
;
9844 /* It is an extension. Skip if we aren't asked to show it. */
9855 /* It is an processor. Skip if we show only extension. */
9858 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9860 /* It is an impossible processor - skip. */
9864 /* Reserve 2 spaces for ", " or ",\0" */
9867 /* Check if there is any room. */
9875 p
= mempcpy (p
, name
, len
);
9879 /* Output the current message now and start a new one. */
9882 fprintf (stream
, "%s\n", message
);
9884 left
= size
- (start
- message
) - len
- 2;
9886 gas_assert (left
>= 0);
9888 p
= mempcpy (p
, name
, len
);
9893 fprintf (stream
, "%s\n", message
);
9897 md_show_usage (FILE *stream
)
9899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9900 fprintf (stream
, _("\
9902 -V print assembler version number\n\
9905 fprintf (stream
, _("\
9906 -n Do not optimize code alignment\n\
9907 -q quieten some warnings\n"));
9908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9909 fprintf (stream
, _("\
9912 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9913 || defined (TE_PE) || defined (TE_PEP))
9914 fprintf (stream
, _("\
9915 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9917 #ifdef SVR4_COMMENT_CHARS
9918 fprintf (stream
, _("\
9919 --divide do not treat `/' as a comment character\n"));
9921 fprintf (stream
, _("\
9922 --divide ignored\n"));
9924 fprintf (stream
, _("\
9925 -march=CPU[,+EXTENSION...]\n\
9926 generate code for CPU and EXTENSION, CPU is one of:\n"));
9927 show_arch (stream
, 0, 1);
9928 fprintf (stream
, _("\
9929 EXTENSION is combination of:\n"));
9930 show_arch (stream
, 1, 0);
9931 fprintf (stream
, _("\
9932 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9933 show_arch (stream
, 0, 0);
9934 fprintf (stream
, _("\
9935 -msse2avx encode SSE instructions with VEX prefix\n"));
9936 fprintf (stream
, _("\
9937 -msse-check=[none|error|warning]\n\
9938 check SSE instructions\n"));
9939 fprintf (stream
, _("\
9940 -moperand-check=[none|error|warning]\n\
9941 check operand combinations for validity\n"));
9942 fprintf (stream
, _("\
9943 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9945 fprintf (stream
, _("\
9946 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9948 fprintf (stream
, _("\
9949 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9950 for EVEX.W bit ignored instructions\n"));
9951 fprintf (stream
, _("\
9952 -mevexrcig=[rne|rd|ru|rz]\n\
9953 encode EVEX instructions with specific EVEX.RC value\n\
9954 for SAE-only ignored instructions\n"));
9955 fprintf (stream
, _("\
9956 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9957 fprintf (stream
, _("\
9958 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9959 fprintf (stream
, _("\
9960 -mindex-reg support pseudo index registers\n"));
9961 fprintf (stream
, _("\
9962 -mnaked-reg don't require `%%' prefix for registers\n"));
9963 fprintf (stream
, _("\
9964 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9965 fprintf (stream
, _("\
9966 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9967 # if defined (TE_PE) || defined (TE_PEP)
9968 fprintf (stream
, _("\
9969 -mbig-obj generate big object files\n"));
9971 fprintf (stream
, _("\
9972 -momit-lock-prefix=[no|yes]\n\
9973 strip all lock prefixes\n"));
9976 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9977 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9978 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9980 /* Pick the target format to use. */
9983 i386_target_format (void)
9985 if (!strncmp (default_arch
, "x86_64", 6))
9987 update_code_flag (CODE_64BIT
, 1);
9988 if (default_arch
[6] == '\0')
9989 x86_elf_abi
= X86_64_ABI
;
9991 x86_elf_abi
= X86_64_X32_ABI
;
9993 else if (!strcmp (default_arch
, "i386"))
9994 update_code_flag (CODE_32BIT
, 1);
9996 as_fatal (_("unknown architecture"));
9998 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9999 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10000 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10001 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10003 switch (OUTPUT_FLAVOR
)
10005 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10006 case bfd_target_aout_flavour
:
10007 return AOUT_TARGET_FORMAT
;
10009 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10010 # if defined (TE_PE) || defined (TE_PEP)
10011 case bfd_target_coff_flavour
:
10012 if (flag_code
== CODE_64BIT
)
10013 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10016 # elif defined (TE_GO32)
10017 case bfd_target_coff_flavour
:
10018 return "coff-go32";
10020 case bfd_target_coff_flavour
:
10021 return "coff-i386";
10024 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10025 case bfd_target_elf_flavour
:
10027 const char *format
;
10029 switch (x86_elf_abi
)
10032 format
= ELF_TARGET_FORMAT
;
10035 use_rela_relocations
= 1;
10037 format
= ELF_TARGET_FORMAT64
;
10039 case X86_64_X32_ABI
:
10040 use_rela_relocations
= 1;
10042 disallow_64bit_reloc
= 1;
10043 format
= ELF_TARGET_FORMAT32
;
10046 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10048 if (x86_elf_abi
!= X86_64_ABI
)
10049 as_fatal (_("Intel L1OM is 64bit only"));
10050 return ELF_TARGET_L1OM_FORMAT
;
10052 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10054 if (x86_elf_abi
!= X86_64_ABI
)
10055 as_fatal (_("Intel K1OM is 64bit only"));
10056 return ELF_TARGET_K1OM_FORMAT
;
10062 #if defined (OBJ_MACH_O)
10063 case bfd_target_mach_o_flavour
:
10064 if (flag_code
== CODE_64BIT
)
10066 use_rela_relocations
= 1;
10068 return "mach-o-x86-64";
10071 return "mach-o-i386";
10079 #endif /* OBJ_MAYBE_ more than one */
10082 md_undefined_symbol (char *name
)
10084 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10085 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10086 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10087 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10091 if (symbol_find (name
))
10092 as_bad (_("GOT already in symbol table"));
10093 GOT_symbol
= symbol_new (name
, undefined_section
,
10094 (valueT
) 0, &zero_address_frag
);
10101 /* Round up a section size to the appropriate boundary. */
10104 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10106 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10107 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10109 /* For a.out, force the section size to be aligned. If we don't do
10110 this, BFD will align it for us, but it will not write out the
10111 final bytes of the section. This may be a bug in BFD, but it is
10112 easier to fix it here since that is how the other a.out targets
10116 align
= bfd_get_section_alignment (stdoutput
, segment
);
10117 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10124 /* On the i386, PC-relative offsets are relative to the start of the
10125 next instruction. That is, the address of the offset, plus its
10126 size, since the offset is always the last part of the insn. */
10129 md_pcrel_from (fixS
*fixP
)
10131 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10137 s_bss (int ignore ATTRIBUTE_UNUSED
)
10141 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10143 obj_elf_section_change_hook ();
10145 temp
= get_absolute_expression ();
10146 subseg_set (bss_section
, (subsegT
) temp
);
10147 demand_empty_rest_of_line ();
10153 i386_validate_fix (fixS
*fixp
)
10155 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10157 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10161 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10166 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10168 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10170 fixp
->fx_subsy
= 0;
10175 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10178 bfd_reloc_code_real_type code
;
10180 switch (fixp
->fx_r_type
)
10182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10183 case BFD_RELOC_SIZE32
:
10184 case BFD_RELOC_SIZE64
:
10185 if (S_IS_DEFINED (fixp
->fx_addsy
)
10186 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10188 /* Resolve size relocation against local symbol to size of
10189 the symbol plus addend. */
10190 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10191 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10192 && !fits_in_unsigned_long (value
))
10193 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10194 _("symbol size computation overflow"));
10195 fixp
->fx_addsy
= NULL
;
10196 fixp
->fx_subsy
= NULL
;
10197 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10202 case BFD_RELOC_X86_64_PLT32
:
10203 case BFD_RELOC_X86_64_GOT32
:
10204 case BFD_RELOC_X86_64_GOTPCREL
:
10205 case BFD_RELOC_386_PLT32
:
10206 case BFD_RELOC_386_GOT32
:
10207 case BFD_RELOC_386_GOTOFF
:
10208 case BFD_RELOC_386_GOTPC
:
10209 case BFD_RELOC_386_TLS_GD
:
10210 case BFD_RELOC_386_TLS_LDM
:
10211 case BFD_RELOC_386_TLS_LDO_32
:
10212 case BFD_RELOC_386_TLS_IE_32
:
10213 case BFD_RELOC_386_TLS_IE
:
10214 case BFD_RELOC_386_TLS_GOTIE
:
10215 case BFD_RELOC_386_TLS_LE_32
:
10216 case BFD_RELOC_386_TLS_LE
:
10217 case BFD_RELOC_386_TLS_GOTDESC
:
10218 case BFD_RELOC_386_TLS_DESC_CALL
:
10219 case BFD_RELOC_X86_64_TLSGD
:
10220 case BFD_RELOC_X86_64_TLSLD
:
10221 case BFD_RELOC_X86_64_DTPOFF32
:
10222 case BFD_RELOC_X86_64_DTPOFF64
:
10223 case BFD_RELOC_X86_64_GOTTPOFF
:
10224 case BFD_RELOC_X86_64_TPOFF32
:
10225 case BFD_RELOC_X86_64_TPOFF64
:
10226 case BFD_RELOC_X86_64_GOTOFF64
:
10227 case BFD_RELOC_X86_64_GOTPC32
:
10228 case BFD_RELOC_X86_64_GOT64
:
10229 case BFD_RELOC_X86_64_GOTPCREL64
:
10230 case BFD_RELOC_X86_64_GOTPC64
:
10231 case BFD_RELOC_X86_64_GOTPLT64
:
10232 case BFD_RELOC_X86_64_PLTOFF64
:
10233 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10234 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10235 case BFD_RELOC_RVA
:
10236 case BFD_RELOC_VTABLE_ENTRY
:
10237 case BFD_RELOC_VTABLE_INHERIT
:
10239 case BFD_RELOC_32_SECREL
:
10241 code
= fixp
->fx_r_type
;
10243 case BFD_RELOC_X86_64_32S
:
10244 if (!fixp
->fx_pcrel
)
10246 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10247 code
= fixp
->fx_r_type
;
10251 if (fixp
->fx_pcrel
)
10253 switch (fixp
->fx_size
)
10256 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10257 _("can not do %d byte pc-relative relocation"),
10259 code
= BFD_RELOC_32_PCREL
;
10261 case 1: code
= BFD_RELOC_8_PCREL
; break;
10262 case 2: code
= BFD_RELOC_16_PCREL
; break;
10263 case 4: code
= BFD_RELOC_32_PCREL
; break;
10265 case 8: code
= BFD_RELOC_64_PCREL
; break;
10271 switch (fixp
->fx_size
)
10274 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10275 _("can not do %d byte relocation"),
10277 code
= BFD_RELOC_32
;
10279 case 1: code
= BFD_RELOC_8
; break;
10280 case 2: code
= BFD_RELOC_16
; break;
10281 case 4: code
= BFD_RELOC_32
; break;
10283 case 8: code
= BFD_RELOC_64
; break;
10290 if ((code
== BFD_RELOC_32
10291 || code
== BFD_RELOC_32_PCREL
10292 || code
== BFD_RELOC_X86_64_32S
)
10294 && fixp
->fx_addsy
== GOT_symbol
)
10297 code
= BFD_RELOC_386_GOTPC
;
10299 code
= BFD_RELOC_X86_64_GOTPC32
;
10301 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10303 && fixp
->fx_addsy
== GOT_symbol
)
10305 code
= BFD_RELOC_X86_64_GOTPC64
;
10308 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10309 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10310 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10312 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10314 if (!use_rela_relocations
)
10316 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10317 vtable entry to be used in the relocation's section offset. */
10318 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10319 rel
->address
= fixp
->fx_offset
;
10320 #if defined (OBJ_COFF) && defined (TE_PE)
10321 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10322 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10327 /* Use the rela in 64bit mode. */
10330 if (disallow_64bit_reloc
)
10333 case BFD_RELOC_X86_64_DTPOFF64
:
10334 case BFD_RELOC_X86_64_TPOFF64
:
10335 case BFD_RELOC_64_PCREL
:
10336 case BFD_RELOC_X86_64_GOTOFF64
:
10337 case BFD_RELOC_X86_64_GOT64
:
10338 case BFD_RELOC_X86_64_GOTPCREL64
:
10339 case BFD_RELOC_X86_64_GOTPC64
:
10340 case BFD_RELOC_X86_64_GOTPLT64
:
10341 case BFD_RELOC_X86_64_PLTOFF64
:
10342 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10343 _("cannot represent relocation type %s in x32 mode"),
10344 bfd_get_reloc_code_name (code
));
10350 if (!fixp
->fx_pcrel
)
10351 rel
->addend
= fixp
->fx_offset
;
10355 case BFD_RELOC_X86_64_PLT32
:
10356 case BFD_RELOC_X86_64_GOT32
:
10357 case BFD_RELOC_X86_64_GOTPCREL
:
10358 case BFD_RELOC_X86_64_TLSGD
:
10359 case BFD_RELOC_X86_64_TLSLD
:
10360 case BFD_RELOC_X86_64_GOTTPOFF
:
10361 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10362 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10363 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10366 rel
->addend
= (section
->vma
10368 + fixp
->fx_addnumber
10369 + md_pcrel_from (fixp
));
10374 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10375 if (rel
->howto
== NULL
)
10377 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10378 _("cannot represent relocation type %s"),
10379 bfd_get_reloc_code_name (code
));
10380 /* Set howto to a garbage value so that we can keep going. */
10381 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10382 gas_assert (rel
->howto
!= NULL
);
10388 #include "tc-i386-intel.c"
10391 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10393 int saved_naked_reg
;
10394 char saved_register_dot
;
10396 saved_naked_reg
= allow_naked_reg
;
10397 allow_naked_reg
= 1;
10398 saved_register_dot
= register_chars
['.'];
10399 register_chars
['.'] = '.';
10400 allow_pseudo_reg
= 1;
10401 expression_and_evaluate (exp
);
10402 allow_pseudo_reg
= 0;
10403 register_chars
['.'] = saved_register_dot
;
10404 allow_naked_reg
= saved_naked_reg
;
10406 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10408 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10410 exp
->X_op
= O_constant
;
10411 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10412 .dw2_regnum
[flag_code
>> 1];
10415 exp
->X_op
= O_illegal
;
10420 tc_x86_frame_initial_instructions (void)
10422 static unsigned int sp_regno
[2];
10424 if (!sp_regno
[flag_code
>> 1])
10426 char *saved_input
= input_line_pointer
;
10427 char sp
[][4] = {"esp", "rsp"};
10430 input_line_pointer
= sp
[flag_code
>> 1];
10431 tc_x86_parse_to_dw2regnum (&exp
);
10432 gas_assert (exp
.X_op
== O_constant
);
10433 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10434 input_line_pointer
= saved_input
;
10437 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10438 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10442 x86_dwarf2_addr_size (void)
10444 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10445 if (x86_elf_abi
== X86_64_X32_ABI
)
10448 return bfd_arch_bits_per_address (stdoutput
) / 8;
10452 i386_elf_section_type (const char *str
, size_t len
)
10454 if (flag_code
== CODE_64BIT
10455 && len
== sizeof ("unwind") - 1
10456 && strncmp (str
, "unwind", 6) == 0)
10457 return SHT_X86_64_UNWIND
;
10464 i386_solaris_fix_up_eh_frame (segT sec
)
10466 if (flag_code
== CODE_64BIT
)
10467 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10473 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10477 exp
.X_op
= O_secrel
;
10478 exp
.X_add_symbol
= symbol
;
10479 exp
.X_add_number
= 0;
10480 emit_expr (&exp
, size
);
10484 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10485 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10488 x86_64_section_letter (int letter
, char **ptr_msg
)
10490 if (flag_code
== CODE_64BIT
)
10493 return SHF_X86_64_LARGE
;
10495 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10498 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10503 x86_64_section_word (char *str
, size_t len
)
10505 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10506 return SHF_X86_64_LARGE
;
10512 handle_large_common (int small ATTRIBUTE_UNUSED
)
10514 if (flag_code
!= CODE_64BIT
)
10516 s_comm_internal (0, elf_common_parse
);
10517 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10521 static segT lbss_section
;
10522 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10523 asection
*saved_bss_section
= bss_section
;
10525 if (lbss_section
== NULL
)
10527 flagword applicable
;
10528 segT seg
= now_seg
;
10529 subsegT subseg
= now_subseg
;
10531 /* The .lbss section is for local .largecomm symbols. */
10532 lbss_section
= subseg_new (".lbss", 0);
10533 applicable
= bfd_applicable_section_flags (stdoutput
);
10534 bfd_set_section_flags (stdoutput
, lbss_section
,
10535 applicable
& SEC_ALLOC
);
10536 seg_info (lbss_section
)->bss
= 1;
10538 subseg_set (seg
, subseg
);
10541 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10542 bss_section
= lbss_section
;
10544 s_comm_internal (0, elf_common_parse
);
10546 elf_com_section_ptr
= saved_com_section_ptr
;
10547 bss_section
= saved_bss_section
;
10550 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */