1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPCODE_LENGTH holds the number of base opcode bytes. */
318 unsigned char opcode_length
;
320 /* OPERANDS gives the number of given operands. */
321 unsigned int operands
;
323 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
324 of given register, displacement, memory operands and immediate
326 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
328 /* TYPES [i] is the type (see above #defines) which tells us how to
329 use OP[i] for the corresponding operand. */
330 i386_operand_type types
[MAX_OPERANDS
];
332 /* Displacement expression, immediate expression, or register for each
334 union i386_op op
[MAX_OPERANDS
];
336 /* Flags for operands. */
337 unsigned int flags
[MAX_OPERANDS
];
338 #define Operand_PCrel 1
339 #define Operand_Mem 2
341 /* Relocation type for operand */
342 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
344 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
345 the base index byte below. */
346 const reg_entry
*base_reg
;
347 const reg_entry
*index_reg
;
348 unsigned int log2_scale_factor
;
350 /* SEG gives the seg_entries of this insn. They are zero unless
351 explicit segment overrides are given. */
352 const seg_entry
*seg
[2];
354 /* Copied first memory operand string, for re-checking. */
357 /* PREFIX holds all the given prefix opcodes (usually null).
358 PREFIXES is the number of prefix opcodes. */
359 unsigned int prefixes
;
360 unsigned char prefix
[MAX_PREFIXES
];
362 /* Register is in low 3 bits of opcode. */
363 bfd_boolean short_form
;
365 /* The operand to a branch insn indicates an absolute branch. */
366 bfd_boolean jumpabsolute
;
368 /* Extended states. */
376 xstate_ymm
= 1 << 2 | xstate_xmm
,
378 xstate_zmm
= 1 << 3 | xstate_ymm
,
381 /* Use MASK state. */
385 /* Has GOTPC or TLS relocation. */
386 bfd_boolean has_gotpc_tls_reloc
;
388 /* RM and SIB are the modrm byte and the sib byte where the
389 addressing modes of this insn are encoded. */
396 /* Masking attributes. */
397 struct Mask_Operation
*mask
;
399 /* Rounding control and SAE attributes. */
400 struct RC_Operation
*rounding
;
402 /* Broadcasting attributes. */
403 struct Broadcast_Operation
*broadcast
;
405 /* Compressed disp8*N attribute. */
406 unsigned int memshift
;
408 /* Prefer load or store in encoding. */
411 dir_encoding_default
= 0,
417 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
420 disp_encoding_default
= 0,
426 /* Prefer the REX byte in encoding. */
427 bfd_boolean rex_encoding
;
429 /* Disable instruction size optimization. */
430 bfd_boolean no_optimize
;
432 /* How to encode vector instructions. */
435 vex_encoding_default
= 0,
443 const char *rep_prefix
;
446 const char *hle_prefix
;
448 /* Have BND prefix. */
449 const char *bnd_prefix
;
451 /* Have NOTRACK prefix. */
452 const char *notrack_prefix
;
455 enum i386_error error
;
458 typedef struct _i386_insn i386_insn
;
460 /* Link RC type with corresponding string, that'll be looked for in
469 static const struct RC_name RC_NamesTable
[] =
471 { rne
, STRING_COMMA_LEN ("rn-sae") },
472 { rd
, STRING_COMMA_LEN ("rd-sae") },
473 { ru
, STRING_COMMA_LEN ("ru-sae") },
474 { rz
, STRING_COMMA_LEN ("rz-sae") },
475 { saeonly
, STRING_COMMA_LEN ("sae") },
478 /* List of chars besides those in app.c:symbol_chars that can start an
479 operand. Used to prevent the scrubber eating vital white-space. */
480 const char extra_symbol_chars
[] = "*%-([{}"
489 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
490 && !defined (TE_GNU) \
491 && !defined (TE_LINUX) \
492 && !defined (TE_FreeBSD) \
493 && !defined (TE_DragonFly) \
494 && !defined (TE_NetBSD))
495 /* This array holds the chars that always start a comment. If the
496 pre-processor is disabled, these aren't very useful. The option
497 --divide will remove '/' from this list. */
498 const char *i386_comment_chars
= "#/";
499 #define SVR4_COMMENT_CHARS 1
500 #define PREFIX_SEPARATOR '\\'
503 const char *i386_comment_chars
= "#";
504 #define PREFIX_SEPARATOR '/'
507 /* This array holds the chars that only start a comment at the beginning of
508 a line. If the line seems to have the form '# 123 filename'
509 .line and .file directives will appear in the pre-processed output.
510 Note that input_file.c hand checks for '#' at the beginning of the
511 first line of the input file. This is because the compiler outputs
512 #NO_APP at the beginning of its output.
513 Also note that comments started like this one will always work if
514 '/' isn't otherwise defined. */
515 const char line_comment_chars
[] = "#/";
517 const char line_separator_chars
[] = ";";
519 /* Chars that can be used to separate mant from exp in floating point
521 const char EXP_CHARS
[] = "eE";
523 /* Chars that mean this number is a floating point constant
526 const char FLT_CHARS
[] = "fFdDxX";
528 /* Tables for lexical analysis. */
529 static char mnemonic_chars
[256];
530 static char register_chars
[256];
531 static char operand_chars
[256];
532 static char identifier_chars
[256];
533 static char digit_chars
[256];
535 /* Lexical macros. */
536 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
537 #define is_operand_char(x) (operand_chars[(unsigned char) x])
538 #define is_register_char(x) (register_chars[(unsigned char) x])
539 #define is_space_char(x) ((x) == ' ')
540 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
541 #define is_digit_char(x) (digit_chars[(unsigned char) x])
543 /* All non-digit non-letter characters that may occur in an operand. */
544 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
546 /* md_assemble() always leaves the strings it's passed unaltered. To
547 effect this we maintain a stack of saved characters that we've smashed
548 with '\0's (indicating end of strings for various sub-fields of the
549 assembler instruction). */
550 static char save_stack
[32];
551 static char *save_stack_p
;
552 #define END_STRING_AND_SAVE(s) \
553 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
554 #define RESTORE_END_STRING(s) \
555 do { *(s) = *--save_stack_p; } while (0)
557 /* The instruction we're assembling. */
560 /* Possible templates for current insn. */
561 static const templates
*current_templates
;
563 /* Per instruction expressionS buffers: max displacements & immediates. */
564 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
565 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
567 /* Current operand we are working on. */
568 static int this_operand
= -1;
570 /* We support four different modes. FLAG_CODE variable is used to distinguish
578 static enum flag_code flag_code
;
579 static unsigned int object_64bit
;
580 static unsigned int disallow_64bit_reloc
;
581 static int use_rela_relocations
= 0;
582 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
583 static const char *tls_get_addr
;
585 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
586 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
587 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
589 /* The ELF ABI to use. */
597 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
600 #if defined (TE_PE) || defined (TE_PEP)
601 /* Use big object file format. */
602 static int use_big_obj
= 0;
605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
606 /* 1 if generating code for a shared library. */
607 static int shared
= 0;
610 /* 1 for intel syntax,
612 static int intel_syntax
= 0;
614 static enum x86_64_isa
616 amd64
= 1, /* AMD64 ISA. */
617 intel64
/* Intel64 ISA. */
620 /* 1 for intel mnemonic,
621 0 if att mnemonic. */
622 static int intel_mnemonic
= !SYSV386_COMPAT
;
624 /* 1 if pseudo registers are permitted. */
625 static int allow_pseudo_reg
= 0;
627 /* 1 if register prefix % not required. */
628 static int allow_naked_reg
= 0;
630 /* 1 if the assembler should add BND prefix for all control-transferring
631 instructions supporting it, even if this prefix wasn't specified
633 static int add_bnd_prefix
= 0;
635 /* 1 if pseudo index register, eiz/riz, is allowed . */
636 static int allow_index_reg
= 0;
638 /* 1 if the assembler should ignore LOCK prefix, even if it was
639 specified explicitly. */
640 static int omit_lock_prefix
= 0;
642 /* 1 if the assembler should encode lfence, mfence, and sfence as
643 "lock addl $0, (%{re}sp)". */
644 static int avoid_fence
= 0;
646 /* 1 if lfence should be inserted after every load. */
647 static int lfence_after_load
= 0;
649 /* Non-zero if lfence should be inserted before indirect branch. */
650 static enum lfence_before_indirect_branch_kind
652 lfence_branch_none
= 0,
653 lfence_branch_register
,
654 lfence_branch_memory
,
657 lfence_before_indirect_branch
;
659 /* Non-zero if lfence should be inserted before ret. */
660 static enum lfence_before_ret_kind
662 lfence_before_ret_none
= 0,
663 lfence_before_ret_not
,
664 lfence_before_ret_or
,
665 lfence_before_ret_shl
669 /* Types of previous instruction is .byte or prefix. */
684 /* 1 if the assembler should generate relax relocations. */
686 static int generate_relax_relocations
687 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
689 static enum check_kind
695 sse_check
, operand_check
= check_warning
;
697 /* Non-zero if branches should be aligned within power of 2 boundary. */
698 static int align_branch_power
= 0;
700 /* Types of branches to align. */
701 enum align_branch_kind
703 align_branch_none
= 0,
704 align_branch_jcc
= 1,
705 align_branch_fused
= 2,
706 align_branch_jmp
= 3,
707 align_branch_call
= 4,
708 align_branch_indirect
= 5,
712 /* Type bits of branches to align. */
713 enum align_branch_bit
715 align_branch_jcc_bit
= 1 << align_branch_jcc
,
716 align_branch_fused_bit
= 1 << align_branch_fused
,
717 align_branch_jmp_bit
= 1 << align_branch_jmp
,
718 align_branch_call_bit
= 1 << align_branch_call
,
719 align_branch_indirect_bit
= 1 << align_branch_indirect
,
720 align_branch_ret_bit
= 1 << align_branch_ret
723 static unsigned int align_branch
= (align_branch_jcc_bit
724 | align_branch_fused_bit
725 | align_branch_jmp_bit
);
727 /* Types of condition jump used by macro-fusion. */
730 mf_jcc_jo
= 0, /* base opcode 0x70 */
731 mf_jcc_jc
, /* base opcode 0x72 */
732 mf_jcc_je
, /* base opcode 0x74 */
733 mf_jcc_jna
, /* base opcode 0x76 */
734 mf_jcc_js
, /* base opcode 0x78 */
735 mf_jcc_jp
, /* base opcode 0x7a */
736 mf_jcc_jl
, /* base opcode 0x7c */
737 mf_jcc_jle
, /* base opcode 0x7e */
740 /* Types of compare flag-modifying insntructions used by macro-fusion. */
743 mf_cmp_test_and
, /* test/cmp */
744 mf_cmp_alu_cmp
, /* add/sub/cmp */
745 mf_cmp_incdec
/* inc/dec */
748 /* The maximum padding size for fused jcc. CMP like instruction can
749 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
751 #define MAX_FUSED_JCC_PADDING_SIZE 20
753 /* The maximum number of prefixes added for an instruction. */
754 static unsigned int align_branch_prefix_size
= 5;
757 1. Clear the REX_W bit with register operand if possible.
758 2. Above plus use 128bit vector instruction to clear the full vector
761 static int optimize
= 0;
764 1. Clear the REX_W bit with register operand if possible.
765 2. Above plus use 128bit vector instruction to clear the full vector
767 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
770 static int optimize_for_space
= 0;
772 /* Register prefix used for error message. */
773 static const char *register_prefix
= "%";
775 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
776 leave, push, and pop instructions so that gcc has the same stack
777 frame as in 32 bit mode. */
778 static char stackop_size
= '\0';
780 /* Non-zero to optimize code alignment. */
781 int optimize_align_code
= 1;
783 /* Non-zero to quieten some warnings. */
784 static int quiet_warnings
= 0;
787 static const char *cpu_arch_name
= NULL
;
788 static char *cpu_sub_arch_name
= NULL
;
790 /* CPU feature flags. */
791 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
793 /* If we have selected a cpu we are generating instructions for. */
794 static int cpu_arch_tune_set
= 0;
796 /* Cpu we are generating instructions for. */
797 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
799 /* CPU feature flags of cpu we are generating instructions for. */
800 static i386_cpu_flags cpu_arch_tune_flags
;
802 /* CPU instruction set architecture used. */
803 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
805 /* CPU feature flags of instruction set architecture used. */
806 i386_cpu_flags cpu_arch_isa_flags
;
808 /* If set, conditional jumps are not automatically promoted to handle
809 larger than a byte offset. */
810 static unsigned int no_cond_jump_promotion
= 0;
812 /* Encode SSE instructions with VEX prefix. */
813 static unsigned int sse2avx
;
815 /* Encode scalar AVX instructions with specific vector length. */
822 /* Encode VEX WIG instructions with specific vex.w. */
829 /* Encode scalar EVEX LIG instructions with specific vector length. */
837 /* Encode EVEX WIG instructions with specific evex.w. */
844 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
845 static enum rc_type evexrcig
= rne
;
847 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
848 static symbolS
*GOT_symbol
;
850 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
851 unsigned int x86_dwarf2_return_column
;
853 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
854 int x86_cie_data_alignment
;
856 /* Interface to relax_segment.
857 There are 3 major relax states for 386 jump insns because the
858 different types of jumps add different sizes to frags when we're
859 figuring out what sort of jump to choose to reach a given label.
861 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
862 branches which are handled by md_estimate_size_before_relax() and
863 i386_generic_table_relax_frag(). */
866 #define UNCOND_JUMP 0
868 #define COND_JUMP86 2
869 #define BRANCH_PADDING 3
870 #define BRANCH_PREFIX 4
871 #define FUSED_JCC_PADDING 5
876 #define SMALL16 (SMALL | CODE16)
878 #define BIG16 (BIG | CODE16)
882 #define INLINE __inline__
888 #define ENCODE_RELAX_STATE(type, size) \
889 ((relax_substateT) (((type) << 2) | (size)))
890 #define TYPE_FROM_RELAX_STATE(s) \
892 #define DISP_SIZE_FROM_RELAX_STATE(s) \
893 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
895 /* This table is used by relax_frag to promote short jumps to long
896 ones where necessary. SMALL (short) jumps may be promoted to BIG
897 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
898 don't allow a short jump in a 32 bit code segment to be promoted to
899 a 16 bit offset jump because it's slower (requires data size
900 prefix), and doesn't work, unless the destination is in the bottom
901 64k of the code segment (The top 16 bits of eip are zeroed). */
903 const relax_typeS md_relax_table
[] =
906 1) most positive reach of this state,
907 2) most negative reach of this state,
908 3) how many bytes this mode will have in the variable part of the frag
909 4) which index into the table to try if we can't fit into this one. */
911 /* UNCOND_JUMP states. */
912 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
914 /* dword jmp adds 4 bytes to frag:
915 0 extra opcode bytes, 4 displacement bytes. */
917 /* word jmp adds 2 byte2 to frag:
918 0 extra opcode bytes, 2 displacement bytes. */
921 /* COND_JUMP states. */
922 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
924 /* dword conditionals adds 5 bytes to frag:
925 1 extra opcode byte, 4 displacement bytes. */
927 /* word conditionals add 3 bytes to frag:
928 1 extra opcode byte, 2 displacement bytes. */
931 /* COND_JUMP86 states. */
932 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
933 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
934 /* dword conditionals adds 5 bytes to frag:
935 1 extra opcode byte, 4 displacement bytes. */
937 /* word conditionals add 4 bytes to frag:
938 1 displacement byte and a 3 byte long branch insn. */
942 static const arch_entry cpu_arch
[] =
944 /* Do not replace the first two entries - i386_target_format()
945 relies on them being there in this order. */
946 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
947 CPU_GENERIC32_FLAGS
, 0 },
948 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
949 CPU_GENERIC64_FLAGS
, 0 },
950 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
952 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
958 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
960 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
962 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
964 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
966 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
967 CPU_PENTIUMPRO_FLAGS
, 0 },
968 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
970 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
972 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
974 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
976 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
977 CPU_NOCONA_FLAGS
, 0 },
978 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
980 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
982 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
983 CPU_CORE2_FLAGS
, 1 },
984 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
985 CPU_CORE2_FLAGS
, 0 },
986 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
987 CPU_COREI7_FLAGS
, 0 },
988 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
990 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
992 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
993 CPU_IAMCU_FLAGS
, 0 },
994 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
996 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
998 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
999 CPU_ATHLON_FLAGS
, 0 },
1000 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
1002 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
1004 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1006 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1007 CPU_AMDFAM10_FLAGS
, 0 },
1008 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1009 CPU_BDVER1_FLAGS
, 0 },
1010 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1011 CPU_BDVER2_FLAGS
, 0 },
1012 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1013 CPU_BDVER3_FLAGS
, 0 },
1014 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1015 CPU_BDVER4_FLAGS
, 0 },
1016 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1017 CPU_ZNVER1_FLAGS
, 0 },
1018 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1019 CPU_ZNVER2_FLAGS
, 0 },
1020 { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER
,
1021 CPU_ZNVER3_FLAGS
, 0 },
1022 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1023 CPU_BTVER1_FLAGS
, 0 },
1024 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1025 CPU_BTVER2_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1027 CPU_8087_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1032 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1034 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1035 CPU_CMOV_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1037 CPU_FXSR_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1040 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1042 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1043 CPU_SSE2_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1045 CPU_SSE3_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1047 CPU_SSE4A_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1049 CPU_SSSE3_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1051 CPU_SSE4_1_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1053 CPU_SSE4_2_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1055 CPU_SSE4_2_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1058 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1059 CPU_AVX2_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1061 CPU_AVX512F_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1063 CPU_AVX512CD_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1065 CPU_AVX512ER_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1067 CPU_AVX512PF_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1069 CPU_AVX512DQ_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1071 CPU_AVX512BW_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1073 CPU_AVX512VL_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1076 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1077 CPU_VMFUNC_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1080 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1081 CPU_XSAVE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1083 CPU_XSAVEOPT_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1085 CPU_XSAVEC_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1087 CPU_XSAVES_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1090 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1091 CPU_PCLMUL_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1093 CPU_PCLMUL_FLAGS
, 1 },
1094 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1095 CPU_FSGSBASE_FLAGS
, 0 },
1096 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1097 CPU_RDRND_FLAGS
, 0 },
1098 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1099 CPU_F16C_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1101 CPU_BMI2_FLAGS
, 0 },
1102 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1104 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1105 CPU_FMA4_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1108 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1111 CPU_MOVBE_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1113 CPU_CX16_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1116 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1117 CPU_LZCNT_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1119 CPU_POPCNT_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1122 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1124 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1125 CPU_INVPCID_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1127 CPU_CLFLUSH_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1130 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1131 CPU_SYSCALL_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1133 CPU_RDTSCP_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1135 CPU_3DNOW_FLAGS
, 0 },
1136 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1137 CPU_3DNOWA_FLAGS
, 0 },
1138 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1139 CPU_PADLOCK_FLAGS
, 0 },
1140 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1141 CPU_SVME_FLAGS
, 1 },
1142 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1143 CPU_SVME_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1145 CPU_SSE4A_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1148 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1150 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1152 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1154 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1155 CPU_RDSEED_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1157 CPU_PRFCHW_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1159 CPU_SMAP_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1162 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1164 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1165 CPU_CLFLUSHOPT_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1167 CPU_PREFETCHWT1_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1170 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1171 CPU_CLWB_FLAGS
, 0 },
1172 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1173 CPU_AVX512IFMA_FLAGS
, 0 },
1174 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1175 CPU_AVX512VBMI_FLAGS
, 0 },
1176 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1177 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1178 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1179 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1180 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1181 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1182 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1183 CPU_AVX512_VBMI2_FLAGS
, 0 },
1184 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1185 CPU_AVX512_VNNI_FLAGS
, 0 },
1186 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1187 CPU_AVX512_BITALG_FLAGS
, 0 },
1188 { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN
,
1189 CPU_AVX_VNNI_FLAGS
, 0 },
1190 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1191 CPU_CLZERO_FLAGS
, 0 },
1192 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1193 CPU_MWAITX_FLAGS
, 0 },
1194 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1195 CPU_OSPKE_FLAGS
, 0 },
1196 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1197 CPU_RDPID_FLAGS
, 0 },
1198 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1199 CPU_PTWRITE_FLAGS
, 0 },
1200 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1202 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1203 CPU_SHSTK_FLAGS
, 0 },
1204 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1205 CPU_GFNI_FLAGS
, 0 },
1206 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1207 CPU_VAES_FLAGS
, 0 },
1208 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1209 CPU_VPCLMULQDQ_FLAGS
, 0 },
1210 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1211 CPU_WBNOINVD_FLAGS
, 0 },
1212 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1213 CPU_PCONFIG_FLAGS
, 0 },
1214 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1215 CPU_WAITPKG_FLAGS
, 0 },
1216 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1217 CPU_CLDEMOTE_FLAGS
, 0 },
1218 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1219 CPU_AMX_INT8_FLAGS
, 0 },
1220 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1221 CPU_AMX_BF16_FLAGS
, 0 },
1222 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1223 CPU_AMX_TILE_FLAGS
, 0 },
1224 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1225 CPU_MOVDIRI_FLAGS
, 0 },
1226 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1227 CPU_MOVDIR64B_FLAGS
, 0 },
1228 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1229 CPU_AVX512_BF16_FLAGS
, 0 },
1230 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1231 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1232 { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN
,
1234 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1235 CPU_ENQCMD_FLAGS
, 0 },
1236 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1237 CPU_SERIALIZE_FLAGS
, 0 },
1238 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1239 CPU_RDPRU_FLAGS
, 0 },
1240 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1241 CPU_MCOMMIT_FLAGS
, 0 },
1242 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1243 CPU_SEV_ES_FLAGS
, 0 },
1244 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1245 CPU_TSXLDTRK_FLAGS
, 0 },
1246 { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN
,
1248 { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN
,
1249 CPU_WIDEKL_FLAGS
, 0 },
1250 { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN
,
1251 CPU_UINTR_FLAGS
, 0 },
1252 { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN
,
1253 CPU_HRESET_FLAGS
, 0 },
1256 static const noarch_entry cpu_noarch
[] =
1258 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1259 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1260 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1261 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1262 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1263 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1264 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1265 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1266 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1267 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1268 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1269 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1270 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1271 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1272 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1273 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1274 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1275 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1276 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1277 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1280 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1281 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1282 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1283 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1284 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1285 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1286 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1287 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1288 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1289 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1290 { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS
},
1291 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1292 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1293 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1294 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1295 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1296 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1297 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1298 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1299 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1300 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1301 { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS
},
1302 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1303 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1304 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1305 { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS
},
1306 { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS
},
1307 { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS
},
1308 { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS
},
1312 /* Like s_lcomm_internal in gas/read.c but the alignment string
1313 is allowed to be optional. */
1316 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1323 && *input_line_pointer
== ',')
1325 align
= parse_align (needs_align
- 1);
1327 if (align
== (addressT
) -1)
1342 bss_alloc (symbolP
, size
, align
);
1347 pe_lcomm (int needs_align
)
1349 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1353 const pseudo_typeS md_pseudo_table
[] =
1355 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1356 {"align", s_align_bytes
, 0},
1358 {"align", s_align_ptwo
, 0},
1360 {"arch", set_cpu_arch
, 0},
1364 {"lcomm", pe_lcomm
, 1},
1366 {"ffloat", float_cons
, 'f'},
1367 {"dfloat", float_cons
, 'd'},
1368 {"tfloat", float_cons
, 'x'},
1370 {"slong", signed_cons
, 4},
1371 {"noopt", s_ignore
, 0},
1372 {"optim", s_ignore
, 0},
1373 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1374 {"code16", set_code_flag
, CODE_16BIT
},
1375 {"code32", set_code_flag
, CODE_32BIT
},
1377 {"code64", set_code_flag
, CODE_64BIT
},
1379 {"intel_syntax", set_intel_syntax
, 1},
1380 {"att_syntax", set_intel_syntax
, 0},
1381 {"intel_mnemonic", set_intel_mnemonic
, 1},
1382 {"att_mnemonic", set_intel_mnemonic
, 0},
1383 {"allow_index_reg", set_allow_index_reg
, 1},
1384 {"disallow_index_reg", set_allow_index_reg
, 0},
1385 {"sse_check", set_check
, 0},
1386 {"operand_check", set_check
, 1},
1387 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1388 {"largecomm", handle_large_common
, 0},
1390 {"file", dwarf2_directive_file
, 0},
1391 {"loc", dwarf2_directive_loc
, 0},
1392 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1395 {"secrel32", pe_directive_secrel
, 0},
1400 /* For interface with expression (). */
1401 extern char *input_line_pointer
;
1403 /* Hash table for instruction mnemonic lookup. */
1404 static htab_t op_hash
;
1406 /* Hash table for register lookup. */
1407 static htab_t reg_hash
;
1409 /* Various efficient no-op patterns for aligning code labels.
1410 Note: Don't try to assemble the instructions in the comments.
1411 0L and 0w are not legal. */
1412 static const unsigned char f32_1
[] =
1414 static const unsigned char f32_2
[] =
1415 {0x66,0x90}; /* xchg %ax,%ax */
1416 static const unsigned char f32_3
[] =
1417 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1418 static const unsigned char f32_4
[] =
1419 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1420 static const unsigned char f32_6
[] =
1421 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1422 static const unsigned char f32_7
[] =
1423 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1424 static const unsigned char f16_3
[] =
1425 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1426 static const unsigned char f16_4
[] =
1427 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1428 static const unsigned char jump_disp8
[] =
1429 {0xeb}; /* jmp disp8 */
1430 static const unsigned char jump32_disp32
[] =
1431 {0xe9}; /* jmp disp32 */
1432 static const unsigned char jump16_disp32
[] =
1433 {0x66,0xe9}; /* jmp disp32 */
1434 /* 32-bit NOPs patterns. */
1435 static const unsigned char *const f32_patt
[] = {
1436 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1438 /* 16-bit NOPs patterns. */
1439 static const unsigned char *const f16_patt
[] = {
1440 f32_1
, f32_2
, f16_3
, f16_4
1442 /* nopl (%[re]ax) */
1443 static const unsigned char alt_3
[] =
1445 /* nopl 0(%[re]ax) */
1446 static const unsigned char alt_4
[] =
1447 {0x0f,0x1f,0x40,0x00};
1448 /* nopl 0(%[re]ax,%[re]ax,1) */
1449 static const unsigned char alt_5
[] =
1450 {0x0f,0x1f,0x44,0x00,0x00};
1451 /* nopw 0(%[re]ax,%[re]ax,1) */
1452 static const unsigned char alt_6
[] =
1453 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1454 /* nopl 0L(%[re]ax) */
1455 static const unsigned char alt_7
[] =
1456 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1457 /* nopl 0L(%[re]ax,%[re]ax,1) */
1458 static const unsigned char alt_8
[] =
1459 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1460 /* nopw 0L(%[re]ax,%[re]ax,1) */
1461 static const unsigned char alt_9
[] =
1462 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1463 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1464 static const unsigned char alt_10
[] =
1465 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1466 /* data16 nopw %cs:0L(%eax,%eax,1) */
1467 static const unsigned char alt_11
[] =
1468 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1469 /* 32-bit and 64-bit NOPs patterns. */
1470 static const unsigned char *const alt_patt
[] = {
1471 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1472 alt_9
, alt_10
, alt_11
1475 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1476 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1479 i386_output_nops (char *where
, const unsigned char *const *patt
,
1480 int count
, int max_single_nop_size
)
1483 /* Place the longer NOP first. */
1486 const unsigned char *nops
;
1488 if (max_single_nop_size
< 1)
1490 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1491 max_single_nop_size
);
1495 nops
= patt
[max_single_nop_size
- 1];
1497 /* Use the smaller one if the requsted one isn't available. */
1500 max_single_nop_size
--;
1501 nops
= patt
[max_single_nop_size
- 1];
1504 last
= count
% max_single_nop_size
;
1507 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1508 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1512 nops
= patt
[last
- 1];
1515 /* Use the smaller one plus one-byte NOP if the needed one
1518 nops
= patt
[last
- 1];
1519 memcpy (where
+ offset
, nops
, last
);
1520 where
[offset
+ last
] = *patt
[0];
1523 memcpy (where
+ offset
, nops
, last
);
1528 fits_in_imm7 (offsetT num
)
1530 return (num
& 0x7f) == num
;
1534 fits_in_imm31 (offsetT num
)
1536 return (num
& 0x7fffffff) == num
;
1539 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1540 single NOP instruction LIMIT. */
1543 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1545 const unsigned char *const *patt
= NULL
;
1546 int max_single_nop_size
;
1547 /* Maximum number of NOPs before switching to jump over NOPs. */
1548 int max_number_of_nops
;
1550 switch (fragP
->fr_type
)
1555 case rs_machine_dependent
:
1556 /* Allow NOP padding for jumps and calls. */
1557 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1558 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1565 /* We need to decide which NOP sequence to use for 32bit and
1566 64bit. When -mtune= is used:
1568 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1569 PROCESSOR_GENERIC32, f32_patt will be used.
1570 2. For the rest, alt_patt will be used.
1572 When -mtune= isn't used, alt_patt will be used if
1573 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1576 When -march= or .arch is used, we can't use anything beyond
1577 cpu_arch_isa_flags. */
1579 if (flag_code
== CODE_16BIT
)
1582 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1583 /* Limit number of NOPs to 2 in 16-bit mode. */
1584 max_number_of_nops
= 2;
1588 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1590 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1591 switch (cpu_arch_tune
)
1593 case PROCESSOR_UNKNOWN
:
1594 /* We use cpu_arch_isa_flags to check if we SHOULD
1595 optimize with nops. */
1596 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1601 case PROCESSOR_PENTIUM4
:
1602 case PROCESSOR_NOCONA
:
1603 case PROCESSOR_CORE
:
1604 case PROCESSOR_CORE2
:
1605 case PROCESSOR_COREI7
:
1606 case PROCESSOR_L1OM
:
1607 case PROCESSOR_K1OM
:
1608 case PROCESSOR_GENERIC64
:
1610 case PROCESSOR_ATHLON
:
1612 case PROCESSOR_AMDFAM10
:
1614 case PROCESSOR_ZNVER
:
1618 case PROCESSOR_I386
:
1619 case PROCESSOR_I486
:
1620 case PROCESSOR_PENTIUM
:
1621 case PROCESSOR_PENTIUMPRO
:
1622 case PROCESSOR_IAMCU
:
1623 case PROCESSOR_GENERIC32
:
1630 switch (fragP
->tc_frag_data
.tune
)
1632 case PROCESSOR_UNKNOWN
:
1633 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1634 PROCESSOR_UNKNOWN. */
1638 case PROCESSOR_I386
:
1639 case PROCESSOR_I486
:
1640 case PROCESSOR_PENTIUM
:
1641 case PROCESSOR_IAMCU
:
1643 case PROCESSOR_ATHLON
:
1645 case PROCESSOR_AMDFAM10
:
1647 case PROCESSOR_ZNVER
:
1649 case PROCESSOR_GENERIC32
:
1650 /* We use cpu_arch_isa_flags to check if we CAN optimize
1652 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1657 case PROCESSOR_PENTIUMPRO
:
1658 case PROCESSOR_PENTIUM4
:
1659 case PROCESSOR_NOCONA
:
1660 case PROCESSOR_CORE
:
1661 case PROCESSOR_CORE2
:
1662 case PROCESSOR_COREI7
:
1663 case PROCESSOR_L1OM
:
1664 case PROCESSOR_K1OM
:
1665 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1670 case PROCESSOR_GENERIC64
:
1676 if (patt
== f32_patt
)
1678 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1679 /* Limit number of NOPs to 2 for older processors. */
1680 max_number_of_nops
= 2;
1684 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1685 /* Limit number of NOPs to 7 for newer processors. */
1686 max_number_of_nops
= 7;
1691 limit
= max_single_nop_size
;
1693 if (fragP
->fr_type
== rs_fill_nop
)
1695 /* Output NOPs for .nop directive. */
1696 if (limit
> max_single_nop_size
)
1698 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1699 _("invalid single nop size: %d "
1700 "(expect within [0, %d])"),
1701 limit
, max_single_nop_size
);
1705 else if (fragP
->fr_type
!= rs_machine_dependent
)
1706 fragP
->fr_var
= count
;
1708 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1710 /* Generate jump over NOPs. */
1711 offsetT disp
= count
- 2;
1712 if (fits_in_imm7 (disp
))
1714 /* Use "jmp disp8" if possible. */
1716 where
[0] = jump_disp8
[0];
1722 unsigned int size_of_jump
;
1724 if (flag_code
== CODE_16BIT
)
1726 where
[0] = jump16_disp32
[0];
1727 where
[1] = jump16_disp32
[1];
1732 where
[0] = jump32_disp32
[0];
1736 count
-= size_of_jump
+ 4;
1737 if (!fits_in_imm31 (count
))
1739 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1740 _("jump over nop padding out of range"));
1744 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1745 where
+= size_of_jump
+ 4;
1749 /* Generate multiple NOPs. */
1750 i386_output_nops (where
, patt
, count
, limit
);
1754 operand_type_all_zero (const union i386_operand_type
*x
)
1756 switch (ARRAY_SIZE(x
->array
))
1767 return !x
->array
[0];
1774 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1776 switch (ARRAY_SIZE(x
->array
))
1792 x
->bitfield
.class = ClassNone
;
1793 x
->bitfield
.instance
= InstanceNone
;
1797 operand_type_equal (const union i386_operand_type
*x
,
1798 const union i386_operand_type
*y
)
1800 switch (ARRAY_SIZE(x
->array
))
1803 if (x
->array
[2] != y
->array
[2])
1807 if (x
->array
[1] != y
->array
[1])
1811 return x
->array
[0] == y
->array
[0];
1819 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1821 switch (ARRAY_SIZE(x
->array
))
1836 return !x
->array
[0];
1843 cpu_flags_equal (const union i386_cpu_flags
*x
,
1844 const union i386_cpu_flags
*y
)
1846 switch (ARRAY_SIZE(x
->array
))
1849 if (x
->array
[3] != y
->array
[3])
1853 if (x
->array
[2] != y
->array
[2])
1857 if (x
->array
[1] != y
->array
[1])
1861 return x
->array
[0] == y
->array
[0];
1869 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1871 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1872 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1875 static INLINE i386_cpu_flags
1876 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1878 switch (ARRAY_SIZE (x
.array
))
1881 x
.array
[3] &= y
.array
[3];
1884 x
.array
[2] &= y
.array
[2];
1887 x
.array
[1] &= y
.array
[1];
1890 x
.array
[0] &= y
.array
[0];
1898 static INLINE i386_cpu_flags
1899 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1901 switch (ARRAY_SIZE (x
.array
))
1904 x
.array
[3] |= y
.array
[3];
1907 x
.array
[2] |= y
.array
[2];
1910 x
.array
[1] |= y
.array
[1];
1913 x
.array
[0] |= y
.array
[0];
1921 static INLINE i386_cpu_flags
1922 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1924 switch (ARRAY_SIZE (x
.array
))
1927 x
.array
[3] &= ~y
.array
[3];
1930 x
.array
[2] &= ~y
.array
[2];
1933 x
.array
[1] &= ~y
.array
[1];
1936 x
.array
[0] &= ~y
.array
[0];
1944 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1946 #define CPU_FLAGS_ARCH_MATCH 0x1
1947 #define CPU_FLAGS_64BIT_MATCH 0x2
1949 #define CPU_FLAGS_PERFECT_MATCH \
1950 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1952 /* Return CPU flags match bits. */
1955 cpu_flags_match (const insn_template
*t
)
1957 i386_cpu_flags x
= t
->cpu_flags
;
1958 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1960 x
.bitfield
.cpu64
= 0;
1961 x
.bitfield
.cpuno64
= 0;
1963 if (cpu_flags_all_zero (&x
))
1965 /* This instruction is available on all archs. */
1966 match
|= CPU_FLAGS_ARCH_MATCH
;
1970 /* This instruction is available only on some archs. */
1971 i386_cpu_flags cpu
= cpu_arch_flags
;
1973 /* AVX512VL is no standalone feature - match it and then strip it. */
1974 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1976 x
.bitfield
.cpuavx512vl
= 0;
1978 cpu
= cpu_flags_and (x
, cpu
);
1979 if (!cpu_flags_all_zero (&cpu
))
1981 if (x
.bitfield
.cpuavx
)
1983 /* We need to check a few extra flags with AVX. */
1984 if (cpu
.bitfield
.cpuavx
1985 && (!t
->opcode_modifier
.sse2avx
1986 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1987 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1988 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1989 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1990 match
|= CPU_FLAGS_ARCH_MATCH
;
1992 else if (x
.bitfield
.cpuavx512f
)
1994 /* We need to check a few extra flags with AVX512F. */
1995 if (cpu
.bitfield
.cpuavx512f
1996 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1997 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1998 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1999 match
|= CPU_FLAGS_ARCH_MATCH
;
2002 match
|= CPU_FLAGS_ARCH_MATCH
;
2008 static INLINE i386_operand_type
2009 operand_type_and (i386_operand_type x
, i386_operand_type y
)
2011 if (x
.bitfield
.class != y
.bitfield
.class)
2012 x
.bitfield
.class = ClassNone
;
2013 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
2014 x
.bitfield
.instance
= InstanceNone
;
2016 switch (ARRAY_SIZE (x
.array
))
2019 x
.array
[2] &= y
.array
[2];
2022 x
.array
[1] &= y
.array
[1];
2025 x
.array
[0] &= y
.array
[0];
2033 static INLINE i386_operand_type
2034 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2036 gas_assert (y
.bitfield
.class == ClassNone
);
2037 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2039 switch (ARRAY_SIZE (x
.array
))
2042 x
.array
[2] &= ~y
.array
[2];
2045 x
.array
[1] &= ~y
.array
[1];
2048 x
.array
[0] &= ~y
.array
[0];
2056 static INLINE i386_operand_type
2057 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2059 gas_assert (x
.bitfield
.class == ClassNone
||
2060 y
.bitfield
.class == ClassNone
||
2061 x
.bitfield
.class == y
.bitfield
.class);
2062 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2063 y
.bitfield
.instance
== InstanceNone
||
2064 x
.bitfield
.instance
== y
.bitfield
.instance
);
2066 switch (ARRAY_SIZE (x
.array
))
2069 x
.array
[2] |= y
.array
[2];
2072 x
.array
[1] |= y
.array
[1];
2075 x
.array
[0] |= y
.array
[0];
2083 static INLINE i386_operand_type
2084 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2086 gas_assert (y
.bitfield
.class == ClassNone
);
2087 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2089 switch (ARRAY_SIZE (x
.array
))
2092 x
.array
[2] ^= y
.array
[2];
2095 x
.array
[1] ^= y
.array
[1];
2098 x
.array
[0] ^= y
.array
[0];
2106 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2107 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2108 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2109 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2110 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2111 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2112 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2113 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2114 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2115 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2116 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2117 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2118 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2119 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2120 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2121 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2122 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2133 operand_type_check (i386_operand_type t
, enum operand_type c
)
2138 return t
.bitfield
.class == Reg
;
2141 return (t
.bitfield
.imm8
2145 || t
.bitfield
.imm32s
2146 || t
.bitfield
.imm64
);
2149 return (t
.bitfield
.disp8
2150 || t
.bitfield
.disp16
2151 || t
.bitfield
.disp32
2152 || t
.bitfield
.disp32s
2153 || t
.bitfield
.disp64
);
2156 return (t
.bitfield
.disp8
2157 || t
.bitfield
.disp16
2158 || t
.bitfield
.disp32
2159 || t
.bitfield
.disp32s
2160 || t
.bitfield
.disp64
2161 || t
.bitfield
.baseindex
);
2170 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2171 between operand GIVEN and opeand WANTED for instruction template T. */
2174 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2177 return !((i
.types
[given
].bitfield
.byte
2178 && !t
->operand_types
[wanted
].bitfield
.byte
)
2179 || (i
.types
[given
].bitfield
.word
2180 && !t
->operand_types
[wanted
].bitfield
.word
)
2181 || (i
.types
[given
].bitfield
.dword
2182 && !t
->operand_types
[wanted
].bitfield
.dword
)
2183 || (i
.types
[given
].bitfield
.qword
2184 && !t
->operand_types
[wanted
].bitfield
.qword
)
2185 || (i
.types
[given
].bitfield
.tbyte
2186 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2189 /* Return 1 if there is no conflict in SIMD register between operand
2190 GIVEN and opeand WANTED for instruction template T. */
2193 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2196 return !((i
.types
[given
].bitfield
.xmmword
2197 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2198 || (i
.types
[given
].bitfield
.ymmword
2199 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2200 || (i
.types
[given
].bitfield
.zmmword
2201 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2202 || (i
.types
[given
].bitfield
.tmmword
2203 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2206 /* Return 1 if there is no conflict in any size between operand GIVEN
2207 and opeand WANTED for instruction template T. */
2210 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2213 return (match_operand_size (t
, wanted
, given
)
2214 && !((i
.types
[given
].bitfield
.unspecified
2216 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2217 || (i
.types
[given
].bitfield
.fword
2218 && !t
->operand_types
[wanted
].bitfield
.fword
)
2219 /* For scalar opcode templates to allow register and memory
2220 operands at the same time, some special casing is needed
2221 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2222 down-conversion vpmov*. */
2223 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2224 && t
->operand_types
[wanted
].bitfield
.byte
2225 + t
->operand_types
[wanted
].bitfield
.word
2226 + t
->operand_types
[wanted
].bitfield
.dword
2227 + t
->operand_types
[wanted
].bitfield
.qword
2228 > !!t
->opcode_modifier
.broadcast
)
2229 ? (i
.types
[given
].bitfield
.xmmword
2230 || i
.types
[given
].bitfield
.ymmword
2231 || i
.types
[given
].bitfield
.zmmword
)
2232 : !match_simd_size(t
, wanted
, given
))));
2235 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2236 operands for instruction template T, and it has MATCH_REVERSE set if there
2237 is no size conflict on any operands for the template with operands reversed
2238 (and the template allows for reversing in the first place). */
2240 #define MATCH_STRAIGHT 1
2241 #define MATCH_REVERSE 2
2243 static INLINE
unsigned int
2244 operand_size_match (const insn_template
*t
)
2246 unsigned int j
, match
= MATCH_STRAIGHT
;
2248 /* Don't check non-absolute jump instructions. */
2249 if (t
->opcode_modifier
.jump
2250 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2253 /* Check memory and accumulator operand size. */
2254 for (j
= 0; j
< i
.operands
; j
++)
2256 if (i
.types
[j
].bitfield
.class != Reg
2257 && i
.types
[j
].bitfield
.class != RegSIMD
2258 && t
->opcode_modifier
.anysize
)
2261 if (t
->operand_types
[j
].bitfield
.class == Reg
2262 && !match_operand_size (t
, j
, j
))
2268 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2269 && !match_simd_size (t
, j
, j
))
2275 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2276 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2282 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2289 if (!t
->opcode_modifier
.d
)
2293 i
.error
= operand_size_mismatch
;
2297 /* Check reverse. */
2298 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2300 for (j
= 0; j
< i
.operands
; j
++)
2302 unsigned int given
= i
.operands
- j
- 1;
2304 if (t
->operand_types
[j
].bitfield
.class == Reg
2305 && !match_operand_size (t
, j
, given
))
2308 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2309 && !match_simd_size (t
, j
, given
))
2312 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2313 && (!match_operand_size (t
, j
, given
)
2314 || !match_simd_size (t
, j
, given
)))
2317 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2321 return match
| MATCH_REVERSE
;
2325 operand_type_match (i386_operand_type overlap
,
2326 i386_operand_type given
)
2328 i386_operand_type temp
= overlap
;
2330 temp
.bitfield
.unspecified
= 0;
2331 temp
.bitfield
.byte
= 0;
2332 temp
.bitfield
.word
= 0;
2333 temp
.bitfield
.dword
= 0;
2334 temp
.bitfield
.fword
= 0;
2335 temp
.bitfield
.qword
= 0;
2336 temp
.bitfield
.tbyte
= 0;
2337 temp
.bitfield
.xmmword
= 0;
2338 temp
.bitfield
.ymmword
= 0;
2339 temp
.bitfield
.zmmword
= 0;
2340 temp
.bitfield
.tmmword
= 0;
2341 if (operand_type_all_zero (&temp
))
2344 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2348 i
.error
= operand_type_mismatch
;
2352 /* If given types g0 and g1 are registers they must be of the same type
2353 unless the expected operand type register overlap is null.
2354 Some Intel syntax memory operand size checking also happens here. */
2357 operand_type_register_match (i386_operand_type g0
,
2358 i386_operand_type t0
,
2359 i386_operand_type g1
,
2360 i386_operand_type t1
)
2362 if (g0
.bitfield
.class != Reg
2363 && g0
.bitfield
.class != RegSIMD
2364 && (!operand_type_check (g0
, anymem
)
2365 || g0
.bitfield
.unspecified
2366 || (t0
.bitfield
.class != Reg
2367 && t0
.bitfield
.class != RegSIMD
)))
2370 if (g1
.bitfield
.class != Reg
2371 && g1
.bitfield
.class != RegSIMD
2372 && (!operand_type_check (g1
, anymem
)
2373 || g1
.bitfield
.unspecified
2374 || (t1
.bitfield
.class != Reg
2375 && t1
.bitfield
.class != RegSIMD
)))
2378 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2379 && g0
.bitfield
.word
== g1
.bitfield
.word
2380 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2381 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2382 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2383 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2384 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2387 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2388 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2389 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2390 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2391 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2392 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2393 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2396 i
.error
= register_type_mismatch
;
2401 static INLINE
unsigned int
2402 register_number (const reg_entry
*r
)
2404 unsigned int nr
= r
->reg_num
;
2406 if (r
->reg_flags
& RegRex
)
2409 if (r
->reg_flags
& RegVRex
)
2415 static INLINE
unsigned int
2416 mode_from_disp_size (i386_operand_type t
)
2418 if (t
.bitfield
.disp8
)
2420 else if (t
.bitfield
.disp16
2421 || t
.bitfield
.disp32
2422 || t
.bitfield
.disp32s
)
2429 fits_in_signed_byte (addressT num
)
2431 return num
+ 0x80 <= 0xff;
2435 fits_in_unsigned_byte (addressT num
)
2441 fits_in_unsigned_word (addressT num
)
2443 return num
<= 0xffff;
2447 fits_in_signed_word (addressT num
)
2449 return num
+ 0x8000 <= 0xffff;
2453 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2458 return num
+ 0x80000000 <= 0xffffffff;
2460 } /* fits_in_signed_long() */
2463 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2468 return num
<= 0xffffffff;
2470 } /* fits_in_unsigned_long() */
2473 fits_in_disp8 (offsetT num
)
2475 int shift
= i
.memshift
;
2481 mask
= (1 << shift
) - 1;
2483 /* Return 0 if NUM isn't properly aligned. */
2487 /* Check if NUM will fit in 8bit after shift. */
2488 return fits_in_signed_byte (num
>> shift
);
2492 fits_in_imm4 (offsetT num
)
2494 return (num
& 0xf) == num
;
2497 static i386_operand_type
2498 smallest_imm_type (offsetT num
)
2500 i386_operand_type t
;
2502 operand_type_set (&t
, 0);
2503 t
.bitfield
.imm64
= 1;
2505 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2507 /* This code is disabled on the 486 because all the Imm1 forms
2508 in the opcode table are slower on the i486. They're the
2509 versions with the implicitly specified single-position
2510 displacement, which has another syntax if you really want to
2512 t
.bitfield
.imm1
= 1;
2513 t
.bitfield
.imm8
= 1;
2514 t
.bitfield
.imm8s
= 1;
2515 t
.bitfield
.imm16
= 1;
2516 t
.bitfield
.imm32
= 1;
2517 t
.bitfield
.imm32s
= 1;
2519 else if (fits_in_signed_byte (num
))
2521 t
.bitfield
.imm8
= 1;
2522 t
.bitfield
.imm8s
= 1;
2523 t
.bitfield
.imm16
= 1;
2524 t
.bitfield
.imm32
= 1;
2525 t
.bitfield
.imm32s
= 1;
2527 else if (fits_in_unsigned_byte (num
))
2529 t
.bitfield
.imm8
= 1;
2530 t
.bitfield
.imm16
= 1;
2531 t
.bitfield
.imm32
= 1;
2532 t
.bitfield
.imm32s
= 1;
2534 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2536 t
.bitfield
.imm16
= 1;
2537 t
.bitfield
.imm32
= 1;
2538 t
.bitfield
.imm32s
= 1;
2540 else if (fits_in_signed_long (num
))
2542 t
.bitfield
.imm32
= 1;
2543 t
.bitfield
.imm32s
= 1;
2545 else if (fits_in_unsigned_long (num
))
2546 t
.bitfield
.imm32
= 1;
2552 offset_in_range (offsetT val
, int size
)
2558 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2559 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2560 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2562 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2567 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2569 char buf1
[40], buf2
[40];
2571 sprint_value (buf1
, val
);
2572 sprint_value (buf2
, val
& mask
);
2573 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2588 a. PREFIX_EXIST if attempting to add a prefix where one from the
2589 same class already exists.
2590 b. PREFIX_LOCK if lock prefix is added.
2591 c. PREFIX_REP if rep/repne prefix is added.
2592 d. PREFIX_DS if ds prefix is added.
2593 e. PREFIX_OTHER if other prefix is added.
2596 static enum PREFIX_GROUP
2597 add_prefix (unsigned int prefix
)
2599 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2602 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2603 && flag_code
== CODE_64BIT
)
2605 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2606 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2607 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2608 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2619 case DS_PREFIX_OPCODE
:
2622 case CS_PREFIX_OPCODE
:
2623 case ES_PREFIX_OPCODE
:
2624 case FS_PREFIX_OPCODE
:
2625 case GS_PREFIX_OPCODE
:
2626 case SS_PREFIX_OPCODE
:
2630 case REPNE_PREFIX_OPCODE
:
2631 case REPE_PREFIX_OPCODE
:
2636 case LOCK_PREFIX_OPCODE
:
2645 case ADDR_PREFIX_OPCODE
:
2649 case DATA_PREFIX_OPCODE
:
2653 if (i
.prefix
[q
] != 0)
2661 i
.prefix
[q
] |= prefix
;
2664 as_bad (_("same type of prefix used twice"));
2670 update_code_flag (int value
, int check
)
2672 PRINTF_LIKE ((*as_error
));
2674 flag_code
= (enum flag_code
) value
;
2675 if (flag_code
== CODE_64BIT
)
2677 cpu_arch_flags
.bitfield
.cpu64
= 1;
2678 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2682 cpu_arch_flags
.bitfield
.cpu64
= 0;
2683 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2685 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2688 as_error
= as_fatal
;
2691 (*as_error
) (_("64bit mode not supported on `%s'."),
2692 cpu_arch_name
? cpu_arch_name
: default_arch
);
2694 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2697 as_error
= as_fatal
;
2700 (*as_error
) (_("32bit mode not supported on `%s'."),
2701 cpu_arch_name
? cpu_arch_name
: default_arch
);
2703 stackop_size
= '\0';
2707 set_code_flag (int value
)
2709 update_code_flag (value
, 0);
2713 set_16bit_gcc_code_flag (int new_code_flag
)
2715 flag_code
= (enum flag_code
) new_code_flag
;
2716 if (flag_code
!= CODE_16BIT
)
2718 cpu_arch_flags
.bitfield
.cpu64
= 0;
2719 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2720 stackop_size
= LONG_MNEM_SUFFIX
;
2724 set_intel_syntax (int syntax_flag
)
2726 /* Find out if register prefixing is specified. */
2727 int ask_naked_reg
= 0;
2730 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2733 int e
= get_symbol_name (&string
);
2735 if (strcmp (string
, "prefix") == 0)
2737 else if (strcmp (string
, "noprefix") == 0)
2740 as_bad (_("bad argument to syntax directive."));
2741 (void) restore_line_pointer (e
);
2743 demand_empty_rest_of_line ();
2745 intel_syntax
= syntax_flag
;
2747 if (ask_naked_reg
== 0)
2748 allow_naked_reg
= (intel_syntax
2749 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2751 allow_naked_reg
= (ask_naked_reg
< 0);
2753 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2755 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2756 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2757 register_prefix
= allow_naked_reg
? "" : "%";
2761 set_intel_mnemonic (int mnemonic_flag
)
2763 intel_mnemonic
= mnemonic_flag
;
2767 set_allow_index_reg (int flag
)
2769 allow_index_reg
= flag
;
2773 set_check (int what
)
2775 enum check_kind
*kind
;
2780 kind
= &operand_check
;
2791 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2794 int e
= get_symbol_name (&string
);
2796 if (strcmp (string
, "none") == 0)
2798 else if (strcmp (string
, "warning") == 0)
2799 *kind
= check_warning
;
2800 else if (strcmp (string
, "error") == 0)
2801 *kind
= check_error
;
2803 as_bad (_("bad argument to %s_check directive."), str
);
2804 (void) restore_line_pointer (e
);
2807 as_bad (_("missing argument for %s_check directive"), str
);
2809 demand_empty_rest_of_line ();
2813 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2814 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2816 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2817 static const char *arch
;
2819 /* Intel LIOM is only supported on ELF. */
2825 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2826 use default_arch. */
2827 arch
= cpu_arch_name
;
2829 arch
= default_arch
;
2832 /* If we are targeting Intel MCU, we must enable it. */
2833 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2834 || new_flag
.bitfield
.cpuiamcu
)
2837 /* If we are targeting Intel L1OM, we must enable it. */
2838 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2839 || new_flag
.bitfield
.cpul1om
)
2842 /* If we are targeting Intel K1OM, we must enable it. */
2843 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2844 || new_flag
.bitfield
.cpuk1om
)
2847 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2852 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2856 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2859 int e
= get_symbol_name (&string
);
2861 i386_cpu_flags flags
;
2863 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2865 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2867 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2871 cpu_arch_name
= cpu_arch
[j
].name
;
2872 cpu_sub_arch_name
= NULL
;
2873 cpu_arch_flags
= cpu_arch
[j
].flags
;
2874 if (flag_code
== CODE_64BIT
)
2876 cpu_arch_flags
.bitfield
.cpu64
= 1;
2877 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2881 cpu_arch_flags
.bitfield
.cpu64
= 0;
2882 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2884 cpu_arch_isa
= cpu_arch
[j
].type
;
2885 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2886 if (!cpu_arch_tune_set
)
2888 cpu_arch_tune
= cpu_arch_isa
;
2889 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2894 flags
= cpu_flags_or (cpu_arch_flags
,
2897 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2899 if (cpu_sub_arch_name
)
2901 char *name
= cpu_sub_arch_name
;
2902 cpu_sub_arch_name
= concat (name
,
2904 (const char *) NULL
);
2908 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2909 cpu_arch_flags
= flags
;
2910 cpu_arch_isa_flags
= flags
;
2914 = cpu_flags_or (cpu_arch_isa_flags
,
2916 (void) restore_line_pointer (e
);
2917 demand_empty_rest_of_line ();
2922 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2924 /* Disable an ISA extension. */
2925 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2926 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2928 flags
= cpu_flags_and_not (cpu_arch_flags
,
2929 cpu_noarch
[j
].flags
);
2930 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2932 if (cpu_sub_arch_name
)
2934 char *name
= cpu_sub_arch_name
;
2935 cpu_sub_arch_name
= concat (name
, string
,
2936 (const char *) NULL
);
2940 cpu_sub_arch_name
= xstrdup (string
);
2941 cpu_arch_flags
= flags
;
2942 cpu_arch_isa_flags
= flags
;
2944 (void) restore_line_pointer (e
);
2945 demand_empty_rest_of_line ();
2949 j
= ARRAY_SIZE (cpu_arch
);
2952 if (j
>= ARRAY_SIZE (cpu_arch
))
2953 as_bad (_("no such architecture: `%s'"), string
);
2955 *input_line_pointer
= e
;
2958 as_bad (_("missing cpu architecture"));
2960 no_cond_jump_promotion
= 0;
2961 if (*input_line_pointer
== ','
2962 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2967 ++input_line_pointer
;
2968 e
= get_symbol_name (&string
);
2970 if (strcmp (string
, "nojumps") == 0)
2971 no_cond_jump_promotion
= 1;
2972 else if (strcmp (string
, "jumps") == 0)
2975 as_bad (_("no such architecture modifier: `%s'"), string
);
2977 (void) restore_line_pointer (e
);
2980 demand_empty_rest_of_line ();
2983 enum bfd_architecture
2986 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2988 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2989 || flag_code
!= CODE_64BIT
)
2990 as_fatal (_("Intel L1OM is 64bit ELF only"));
2991 return bfd_arch_l1om
;
2993 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2995 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2996 || flag_code
!= CODE_64BIT
)
2997 as_fatal (_("Intel K1OM is 64bit ELF only"));
2998 return bfd_arch_k1om
;
3000 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3002 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3003 || flag_code
== CODE_64BIT
)
3004 as_fatal (_("Intel MCU is 32bit ELF only"));
3005 return bfd_arch_iamcu
;
3008 return bfd_arch_i386
;
3014 if (!strncmp (default_arch
, "x86_64", 6))
3016 if (cpu_arch_isa
== PROCESSOR_L1OM
)
3018 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3019 || default_arch
[6] != '\0')
3020 as_fatal (_("Intel L1OM is 64bit ELF only"));
3021 return bfd_mach_l1om
;
3023 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3025 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3026 || default_arch
[6] != '\0')
3027 as_fatal (_("Intel K1OM is 64bit ELF only"));
3028 return bfd_mach_k1om
;
3030 else if (default_arch
[6] == '\0')
3031 return bfd_mach_x86_64
;
3033 return bfd_mach_x64_32
;
3035 else if (!strcmp (default_arch
, "i386")
3036 || !strcmp (default_arch
, "iamcu"))
3038 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3040 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3041 as_fatal (_("Intel MCU is 32bit ELF only"));
3042 return bfd_mach_i386_iamcu
;
3045 return bfd_mach_i386_i386
;
3048 as_fatal (_("unknown architecture"));
3054 /* Support pseudo prefixes like {disp32}. */
3055 lex_type
['{'] = LEX_BEGIN_NAME
;
3057 /* Initialize op_hash hash table. */
3058 op_hash
= str_htab_create ();
3061 const insn_template
*optab
;
3062 templates
*core_optab
;
3064 /* Setup for loop. */
3066 core_optab
= XNEW (templates
);
3067 core_optab
->start
= optab
;
3072 if (optab
->name
== NULL
3073 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3075 /* different name --> ship out current template list;
3076 add to hash table; & begin anew. */
3077 core_optab
->end
= optab
;
3078 if (str_hash_insert (op_hash
, (optab
- 1)->name
, core_optab
, 0))
3079 as_fatal (_("duplicate %s"), (optab
- 1)->name
);
3081 if (optab
->name
== NULL
)
3083 core_optab
= XNEW (templates
);
3084 core_optab
->start
= optab
;
3089 /* Initialize reg_hash hash table. */
3090 reg_hash
= str_htab_create ();
3092 const reg_entry
*regtab
;
3093 unsigned int regtab_size
= i386_regtab_size
;
3095 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3096 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3097 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3100 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3105 for (c
= 0; c
< 256; c
++)
3110 mnemonic_chars
[c
] = c
;
3111 register_chars
[c
] = c
;
3112 operand_chars
[c
] = c
;
3114 else if (ISLOWER (c
))
3116 mnemonic_chars
[c
] = c
;
3117 register_chars
[c
] = c
;
3118 operand_chars
[c
] = c
;
3120 else if (ISUPPER (c
))
3122 mnemonic_chars
[c
] = TOLOWER (c
);
3123 register_chars
[c
] = mnemonic_chars
[c
];
3124 operand_chars
[c
] = c
;
3126 else if (c
== '{' || c
== '}')
3128 mnemonic_chars
[c
] = c
;
3129 operand_chars
[c
] = c
;
3131 #ifdef SVR4_COMMENT_CHARS
3132 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3133 operand_chars
[c
] = c
;
3136 if (ISALPHA (c
) || ISDIGIT (c
))
3137 identifier_chars
[c
] = c
;
3140 identifier_chars
[c
] = c
;
3141 operand_chars
[c
] = c
;
3146 identifier_chars
['@'] = '@';
3149 identifier_chars
['?'] = '?';
3150 operand_chars
['?'] = '?';
3152 digit_chars
['-'] = '-';
3153 mnemonic_chars
['_'] = '_';
3154 mnemonic_chars
['-'] = '-';
3155 mnemonic_chars
['.'] = '.';
3156 identifier_chars
['_'] = '_';
3157 identifier_chars
['.'] = '.';
3159 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3160 operand_chars
[(unsigned char) *p
] = *p
;
3163 if (flag_code
== CODE_64BIT
)
3165 #if defined (OBJ_COFF) && defined (TE_PE)
3166 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3169 x86_dwarf2_return_column
= 16;
3171 x86_cie_data_alignment
= -8;
3175 x86_dwarf2_return_column
= 8;
3176 x86_cie_data_alignment
= -4;
3179 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3180 can be turned into BRANCH_PREFIX frag. */
3181 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3186 i386_print_statistics (FILE *file
)
3188 htab_print_statistics (file
, "i386 opcode", op_hash
);
3189 htab_print_statistics (file
, "i386 register", reg_hash
);
3194 /* Debugging routines for md_assemble. */
3195 static void pte (insn_template
*);
3196 static void pt (i386_operand_type
);
3197 static void pe (expressionS
*);
3198 static void ps (symbolS
*);
3201 pi (const char *line
, i386_insn
*x
)
3205 fprintf (stdout
, "%s: template ", line
);
3207 fprintf (stdout
, " address: base %s index %s scale %x\n",
3208 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3209 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3210 x
->log2_scale_factor
);
3211 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3212 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3213 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3214 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3215 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3216 (x
->rex
& REX_W
) != 0,
3217 (x
->rex
& REX_R
) != 0,
3218 (x
->rex
& REX_X
) != 0,
3219 (x
->rex
& REX_B
) != 0);
3220 for (j
= 0; j
< x
->operands
; j
++)
3222 fprintf (stdout
, " #%d: ", j
+ 1);
3224 fprintf (stdout
, "\n");
3225 if (x
->types
[j
].bitfield
.class == Reg
3226 || x
->types
[j
].bitfield
.class == RegMMX
3227 || x
->types
[j
].bitfield
.class == RegSIMD
3228 || x
->types
[j
].bitfield
.class == RegMask
3229 || x
->types
[j
].bitfield
.class == SReg
3230 || x
->types
[j
].bitfield
.class == RegCR
3231 || x
->types
[j
].bitfield
.class == RegDR
3232 || x
->types
[j
].bitfield
.class == RegTR
3233 || x
->types
[j
].bitfield
.class == RegBND
)
3234 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3235 if (operand_type_check (x
->types
[j
], imm
))
3237 if (operand_type_check (x
->types
[j
], disp
))
3238 pe (x
->op
[j
].disps
);
3243 pte (insn_template
*t
)
3245 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3246 static const char *const opc_spc
[] = {
3247 NULL
, "0f", "0f38", "0f3a", NULL
, NULL
, NULL
, NULL
,
3248 "XOP08", "XOP09", "XOP0A",
3252 fprintf (stdout
, " %d operands ", t
->operands
);
3253 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3254 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3255 if (opc_spc
[t
->opcode_modifier
.opcodespace
])
3256 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_modifier
.opcodespace
]);
3257 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3258 if (t
->extension_opcode
!= None
)
3259 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3260 if (t
->opcode_modifier
.d
)
3261 fprintf (stdout
, "D");
3262 if (t
->opcode_modifier
.w
)
3263 fprintf (stdout
, "W");
3264 fprintf (stdout
, "\n");
3265 for (j
= 0; j
< t
->operands
; j
++)
3267 fprintf (stdout
, " #%d type ", j
+ 1);
3268 pt (t
->operand_types
[j
]);
3269 fprintf (stdout
, "\n");
3276 fprintf (stdout
, " operation %d\n", e
->X_op
);
3277 fprintf (stdout
, " add_number %ld (%lx)\n",
3278 (long) e
->X_add_number
, (long) e
->X_add_number
);
3279 if (e
->X_add_symbol
)
3281 fprintf (stdout
, " add_symbol ");
3282 ps (e
->X_add_symbol
);
3283 fprintf (stdout
, "\n");
3287 fprintf (stdout
, " op_symbol ");
3288 ps (e
->X_op_symbol
);
3289 fprintf (stdout
, "\n");
3296 fprintf (stdout
, "%s type %s%s",
3298 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3299 segment_name (S_GET_SEGMENT (s
)));
3302 static struct type_name
3304 i386_operand_type mask
;
3307 const type_names
[] =
3309 { OPERAND_TYPE_REG8
, "r8" },
3310 { OPERAND_TYPE_REG16
, "r16" },
3311 { OPERAND_TYPE_REG32
, "r32" },
3312 { OPERAND_TYPE_REG64
, "r64" },
3313 { OPERAND_TYPE_ACC8
, "acc8" },
3314 { OPERAND_TYPE_ACC16
, "acc16" },
3315 { OPERAND_TYPE_ACC32
, "acc32" },
3316 { OPERAND_TYPE_ACC64
, "acc64" },
3317 { OPERAND_TYPE_IMM8
, "i8" },
3318 { OPERAND_TYPE_IMM8
, "i8s" },
3319 { OPERAND_TYPE_IMM16
, "i16" },
3320 { OPERAND_TYPE_IMM32
, "i32" },
3321 { OPERAND_TYPE_IMM32S
, "i32s" },
3322 { OPERAND_TYPE_IMM64
, "i64" },
3323 { OPERAND_TYPE_IMM1
, "i1" },
3324 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3325 { OPERAND_TYPE_DISP8
, "d8" },
3326 { OPERAND_TYPE_DISP16
, "d16" },
3327 { OPERAND_TYPE_DISP32
, "d32" },
3328 { OPERAND_TYPE_DISP32S
, "d32s" },
3329 { OPERAND_TYPE_DISP64
, "d64" },
3330 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3331 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3332 { OPERAND_TYPE_CONTROL
, "control reg" },
3333 { OPERAND_TYPE_TEST
, "test reg" },
3334 { OPERAND_TYPE_DEBUG
, "debug reg" },
3335 { OPERAND_TYPE_FLOATREG
, "FReg" },
3336 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3337 { OPERAND_TYPE_SREG
, "SReg" },
3338 { OPERAND_TYPE_REGMMX
, "rMMX" },
3339 { OPERAND_TYPE_REGXMM
, "rXMM" },
3340 { OPERAND_TYPE_REGYMM
, "rYMM" },
3341 { OPERAND_TYPE_REGZMM
, "rZMM" },
3342 { OPERAND_TYPE_REGTMM
, "rTMM" },
3343 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3347 pt (i386_operand_type t
)
3350 i386_operand_type a
;
3352 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3354 a
= operand_type_and (t
, type_names
[j
].mask
);
3355 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3356 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3361 #endif /* DEBUG386 */
3363 static bfd_reloc_code_real_type
3364 reloc (unsigned int size
,
3367 bfd_reloc_code_real_type other
)
3369 if (other
!= NO_RELOC
)
3371 reloc_howto_type
*rel
;
3376 case BFD_RELOC_X86_64_GOT32
:
3377 return BFD_RELOC_X86_64_GOT64
;
3379 case BFD_RELOC_X86_64_GOTPLT64
:
3380 return BFD_RELOC_X86_64_GOTPLT64
;
3382 case BFD_RELOC_X86_64_PLTOFF64
:
3383 return BFD_RELOC_X86_64_PLTOFF64
;
3385 case BFD_RELOC_X86_64_GOTPC32
:
3386 other
= BFD_RELOC_X86_64_GOTPC64
;
3388 case BFD_RELOC_X86_64_GOTPCREL
:
3389 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3391 case BFD_RELOC_X86_64_TPOFF32
:
3392 other
= BFD_RELOC_X86_64_TPOFF64
;
3394 case BFD_RELOC_X86_64_DTPOFF32
:
3395 other
= BFD_RELOC_X86_64_DTPOFF64
;
3401 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3402 if (other
== BFD_RELOC_SIZE32
)
3405 other
= BFD_RELOC_SIZE64
;
3408 as_bad (_("there are no pc-relative size relocations"));
3414 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3415 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3418 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3420 as_bad (_("unknown relocation (%u)"), other
);
3421 else if (size
!= bfd_get_reloc_size (rel
))
3422 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3423 bfd_get_reloc_size (rel
),
3425 else if (pcrel
&& !rel
->pc_relative
)
3426 as_bad (_("non-pc-relative relocation for pc-relative field"));
3427 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3429 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3431 as_bad (_("relocated field and relocation type differ in signedness"));
3440 as_bad (_("there are no unsigned pc-relative relocations"));
3443 case 1: return BFD_RELOC_8_PCREL
;
3444 case 2: return BFD_RELOC_16_PCREL
;
3445 case 4: return BFD_RELOC_32_PCREL
;
3446 case 8: return BFD_RELOC_64_PCREL
;
3448 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3455 case 4: return BFD_RELOC_X86_64_32S
;
3460 case 1: return BFD_RELOC_8
;
3461 case 2: return BFD_RELOC_16
;
3462 case 4: return BFD_RELOC_32
;
3463 case 8: return BFD_RELOC_64
;
3465 as_bad (_("cannot do %s %u byte relocation"),
3466 sign
> 0 ? "signed" : "unsigned", size
);
3472 /* Here we decide which fixups can be adjusted to make them relative to
3473 the beginning of the section instead of the symbol. Basically we need
3474 to make sure that the dynamic relocations are done correctly, so in
3475 some cases we force the original symbol to be used. */
3478 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3480 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3484 /* Don't adjust pc-relative references to merge sections in 64-bit
3486 if (use_rela_relocations
3487 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3491 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3492 and changed later by validate_fix. */
3493 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3494 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3497 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3498 for size relocations. */
3499 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3500 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3501 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3502 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3503 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3504 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3505 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3506 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3507 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3508 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3509 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3510 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3511 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3512 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3513 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3514 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3515 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3516 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3517 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3518 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3519 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3520 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3521 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3522 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3523 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3524 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3525 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3526 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3527 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3528 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3529 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3536 intel_float_operand (const char *mnemonic
)
3538 /* Note that the value returned is meaningful only for opcodes with (memory)
3539 operands, hence the code here is free to improperly handle opcodes that
3540 have no operands (for better performance and smaller code). */
3542 if (mnemonic
[0] != 'f')
3543 return 0; /* non-math */
3545 switch (mnemonic
[1])
3547 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3548 the fs segment override prefix not currently handled because no
3549 call path can make opcodes without operands get here */
3551 return 2 /* integer op */;
3553 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3554 return 3; /* fldcw/fldenv */
3557 if (mnemonic
[2] != 'o' /* fnop */)
3558 return 3; /* non-waiting control op */
3561 if (mnemonic
[2] == 's')
3562 return 3; /* frstor/frstpm */
3565 if (mnemonic
[2] == 'a')
3566 return 3; /* fsave */
3567 if (mnemonic
[2] == 't')
3569 switch (mnemonic
[3])
3571 case 'c': /* fstcw */
3572 case 'd': /* fstdw */
3573 case 'e': /* fstenv */
3574 case 's': /* fsts[gw] */
3580 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3581 return 0; /* fxsave/fxrstor are not really math ops */
3589 install_template (const insn_template
*t
)
3595 /* Note that for pseudo prefixes this produces a length of 1. But for them
3596 the length isn't interesting at all. */
3597 for (l
= 1; l
< 4; ++l
)
3598 if (!(t
->base_opcode
>> (8 * l
)))
3601 i
.opcode_length
= l
;
3604 /* Build the VEX prefix. */
3607 build_vex_prefix (const insn_template
*t
)
3609 unsigned int register_specifier
;
3610 unsigned int vector_length
;
3613 /* Check register specifier. */
3614 if (i
.vex
.register_specifier
)
3616 register_specifier
=
3617 ~register_number (i
.vex
.register_specifier
) & 0xf;
3618 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3621 register_specifier
= 0xf;
3623 /* Use 2-byte VEX prefix by swapping destination and source operand
3624 if there are more than 1 register operand. */
3625 if (i
.reg_operands
> 1
3626 && i
.vec_encoding
!= vex_encoding_vex3
3627 && i
.dir_encoding
== dir_encoding_default
3628 && i
.operands
== i
.reg_operands
3629 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3630 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3631 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3634 unsigned int xchg
= i
.operands
- 1;
3635 union i386_op temp_op
;
3636 i386_operand_type temp_type
;
3638 temp_type
= i
.types
[xchg
];
3639 i
.types
[xchg
] = i
.types
[0];
3640 i
.types
[0] = temp_type
;
3641 temp_op
= i
.op
[xchg
];
3642 i
.op
[xchg
] = i
.op
[0];
3645 gas_assert (i
.rm
.mode
== 3);
3649 i
.rm
.regmem
= i
.rm
.reg
;
3652 if (i
.tm
.opcode_modifier
.d
)
3653 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3654 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3655 else /* Use the next insn. */
3656 install_template (&t
[1]);
3659 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3660 are no memory operands and at least 3 register ones. */
3661 if (i
.reg_operands
>= 3
3662 && i
.vec_encoding
!= vex_encoding_vex3
3663 && i
.reg_operands
== i
.operands
- i
.imm_operands
3664 && i
.tm
.opcode_modifier
.vex
3665 && i
.tm
.opcode_modifier
.commutative
3666 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3668 && i
.vex
.register_specifier
3669 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3671 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3672 union i386_op temp_op
;
3673 i386_operand_type temp_type
;
3675 gas_assert (i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
);
3676 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3677 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3678 &i
.types
[i
.operands
- 3]));
3679 gas_assert (i
.rm
.mode
== 3);
3681 temp_type
= i
.types
[xchg
];
3682 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3683 i
.types
[xchg
+ 1] = temp_type
;
3684 temp_op
= i
.op
[xchg
];
3685 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3686 i
.op
[xchg
+ 1] = temp_op
;
3689 xchg
= i
.rm
.regmem
| 8;
3690 i
.rm
.regmem
= ~register_specifier
& 0xf;
3691 gas_assert (!(i
.rm
.regmem
& 8));
3692 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3693 register_specifier
= ~xchg
& 0xf;
3696 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3697 vector_length
= avxscalar
;
3698 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3704 /* Determine vector length from the last multi-length vector
3707 for (op
= t
->operands
; op
--;)
3708 if (t
->operand_types
[op
].bitfield
.xmmword
3709 && t
->operand_types
[op
].bitfield
.ymmword
3710 && i
.types
[op
].bitfield
.ymmword
)
3717 /* Check the REX.W bit and VEXW. */
3718 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3719 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3720 else if (i
.tm
.opcode_modifier
.vexw
)
3721 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3723 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3725 /* Use 2-byte VEX prefix if possible. */
3727 && i
.vec_encoding
!= vex_encoding_vex3
3728 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
3729 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3731 /* 2-byte VEX prefix. */
3735 i
.vex
.bytes
[0] = 0xc5;
3737 /* Check the REX.R bit. */
3738 r
= (i
.rex
& REX_R
) ? 0 : 1;
3739 i
.vex
.bytes
[1] = (r
<< 7
3740 | register_specifier
<< 3
3741 | vector_length
<< 2
3742 | i
.tm
.opcode_modifier
.opcodeprefix
);
3746 /* 3-byte VEX prefix. */
3749 switch (i
.tm
.opcode_modifier
.opcodespace
)
3754 i
.vex
.bytes
[0] = 0xc4;
3759 i
.vex
.bytes
[0] = 0x8f;
3765 /* The high 3 bits of the second VEX byte are 1's compliment
3766 of RXB bits from REX. */
3767 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3769 i
.vex
.bytes
[2] = (w
<< 7
3770 | register_specifier
<< 3
3771 | vector_length
<< 2
3772 | i
.tm
.opcode_modifier
.opcodeprefix
);
3776 static INLINE bfd_boolean
3777 is_evex_encoding (const insn_template
*t
)
3779 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3780 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3781 || t
->opcode_modifier
.sae
;
3784 static INLINE bfd_boolean
3785 is_any_vex_encoding (const insn_template
*t
)
3787 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3790 /* Build the EVEX prefix. */
3793 build_evex_prefix (void)
3795 unsigned int register_specifier
, w
;
3796 rex_byte vrex_used
= 0;
3798 /* Check register specifier. */
3799 if (i
.vex
.register_specifier
)
3801 gas_assert ((i
.vrex
& REX_X
) == 0);
3803 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3804 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3805 register_specifier
+= 8;
3806 /* The upper 16 registers are encoded in the fourth byte of the
3808 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3809 i
.vex
.bytes
[3] = 0x8;
3810 register_specifier
= ~register_specifier
& 0xf;
3814 register_specifier
= 0xf;
3816 /* Encode upper 16 vector index register in the fourth byte of
3818 if (!(i
.vrex
& REX_X
))
3819 i
.vex
.bytes
[3] = 0x8;
3824 /* 4 byte EVEX prefix. */
3826 i
.vex
.bytes
[0] = 0x62;
3828 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3830 gas_assert (i
.tm
.opcode_modifier
.opcodespace
>= SPACE_0F
);
3831 gas_assert (i
.tm
.opcode_modifier
.opcodespace
<= SPACE_0F3A
);
3832 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | i
.tm
.opcode_modifier
.opcodespace
;
3834 /* The fifth bit of the second EVEX byte is 1's compliment of the
3835 REX_R bit in VREX. */
3836 if (!(i
.vrex
& REX_R
))
3837 i
.vex
.bytes
[1] |= 0x10;
3841 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3843 /* When all operands are registers, the REX_X bit in REX is not
3844 used. We reuse it to encode the upper 16 registers, which is
3845 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3846 as 1's compliment. */
3847 if ((i
.vrex
& REX_B
))
3850 i
.vex
.bytes
[1] &= ~0x40;
3854 /* EVEX instructions shouldn't need the REX prefix. */
3855 i
.vrex
&= ~vrex_used
;
3856 gas_assert (i
.vrex
== 0);
3858 /* Check the REX.W bit and VEXW. */
3859 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3860 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3861 else if (i
.tm
.opcode_modifier
.vexw
)
3862 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3864 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3866 /* The third byte of the EVEX prefix. */
3867 i
.vex
.bytes
[2] = ((w
<< 7)
3868 | (register_specifier
<< 3)
3869 | 4 /* Encode the U bit. */
3870 | i
.tm
.opcode_modifier
.opcodeprefix
);
3872 /* The fourth byte of the EVEX prefix. */
3873 /* The zeroing-masking bit. */
3874 if (i
.mask
&& i
.mask
->zeroing
)
3875 i
.vex
.bytes
[3] |= 0x80;
3877 /* Don't always set the broadcast bit if there is no RC. */
3880 /* Encode the vector length. */
3881 unsigned int vec_length
;
3883 if (!i
.tm
.opcode_modifier
.evex
3884 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3888 /* Determine vector length from the last multi-length vector
3890 for (op
= i
.operands
; op
--;)
3891 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3892 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3893 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3895 if (i
.types
[op
].bitfield
.zmmword
)
3897 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3900 else if (i
.types
[op
].bitfield
.ymmword
)
3902 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3905 else if (i
.types
[op
].bitfield
.xmmword
)
3907 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3910 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3912 switch (i
.broadcast
->bytes
)
3915 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3918 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3921 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3930 if (op
>= MAX_OPERANDS
)
3934 switch (i
.tm
.opcode_modifier
.evex
)
3936 case EVEXLIG
: /* LL' is ignored */
3937 vec_length
= evexlig
<< 5;
3940 vec_length
= 0 << 5;
3943 vec_length
= 1 << 5;
3946 vec_length
= 2 << 5;
3952 i
.vex
.bytes
[3] |= vec_length
;
3953 /* Encode the broadcast bit. */
3955 i
.vex
.bytes
[3] |= 0x10;
3959 if (i
.rounding
->type
!= saeonly
)
3960 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3962 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3965 if (i
.mask
&& i
.mask
->mask
)
3966 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3970 process_immext (void)
3974 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3975 which is coded in the same place as an 8-bit immediate field
3976 would be. Here we fake an 8-bit immediate operand from the
3977 opcode suffix stored in tm.extension_opcode.
3979 AVX instructions also use this encoding, for some of
3980 3 argument instructions. */
3982 gas_assert (i
.imm_operands
<= 1
3984 || (is_any_vex_encoding (&i
.tm
)
3985 && i
.operands
<= 4)));
3987 exp
= &im_expressions
[i
.imm_operands
++];
3988 i
.op
[i
.operands
].imms
= exp
;
3989 i
.types
[i
.operands
] = imm8
;
3991 exp
->X_op
= O_constant
;
3992 exp
->X_add_number
= i
.tm
.extension_opcode
;
3993 i
.tm
.extension_opcode
= None
;
4000 switch (i
.tm
.opcode_modifier
.prefixok
)
4008 as_bad (_("invalid instruction `%s' after `%s'"),
4009 i
.tm
.name
, i
.hle_prefix
);
4012 if (i
.prefix
[LOCK_PREFIX
])
4014 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4018 case PrefixHLERelease
:
4019 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4021 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4025 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4027 as_bad (_("memory destination needed for instruction `%s'"
4028 " after `xrelease'"), i
.tm
.name
);
4035 /* Try the shortest encoding by shortening operand size. */
4038 optimize_encoding (void)
4042 if (optimize_for_space
4043 && !is_any_vex_encoding (&i
.tm
)
4044 && i
.reg_operands
== 1
4045 && i
.imm_operands
== 1
4046 && !i
.types
[1].bitfield
.byte
4047 && i
.op
[0].imms
->X_op
== O_constant
4048 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4049 && (i
.tm
.base_opcode
== 0xa8
4050 || (i
.tm
.base_opcode
== 0xf6
4051 && i
.tm
.extension_opcode
== 0x0)))
4054 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4056 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4057 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4059 i
.types
[1].bitfield
.byte
= 1;
4060 /* Ignore the suffix. */
4062 /* Convert to byte registers. */
4063 if (i
.types
[1].bitfield
.word
)
4065 else if (i
.types
[1].bitfield
.dword
)
4069 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4074 else if (flag_code
== CODE_64BIT
4075 && !is_any_vex_encoding (&i
.tm
)
4076 && ((i
.types
[1].bitfield
.qword
4077 && i
.reg_operands
== 1
4078 && i
.imm_operands
== 1
4079 && i
.op
[0].imms
->X_op
== O_constant
4080 && ((i
.tm
.base_opcode
== 0xb8
4081 && i
.tm
.extension_opcode
== None
4082 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4083 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4084 && ((i
.tm
.base_opcode
== 0x24
4085 || i
.tm
.base_opcode
== 0xa8)
4086 || (i
.tm
.base_opcode
== 0x80
4087 && i
.tm
.extension_opcode
== 0x4)
4088 || ((i
.tm
.base_opcode
== 0xf6
4089 || (i
.tm
.base_opcode
| 1) == 0xc7)
4090 && i
.tm
.extension_opcode
== 0x0)))
4091 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4092 && i
.tm
.base_opcode
== 0x83
4093 && i
.tm
.extension_opcode
== 0x4)))
4094 || (i
.types
[0].bitfield
.qword
4095 && ((i
.reg_operands
== 2
4096 && i
.op
[0].regs
== i
.op
[1].regs
4097 && (i
.tm
.base_opcode
== 0x30
4098 || i
.tm
.base_opcode
== 0x28))
4099 || (i
.reg_operands
== 1
4101 && i
.tm
.base_opcode
== 0x30)))))
4104 andq $imm31, %r64 -> andl $imm31, %r32
4105 andq $imm7, %r64 -> andl $imm7, %r32
4106 testq $imm31, %r64 -> testl $imm31, %r32
4107 xorq %r64, %r64 -> xorl %r32, %r32
4108 subq %r64, %r64 -> subl %r32, %r32
4109 movq $imm31, %r64 -> movl $imm31, %r32
4110 movq $imm32, %r64 -> movl $imm32, %r32
4112 i
.tm
.opcode_modifier
.norex64
= 1;
4113 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4116 movq $imm31, %r64 -> movl $imm31, %r32
4117 movq $imm32, %r64 -> movl $imm32, %r32
4119 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4120 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4121 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4122 i
.types
[0].bitfield
.imm32
= 1;
4123 i
.types
[0].bitfield
.imm32s
= 0;
4124 i
.types
[0].bitfield
.imm64
= 0;
4125 i
.types
[1].bitfield
.dword
= 1;
4126 i
.types
[1].bitfield
.qword
= 0;
4127 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4130 movq $imm31, %r64 -> movl $imm31, %r32
4132 i
.tm
.base_opcode
= 0xb8;
4133 i
.tm
.extension_opcode
= None
;
4134 i
.tm
.opcode_modifier
.w
= 0;
4135 i
.tm
.opcode_modifier
.modrm
= 0;
4139 else if (optimize
> 1
4140 && !optimize_for_space
4141 && !is_any_vex_encoding (&i
.tm
)
4142 && i
.reg_operands
== 2
4143 && i
.op
[0].regs
== i
.op
[1].regs
4144 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4145 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4146 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4149 andb %rN, %rN -> testb %rN, %rN
4150 andw %rN, %rN -> testw %rN, %rN
4151 andq %rN, %rN -> testq %rN, %rN
4152 orb %rN, %rN -> testb %rN, %rN
4153 orw %rN, %rN -> testw %rN, %rN
4154 orq %rN, %rN -> testq %rN, %rN
4156 and outside of 64-bit mode
4158 andl %rN, %rN -> testl %rN, %rN
4159 orl %rN, %rN -> testl %rN, %rN
4161 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4163 else if (i
.reg_operands
== 3
4164 && i
.op
[0].regs
== i
.op
[1].regs
4165 && !i
.types
[2].bitfield
.xmmword
4166 && (i
.tm
.opcode_modifier
.vex
4167 || ((!i
.mask
|| i
.mask
->zeroing
)
4169 && is_evex_encoding (&i
.tm
)
4170 && (i
.vec_encoding
!= vex_encoding_evex
4171 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4172 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4173 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4174 && i
.types
[2].bitfield
.ymmword
))))
4175 && ((i
.tm
.base_opcode
== 0x55
4176 || i
.tm
.base_opcode
== 0x57
4177 || i
.tm
.base_opcode
== 0xdf
4178 || i
.tm
.base_opcode
== 0xef
4179 || i
.tm
.base_opcode
== 0xf8
4180 || i
.tm
.base_opcode
== 0xf9
4181 || i
.tm
.base_opcode
== 0xfa
4182 || i
.tm
.base_opcode
== 0xfb
4183 || i
.tm
.base_opcode
== 0x42
4184 || i
.tm
.base_opcode
== 0x47)
4185 && i
.tm
.extension_opcode
== None
))
4188 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4190 EVEX VOP %zmmM, %zmmM, %zmmN
4191 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4192 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4193 EVEX VOP %ymmM, %ymmM, %ymmN
4194 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4195 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4196 VEX VOP %ymmM, %ymmM, %ymmN
4197 -> VEX VOP %xmmM, %xmmM, %xmmN
4198 VOP, one of vpandn and vpxor:
4199 VEX VOP %ymmM, %ymmM, %ymmN
4200 -> VEX VOP %xmmM, %xmmM, %xmmN
4201 VOP, one of vpandnd and vpandnq:
4202 EVEX VOP %zmmM, %zmmM, %zmmN
4203 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4204 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4205 EVEX VOP %ymmM, %ymmM, %ymmN
4206 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4207 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4208 VOP, one of vpxord and vpxorq:
4209 EVEX VOP %zmmM, %zmmM, %zmmN
4210 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4211 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4212 EVEX VOP %ymmM, %ymmM, %ymmN
4213 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4214 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4215 VOP, one of kxord and kxorq:
4216 VEX VOP %kM, %kM, %kN
4217 -> VEX kxorw %kM, %kM, %kN
4218 VOP, one of kandnd and kandnq:
4219 VEX VOP %kM, %kM, %kN
4220 -> VEX kandnw %kM, %kM, %kN
4222 if (is_evex_encoding (&i
.tm
))
4224 if (i
.vec_encoding
!= vex_encoding_evex
)
4226 i
.tm
.opcode_modifier
.vex
= VEX128
;
4227 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4228 i
.tm
.opcode_modifier
.evex
= 0;
4230 else if (optimize
> 1)
4231 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4235 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4237 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4238 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4241 i
.tm
.opcode_modifier
.vex
= VEX128
;
4243 if (i
.tm
.opcode_modifier
.vex
)
4244 for (j
= 0; j
< 3; j
++)
4246 i
.types
[j
].bitfield
.xmmword
= 1;
4247 i
.types
[j
].bitfield
.ymmword
= 0;
4250 else if (i
.vec_encoding
!= vex_encoding_evex
4251 && !i
.types
[0].bitfield
.zmmword
4252 && !i
.types
[1].bitfield
.zmmword
4255 && is_evex_encoding (&i
.tm
)
4256 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4257 || (i
.tm
.base_opcode
& ~4) == 0xdb
4258 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4259 && i
.tm
.extension_opcode
== None
)
4262 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4263 vmovdqu32 and vmovdqu64:
4264 EVEX VOP %xmmM, %xmmN
4265 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4266 EVEX VOP %ymmM, %ymmN
4267 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4269 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4271 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4273 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4275 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4276 VOP, one of vpand, vpandn, vpor, vpxor:
4277 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4278 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4279 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4280 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4281 EVEX VOP{d,q} mem, %xmmM, %xmmN
4282 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4283 EVEX VOP{d,q} mem, %ymmM, %ymmN
4284 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4286 for (j
= 0; j
< i
.operands
; j
++)
4287 if (operand_type_check (i
.types
[j
], disp
)
4288 && i
.op
[j
].disps
->X_op
== O_constant
)
4290 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4291 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4292 bytes, we choose EVEX Disp8 over VEX Disp32. */
4293 int evex_disp8
, vex_disp8
;
4294 unsigned int memshift
= i
.memshift
;
4295 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4297 evex_disp8
= fits_in_disp8 (n
);
4299 vex_disp8
= fits_in_disp8 (n
);
4300 if (evex_disp8
!= vex_disp8
)
4302 i
.memshift
= memshift
;
4306 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4309 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4310 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4311 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4312 i
.tm
.opcode_modifier
.vex
4313 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4314 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4315 /* VPAND, VPOR, and VPXOR are commutative. */
4316 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4317 i
.tm
.opcode_modifier
.commutative
= 1;
4318 i
.tm
.opcode_modifier
.evex
= 0;
4319 i
.tm
.opcode_modifier
.masking
= 0;
4320 i
.tm
.opcode_modifier
.broadcast
= 0;
4321 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4324 i
.types
[j
].bitfield
.disp8
4325 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4329 /* Return non-zero for load instruction. */
4335 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4336 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4340 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4341 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4342 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4343 if (i
.tm
.opcode_modifier
.anysize
)
4346 /* pop, popf, popa. */
4347 if (strcmp (i
.tm
.name
, "pop") == 0
4348 || i
.tm
.base_opcode
== 0x9d
4349 || i
.tm
.base_opcode
== 0x61)
4352 /* movs, cmps, lods, scas. */
4353 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4357 if (base_opcode
== 0x6f
4358 || i
.tm
.base_opcode
== 0xd7)
4360 /* NB: For AMD-specific insns with implicit memory operands,
4361 they're intentionally not covered. */
4364 /* No memory operand. */
4365 if (!i
.mem_operands
)
4371 if (i
.tm
.base_opcode
== 0xae
4372 && i
.tm
.opcode_modifier
.vex
4373 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_0F
4374 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4375 && i
.tm
.extension_opcode
== 2)
4380 /* test, not, neg, mul, imul, div, idiv. */
4381 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4382 && i
.tm
.extension_opcode
!= 1)
4386 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4389 /* add, or, adc, sbb, and, sub, xor, cmp. */
4390 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4393 /* bt, bts, btr, btc. */
4394 if (i
.tm
.base_opcode
== 0xfba
4395 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4398 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4399 if ((base_opcode
== 0xc1
4400 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4401 && i
.tm
.extension_opcode
!= 6)
4404 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4405 if (i
.tm
.base_opcode
== 0xfc7
4406 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4407 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4408 || i
.tm
.extension_opcode
== 6))
4411 /* fxrstor, ldmxcsr, xrstor. */
4412 if (i
.tm
.base_opcode
== 0xfae
4413 && (i
.tm
.extension_opcode
== 1
4414 || i
.tm
.extension_opcode
== 2
4415 || i
.tm
.extension_opcode
== 5))
4418 /* lgdt, lidt, lmsw. */
4419 if (i
.tm
.base_opcode
== 0xf01
4420 && (i
.tm
.extension_opcode
== 2
4421 || i
.tm
.extension_opcode
== 3
4422 || i
.tm
.extension_opcode
== 6))
4425 /* Check for x87 instructions. */
4426 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4428 /* Skip fst, fstp, fstenv, fstcw. */
4429 if (i
.tm
.base_opcode
== 0xd9
4430 && (i
.tm
.extension_opcode
== 2
4431 || i
.tm
.extension_opcode
== 3
4432 || i
.tm
.extension_opcode
== 6
4433 || i
.tm
.extension_opcode
== 7))
4436 /* Skip fisttp, fist, fistp, fstp. */
4437 if (i
.tm
.base_opcode
== 0xdb
4438 && (i
.tm
.extension_opcode
== 1
4439 || i
.tm
.extension_opcode
== 2
4440 || i
.tm
.extension_opcode
== 3
4441 || i
.tm
.extension_opcode
== 7))
4444 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4445 if (i
.tm
.base_opcode
== 0xdd
4446 && (i
.tm
.extension_opcode
== 1
4447 || i
.tm
.extension_opcode
== 2
4448 || i
.tm
.extension_opcode
== 3
4449 || i
.tm
.extension_opcode
== 6
4450 || i
.tm
.extension_opcode
== 7))
4453 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4454 if (i
.tm
.base_opcode
== 0xdf
4455 && (i
.tm
.extension_opcode
== 1
4456 || i
.tm
.extension_opcode
== 2
4457 || i
.tm
.extension_opcode
== 3
4458 || i
.tm
.extension_opcode
== 6
4459 || i
.tm
.extension_opcode
== 7))
4466 dest
= i
.operands
- 1;
4468 /* Check fake imm8 operand and 3 source operands. */
4469 if ((i
.tm
.opcode_modifier
.immext
4470 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4471 && i
.types
[dest
].bitfield
.imm8
)
4474 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4476 && (base_opcode
== 0x1
4477 || base_opcode
== 0x9
4478 || base_opcode
== 0x11
4479 || base_opcode
== 0x19
4480 || base_opcode
== 0x21
4481 || base_opcode
== 0x29
4482 || base_opcode
== 0x31
4483 || base_opcode
== 0x39
4484 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4485 || base_opcode
== 0xfc1))
4488 /* Check for load instruction. */
4489 return (i
.types
[dest
].bitfield
.class != ClassNone
4490 || i
.types
[dest
].bitfield
.instance
== Accum
);
4493 /* Output lfence, 0xfaee8, after instruction. */
4496 insert_lfence_after (void)
4498 if (lfence_after_load
&& load_insn_p ())
4500 /* There are also two REP string instructions that require
4501 special treatment. Specifically, the compare string (CMPS)
4502 and scan string (SCAS) instructions set EFLAGS in a manner
4503 that depends on the data being compared/scanned. When used
4504 with a REP prefix, the number of iterations may therefore
4505 vary depending on this data. If the data is a program secret
4506 chosen by the adversary using an LVI method,
4507 then this data-dependent behavior may leak some aspect
4509 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4510 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4511 && i
.prefix
[REP_PREFIX
])
4513 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4516 char *p
= frag_more (3);
4523 /* Output lfence, 0xfaee8, before instruction. */
4526 insert_lfence_before (void)
4530 if (is_any_vex_encoding (&i
.tm
))
4533 if (i
.tm
.base_opcode
== 0xff
4534 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4536 /* Insert lfence before indirect branch if needed. */
4538 if (lfence_before_indirect_branch
== lfence_branch_none
)
4541 if (i
.operands
!= 1)
4544 if (i
.reg_operands
== 1)
4546 /* Indirect branch via register. Don't insert lfence with
4547 -mlfence-after-load=yes. */
4548 if (lfence_after_load
4549 || lfence_before_indirect_branch
== lfence_branch_memory
)
4552 else if (i
.mem_operands
== 1
4553 && lfence_before_indirect_branch
!= lfence_branch_register
)
4555 as_warn (_("indirect `%s` with memory operand should be avoided"),
4562 if (last_insn
.kind
!= last_insn_other
4563 && last_insn
.seg
== now_seg
)
4565 as_warn_where (last_insn
.file
, last_insn
.line
,
4566 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4567 last_insn
.name
, i
.tm
.name
);
4578 /* Output or/not/shl and lfence before near ret. */
4579 if (lfence_before_ret
!= lfence_before_ret_none
4580 && (i
.tm
.base_opcode
== 0xc2
4581 || i
.tm
.base_opcode
== 0xc3))
4583 if (last_insn
.kind
!= last_insn_other
4584 && last_insn
.seg
== now_seg
)
4586 as_warn_where (last_insn
.file
, last_insn
.line
,
4587 _("`%s` skips -mlfence-before-ret on `%s`"),
4588 last_insn
.name
, i
.tm
.name
);
4592 /* Near ret ingore operand size override under CPU64. */
4593 char prefix
= flag_code
== CODE_64BIT
4595 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4597 if (lfence_before_ret
== lfence_before_ret_not
)
4599 /* not: 0xf71424, may add prefix
4600 for operand size override or 64-bit code. */
4601 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4615 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4618 if (lfence_before_ret
== lfence_before_ret_or
)
4620 /* or: 0x830c2400, may add prefix
4621 for operand size override or 64-bit code. */
4627 /* shl: 0xc1242400, may add prefix
4628 for operand size override or 64-bit code. */
4643 /* This is the guts of the machine-dependent assembler. LINE points to a
4644 machine dependent instruction. This function is supposed to emit
4645 the frags/bytes it assembles to. */
4648 md_assemble (char *line
)
4651 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4652 const insn_template
*t
;
4654 /* Initialize globals. */
4655 memset (&i
, '\0', sizeof (i
));
4656 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4657 i
.reloc
[j
] = NO_RELOC
;
4658 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4659 memset (im_expressions
, '\0', sizeof (im_expressions
));
4660 save_stack_p
= save_stack
;
4662 /* First parse an instruction mnemonic & call i386_operand for the operands.
4663 We assume that the scrubber has arranged it so that line[0] is the valid
4664 start of a (possibly prefixed) mnemonic. */
4666 line
= parse_insn (line
, mnemonic
);
4669 mnem_suffix
= i
.suffix
;
4671 line
= parse_operands (line
, mnemonic
);
4673 xfree (i
.memop1_string
);
4674 i
.memop1_string
= NULL
;
4678 /* Now we've parsed the mnemonic into a set of templates, and have the
4679 operands at hand. */
4681 /* All Intel opcodes have reversed operands except for "bound", "enter",
4682 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4683 intersegment "jmp" and "call" instructions with 2 immediate operands so
4684 that the immediate segment precedes the offset, as it does when in AT&T
4688 && (strcmp (mnemonic
, "bound") != 0)
4689 && (strcmp (mnemonic
, "invlpga") != 0)
4690 && (strncmp (mnemonic
, "monitor", 7) != 0)
4691 && (strncmp (mnemonic
, "mwait", 5) != 0)
4692 && (strcmp (mnemonic
, "tpause") != 0)
4693 && (strcmp (mnemonic
, "umwait") != 0)
4694 && !(operand_type_check (i
.types
[0], imm
)
4695 && operand_type_check (i
.types
[1], imm
)))
4698 /* The order of the immediates should be reversed
4699 for 2 immediates extrq and insertq instructions */
4700 if (i
.imm_operands
== 2
4701 && (strcmp (mnemonic
, "extrq") == 0
4702 || strcmp (mnemonic
, "insertq") == 0))
4703 swap_2_operands (0, 1);
4708 /* Don't optimize displacement for movabs since it only takes 64bit
4711 && i
.disp_encoding
!= disp_encoding_32bit
4712 && (flag_code
!= CODE_64BIT
4713 || strcmp (mnemonic
, "movabs") != 0))
4716 /* Next, we find a template that matches the given insn,
4717 making sure the overlap of the given operands types is consistent
4718 with the template operand types. */
4720 if (!(t
= match_template (mnem_suffix
)))
4723 if (sse_check
!= check_none
4724 && !i
.tm
.opcode_modifier
.noavx
4725 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4726 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4727 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4728 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4729 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4730 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4731 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4732 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4733 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4734 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4735 || i
.tm
.cpu_flags
.bitfield
.cpusha
4736 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4738 (sse_check
== check_warning
4740 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4743 if (i
.tm
.opcode_modifier
.fwait
)
4744 if (!add_prefix (FWAIT_OPCODE
))
4747 /* Check if REP prefix is OK. */
4748 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
4750 as_bad (_("invalid instruction `%s' after `%s'"),
4751 i
.tm
.name
, i
.rep_prefix
);
4755 /* Check for lock without a lockable instruction. Destination operand
4756 must be memory unless it is xchg (0x86). */
4757 if (i
.prefix
[LOCK_PREFIX
]
4758 && (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
4759 || i
.mem_operands
== 0
4760 || (i
.tm
.base_opcode
!= 0x86
4761 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4763 as_bad (_("expecting lockable instruction after `lock'"));
4767 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4768 if (i
.prefix
[DATA_PREFIX
]
4769 && (is_any_vex_encoding (&i
.tm
)
4770 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4771 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4773 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4777 /* Check if HLE prefix is OK. */
4778 if (i
.hle_prefix
&& !check_hle ())
4781 /* Check BND prefix. */
4782 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4783 as_bad (_("expecting valid branch instruction after `bnd'"));
4785 /* Check NOTRACK prefix. */
4786 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
4787 as_bad (_("expecting indirect branch instruction after `notrack'"));
4789 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4791 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4792 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4793 else if (flag_code
!= CODE_16BIT
4794 ? i
.prefix
[ADDR_PREFIX
]
4795 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4796 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4799 /* Insert BND prefix. */
4800 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4802 if (!i
.prefix
[BND_PREFIX
])
4803 add_prefix (BND_PREFIX_OPCODE
);
4804 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4806 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4807 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4811 /* Check string instruction segment overrides. */
4812 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4814 gas_assert (i
.mem_operands
);
4815 if (!check_string ())
4817 i
.disp_operands
= 0;
4820 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4821 optimize_encoding ();
4823 if (!process_suffix ())
4826 /* Update operand types and check extended states. */
4827 for (j
= 0; j
< i
.operands
; j
++)
4829 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4830 switch (i
.tm
.operand_types
[j
].bitfield
.class)
4835 i
.xstate
|= xstate_mmx
;
4838 i
.xstate
|= xstate_mask
;
4841 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
4842 i
.xstate
|= xstate_tmm
;
4843 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
4844 i
.xstate
|= xstate_zmm
;
4845 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
4846 i
.xstate
|= xstate_ymm
;
4847 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
4848 i
.xstate
|= xstate_xmm
;
4853 /* Make still unresolved immediate matches conform to size of immediate
4854 given in i.suffix. */
4855 if (!finalize_imm ())
4858 if (i
.types
[0].bitfield
.imm1
)
4859 i
.imm_operands
= 0; /* kludge for shift insns. */
4861 /* We only need to check those implicit registers for instructions
4862 with 3 operands or less. */
4863 if (i
.operands
<= 3)
4864 for (j
= 0; j
< i
.operands
; j
++)
4865 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4866 && !i
.types
[j
].bitfield
.xmmword
)
4869 /* For insns with operands there are more diddles to do to the opcode. */
4872 if (!process_operands ())
4875 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4877 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4878 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4881 if (is_any_vex_encoding (&i
.tm
))
4883 if (!cpu_arch_flags
.bitfield
.cpui286
)
4885 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4890 /* Check for explicit REX prefix. */
4891 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4893 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4897 if (i
.tm
.opcode_modifier
.vex
)
4898 build_vex_prefix (t
);
4900 build_evex_prefix ();
4902 /* The individual REX.RXBW bits got consumed. */
4903 i
.rex
&= REX_OPCODE
;
4906 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4907 instructions may define INT_OPCODE as well, so avoid this corner
4908 case for those instructions that use MODRM. */
4909 if (i
.tm
.base_opcode
== INT_OPCODE
4910 && !i
.tm
.opcode_modifier
.modrm
4911 && i
.op
[0].imms
->X_add_number
== 3)
4913 i
.tm
.base_opcode
= INT3_OPCODE
;
4917 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4918 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4919 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4920 && i
.op
[0].disps
->X_op
== O_constant
)
4922 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4923 the absolute address given by the constant. Since ix86 jumps and
4924 calls are pc relative, we need to generate a reloc. */
4925 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4926 i
.op
[0].disps
->X_op
= O_symbol
;
4929 /* For 8 bit registers we need an empty rex prefix. Also if the
4930 instruction already has a prefix, we need to convert old
4931 registers to new ones. */
4933 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4934 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4935 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4936 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4937 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4938 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4943 i
.rex
|= REX_OPCODE
;
4944 for (x
= 0; x
< 2; x
++)
4946 /* Look for 8 bit operand that uses old registers. */
4947 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4948 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4950 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4951 /* In case it is "hi" register, give up. */
4952 if (i
.op
[x
].regs
->reg_num
> 3)
4953 as_bad (_("can't encode register '%s%s' in an "
4954 "instruction requiring REX prefix."),
4955 register_prefix
, i
.op
[x
].regs
->reg_name
);
4957 /* Otherwise it is equivalent to the extended register.
4958 Since the encoding doesn't change this is merely
4959 cosmetic cleanup for debug output. */
4961 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4966 if (i
.rex
== 0 && i
.rex_encoding
)
4968 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4969 that uses legacy register. If it is "hi" register, don't add
4970 the REX_OPCODE byte. */
4972 for (x
= 0; x
< 2; x
++)
4973 if (i
.types
[x
].bitfield
.class == Reg
4974 && i
.types
[x
].bitfield
.byte
4975 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4976 && i
.op
[x
].regs
->reg_num
> 3)
4978 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4979 i
.rex_encoding
= FALSE
;
4988 add_prefix (REX_OPCODE
| i
.rex
);
4990 insert_lfence_before ();
4992 /* We are ready to output the insn. */
4995 insert_lfence_after ();
4997 last_insn
.seg
= now_seg
;
4999 if (i
.tm
.opcode_modifier
.isprefix
)
5001 last_insn
.kind
= last_insn_prefix
;
5002 last_insn
.name
= i
.tm
.name
;
5003 last_insn
.file
= as_where (&last_insn
.line
);
5006 last_insn
.kind
= last_insn_other
;
5010 parse_insn (char *line
, char *mnemonic
)
5013 char *token_start
= l
;
5016 const insn_template
*t
;
5022 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5027 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5029 as_bad (_("no such instruction: `%s'"), token_start
);
5034 if (!is_space_char (*l
)
5035 && *l
!= END_OF_INSN
5037 || (*l
!= PREFIX_SEPARATOR
5040 as_bad (_("invalid character %s in mnemonic"),
5041 output_invalid (*l
));
5044 if (token_start
== l
)
5046 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5047 as_bad (_("expecting prefix; got nothing"));
5049 as_bad (_("expecting mnemonic; got nothing"));
5053 /* Look up instruction (or prefix) via hash table. */
5054 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5056 if (*l
!= END_OF_INSN
5057 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5058 && current_templates
5059 && current_templates
->start
->opcode_modifier
.isprefix
)
5061 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5063 as_bad ((flag_code
!= CODE_64BIT
5064 ? _("`%s' is only supported in 64-bit mode")
5065 : _("`%s' is not supported in 64-bit mode")),
5066 current_templates
->start
->name
);
5069 /* If we are in 16-bit mode, do not allow addr16 or data16.
5070 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5071 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5072 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5073 && flag_code
!= CODE_64BIT
5074 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5075 ^ (flag_code
== CODE_16BIT
)))
5077 as_bad (_("redundant %s prefix"),
5078 current_templates
->start
->name
);
5082 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5084 /* Handle pseudo prefixes. */
5085 switch (current_templates
->start
->extension_opcode
)
5089 i
.disp_encoding
= disp_encoding_8bit
;
5093 i
.disp_encoding
= disp_encoding_16bit
;
5097 i
.disp_encoding
= disp_encoding_32bit
;
5101 i
.dir_encoding
= dir_encoding_load
;
5105 i
.dir_encoding
= dir_encoding_store
;
5109 i
.vec_encoding
= vex_encoding_vex
;
5113 i
.vec_encoding
= vex_encoding_vex3
;
5117 i
.vec_encoding
= vex_encoding_evex
;
5121 i
.rex_encoding
= TRUE
;
5123 case Prefix_NoOptimize
:
5125 i
.no_optimize
= TRUE
;
5133 /* Add prefix, checking for repeated prefixes. */
5134 switch (add_prefix (current_templates
->start
->base_opcode
))
5139 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5140 i
.notrack_prefix
= current_templates
->start
->name
;
5143 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5144 i
.hle_prefix
= current_templates
->start
->name
;
5145 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5146 i
.bnd_prefix
= current_templates
->start
->name
;
5148 i
.rep_prefix
= current_templates
->start
->name
;
5154 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5161 if (!current_templates
)
5163 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5164 Check if we should swap operand or force 32bit displacement in
5166 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5167 i
.dir_encoding
= dir_encoding_swap
;
5168 else if (mnem_p
- 3 == dot_p
5171 i
.disp_encoding
= disp_encoding_8bit
;
5172 else if (mnem_p
- 4 == dot_p
5176 i
.disp_encoding
= disp_encoding_32bit
;
5181 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5184 if (!current_templates
)
5187 if (mnem_p
> mnemonic
)
5189 /* See if we can get a match by trimming off a suffix. */
5192 case WORD_MNEM_SUFFIX
:
5193 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5194 i
.suffix
= SHORT_MNEM_SUFFIX
;
5197 case BYTE_MNEM_SUFFIX
:
5198 case QWORD_MNEM_SUFFIX
:
5199 i
.suffix
= mnem_p
[-1];
5202 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5204 case SHORT_MNEM_SUFFIX
:
5205 case LONG_MNEM_SUFFIX
:
5208 i
.suffix
= mnem_p
[-1];
5211 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5219 if (intel_float_operand (mnemonic
) == 1)
5220 i
.suffix
= SHORT_MNEM_SUFFIX
;
5222 i
.suffix
= LONG_MNEM_SUFFIX
;
5225 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5231 if (!current_templates
)
5233 as_bad (_("no such instruction: `%s'"), token_start
);
5238 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5239 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5241 /* Check for a branch hint. We allow ",pt" and ",pn" for
5242 predict taken and predict not taken respectively.
5243 I'm not sure that branch hints actually do anything on loop
5244 and jcxz insns (JumpByte) for current Pentium4 chips. They
5245 may work in the future and it doesn't hurt to accept them
5247 if (l
[0] == ',' && l
[1] == 'p')
5251 if (!add_prefix (DS_PREFIX_OPCODE
))
5255 else if (l
[2] == 'n')
5257 if (!add_prefix (CS_PREFIX_OPCODE
))
5263 /* Any other comma loses. */
5266 as_bad (_("invalid character %s in mnemonic"),
5267 output_invalid (*l
));
5271 /* Check if instruction is supported on specified architecture. */
5273 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5275 supported
|= cpu_flags_match (t
);
5276 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5278 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5279 as_warn (_("use .code16 to ensure correct addressing mode"));
5285 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5286 as_bad (flag_code
== CODE_64BIT
5287 ? _("`%s' is not supported in 64-bit mode")
5288 : _("`%s' is only supported in 64-bit mode"),
5289 current_templates
->start
->name
);
5291 as_bad (_("`%s' is not supported on `%s%s'"),
5292 current_templates
->start
->name
,
5293 cpu_arch_name
? cpu_arch_name
: default_arch
,
5294 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5300 parse_operands (char *l
, const char *mnemonic
)
5304 /* 1 if operand is pending after ','. */
5305 unsigned int expecting_operand
= 0;
5307 /* Non-zero if operand parens not balanced. */
5308 unsigned int paren_not_balanced
;
5310 while (*l
!= END_OF_INSN
)
5312 /* Skip optional white space before operand. */
5313 if (is_space_char (*l
))
5315 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5317 as_bad (_("invalid character %s before operand %d"),
5318 output_invalid (*l
),
5322 token_start
= l
; /* After white space. */
5323 paren_not_balanced
= 0;
5324 while (paren_not_balanced
|| *l
!= ',')
5326 if (*l
== END_OF_INSN
)
5328 if (paren_not_balanced
)
5331 as_bad (_("unbalanced parenthesis in operand %d."),
5334 as_bad (_("unbalanced brackets in operand %d."),
5339 break; /* we are done */
5341 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5343 as_bad (_("invalid character %s in operand %d"),
5344 output_invalid (*l
),
5351 ++paren_not_balanced
;
5353 --paren_not_balanced
;
5358 ++paren_not_balanced
;
5360 --paren_not_balanced
;
5364 if (l
!= token_start
)
5365 { /* Yes, we've read in another operand. */
5366 unsigned int operand_ok
;
5367 this_operand
= i
.operands
++;
5368 if (i
.operands
> MAX_OPERANDS
)
5370 as_bad (_("spurious operands; (%d operands/instruction max)"),
5374 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5375 /* Now parse operand adding info to 'i' as we go along. */
5376 END_STRING_AND_SAVE (l
);
5378 if (i
.mem_operands
> 1)
5380 as_bad (_("too many memory references for `%s'"),
5387 i386_intel_operand (token_start
,
5388 intel_float_operand (mnemonic
));
5390 operand_ok
= i386_att_operand (token_start
);
5392 RESTORE_END_STRING (l
);
5398 if (expecting_operand
)
5400 expecting_operand_after_comma
:
5401 as_bad (_("expecting operand after ','; got nothing"));
5406 as_bad (_("expecting operand before ','; got nothing"));
5411 /* Now *l must be either ',' or END_OF_INSN. */
5414 if (*++l
== END_OF_INSN
)
5416 /* Just skip it, if it's \n complain. */
5417 goto expecting_operand_after_comma
;
5419 expecting_operand
= 1;
5426 swap_2_operands (int xchg1
, int xchg2
)
5428 union i386_op temp_op
;
5429 i386_operand_type temp_type
;
5430 unsigned int temp_flags
;
5431 enum bfd_reloc_code_real temp_reloc
;
5433 temp_type
= i
.types
[xchg2
];
5434 i
.types
[xchg2
] = i
.types
[xchg1
];
5435 i
.types
[xchg1
] = temp_type
;
5437 temp_flags
= i
.flags
[xchg2
];
5438 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5439 i
.flags
[xchg1
] = temp_flags
;
5441 temp_op
= i
.op
[xchg2
];
5442 i
.op
[xchg2
] = i
.op
[xchg1
];
5443 i
.op
[xchg1
] = temp_op
;
5445 temp_reloc
= i
.reloc
[xchg2
];
5446 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5447 i
.reloc
[xchg1
] = temp_reloc
;
5451 if (i
.mask
->operand
== xchg1
)
5452 i
.mask
->operand
= xchg2
;
5453 else if (i
.mask
->operand
== xchg2
)
5454 i
.mask
->operand
= xchg1
;
5458 if (i
.broadcast
->operand
== xchg1
)
5459 i
.broadcast
->operand
= xchg2
;
5460 else if (i
.broadcast
->operand
== xchg2
)
5461 i
.broadcast
->operand
= xchg1
;
5465 if (i
.rounding
->operand
== xchg1
)
5466 i
.rounding
->operand
= xchg2
;
5467 else if (i
.rounding
->operand
== xchg2
)
5468 i
.rounding
->operand
= xchg1
;
5473 swap_operands (void)
5479 swap_2_operands (1, i
.operands
- 2);
5483 swap_2_operands (0, i
.operands
- 1);
5489 if (i
.mem_operands
== 2)
5491 const seg_entry
*temp_seg
;
5492 temp_seg
= i
.seg
[0];
5493 i
.seg
[0] = i
.seg
[1];
5494 i
.seg
[1] = temp_seg
;
5498 /* Try to ensure constant immediates are represented in the smallest
5503 char guess_suffix
= 0;
5507 guess_suffix
= i
.suffix
;
5508 else if (i
.reg_operands
)
5510 /* Figure out a suffix from the last register operand specified.
5511 We can't do this properly yet, i.e. excluding special register
5512 instances, but the following works for instructions with
5513 immediates. In any case, we can't set i.suffix yet. */
5514 for (op
= i
.operands
; --op
>= 0;)
5515 if (i
.types
[op
].bitfield
.class != Reg
)
5517 else if (i
.types
[op
].bitfield
.byte
)
5519 guess_suffix
= BYTE_MNEM_SUFFIX
;
5522 else if (i
.types
[op
].bitfield
.word
)
5524 guess_suffix
= WORD_MNEM_SUFFIX
;
5527 else if (i
.types
[op
].bitfield
.dword
)
5529 guess_suffix
= LONG_MNEM_SUFFIX
;
5532 else if (i
.types
[op
].bitfield
.qword
)
5534 guess_suffix
= QWORD_MNEM_SUFFIX
;
5538 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5539 guess_suffix
= WORD_MNEM_SUFFIX
;
5541 for (op
= i
.operands
; --op
>= 0;)
5542 if (operand_type_check (i
.types
[op
], imm
))
5544 switch (i
.op
[op
].imms
->X_op
)
5547 /* If a suffix is given, this operand may be shortened. */
5548 switch (guess_suffix
)
5550 case LONG_MNEM_SUFFIX
:
5551 i
.types
[op
].bitfield
.imm32
= 1;
5552 i
.types
[op
].bitfield
.imm64
= 1;
5554 case WORD_MNEM_SUFFIX
:
5555 i
.types
[op
].bitfield
.imm16
= 1;
5556 i
.types
[op
].bitfield
.imm32
= 1;
5557 i
.types
[op
].bitfield
.imm32s
= 1;
5558 i
.types
[op
].bitfield
.imm64
= 1;
5560 case BYTE_MNEM_SUFFIX
:
5561 i
.types
[op
].bitfield
.imm8
= 1;
5562 i
.types
[op
].bitfield
.imm8s
= 1;
5563 i
.types
[op
].bitfield
.imm16
= 1;
5564 i
.types
[op
].bitfield
.imm32
= 1;
5565 i
.types
[op
].bitfield
.imm32s
= 1;
5566 i
.types
[op
].bitfield
.imm64
= 1;
5570 /* If this operand is at most 16 bits, convert it
5571 to a signed 16 bit number before trying to see
5572 whether it will fit in an even smaller size.
5573 This allows a 16-bit operand such as $0xffe0 to
5574 be recognised as within Imm8S range. */
5575 if ((i
.types
[op
].bitfield
.imm16
)
5576 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5578 i
.op
[op
].imms
->X_add_number
=
5579 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5582 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5583 if ((i
.types
[op
].bitfield
.imm32
)
5584 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5587 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5588 ^ ((offsetT
) 1 << 31))
5589 - ((offsetT
) 1 << 31));
5593 = operand_type_or (i
.types
[op
],
5594 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5596 /* We must avoid matching of Imm32 templates when 64bit
5597 only immediate is available. */
5598 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5599 i
.types
[op
].bitfield
.imm32
= 0;
5606 /* Symbols and expressions. */
5608 /* Convert symbolic operand to proper sizes for matching, but don't
5609 prevent matching a set of insns that only supports sizes other
5610 than those matching the insn suffix. */
5612 i386_operand_type mask
, allowed
;
5613 const insn_template
*t
;
5615 operand_type_set (&mask
, 0);
5616 operand_type_set (&allowed
, 0);
5618 for (t
= current_templates
->start
;
5619 t
< current_templates
->end
;
5622 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5623 allowed
= operand_type_and (allowed
, anyimm
);
5625 switch (guess_suffix
)
5627 case QWORD_MNEM_SUFFIX
:
5628 mask
.bitfield
.imm64
= 1;
5629 mask
.bitfield
.imm32s
= 1;
5631 case LONG_MNEM_SUFFIX
:
5632 mask
.bitfield
.imm32
= 1;
5634 case WORD_MNEM_SUFFIX
:
5635 mask
.bitfield
.imm16
= 1;
5637 case BYTE_MNEM_SUFFIX
:
5638 mask
.bitfield
.imm8
= 1;
5643 allowed
= operand_type_and (mask
, allowed
);
5644 if (!operand_type_all_zero (&allowed
))
5645 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5652 /* Try to use the smallest displacement type too. */
5654 optimize_disp (void)
5658 for (op
= i
.operands
; --op
>= 0;)
5659 if (operand_type_check (i
.types
[op
], disp
))
5661 if (i
.op
[op
].disps
->X_op
== O_constant
)
5663 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5665 if (i
.types
[op
].bitfield
.disp16
5666 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5668 /* If this operand is at most 16 bits, convert
5669 to a signed 16 bit number and don't use 64bit
5671 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5672 i
.types
[op
].bitfield
.disp64
= 0;
5675 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5676 if (i
.types
[op
].bitfield
.disp32
5677 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5679 /* If this operand is at most 32 bits, convert
5680 to a signed 32 bit number and don't use 64bit
5682 op_disp
&= (((offsetT
) 2 << 31) - 1);
5683 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5684 i
.types
[op
].bitfield
.disp64
= 0;
5687 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5689 i
.types
[op
].bitfield
.disp8
= 0;
5690 i
.types
[op
].bitfield
.disp16
= 0;
5691 i
.types
[op
].bitfield
.disp32
= 0;
5692 i
.types
[op
].bitfield
.disp32s
= 0;
5693 i
.types
[op
].bitfield
.disp64
= 0;
5697 else if (flag_code
== CODE_64BIT
)
5699 if (fits_in_signed_long (op_disp
))
5701 i
.types
[op
].bitfield
.disp64
= 0;
5702 i
.types
[op
].bitfield
.disp32s
= 1;
5704 if (i
.prefix
[ADDR_PREFIX
]
5705 && fits_in_unsigned_long (op_disp
))
5706 i
.types
[op
].bitfield
.disp32
= 1;
5708 if ((i
.types
[op
].bitfield
.disp32
5709 || i
.types
[op
].bitfield
.disp32s
5710 || i
.types
[op
].bitfield
.disp16
)
5711 && fits_in_disp8 (op_disp
))
5712 i
.types
[op
].bitfield
.disp8
= 1;
5714 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5715 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5717 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5718 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5719 i
.types
[op
].bitfield
.disp8
= 0;
5720 i
.types
[op
].bitfield
.disp16
= 0;
5721 i
.types
[op
].bitfield
.disp32
= 0;
5722 i
.types
[op
].bitfield
.disp32s
= 0;
5723 i
.types
[op
].bitfield
.disp64
= 0;
5726 /* We only support 64bit displacement on constants. */
5727 i
.types
[op
].bitfield
.disp64
= 0;
5731 /* Return 1 if there is a match in broadcast bytes between operand
5732 GIVEN and instruction template T. */
5735 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5737 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5738 && i
.types
[given
].bitfield
.byte
)
5739 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5740 && i
.types
[given
].bitfield
.word
)
5741 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5742 && i
.types
[given
].bitfield
.dword
)
5743 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5744 && i
.types
[given
].bitfield
.qword
));
5747 /* Check if operands are valid for the instruction. */
5750 check_VecOperands (const insn_template
*t
)
5755 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5756 any one operand are implicity requiring AVX512VL support if the actual
5757 operand size is YMMword or XMMword. Since this function runs after
5758 template matching, there's no need to check for YMMword/XMMword in
5760 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5761 if (!cpu_flags_all_zero (&cpu
)
5762 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5763 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5765 for (op
= 0; op
< t
->operands
; ++op
)
5767 if (t
->operand_types
[op
].bitfield
.zmmword
5768 && (i
.types
[op
].bitfield
.ymmword
5769 || i
.types
[op
].bitfield
.xmmword
))
5771 i
.error
= unsupported
;
5777 /* Without VSIB byte, we can't have a vector register for index. */
5778 if (!t
->opcode_modifier
.sib
5780 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5781 || i
.index_reg
->reg_type
.bitfield
.ymmword
5782 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5784 i
.error
= unsupported_vector_index_register
;
5788 /* Check if default mask is allowed. */
5789 if (t
->opcode_modifier
.nodefmask
5790 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5792 i
.error
= no_default_mask
;
5796 /* For VSIB byte, we need a vector register for index, and all vector
5797 registers must be distinct. */
5798 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5801 || !((t
->opcode_modifier
.sib
== VECSIB128
5802 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5803 || (t
->opcode_modifier
.sib
== VECSIB256
5804 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5805 || (t
->opcode_modifier
.sib
== VECSIB512
5806 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5808 i
.error
= invalid_vsib_address
;
5812 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5813 if (i
.reg_operands
== 2 && !i
.mask
)
5815 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5816 gas_assert (i
.types
[0].bitfield
.xmmword
5817 || i
.types
[0].bitfield
.ymmword
);
5818 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5819 gas_assert (i
.types
[2].bitfield
.xmmword
5820 || i
.types
[2].bitfield
.ymmword
);
5821 if (operand_check
== check_none
)
5823 if (register_number (i
.op
[0].regs
)
5824 != register_number (i
.index_reg
)
5825 && register_number (i
.op
[2].regs
)
5826 != register_number (i
.index_reg
)
5827 && register_number (i
.op
[0].regs
)
5828 != register_number (i
.op
[2].regs
))
5830 if (operand_check
== check_error
)
5832 i
.error
= invalid_vector_register_set
;
5835 as_warn (_("mask, index, and destination registers should be distinct"));
5837 else if (i
.reg_operands
== 1 && i
.mask
)
5839 if (i
.types
[1].bitfield
.class == RegSIMD
5840 && (i
.types
[1].bitfield
.xmmword
5841 || i
.types
[1].bitfield
.ymmword
5842 || i
.types
[1].bitfield
.zmmword
)
5843 && (register_number (i
.op
[1].regs
)
5844 == register_number (i
.index_reg
)))
5846 if (operand_check
== check_error
)
5848 i
.error
= invalid_vector_register_set
;
5851 if (operand_check
!= check_none
)
5852 as_warn (_("index and destination registers should be distinct"));
5857 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5859 if (t
->operand_types
[0].bitfield
.tmmword
5860 && i
.reg_operands
== 3)
5862 if (register_number (i
.op
[0].regs
)
5863 == register_number (i
.op
[1].regs
)
5864 || register_number (i
.op
[0].regs
)
5865 == register_number (i
.op
[2].regs
)
5866 || register_number (i
.op
[1].regs
)
5867 == register_number (i
.op
[2].regs
))
5869 i
.error
= invalid_tmm_register_set
;
5874 /* Check if broadcast is supported by the instruction and is applied
5875 to the memory operand. */
5878 i386_operand_type type
, overlap
;
5880 /* Check if specified broadcast is supported in this instruction,
5881 and its broadcast bytes match the memory operand. */
5882 op
= i
.broadcast
->operand
;
5883 if (!t
->opcode_modifier
.broadcast
5884 || !(i
.flags
[op
] & Operand_Mem
)
5885 || (!i
.types
[op
].bitfield
.unspecified
5886 && !match_broadcast_size (t
, op
)))
5889 i
.error
= unsupported_broadcast
;
5893 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5894 * i
.broadcast
->type
);
5895 operand_type_set (&type
, 0);
5896 switch (i
.broadcast
->bytes
)
5899 type
.bitfield
.word
= 1;
5902 type
.bitfield
.dword
= 1;
5905 type
.bitfield
.qword
= 1;
5908 type
.bitfield
.xmmword
= 1;
5911 type
.bitfield
.ymmword
= 1;
5914 type
.bitfield
.zmmword
= 1;
5920 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5921 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5922 && t
->operand_types
[op
].bitfield
.byte
5923 + t
->operand_types
[op
].bitfield
.word
5924 + t
->operand_types
[op
].bitfield
.dword
5925 + t
->operand_types
[op
].bitfield
.qword
> 1)
5927 overlap
.bitfield
.xmmword
= 0;
5928 overlap
.bitfield
.ymmword
= 0;
5929 overlap
.bitfield
.zmmword
= 0;
5931 if (operand_type_all_zero (&overlap
))
5934 if (t
->opcode_modifier
.checkregsize
)
5938 type
.bitfield
.baseindex
= 1;
5939 for (j
= 0; j
< i
.operands
; ++j
)
5942 && !operand_type_register_match(i
.types
[j
],
5943 t
->operand_types
[j
],
5945 t
->operand_types
[op
]))
5950 /* If broadcast is supported in this instruction, we need to check if
5951 operand of one-element size isn't specified without broadcast. */
5952 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5954 /* Find memory operand. */
5955 for (op
= 0; op
< i
.operands
; op
++)
5956 if (i
.flags
[op
] & Operand_Mem
)
5958 gas_assert (op
< i
.operands
);
5959 /* Check size of the memory operand. */
5960 if (match_broadcast_size (t
, op
))
5962 i
.error
= broadcast_needed
;
5967 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5969 /* Check if requested masking is supported. */
5972 switch (t
->opcode_modifier
.masking
)
5976 case MERGING_MASKING
:
5977 if (i
.mask
->zeroing
)
5980 i
.error
= unsupported_masking
;
5984 case DYNAMIC_MASKING
:
5985 /* Memory destinations allow only merging masking. */
5986 if (i
.mask
->zeroing
&& i
.mem_operands
)
5988 /* Find memory operand. */
5989 for (op
= 0; op
< i
.operands
; op
++)
5990 if (i
.flags
[op
] & Operand_Mem
)
5992 gas_assert (op
< i
.operands
);
5993 if (op
== i
.operands
- 1)
5995 i
.error
= unsupported_masking
;
6005 /* Check if masking is applied to dest operand. */
6006 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6008 i
.error
= mask_not_on_destination
;
6015 if (!t
->opcode_modifier
.sae
6016 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6018 i
.error
= unsupported_rc_sae
;
6021 /* If the instruction has several immediate operands and one of
6022 them is rounding, the rounding operand should be the last
6023 immediate operand. */
6024 if (i
.imm_operands
> 1
6025 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6027 i
.error
= rc_sae_operand_not_last_imm
;
6032 /* Check the special Imm4 cases; must be the first operand. */
6033 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6035 if (i
.op
[0].imms
->X_op
!= O_constant
6036 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6042 /* Turn off Imm<N> so that update_imm won't complain. */
6043 operand_type_set (&i
.types
[0], 0);
6046 /* Check vector Disp8 operand. */
6047 if (t
->opcode_modifier
.disp8memshift
6048 && i
.disp_encoding
!= disp_encoding_32bit
)
6051 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6052 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6053 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6056 const i386_operand_type
*type
= NULL
;
6059 for (op
= 0; op
< i
.operands
; op
++)
6060 if (i
.flags
[op
] & Operand_Mem
)
6062 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6063 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6064 else if (t
->operand_types
[op
].bitfield
.xmmword
6065 + t
->operand_types
[op
].bitfield
.ymmword
6066 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6067 type
= &t
->operand_types
[op
];
6068 else if (!i
.types
[op
].bitfield
.unspecified
)
6069 type
= &i
.types
[op
];
6071 else if (i
.types
[op
].bitfield
.class == RegSIMD
6072 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6074 if (i
.types
[op
].bitfield
.zmmword
)
6076 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6078 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6084 if (type
->bitfield
.zmmword
)
6086 else if (type
->bitfield
.ymmword
)
6088 else if (type
->bitfield
.xmmword
)
6092 /* For the check in fits_in_disp8(). */
6093 if (i
.memshift
== 0)
6097 for (op
= 0; op
< i
.operands
; op
++)
6098 if (operand_type_check (i
.types
[op
], disp
)
6099 && i
.op
[op
].disps
->X_op
== O_constant
)
6101 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6103 i
.types
[op
].bitfield
.disp8
= 1;
6106 i
.types
[op
].bitfield
.disp8
= 0;
6115 /* Check if encoding requirements are met by the instruction. */
6118 VEX_check_encoding (const insn_template
*t
)
6120 if (i
.vec_encoding
== vex_encoding_error
)
6122 i
.error
= unsupported
;
6126 if (i
.vec_encoding
== vex_encoding_evex
)
6128 /* This instruction must be encoded with EVEX prefix. */
6129 if (!is_evex_encoding (t
))
6131 i
.error
= unsupported
;
6137 if (!t
->opcode_modifier
.vex
)
6139 /* This instruction template doesn't have VEX prefix. */
6140 if (i
.vec_encoding
!= vex_encoding_default
)
6142 i
.error
= unsupported
;
6151 static const insn_template
*
6152 match_template (char mnem_suffix
)
6154 /* Points to template once we've found it. */
6155 const insn_template
*t
;
6156 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6157 i386_operand_type overlap4
;
6158 unsigned int found_reverse_match
;
6159 i386_opcode_modifier suffix_check
;
6160 i386_operand_type operand_types
[MAX_OPERANDS
];
6161 int addr_prefix_disp
;
6162 unsigned int j
, size_match
, check_register
;
6163 enum i386_error specific_error
= 0;
6165 #if MAX_OPERANDS != 5
6166 # error "MAX_OPERANDS must be 5."
6169 found_reverse_match
= 0;
6170 addr_prefix_disp
= -1;
6172 /* Prepare for mnemonic suffix check. */
6173 memset (&suffix_check
, 0, sizeof (suffix_check
));
6174 switch (mnem_suffix
)
6176 case BYTE_MNEM_SUFFIX
:
6177 suffix_check
.no_bsuf
= 1;
6179 case WORD_MNEM_SUFFIX
:
6180 suffix_check
.no_wsuf
= 1;
6182 case SHORT_MNEM_SUFFIX
:
6183 suffix_check
.no_ssuf
= 1;
6185 case LONG_MNEM_SUFFIX
:
6186 suffix_check
.no_lsuf
= 1;
6188 case QWORD_MNEM_SUFFIX
:
6189 suffix_check
.no_qsuf
= 1;
6192 /* NB: In Intel syntax, normally we can check for memory operand
6193 size when there is no mnemonic suffix. But jmp and call have
6194 2 different encodings with Dword memory operand size, one with
6195 No_ldSuf and the other without. i.suffix is set to
6196 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6197 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6198 suffix_check
.no_ldsuf
= 1;
6201 /* Must have right number of operands. */
6202 i
.error
= number_of_operands_mismatch
;
6204 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6206 addr_prefix_disp
= -1;
6207 found_reverse_match
= 0;
6209 if (i
.operands
!= t
->operands
)
6212 /* Check processor support. */
6213 i
.error
= unsupported
;
6214 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6217 /* Check Pseudo Prefix. */
6218 i
.error
= unsupported
;
6219 if (t
->opcode_modifier
.pseudovexprefix
6220 && !(i
.vec_encoding
== vex_encoding_vex
6221 || i
.vec_encoding
== vex_encoding_vex3
))
6224 /* Check AT&T mnemonic. */
6225 i
.error
= unsupported_with_intel_mnemonic
;
6226 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6229 /* Check AT&T/Intel syntax. */
6230 i
.error
= unsupported_syntax
;
6231 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6232 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6235 /* Check Intel64/AMD64 ISA. */
6239 /* Default: Don't accept Intel64. */
6240 if (t
->opcode_modifier
.isa64
== INTEL64
)
6244 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6245 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6249 /* -mintel64: Don't accept AMD64. */
6250 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6255 /* Check the suffix. */
6256 i
.error
= invalid_instruction_suffix
;
6257 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6258 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6259 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6260 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6261 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6262 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6265 size_match
= operand_size_match (t
);
6269 /* This is intentionally not
6271 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6273 as the case of a missing * on the operand is accepted (perhaps with
6274 a warning, issued further down). */
6275 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6277 i
.error
= operand_type_mismatch
;
6281 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6282 operand_types
[j
] = t
->operand_types
[j
];
6284 /* In general, don't allow
6285 - 64-bit operands outside of 64-bit mode,
6286 - 32-bit operands on pre-386. */
6287 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6288 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6289 && flag_code
!= CODE_64BIT
6290 && !(t
->base_opcode
== 0xfc7
6291 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
6292 && t
->extension_opcode
== 1) /* cmpxchg8b */)
6293 || (i
.suffix
== LONG_MNEM_SUFFIX
6294 && !cpu_arch_flags
.bitfield
.cpui386
))
6296 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6297 && !intel_float_operand (t
->name
))
6298 : intel_float_operand (t
->name
) != 2)
6299 && (t
->operands
== i
.imm_operands
6300 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6301 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6302 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6303 || (operand_types
[j
].bitfield
.class != RegMMX
6304 && operand_types
[j
].bitfield
.class != RegSIMD
6305 && operand_types
[j
].bitfield
.class != RegMask
))
6306 && !t
->opcode_modifier
.sib
)
6309 /* Do not verify operands when there are none. */
6312 if (VEX_check_encoding (t
))
6314 specific_error
= i
.error
;
6318 /* We've found a match; break out of loop. */
6322 if (!t
->opcode_modifier
.jump
6323 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6325 /* There should be only one Disp operand. */
6326 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6327 if (operand_type_check (operand_types
[j
], disp
))
6329 if (j
< MAX_OPERANDS
)
6331 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6333 addr_prefix_disp
= j
;
6335 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6336 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6340 override
= !override
;
6343 if (operand_types
[j
].bitfield
.disp32
6344 && operand_types
[j
].bitfield
.disp16
)
6346 operand_types
[j
].bitfield
.disp16
= override
;
6347 operand_types
[j
].bitfield
.disp32
= !override
;
6349 operand_types
[j
].bitfield
.disp32s
= 0;
6350 operand_types
[j
].bitfield
.disp64
= 0;
6354 if (operand_types
[j
].bitfield
.disp32s
6355 || operand_types
[j
].bitfield
.disp64
)
6357 operand_types
[j
].bitfield
.disp64
&= !override
;
6358 operand_types
[j
].bitfield
.disp32s
&= !override
;
6359 operand_types
[j
].bitfield
.disp32
= override
;
6361 operand_types
[j
].bitfield
.disp16
= 0;
6367 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6368 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
6369 && t
->base_opcode
== 0xa0
6370 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
)
6373 /* We check register size if needed. */
6374 if (t
->opcode_modifier
.checkregsize
)
6376 check_register
= (1 << t
->operands
) - 1;
6378 check_register
&= ~(1 << i
.broadcast
->operand
);
6383 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6384 switch (t
->operands
)
6387 if (!operand_type_match (overlap0
, i
.types
[0]))
6391 /* xchg %eax, %eax is a special case. It is an alias for nop
6392 only in 32bit mode and we can use opcode 0x90. In 64bit
6393 mode, we can't use 0x90 for xchg %eax, %eax since it should
6394 zero-extend %eax to %rax. */
6395 if (flag_code
== CODE_64BIT
6396 && t
->base_opcode
== 0x90
6397 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6398 && i
.types
[0].bitfield
.instance
== Accum
6399 && i
.types
[0].bitfield
.dword
6400 && i
.types
[1].bitfield
.instance
== Accum
6401 && i
.types
[1].bitfield
.dword
)
6403 /* xrelease mov %eax, <disp> is another special case. It must not
6404 match the accumulator-only encoding of mov. */
6405 if (flag_code
!= CODE_64BIT
6407 && t
->base_opcode
== 0xa0
6408 && t
->opcode_modifier
.opcodespace
== SPACE_BASE
6409 && i
.types
[0].bitfield
.instance
== Accum
6410 && (i
.flags
[1] & Operand_Mem
))
6415 if (!(size_match
& MATCH_STRAIGHT
))
6417 /* Reverse direction of operands if swapping is possible in the first
6418 place (operands need to be symmetric) and
6419 - the load form is requested, and the template is a store form,
6420 - the store form is requested, and the template is a load form,
6421 - the non-default (swapped) form is requested. */
6422 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6423 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6424 && !operand_type_all_zero (&overlap1
))
6425 switch (i
.dir_encoding
)
6427 case dir_encoding_load
:
6428 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6429 || t
->opcode_modifier
.regmem
)
6433 case dir_encoding_store
:
6434 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6435 && !t
->opcode_modifier
.regmem
)
6439 case dir_encoding_swap
:
6442 case dir_encoding_default
:
6445 /* If we want store form, we skip the current load. */
6446 if ((i
.dir_encoding
== dir_encoding_store
6447 || i
.dir_encoding
== dir_encoding_swap
)
6448 && i
.mem_operands
== 0
6449 && t
->opcode_modifier
.load
)
6454 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6455 if (!operand_type_match (overlap0
, i
.types
[0])
6456 || !operand_type_match (overlap1
, i
.types
[1])
6457 || ((check_register
& 3) == 3
6458 && !operand_type_register_match (i
.types
[0],
6463 /* Check if other direction is valid ... */
6464 if (!t
->opcode_modifier
.d
)
6468 if (!(size_match
& MATCH_REVERSE
))
6470 /* Try reversing direction of operands. */
6471 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6472 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6473 if (!operand_type_match (overlap0
, i
.types
[0])
6474 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6476 && !operand_type_register_match (i
.types
[0],
6477 operand_types
[i
.operands
- 1],
6478 i
.types
[i
.operands
- 1],
6481 /* Does not match either direction. */
6484 /* found_reverse_match holds which of D or FloatR
6486 if (!t
->opcode_modifier
.d
)
6487 found_reverse_match
= 0;
6488 else if (operand_types
[0].bitfield
.tbyte
)
6489 found_reverse_match
= Opcode_FloatD
;
6490 else if (operand_types
[0].bitfield
.xmmword
6491 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6492 || operand_types
[0].bitfield
.class == RegMMX
6493 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6494 || is_any_vex_encoding(t
))
6495 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6496 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6498 found_reverse_match
= Opcode_D
;
6499 if (t
->opcode_modifier
.floatr
)
6500 found_reverse_match
|= Opcode_FloatR
;
6504 /* Found a forward 2 operand match here. */
6505 switch (t
->operands
)
6508 overlap4
= operand_type_and (i
.types
[4],
6512 overlap3
= operand_type_and (i
.types
[3],
6516 overlap2
= operand_type_and (i
.types
[2],
6521 switch (t
->operands
)
6524 if (!operand_type_match (overlap4
, i
.types
[4])
6525 || !operand_type_register_match (i
.types
[3],
6532 if (!operand_type_match (overlap3
, i
.types
[3])
6533 || ((check_register
& 0xa) == 0xa
6534 && !operand_type_register_match (i
.types
[1],
6538 || ((check_register
& 0xc) == 0xc
6539 && !operand_type_register_match (i
.types
[2],
6546 /* Here we make use of the fact that there are no
6547 reverse match 3 operand instructions. */
6548 if (!operand_type_match (overlap2
, i
.types
[2])
6549 || ((check_register
& 5) == 5
6550 && !operand_type_register_match (i
.types
[0],
6554 || ((check_register
& 6) == 6
6555 && !operand_type_register_match (i
.types
[1],
6563 /* Found either forward/reverse 2, 3 or 4 operand match here:
6564 slip through to break. */
6567 /* Check if vector operands are valid. */
6568 if (check_VecOperands (t
))
6570 specific_error
= i
.error
;
6574 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6575 if (VEX_check_encoding (t
))
6577 specific_error
= i
.error
;
6581 /* We've found a match; break out of loop. */
6585 if (t
== current_templates
->end
)
6587 /* We found no match. */
6588 const char *err_msg
;
6589 switch (specific_error
? specific_error
: i
.error
)
6593 case operand_size_mismatch
:
6594 err_msg
= _("operand size mismatch");
6596 case operand_type_mismatch
:
6597 err_msg
= _("operand type mismatch");
6599 case register_type_mismatch
:
6600 err_msg
= _("register type mismatch");
6602 case number_of_operands_mismatch
:
6603 err_msg
= _("number of operands mismatch");
6605 case invalid_instruction_suffix
:
6606 err_msg
= _("invalid instruction suffix");
6609 err_msg
= _("constant doesn't fit in 4 bits");
6611 case unsupported_with_intel_mnemonic
:
6612 err_msg
= _("unsupported with Intel mnemonic");
6614 case unsupported_syntax
:
6615 err_msg
= _("unsupported syntax");
6618 as_bad (_("unsupported instruction `%s'"),
6619 current_templates
->start
->name
);
6621 case invalid_sib_address
:
6622 err_msg
= _("invalid SIB address");
6624 case invalid_vsib_address
:
6625 err_msg
= _("invalid VSIB address");
6627 case invalid_vector_register_set
:
6628 err_msg
= _("mask, index, and destination registers must be distinct");
6630 case invalid_tmm_register_set
:
6631 err_msg
= _("all tmm registers must be distinct");
6633 case unsupported_vector_index_register
:
6634 err_msg
= _("unsupported vector index register");
6636 case unsupported_broadcast
:
6637 err_msg
= _("unsupported broadcast");
6639 case broadcast_needed
:
6640 err_msg
= _("broadcast is needed for operand of such type");
6642 case unsupported_masking
:
6643 err_msg
= _("unsupported masking");
6645 case mask_not_on_destination
:
6646 err_msg
= _("mask not on destination operand");
6648 case no_default_mask
:
6649 err_msg
= _("default mask isn't allowed");
6651 case unsupported_rc_sae
:
6652 err_msg
= _("unsupported static rounding/sae");
6654 case rc_sae_operand_not_last_imm
:
6656 err_msg
= _("RC/SAE operand must precede immediate operands");
6658 err_msg
= _("RC/SAE operand must follow immediate operands");
6660 case invalid_register_operand
:
6661 err_msg
= _("invalid register operand");
6664 as_bad (_("%s for `%s'"), err_msg
,
6665 current_templates
->start
->name
);
6669 if (!quiet_warnings
)
6672 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6673 as_warn (_("indirect %s without `*'"), t
->name
);
6675 if (t
->opcode_modifier
.isprefix
6676 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6678 /* Warn them that a data or address size prefix doesn't
6679 affect assembly of the next line of code. */
6680 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6684 /* Copy the template we found. */
6685 install_template (t
);
6687 if (addr_prefix_disp
!= -1)
6688 i
.tm
.operand_types
[addr_prefix_disp
]
6689 = operand_types
[addr_prefix_disp
];
6691 if (found_reverse_match
)
6693 /* If we found a reverse match we must alter the opcode direction
6694 bit and clear/flip the regmem modifier one. found_reverse_match
6695 holds bits to change (different for int & float insns). */
6697 i
.tm
.base_opcode
^= found_reverse_match
;
6699 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6700 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6702 /* Certain SIMD insns have their load forms specified in the opcode
6703 table, and hence we need to _set_ RegMem instead of clearing it.
6704 We need to avoid setting the bit though on insns like KMOVW. */
6705 i
.tm
.opcode_modifier
.regmem
6706 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6707 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6708 && !i
.tm
.opcode_modifier
.regmem
;
6717 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6718 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6720 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6722 as_bad (_("`%s' operand %u must use `%ses' segment"),
6724 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6729 /* There's only ever one segment override allowed per instruction.
6730 This instruction possibly has a legal segment override on the
6731 second operand, so copy the segment to where non-string
6732 instructions store it, allowing common code. */
6733 i
.seg
[op
] = i
.seg
[1];
6739 process_suffix (void)
6741 bfd_boolean is_crc32
= FALSE
;
6743 /* If matched instruction specifies an explicit instruction mnemonic
6745 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6746 i
.suffix
= WORD_MNEM_SUFFIX
;
6747 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6748 i
.suffix
= LONG_MNEM_SUFFIX
;
6749 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6750 i
.suffix
= QWORD_MNEM_SUFFIX
;
6751 else if (i
.reg_operands
6752 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6753 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6755 unsigned int numop
= i
.operands
;
6757 is_crc32
= (i
.tm
.base_opcode
== 0xf38f0
6758 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
);
6760 /* movsx/movzx want only their source operand considered here, for the
6761 ambiguity checking below. The suffix will be replaced afterwards
6762 to represent the destination (register). */
6763 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6764 || (i
.tm
.base_opcode
== 0x63
6765 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
6766 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6769 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6770 if (is_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
6773 /* If there's no instruction mnemonic suffix we try to invent one
6774 based on GPR operands. */
6777 /* We take i.suffix from the last register operand specified,
6778 Destination register type is more significant than source
6779 register type. crc32 in SSE4.2 prefers source register
6781 unsigned int op
= is_crc32
? 1 : i
.operands
;
6784 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6785 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6787 if (i
.types
[op
].bitfield
.class != Reg
)
6789 if (i
.types
[op
].bitfield
.byte
)
6790 i
.suffix
= BYTE_MNEM_SUFFIX
;
6791 else if (i
.types
[op
].bitfield
.word
)
6792 i
.suffix
= WORD_MNEM_SUFFIX
;
6793 else if (i
.types
[op
].bitfield
.dword
)
6794 i
.suffix
= LONG_MNEM_SUFFIX
;
6795 else if (i
.types
[op
].bitfield
.qword
)
6796 i
.suffix
= QWORD_MNEM_SUFFIX
;
6802 /* As an exception, movsx/movzx silently default to a byte source
6804 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6805 && !i
.suffix
&& !intel_syntax
)
6806 i
.suffix
= BYTE_MNEM_SUFFIX
;
6808 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6811 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6812 && i
.tm
.opcode_modifier
.no_bsuf
)
6814 else if (!check_byte_reg ())
6817 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6820 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6821 && i
.tm
.opcode_modifier
.no_lsuf
6822 && !i
.tm
.opcode_modifier
.todword
6823 && !i
.tm
.opcode_modifier
.toqword
)
6825 else if (!check_long_reg ())
6828 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6831 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6832 && i
.tm
.opcode_modifier
.no_qsuf
6833 && !i
.tm
.opcode_modifier
.todword
6834 && !i
.tm
.opcode_modifier
.toqword
)
6836 else if (!check_qword_reg ())
6839 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6842 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6843 && i
.tm
.opcode_modifier
.no_wsuf
)
6845 else if (!check_word_reg ())
6848 else if (intel_syntax
6849 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6850 /* Do nothing if the instruction is going to ignore the prefix. */
6855 /* Undo the movsx/movzx change done above. */
6858 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6861 i
.suffix
= stackop_size
;
6862 if (stackop_size
== LONG_MNEM_SUFFIX
)
6864 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6865 .code16gcc directive to support 16-bit mode with
6866 32-bit address. For IRET without a suffix, generate
6867 16-bit IRET (opcode 0xcf) to return from an interrupt
6869 if (i
.tm
.base_opcode
== 0xcf)
6871 i
.suffix
= WORD_MNEM_SUFFIX
;
6872 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6874 /* Warn about changed behavior for segment register push/pop. */
6875 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6876 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6881 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6882 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6883 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6884 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6885 && i
.tm
.extension_opcode
<= 3)))
6890 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6892 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6893 || i
.tm
.opcode_modifier
.no_lsuf
)
6894 i
.suffix
= QWORD_MNEM_SUFFIX
;
6899 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6900 i
.suffix
= LONG_MNEM_SUFFIX
;
6903 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6904 i
.suffix
= WORD_MNEM_SUFFIX
;
6910 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6911 /* Also cover lret/retf/iret in 64-bit mode. */
6912 || (flag_code
== CODE_64BIT
6913 && !i
.tm
.opcode_modifier
.no_lsuf
6914 && !i
.tm
.opcode_modifier
.no_qsuf
))
6915 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6916 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6917 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6918 /* Accept FLDENV et al without suffix. */
6919 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6921 unsigned int suffixes
, evex
= 0;
6923 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6924 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6926 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6928 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6930 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6932 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6935 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6936 also suitable for AT&T syntax mode, it was requested that this be
6937 restricted to just Intel syntax. */
6938 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6942 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6944 if (is_evex_encoding (&i
.tm
)
6945 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6947 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6948 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6949 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6950 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6951 if (!i
.tm
.opcode_modifier
.evex
6952 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6953 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6956 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6957 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6958 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6961 /* Any properly sized operand disambiguates the insn. */
6962 if (i
.types
[op
].bitfield
.xmmword
6963 || i
.types
[op
].bitfield
.ymmword
6964 || i
.types
[op
].bitfield
.zmmword
)
6966 suffixes
&= ~(7 << 6);
6971 if ((i
.flags
[op
] & Operand_Mem
)
6972 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6974 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6976 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6978 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6980 if (is_evex_encoding (&i
.tm
))
6986 /* Are multiple suffixes / operand sizes allowed? */
6987 if (suffixes
& (suffixes
- 1))
6990 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6991 || operand_check
== check_error
))
6993 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6996 if (operand_check
== check_error
)
6998 as_bad (_("no instruction mnemonic suffix given and "
6999 "no register operands; can't size `%s'"), i
.tm
.name
);
7002 if (operand_check
== check_warning
)
7003 as_warn (_("%s; using default for `%s'"),
7005 ? _("ambiguous operand size")
7006 : _("no instruction mnemonic suffix given and "
7007 "no register operands"),
7010 if (i
.tm
.opcode_modifier
.floatmf
)
7011 i
.suffix
= SHORT_MNEM_SUFFIX
;
7012 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7013 || (i
.tm
.base_opcode
== 0x63
7014 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7015 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7016 /* handled below */;
7018 i
.tm
.opcode_modifier
.evex
= evex
;
7019 else if (flag_code
== CODE_16BIT
)
7020 i
.suffix
= WORD_MNEM_SUFFIX
;
7021 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7022 i
.suffix
= LONG_MNEM_SUFFIX
;
7024 i
.suffix
= QWORD_MNEM_SUFFIX
;
7028 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7029 || (i
.tm
.base_opcode
== 0x63
7030 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7031 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7033 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7034 In AT&T syntax, if there is no suffix (warned about above), the default
7035 will be byte extension. */
7036 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7037 i
.tm
.base_opcode
|= 1;
7039 /* For further processing, the suffix should represent the destination
7040 (register). This is already the case when one was used with
7041 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7042 no suffix to begin with. */
7043 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7045 if (i
.types
[1].bitfield
.word
)
7046 i
.suffix
= WORD_MNEM_SUFFIX
;
7047 else if (i
.types
[1].bitfield
.qword
)
7048 i
.suffix
= QWORD_MNEM_SUFFIX
;
7050 i
.suffix
= LONG_MNEM_SUFFIX
;
7052 i
.tm
.opcode_modifier
.w
= 0;
7056 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7057 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7058 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7060 /* Change the opcode based on the operand size given by i.suffix. */
7063 /* Size floating point instruction. */
7064 case LONG_MNEM_SUFFIX
:
7065 if (i
.tm
.opcode_modifier
.floatmf
)
7067 i
.tm
.base_opcode
^= 4;
7071 case WORD_MNEM_SUFFIX
:
7072 case QWORD_MNEM_SUFFIX
:
7073 /* It's not a byte, select word/dword operation. */
7074 if (i
.tm
.opcode_modifier
.w
)
7077 i
.tm
.base_opcode
|= 8;
7079 i
.tm
.base_opcode
|= 1;
7082 case SHORT_MNEM_SUFFIX
:
7083 /* Now select between word & dword operations via the operand
7084 size prefix, except for instructions that will ignore this
7086 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7087 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7088 && !i
.tm
.opcode_modifier
.floatmf
7089 && !is_any_vex_encoding (&i
.tm
)
7090 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7091 || (flag_code
== CODE_64BIT
7092 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7094 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7096 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7097 prefix
= ADDR_PREFIX_OPCODE
;
7099 if (!add_prefix (prefix
))
7103 /* Set mode64 for an operand. */
7104 if (i
.suffix
== QWORD_MNEM_SUFFIX
7105 && flag_code
== CODE_64BIT
7106 && !i
.tm
.opcode_modifier
.norex64
7107 && !i
.tm
.opcode_modifier
.vexw
7108 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7110 && ! (i
.operands
== 2
7111 && i
.tm
.base_opcode
== 0x90
7112 && i
.tm
.extension_opcode
== None
7113 && i
.types
[0].bitfield
.instance
== Accum
7114 && i
.types
[0].bitfield
.qword
7115 && i
.types
[1].bitfield
.instance
== Accum
7116 && i
.types
[1].bitfield
.qword
))
7122 /* Select word/dword/qword operation with explicit data sizing prefix
7123 when there are no suitable register operands. */
7124 if (i
.tm
.opcode_modifier
.w
7125 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7127 || (i
.reg_operands
== 1
7129 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7131 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7132 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7135 i
.tm
.base_opcode
|= 1;
7139 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7141 gas_assert (!i
.suffix
);
7142 gas_assert (i
.reg_operands
);
7144 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7147 /* The address size override prefix changes the size of the
7149 if (flag_code
== CODE_64BIT
7150 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7152 as_bad (_("16-bit addressing unavailable for `%s'"),
7157 if ((flag_code
== CODE_32BIT
7158 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7159 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7160 && !add_prefix (ADDR_PREFIX_OPCODE
))
7165 /* Check invalid register operand when the address size override
7166 prefix changes the size of register operands. */
7168 enum { need_word
, need_dword
, need_qword
} need
;
7170 /* Check the register operand for the address size prefix if
7171 the memory operand has no real registers, like symbol, DISP
7173 if (i
.mem_operands
== 1
7174 && i
.reg_operands
== 1
7176 && i
.types
[1].bitfield
.class == Reg
7177 && (flag_code
== CODE_32BIT
7178 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7179 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7180 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7182 && i
.base_reg
->reg_num
== RegIP
7183 && i
.base_reg
->reg_type
.bitfield
.qword
))
7184 && !add_prefix (ADDR_PREFIX_OPCODE
))
7187 if (flag_code
== CODE_32BIT
)
7188 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7189 else if (i
.prefix
[ADDR_PREFIX
])
7192 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7194 for (op
= 0; op
< i
.operands
; op
++)
7196 if (i
.types
[op
].bitfield
.class != Reg
)
7202 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7206 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7210 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7215 as_bad (_("invalid register operand size for `%s'"),
7226 check_byte_reg (void)
7230 for (op
= i
.operands
; --op
>= 0;)
7232 /* Skip non-register operands. */
7233 if (i
.types
[op
].bitfield
.class != Reg
)
7236 /* If this is an eight bit register, it's OK. If it's the 16 or
7237 32 bit version of an eight bit register, we will just use the
7238 low portion, and that's OK too. */
7239 if (i
.types
[op
].bitfield
.byte
)
7242 /* I/O port address operands are OK too. */
7243 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7244 && i
.tm
.operand_types
[op
].bitfield
.word
)
7247 /* crc32 only wants its source operand checked here. */
7248 if (i
.tm
.base_opcode
== 0xf38f0
7249 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
7253 /* Any other register is bad. */
7254 as_bad (_("`%s%s' not allowed with `%s%c'"),
7255 register_prefix
, i
.op
[op
].regs
->reg_name
,
7256 i
.tm
.name
, i
.suffix
);
7263 check_long_reg (void)
7267 for (op
= i
.operands
; --op
>= 0;)
7268 /* Skip non-register operands. */
7269 if (i
.types
[op
].bitfield
.class != Reg
)
7271 /* Reject eight bit registers, except where the template requires
7272 them. (eg. movzb) */
7273 else if (i
.types
[op
].bitfield
.byte
7274 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7275 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7276 && (i
.tm
.operand_types
[op
].bitfield
.word
7277 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7279 as_bad (_("`%s%s' not allowed with `%s%c'"),
7281 i
.op
[op
].regs
->reg_name
,
7286 /* Error if the e prefix on a general reg is missing. */
7287 else if (i
.types
[op
].bitfield
.word
7288 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7289 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7290 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7292 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7293 register_prefix
, i
.op
[op
].regs
->reg_name
,
7297 /* Warn if the r prefix on a general reg is present. */
7298 else if (i
.types
[op
].bitfield
.qword
7299 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7300 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7301 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7304 && i
.tm
.opcode_modifier
.toqword
7305 && i
.types
[0].bitfield
.class != RegSIMD
)
7307 /* Convert to QWORD. We want REX byte. */
7308 i
.suffix
= QWORD_MNEM_SUFFIX
;
7312 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7313 register_prefix
, i
.op
[op
].regs
->reg_name
,
7322 check_qword_reg (void)
7326 for (op
= i
.operands
; --op
>= 0; )
7327 /* Skip non-register operands. */
7328 if (i
.types
[op
].bitfield
.class != Reg
)
7330 /* Reject eight bit registers, except where the template requires
7331 them. (eg. movzb) */
7332 else if (i
.types
[op
].bitfield
.byte
7333 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7334 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7335 && (i
.tm
.operand_types
[op
].bitfield
.word
7336 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7338 as_bad (_("`%s%s' not allowed with `%s%c'"),
7340 i
.op
[op
].regs
->reg_name
,
7345 /* Warn if the r prefix on a general reg is missing. */
7346 else if ((i
.types
[op
].bitfield
.word
7347 || i
.types
[op
].bitfield
.dword
)
7348 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7349 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7350 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7352 /* Prohibit these changes in the 64bit mode, since the
7353 lowering is more complicated. */
7355 && i
.tm
.opcode_modifier
.todword
7356 && i
.types
[0].bitfield
.class != RegSIMD
)
7358 /* Convert to DWORD. We don't want REX byte. */
7359 i
.suffix
= LONG_MNEM_SUFFIX
;
7363 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7364 register_prefix
, i
.op
[op
].regs
->reg_name
,
7373 check_word_reg (void)
7376 for (op
= i
.operands
; --op
>= 0;)
7377 /* Skip non-register operands. */
7378 if (i
.types
[op
].bitfield
.class != Reg
)
7380 /* Reject eight bit registers, except where the template requires
7381 them. (eg. movzb) */
7382 else if (i
.types
[op
].bitfield
.byte
7383 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7384 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7385 && (i
.tm
.operand_types
[op
].bitfield
.word
7386 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7388 as_bad (_("`%s%s' not allowed with `%s%c'"),
7390 i
.op
[op
].regs
->reg_name
,
7395 /* Error if the e or r prefix on a general reg is present. */
7396 else if ((i
.types
[op
].bitfield
.dword
7397 || i
.types
[op
].bitfield
.qword
)
7398 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7399 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7400 && i
.tm
.operand_types
[op
].bitfield
.word
)
7402 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7403 register_prefix
, i
.op
[op
].regs
->reg_name
,
7411 update_imm (unsigned int j
)
7413 i386_operand_type overlap
= i
.types
[j
];
7414 if ((overlap
.bitfield
.imm8
7415 || overlap
.bitfield
.imm8s
7416 || overlap
.bitfield
.imm16
7417 || overlap
.bitfield
.imm32
7418 || overlap
.bitfield
.imm32s
7419 || overlap
.bitfield
.imm64
)
7420 && !operand_type_equal (&overlap
, &imm8
)
7421 && !operand_type_equal (&overlap
, &imm8s
)
7422 && !operand_type_equal (&overlap
, &imm16
)
7423 && !operand_type_equal (&overlap
, &imm32
)
7424 && !operand_type_equal (&overlap
, &imm32s
)
7425 && !operand_type_equal (&overlap
, &imm64
))
7429 i386_operand_type temp
;
7431 operand_type_set (&temp
, 0);
7432 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7434 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7435 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7437 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7438 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7439 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7441 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7442 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7445 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7448 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7449 || operand_type_equal (&overlap
, &imm16_32
)
7450 || operand_type_equal (&overlap
, &imm16_32s
))
7452 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7457 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7458 overlap
= operand_type_and (overlap
, imm32s
);
7459 else if (i
.prefix
[DATA_PREFIX
])
7460 overlap
= operand_type_and (overlap
,
7461 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7462 if (!operand_type_equal (&overlap
, &imm8
)
7463 && !operand_type_equal (&overlap
, &imm8s
)
7464 && !operand_type_equal (&overlap
, &imm16
)
7465 && !operand_type_equal (&overlap
, &imm32
)
7466 && !operand_type_equal (&overlap
, &imm32s
)
7467 && !operand_type_equal (&overlap
, &imm64
))
7469 as_bad (_("no instruction mnemonic suffix given; "
7470 "can't determine immediate size"));
7474 i
.types
[j
] = overlap
;
7484 /* Update the first 2 immediate operands. */
7485 n
= i
.operands
> 2 ? 2 : i
.operands
;
7488 for (j
= 0; j
< n
; j
++)
7489 if (update_imm (j
) == 0)
7492 /* The 3rd operand can't be immediate operand. */
7493 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7500 process_operands (void)
7502 /* Default segment register this instruction will use for memory
7503 accesses. 0 means unknown. This is only for optimizing out
7504 unnecessary segment overrides. */
7505 const seg_entry
*default_seg
= 0;
7507 if (i
.tm
.opcode_modifier
.sse2avx
)
7509 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7511 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7512 i
.prefix
[REX_PREFIX
] = 0;
7515 /* ImmExt should be processed after SSE2AVX. */
7516 else if (i
.tm
.opcode_modifier
.immext
)
7519 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7521 unsigned int dupl
= i
.operands
;
7522 unsigned int dest
= dupl
- 1;
7525 /* The destination must be an xmm register. */
7526 gas_assert (i
.reg_operands
7527 && MAX_OPERANDS
> dupl
7528 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7530 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7531 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7533 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7535 /* Keep xmm0 for instructions with VEX prefix and 3
7537 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7538 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7543 /* We remove the first xmm0 and keep the number of
7544 operands unchanged, which in fact duplicates the
7546 for (j
= 1; j
< i
.operands
; j
++)
7548 i
.op
[j
- 1] = i
.op
[j
];
7549 i
.types
[j
- 1] = i
.types
[j
];
7550 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7551 i
.flags
[j
- 1] = i
.flags
[j
];
7555 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7557 gas_assert ((MAX_OPERANDS
- 1) > dupl
7558 && (i
.tm
.opcode_modifier
.vexsources
7561 /* Add the implicit xmm0 for instructions with VEX prefix
7563 for (j
= i
.operands
; j
> 0; j
--)
7565 i
.op
[j
] = i
.op
[j
- 1];
7566 i
.types
[j
] = i
.types
[j
- 1];
7567 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7568 i
.flags
[j
] = i
.flags
[j
- 1];
7571 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
7572 i
.types
[0] = regxmm
;
7573 i
.tm
.operand_types
[0] = regxmm
;
7576 i
.reg_operands
+= 2;
7581 i
.op
[dupl
] = i
.op
[dest
];
7582 i
.types
[dupl
] = i
.types
[dest
];
7583 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7584 i
.flags
[dupl
] = i
.flags
[dest
];
7593 i
.op
[dupl
] = i
.op
[dest
];
7594 i
.types
[dupl
] = i
.types
[dest
];
7595 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7596 i
.flags
[dupl
] = i
.flags
[dest
];
7599 if (i
.tm
.opcode_modifier
.immext
)
7602 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7603 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7607 for (j
= 1; j
< i
.operands
; j
++)
7609 i
.op
[j
- 1] = i
.op
[j
];
7610 i
.types
[j
- 1] = i
.types
[j
];
7612 /* We need to adjust fields in i.tm since they are used by
7613 build_modrm_byte. */
7614 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7616 i
.flags
[j
- 1] = i
.flags
[j
];
7623 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7625 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7627 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7628 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7629 regnum
= register_number (i
.op
[1].regs
);
7630 first_reg_in_group
= regnum
& ~3;
7631 last_reg_in_group
= first_reg_in_group
+ 3;
7632 if (regnum
!= first_reg_in_group
)
7633 as_warn (_("source register `%s%s' implicitly denotes"
7634 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7635 register_prefix
, i
.op
[1].regs
->reg_name
,
7636 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7637 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7640 else if (i
.tm
.opcode_modifier
.regkludge
)
7642 /* The imul $imm, %reg instruction is converted into
7643 imul $imm, %reg, %reg, and the clr %reg instruction
7644 is converted into xor %reg, %reg. */
7646 unsigned int first_reg_op
;
7648 if (operand_type_check (i
.types
[0], reg
))
7652 /* Pretend we saw the extra register operand. */
7653 gas_assert (i
.reg_operands
== 1
7654 && i
.op
[first_reg_op
+ 1].regs
== 0);
7655 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7656 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7661 if (i
.tm
.opcode_modifier
.modrm
)
7663 /* The opcode is completed (modulo i.tm.extension_opcode which
7664 must be put into the modrm byte). Now, we make the modrm and
7665 index base bytes based on all the info we've collected. */
7667 default_seg
= build_modrm_byte ();
7669 else if (i
.types
[0].bitfield
.class == SReg
)
7671 if (flag_code
!= CODE_64BIT
7672 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7673 && i
.op
[0].regs
->reg_num
== 1
7674 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7675 && i
.op
[0].regs
->reg_num
< 4)
7677 as_bad (_("you can't `%s %s%s'"),
7678 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7681 if ( i
.op
[0].regs
->reg_num
> 3 && i
.opcode_length
== 1 )
7683 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7684 i
.opcode_length
= 2;
7686 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7688 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7692 else if (i
.tm
.opcode_modifier
.isstring
)
7694 /* For the string instructions that allow a segment override
7695 on one of their operands, the default segment is ds. */
7698 else if (i
.short_form
)
7700 /* The register or float register operand is in operand
7702 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7704 /* Register goes in low 3 bits of opcode. */
7705 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7706 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7708 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7710 /* Warn about some common errors, but press on regardless.
7711 The first case can be generated by gcc (<= 2.8.1). */
7712 if (i
.operands
== 2)
7714 /* Reversed arguments on faddp, fsubp, etc. */
7715 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7716 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7717 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7721 /* Extraneous `l' suffix on fp insn. */
7722 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7723 register_prefix
, i
.op
[0].regs
->reg_name
);
7728 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7729 && i
.tm
.base_opcode
== 0x8d /* lea */
7730 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
7731 && !is_any_vex_encoding(&i
.tm
))
7733 if (!quiet_warnings
)
7734 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7738 i
.prefix
[SEG_PREFIX
] = 0;
7742 /* If a segment was explicitly specified, and the specified segment
7743 is neither the default nor the one already recorded from a prefix,
7744 use an opcode prefix to select it. If we never figured out what
7745 the default segment is, then default_seg will be zero at this
7746 point, and the specified segment prefix will always be used. */
7748 && i
.seg
[0] != default_seg
7749 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7751 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7757 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7758 bfd_boolean do_sse2avx
)
7760 if (r
->reg_flags
& RegRex
)
7762 if (i
.rex
& rex_bit
)
7763 as_bad (_("same type of prefix used twice"));
7766 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7768 gas_assert (i
.vex
.register_specifier
== r
);
7769 i
.vex
.register_specifier
+= 8;
7772 if (r
->reg_flags
& RegVRex
)
7776 static const seg_entry
*
7777 build_modrm_byte (void)
7779 const seg_entry
*default_seg
= 0;
7780 unsigned int source
, dest
;
7783 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7786 unsigned int nds
, reg_slot
;
7789 dest
= i
.operands
- 1;
7792 /* There are 2 kinds of instructions:
7793 1. 5 operands: 4 register operands or 3 register operands
7794 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7795 VexW0 or VexW1. The destination must be either XMM, YMM or
7797 2. 4 operands: 4 register operands or 3 register operands
7798 plus 1 memory operand, with VexXDS. */
7799 gas_assert ((i
.reg_operands
== 4
7800 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7801 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7802 && i
.tm
.opcode_modifier
.vexw
7803 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7805 /* If VexW1 is set, the first non-immediate operand is the source and
7806 the second non-immediate one is encoded in the immediate operand. */
7807 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7809 source
= i
.imm_operands
;
7810 reg_slot
= i
.imm_operands
+ 1;
7814 source
= i
.imm_operands
+ 1;
7815 reg_slot
= i
.imm_operands
;
7818 if (i
.imm_operands
== 0)
7820 /* When there is no immediate operand, generate an 8bit
7821 immediate operand to encode the first operand. */
7822 exp
= &im_expressions
[i
.imm_operands
++];
7823 i
.op
[i
.operands
].imms
= exp
;
7824 i
.types
[i
.operands
] = imm8
;
7827 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7828 exp
->X_op
= O_constant
;
7829 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7830 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7834 gas_assert (i
.imm_operands
== 1);
7835 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7836 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7838 /* Turn on Imm8 again so that output_imm will generate it. */
7839 i
.types
[0].bitfield
.imm8
= 1;
7841 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7842 i
.op
[0].imms
->X_add_number
7843 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7844 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7847 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7848 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7853 /* i.reg_operands MUST be the number of real register operands;
7854 implicit registers do not count. If there are 3 register
7855 operands, it must be a instruction with VexNDS. For a
7856 instruction with VexNDD, the destination register is encoded
7857 in VEX prefix. If there are 4 register operands, it must be
7858 a instruction with VEX prefix and 3 sources. */
7859 if (i
.mem_operands
== 0
7860 && ((i
.reg_operands
== 2
7861 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7862 || (i
.reg_operands
== 3
7863 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7864 || (i
.reg_operands
== 4 && vex_3_sources
)))
7872 /* When there are 3 operands, one of them may be immediate,
7873 which may be the first or the last operand. Otherwise,
7874 the first operand must be shift count register (cl) or it
7875 is an instruction with VexNDS. */
7876 gas_assert (i
.imm_operands
== 1
7877 || (i
.imm_operands
== 0
7878 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7879 || (i
.types
[0].bitfield
.instance
== RegC
7880 && i
.types
[0].bitfield
.byte
))));
7881 if (operand_type_check (i
.types
[0], imm
)
7882 || (i
.types
[0].bitfield
.instance
== RegC
7883 && i
.types
[0].bitfield
.byte
))
7889 /* When there are 4 operands, the first two must be 8bit
7890 immediate operands. The source operand will be the 3rd
7893 For instructions with VexNDS, if the first operand
7894 an imm8, the source operand is the 2nd one. If the last
7895 operand is imm8, the source operand is the first one. */
7896 gas_assert ((i
.imm_operands
== 2
7897 && i
.types
[0].bitfield
.imm8
7898 && i
.types
[1].bitfield
.imm8
)
7899 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7900 && i
.imm_operands
== 1
7901 && (i
.types
[0].bitfield
.imm8
7902 || i
.types
[i
.operands
- 1].bitfield
.imm8
7904 if (i
.imm_operands
== 2)
7908 if (i
.types
[0].bitfield
.imm8
)
7915 if (is_evex_encoding (&i
.tm
))
7917 /* For EVEX instructions, when there are 5 operands, the
7918 first one must be immediate operand. If the second one
7919 is immediate operand, the source operand is the 3th
7920 one. If the last one is immediate operand, the source
7921 operand is the 2nd one. */
7922 gas_assert (i
.imm_operands
== 2
7923 && i
.tm
.opcode_modifier
.sae
7924 && operand_type_check (i
.types
[0], imm
));
7925 if (operand_type_check (i
.types
[1], imm
))
7927 else if (operand_type_check (i
.types
[4], imm
))
7941 /* RC/SAE operand could be between DEST and SRC. That happens
7942 when one operand is GPR and the other one is XMM/YMM/ZMM
7944 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7947 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7949 /* For instructions with VexNDS, the register-only source
7950 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7951 register. It is encoded in VEX prefix. */
7953 i386_operand_type op
;
7956 /* Swap two source operands if needed. */
7957 if (i
.tm
.opcode_modifier
.swapsources
)
7965 op
= i
.tm
.operand_types
[vvvv
];
7966 if ((dest
+ 1) >= i
.operands
7967 || ((op
.bitfield
.class != Reg
7968 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7969 && op
.bitfield
.class != RegSIMD
7970 && !operand_type_equal (&op
, ®mask
)))
7972 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7978 /* One of the register operands will be encoded in the i.rm.reg
7979 field, the other in the combined i.rm.mode and i.rm.regmem
7980 fields. If no form of this instruction supports a memory
7981 destination operand, then we assume the source operand may
7982 sometimes be a memory operand and so we need to store the
7983 destination in the i.rm.reg field. */
7984 if (!i
.tm
.opcode_modifier
.regmem
7985 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7987 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7988 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7989 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
7990 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
7994 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7995 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7996 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
7997 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
7999 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8001 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
8004 add_prefix (LOCK_PREFIX_OPCODE
);
8008 { /* If it's not 2 reg operands... */
8013 unsigned int fake_zero_displacement
= 0;
8016 for (op
= 0; op
< i
.operands
; op
++)
8017 if (i
.flags
[op
] & Operand_Mem
)
8019 gas_assert (op
< i
.operands
);
8021 if (i
.tm
.opcode_modifier
.sib
)
8023 /* The index register of VSIB shouldn't be RegIZ. */
8024 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8025 && i
.index_reg
->reg_num
== RegIZ
)
8028 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8031 i
.sib
.base
= NO_BASE_REGISTER
;
8032 i
.sib
.scale
= i
.log2_scale_factor
;
8033 i
.types
[op
].bitfield
.disp8
= 0;
8034 i
.types
[op
].bitfield
.disp16
= 0;
8035 i
.types
[op
].bitfield
.disp64
= 0;
8036 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8038 /* Must be 32 bit */
8039 i
.types
[op
].bitfield
.disp32
= 1;
8040 i
.types
[op
].bitfield
.disp32s
= 0;
8044 i
.types
[op
].bitfield
.disp32
= 0;
8045 i
.types
[op
].bitfield
.disp32s
= 1;
8049 /* Since the mandatory SIB always has index register, so
8050 the code logic remains unchanged. The non-mandatory SIB
8051 without index register is allowed and will be handled
8055 if (i
.index_reg
->reg_num
== RegIZ
)
8056 i
.sib
.index
= NO_INDEX_REGISTER
;
8058 i
.sib
.index
= i
.index_reg
->reg_num
;
8059 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8065 if (i
.base_reg
== 0)
8068 if (!i
.disp_operands
)
8069 fake_zero_displacement
= 1;
8070 if (i
.index_reg
== 0)
8072 i386_operand_type newdisp
;
8074 /* Both check for VSIB and mandatory non-vector SIB. */
8075 gas_assert (!i
.tm
.opcode_modifier
.sib
8076 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8077 /* Operand is just <disp> */
8078 if (flag_code
== CODE_64BIT
)
8080 /* 64bit mode overwrites the 32bit absolute
8081 addressing by RIP relative addressing and
8082 absolute addressing is encoded by one of the
8083 redundant SIB forms. */
8084 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8085 i
.sib
.base
= NO_BASE_REGISTER
;
8086 i
.sib
.index
= NO_INDEX_REGISTER
;
8087 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8089 else if ((flag_code
== CODE_16BIT
)
8090 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8092 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8097 i
.rm
.regmem
= NO_BASE_REGISTER
;
8100 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8101 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8103 else if (!i
.tm
.opcode_modifier
.sib
)
8105 /* !i.base_reg && i.index_reg */
8106 if (i
.index_reg
->reg_num
== RegIZ
)
8107 i
.sib
.index
= NO_INDEX_REGISTER
;
8109 i
.sib
.index
= i
.index_reg
->reg_num
;
8110 i
.sib
.base
= NO_BASE_REGISTER
;
8111 i
.sib
.scale
= i
.log2_scale_factor
;
8112 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8113 i
.types
[op
].bitfield
.disp8
= 0;
8114 i
.types
[op
].bitfield
.disp16
= 0;
8115 i
.types
[op
].bitfield
.disp64
= 0;
8116 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8118 /* Must be 32 bit */
8119 i
.types
[op
].bitfield
.disp32
= 1;
8120 i
.types
[op
].bitfield
.disp32s
= 0;
8124 i
.types
[op
].bitfield
.disp32
= 0;
8125 i
.types
[op
].bitfield
.disp32s
= 1;
8127 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8131 /* RIP addressing for 64bit mode. */
8132 else if (i
.base_reg
->reg_num
== RegIP
)
8134 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8135 i
.rm
.regmem
= NO_BASE_REGISTER
;
8136 i
.types
[op
].bitfield
.disp8
= 0;
8137 i
.types
[op
].bitfield
.disp16
= 0;
8138 i
.types
[op
].bitfield
.disp32
= 0;
8139 i
.types
[op
].bitfield
.disp32s
= 1;
8140 i
.types
[op
].bitfield
.disp64
= 0;
8141 i
.flags
[op
] |= Operand_PCrel
;
8142 if (! i
.disp_operands
)
8143 fake_zero_displacement
= 1;
8145 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8147 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8148 switch (i
.base_reg
->reg_num
)
8151 if (i
.index_reg
== 0)
8153 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8154 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8158 if (i
.index_reg
== 0)
8161 if (operand_type_check (i
.types
[op
], disp
) == 0)
8163 /* fake (%bp) into 0(%bp) */
8164 if (i
.disp_encoding
== disp_encoding_16bit
)
8165 i
.types
[op
].bitfield
.disp16
= 1;
8167 i
.types
[op
].bitfield
.disp8
= 1;
8168 fake_zero_displacement
= 1;
8171 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8172 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8174 default: /* (%si) -> 4 or (%di) -> 5 */
8175 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8177 if (!fake_zero_displacement
8181 fake_zero_displacement
= 1;
8182 if (i
.disp_encoding
== disp_encoding_8bit
)
8183 i
.types
[op
].bitfield
.disp8
= 1;
8185 i
.types
[op
].bitfield
.disp16
= 1;
8187 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8189 else /* i.base_reg and 32/64 bit mode */
8191 if (flag_code
== CODE_64BIT
8192 && operand_type_check (i
.types
[op
], disp
))
8194 i
.types
[op
].bitfield
.disp16
= 0;
8195 i
.types
[op
].bitfield
.disp64
= 0;
8196 if (i
.prefix
[ADDR_PREFIX
] == 0)
8198 i
.types
[op
].bitfield
.disp32
= 0;
8199 i
.types
[op
].bitfield
.disp32s
= 1;
8203 i
.types
[op
].bitfield
.disp32
= 1;
8204 i
.types
[op
].bitfield
.disp32s
= 0;
8208 if (!i
.tm
.opcode_modifier
.sib
)
8209 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8210 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8212 i
.sib
.base
= i
.base_reg
->reg_num
;
8213 /* x86-64 ignores REX prefix bit here to avoid decoder
8215 if (!(i
.base_reg
->reg_flags
& RegRex
)
8216 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8217 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8219 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8221 fake_zero_displacement
= 1;
8222 if (i
.disp_encoding
== disp_encoding_32bit
)
8223 i
.types
[op
].bitfield
.disp32
= 1;
8225 i
.types
[op
].bitfield
.disp8
= 1;
8227 i
.sib
.scale
= i
.log2_scale_factor
;
8228 if (i
.index_reg
== 0)
8230 /* Only check for VSIB. */
8231 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8232 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8233 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8235 /* <disp>(%esp) becomes two byte modrm with no index
8236 register. We've already stored the code for esp
8237 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8238 Any base register besides %esp will not use the
8239 extra modrm byte. */
8240 i
.sib
.index
= NO_INDEX_REGISTER
;
8242 else if (!i
.tm
.opcode_modifier
.sib
)
8244 if (i
.index_reg
->reg_num
== RegIZ
)
8245 i
.sib
.index
= NO_INDEX_REGISTER
;
8247 i
.sib
.index
= i
.index_reg
->reg_num
;
8248 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8249 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8254 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8255 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8259 if (!fake_zero_displacement
8263 fake_zero_displacement
= 1;
8264 if (i
.disp_encoding
== disp_encoding_8bit
)
8265 i
.types
[op
].bitfield
.disp8
= 1;
8267 i
.types
[op
].bitfield
.disp32
= 1;
8269 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8273 if (fake_zero_displacement
)
8275 /* Fakes a zero displacement assuming that i.types[op]
8276 holds the correct displacement size. */
8279 gas_assert (i
.op
[op
].disps
== 0);
8280 exp
= &disp_expressions
[i
.disp_operands
++];
8281 i
.op
[op
].disps
= exp
;
8282 exp
->X_op
= O_constant
;
8283 exp
->X_add_number
= 0;
8284 exp
->X_add_symbol
= (symbolS
*) 0;
8285 exp
->X_op_symbol
= (symbolS
*) 0;
8293 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8295 if (operand_type_check (i
.types
[0], imm
))
8296 i
.vex
.register_specifier
= NULL
;
8299 /* VEX.vvvv encodes one of the sources when the first
8300 operand is not an immediate. */
8301 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8302 i
.vex
.register_specifier
= i
.op
[0].regs
;
8304 i
.vex
.register_specifier
= i
.op
[1].regs
;
8307 /* Destination is a XMM register encoded in the ModRM.reg
8309 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8310 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8313 /* ModRM.rm and VEX.B encodes the other source. */
8314 if (!i
.mem_operands
)
8318 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8319 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8321 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8323 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8327 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8329 i
.vex
.register_specifier
= i
.op
[2].regs
;
8330 if (!i
.mem_operands
)
8333 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8334 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8338 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8339 (if any) based on i.tm.extension_opcode. Again, we must be
8340 careful to make sure that segment/control/debug/test/MMX
8341 registers are coded into the i.rm.reg field. */
8342 else if (i
.reg_operands
)
8345 unsigned int vex_reg
= ~0;
8347 for (op
= 0; op
< i
.operands
; op
++)
8348 if (i
.types
[op
].bitfield
.class == Reg
8349 || i
.types
[op
].bitfield
.class == RegBND
8350 || i
.types
[op
].bitfield
.class == RegMask
8351 || i
.types
[op
].bitfield
.class == SReg
8352 || i
.types
[op
].bitfield
.class == RegCR
8353 || i
.types
[op
].bitfield
.class == RegDR
8354 || i
.types
[op
].bitfield
.class == RegTR
8355 || i
.types
[op
].bitfield
.class == RegSIMD
8356 || i
.types
[op
].bitfield
.class == RegMMX
)
8361 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8363 /* For instructions with VexNDS, the register-only
8364 source operand is encoded in VEX prefix. */
8365 gas_assert (mem
!= (unsigned int) ~0);
8370 gas_assert (op
< i
.operands
);
8374 /* Check register-only source operand when two source
8375 operands are swapped. */
8376 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8377 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8381 gas_assert (mem
== (vex_reg
+ 1)
8382 && op
< i
.operands
);
8387 gas_assert (vex_reg
< i
.operands
);
8391 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8393 /* For instructions with VexNDD, the register destination
8394 is encoded in VEX prefix. */
8395 if (i
.mem_operands
== 0)
8397 /* There is no memory operand. */
8398 gas_assert ((op
+ 2) == i
.operands
);
8403 /* There are only 2 non-immediate operands. */
8404 gas_assert (op
< i
.imm_operands
+ 2
8405 && i
.operands
== i
.imm_operands
+ 2);
8406 vex_reg
= i
.imm_operands
+ 1;
8410 gas_assert (op
< i
.operands
);
8412 if (vex_reg
!= (unsigned int) ~0)
8414 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8416 if ((type
->bitfield
.class != Reg
8417 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8418 && type
->bitfield
.class != RegSIMD
8419 && !operand_type_equal (type
, ®mask
))
8422 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8425 /* Don't set OP operand twice. */
8428 /* If there is an extension opcode to put here, the
8429 register number must be put into the regmem field. */
8430 if (i
.tm
.extension_opcode
!= None
)
8432 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8433 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8434 i
.tm
.opcode_modifier
.sse2avx
);
8438 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8439 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8440 i
.tm
.opcode_modifier
.sse2avx
);
8444 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8445 must set it to 3 to indicate this is a register operand
8446 in the regmem field. */
8447 if (!i
.mem_operands
)
8451 /* Fill in i.rm.reg field with extension opcode (if any). */
8452 if (i
.tm
.extension_opcode
!= None
)
8453 i
.rm
.reg
= i
.tm
.extension_opcode
;
8459 frag_opcode_byte (unsigned char byte
)
8461 if (now_seg
!= absolute_section
)
8462 FRAG_APPEND_1_CHAR (byte
);
8464 ++abs_section_offset
;
8468 flip_code16 (unsigned int code16
)
8470 gas_assert (i
.tm
.operands
== 1);
8472 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8473 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8474 || i
.tm
.operand_types
[0].bitfield
.disp32s
8475 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8480 output_branch (void)
8486 relax_substateT subtype
;
8490 if (now_seg
== absolute_section
)
8492 as_bad (_("relaxable branches not supported in absolute section"));
8496 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8497 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8500 if (i
.prefix
[DATA_PREFIX
] != 0)
8504 code16
^= flip_code16(code16
);
8506 /* Pentium4 branch hints. */
8507 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8508 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8513 if (i
.prefix
[REX_PREFIX
] != 0)
8519 /* BND prefixed jump. */
8520 if (i
.prefix
[BND_PREFIX
] != 0)
8526 if (i
.prefixes
!= 0)
8527 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8529 /* It's always a symbol; End frag & setup for relax.
8530 Make sure there is enough room in this frag for the largest
8531 instruction we may generate in md_convert_frag. This is 2
8532 bytes for the opcode and room for the prefix and largest
8534 frag_grow (prefix
+ 2 + 4);
8535 /* Prefix and 1 opcode byte go in fr_fix. */
8536 p
= frag_more (prefix
+ 1);
8537 if (i
.prefix
[DATA_PREFIX
] != 0)
8538 *p
++ = DATA_PREFIX_OPCODE
;
8539 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8540 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8541 *p
++ = i
.prefix
[SEG_PREFIX
];
8542 if (i
.prefix
[BND_PREFIX
] != 0)
8543 *p
++ = BND_PREFIX_OPCODE
;
8544 if (i
.prefix
[REX_PREFIX
] != 0)
8545 *p
++ = i
.prefix
[REX_PREFIX
];
8546 *p
= i
.tm
.base_opcode
;
8548 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8549 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8550 else if (cpu_arch_flags
.bitfield
.cpui386
)
8551 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8553 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8556 sym
= i
.op
[0].disps
->X_add_symbol
;
8557 off
= i
.op
[0].disps
->X_add_number
;
8559 if (i
.op
[0].disps
->X_op
!= O_constant
8560 && i
.op
[0].disps
->X_op
!= O_symbol
)
8562 /* Handle complex expressions. */
8563 sym
= make_expr_symbol (i
.op
[0].disps
);
8567 /* 1 possible extra opcode + 4 byte displacement go in var part.
8568 Pass reloc in fr_var. */
8569 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8572 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8573 /* Return TRUE iff PLT32 relocation should be used for branching to
8577 need_plt32_p (symbolS
*s
)
8579 /* PLT32 relocation is ELF only. */
8584 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8585 krtld support it. */
8589 /* Since there is no need to prepare for PLT branch on x86-64, we
8590 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8591 be used as a marker for 32-bit PC-relative branches. */
8598 /* Weak or undefined symbol need PLT32 relocation. */
8599 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8602 /* Non-global symbol doesn't need PLT32 relocation. */
8603 if (! S_IS_EXTERNAL (s
))
8606 /* Other global symbols need PLT32 relocation. NB: Symbol with
8607 non-default visibilities are treated as normal global symbol
8608 so that PLT32 relocation can be used as a marker for 32-bit
8609 PC-relative branches. It is useful for linker relaxation. */
8620 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8622 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8624 /* This is a loop or jecxz type instruction. */
8626 if (i
.prefix
[ADDR_PREFIX
] != 0)
8628 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8631 /* Pentium4 branch hints. */
8632 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8633 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8635 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8644 if (flag_code
== CODE_16BIT
)
8647 if (i
.prefix
[DATA_PREFIX
] != 0)
8649 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8651 code16
^= flip_code16(code16
);
8659 /* BND prefixed jump. */
8660 if (i
.prefix
[BND_PREFIX
] != 0)
8662 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8666 if (i
.prefix
[REX_PREFIX
] != 0)
8668 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8672 if (i
.prefixes
!= 0)
8673 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8675 if (now_seg
== absolute_section
)
8677 abs_section_offset
+= i
.opcode_length
+ size
;
8681 p
= frag_more (i
.opcode_length
+ size
);
8682 switch (i
.opcode_length
)
8685 *p
++ = i
.tm
.base_opcode
>> 8;
8688 *p
++ = i
.tm
.base_opcode
;
8694 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8696 && jump_reloc
== NO_RELOC
8697 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8698 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8701 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8703 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8704 i
.op
[0].disps
, 1, jump_reloc
);
8706 /* All jumps handled here are signed, but don't use a signed limit
8707 check for 32 and 16 bit jumps as we want to allow wrap around at
8708 4G and 64k respectively. */
8710 fixP
->fx_signed
= 1;
8714 output_interseg_jump (void)
8722 if (flag_code
== CODE_16BIT
)
8726 if (i
.prefix
[DATA_PREFIX
] != 0)
8733 gas_assert (!i
.prefix
[REX_PREFIX
]);
8739 if (i
.prefixes
!= 0)
8740 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8742 if (now_seg
== absolute_section
)
8744 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8748 /* 1 opcode; 2 segment; offset */
8749 p
= frag_more (prefix
+ 1 + 2 + size
);
8751 if (i
.prefix
[DATA_PREFIX
] != 0)
8752 *p
++ = DATA_PREFIX_OPCODE
;
8754 if (i
.prefix
[REX_PREFIX
] != 0)
8755 *p
++ = i
.prefix
[REX_PREFIX
];
8757 *p
++ = i
.tm
.base_opcode
;
8758 if (i
.op
[1].imms
->X_op
== O_constant
)
8760 offsetT n
= i
.op
[1].imms
->X_add_number
;
8763 && !fits_in_unsigned_word (n
)
8764 && !fits_in_signed_word (n
))
8766 as_bad (_("16-bit jump out of range"));
8769 md_number_to_chars (p
, n
, size
);
8772 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8773 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8776 if (i
.op
[0].imms
->X_op
== O_constant
)
8777 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8779 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
8780 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
8783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8788 asection
*seg
= now_seg
;
8789 subsegT subseg
= now_subseg
;
8791 unsigned int alignment
, align_size_1
;
8792 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8793 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8794 unsigned int padding
;
8796 if (!IS_ELF
|| !x86_used_note
)
8799 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8801 /* The .note.gnu.property section layout:
8803 Field Length Contents
8806 n_descsz 4 The note descriptor size
8807 n_type 4 NT_GNU_PROPERTY_TYPE_0
8809 n_desc n_descsz The program property array
8813 /* Create the .note.gnu.property section. */
8814 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8815 bfd_set_section_flags (sec
,
8822 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8833 bfd_set_section_alignment (sec
, alignment
);
8834 elf_section_type (sec
) = SHT_NOTE
;
8836 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8838 isa_1_descsz_raw
= 4 + 4 + 4;
8839 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8840 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8842 feature_2_descsz_raw
= isa_1_descsz
;
8843 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8845 feature_2_descsz_raw
+= 4 + 4 + 4;
8846 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8847 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8850 descsz
= feature_2_descsz
;
8851 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8852 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8854 /* Write n_namsz. */
8855 md_number_to_chars (p
, (valueT
) 4, 4);
8857 /* Write n_descsz. */
8858 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8861 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8864 memcpy (p
+ 4 * 3, "GNU", 4);
8866 /* Write 4-byte type. */
8867 md_number_to_chars (p
+ 4 * 4,
8868 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8870 /* Write 4-byte data size. */
8871 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8873 /* Write 4-byte data. */
8874 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8876 /* Zero out paddings. */
8877 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8879 memset (p
+ 4 * 7, 0, padding
);
8881 /* Write 4-byte type. */
8882 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8883 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8885 /* Write 4-byte data size. */
8886 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8888 /* Write 4-byte data. */
8889 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8890 (valueT
) x86_feature_2_used
, 4);
8892 /* Zero out paddings. */
8893 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8895 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8897 /* We probably can't restore the current segment, for there likely
8900 subseg_set (seg
, subseg
);
8905 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8906 const char *frag_now_ptr
)
8908 unsigned int len
= 0;
8910 if (start_frag
!= frag_now
)
8912 const fragS
*fr
= start_frag
;
8917 } while (fr
&& fr
!= frag_now
);
8920 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8923 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8924 be macro-fused with conditional jumps.
8925 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8926 or is one of the following format:
8939 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8941 /* No RIP address. */
8942 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8945 /* No VEX/EVEX encoding. */
8946 if (is_any_vex_encoding (&i
.tm
))
8949 /* add, sub without add/sub m, imm. */
8950 if (i
.tm
.base_opcode
<= 5
8951 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8952 || ((i
.tm
.base_opcode
| 3) == 0x83
8953 && (i
.tm
.extension_opcode
== 0x5
8954 || i
.tm
.extension_opcode
== 0x0)))
8956 *mf_cmp_p
= mf_cmp_alu_cmp
;
8957 return !(i
.mem_operands
&& i
.imm_operands
);
8960 /* and without and m, imm. */
8961 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8962 || ((i
.tm
.base_opcode
| 3) == 0x83
8963 && i
.tm
.extension_opcode
== 0x4))
8965 *mf_cmp_p
= mf_cmp_test_and
;
8966 return !(i
.mem_operands
&& i
.imm_operands
);
8969 /* test without test m imm. */
8970 if ((i
.tm
.base_opcode
| 1) == 0x85
8971 || (i
.tm
.base_opcode
| 1) == 0xa9
8972 || ((i
.tm
.base_opcode
| 1) == 0xf7
8973 && i
.tm
.extension_opcode
== 0))
8975 *mf_cmp_p
= mf_cmp_test_and
;
8976 return !(i
.mem_operands
&& i
.imm_operands
);
8979 /* cmp without cmp m, imm. */
8980 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8981 || ((i
.tm
.base_opcode
| 3) == 0x83
8982 && (i
.tm
.extension_opcode
== 0x7)))
8984 *mf_cmp_p
= mf_cmp_alu_cmp
;
8985 return !(i
.mem_operands
&& i
.imm_operands
);
8988 /* inc, dec without inc/dec m. */
8989 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8990 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8991 || ((i
.tm
.base_opcode
| 1) == 0xff
8992 && i
.tm
.extension_opcode
<= 0x1))
8994 *mf_cmp_p
= mf_cmp_incdec
;
8995 return !i
.mem_operands
;
9001 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9004 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9006 /* NB: Don't work with COND_JUMP86 without i386. */
9007 if (!align_branch_power
9008 || now_seg
== absolute_section
9009 || !cpu_arch_flags
.bitfield
.cpui386
9010 || !(align_branch
& align_branch_fused_bit
))
9013 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9015 if (last_insn
.kind
== last_insn_other
9016 || last_insn
.seg
!= now_seg
)
9019 as_warn_where (last_insn
.file
, last_insn
.line
,
9020 _("`%s` skips -malign-branch-boundary on `%s`"),
9021 last_insn
.name
, i
.tm
.name
);
9027 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9030 add_branch_prefix_frag_p (void)
9032 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9033 to PadLock instructions since they include prefixes in opcode. */
9034 if (!align_branch_power
9035 || !align_branch_prefix_size
9036 || now_seg
== absolute_section
9037 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9038 || !cpu_arch_flags
.bitfield
.cpui386
)
9041 /* Don't add prefix if it is a prefix or there is no operand in case
9042 that segment prefix is special. */
9043 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9046 if (last_insn
.kind
== last_insn_other
9047 || last_insn
.seg
!= now_seg
)
9051 as_warn_where (last_insn
.file
, last_insn
.line
,
9052 _("`%s` skips -malign-branch-boundary on `%s`"),
9053 last_insn
.name
, i
.tm
.name
);
9058 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9061 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9062 enum mf_jcc_kind
*mf_jcc_p
)
9066 /* NB: Don't work with COND_JUMP86 without i386. */
9067 if (!align_branch_power
9068 || now_seg
== absolute_section
9069 || !cpu_arch_flags
.bitfield
.cpui386
)
9074 /* Check for jcc and direct jmp. */
9075 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9077 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9079 *branch_p
= align_branch_jmp
;
9080 add_padding
= align_branch
& align_branch_jmp_bit
;
9084 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9085 igore the lowest bit. */
9086 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9087 *branch_p
= align_branch_jcc
;
9088 if ((align_branch
& align_branch_jcc_bit
))
9092 else if (is_any_vex_encoding (&i
.tm
))
9094 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9097 *branch_p
= align_branch_ret
;
9098 if ((align_branch
& align_branch_ret_bit
))
9103 /* Check for indirect jmp, direct and indirect calls. */
9104 if (i
.tm
.base_opcode
== 0xe8)
9107 *branch_p
= align_branch_call
;
9108 if ((align_branch
& align_branch_call_bit
))
9111 else if (i
.tm
.base_opcode
== 0xff
9112 && (i
.tm
.extension_opcode
== 2
9113 || i
.tm
.extension_opcode
== 4))
9115 /* Indirect call and jmp. */
9116 *branch_p
= align_branch_indirect
;
9117 if ((align_branch
& align_branch_indirect_bit
))
9124 && (i
.op
[0].disps
->X_op
== O_symbol
9125 || (i
.op
[0].disps
->X_op
== O_subtract
9126 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9128 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9129 /* No padding to call to global or undefined tls_get_addr. */
9130 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9131 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9137 && last_insn
.kind
!= last_insn_other
9138 && last_insn
.seg
== now_seg
)
9141 as_warn_where (last_insn
.file
, last_insn
.line
,
9142 _("`%s` skips -malign-branch-boundary on `%s`"),
9143 last_insn
.name
, i
.tm
.name
);
9153 fragS
*insn_start_frag
;
9154 offsetT insn_start_off
;
9155 fragS
*fragP
= NULL
;
9156 enum align_branch_kind branch
= align_branch_none
;
9157 /* The initializer is arbitrary just to avoid uninitialized error.
9158 it's actually either assigned in add_branch_padding_frag_p
9159 or never be used. */
9160 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9162 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9163 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9165 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9166 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9167 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9169 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9170 || i
.tm
.cpu_flags
.bitfield
.cpu287
9171 || i
.tm
.cpu_flags
.bitfield
.cpu387
9172 || i
.tm
.cpu_flags
.bitfield
.cpu687
9173 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9174 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9176 if ((i
.xstate
& xstate_mmx
)
9177 || i
.tm
.base_opcode
== 0xf77 /* emms */
9178 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9179 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9183 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9184 i
.xstate
|= xstate_zmm
;
9185 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9186 i
.xstate
|= xstate_ymm
;
9187 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9188 i
.xstate
|= xstate_xmm
;
9191 /* vzeroall / vzeroupper */
9192 if (i
.tm
.base_opcode
== 0x77 && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9193 i
.xstate
|= xstate_ymm
;
9195 if ((i
.xstate
& xstate_xmm
)
9196 /* ldmxcsr / stmxcsr */
9197 || (i
.tm
.base_opcode
== 0xfae && i
.tm
.cpu_flags
.bitfield
.cpusse
)
9198 /* vldmxcsr / vstmxcsr */
9199 || (i
.tm
.base_opcode
== 0xae && i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9200 || i
.tm
.cpu_flags
.bitfield
.cpuwidekl
9201 || i
.tm
.cpu_flags
.bitfield
.cpukl
)
9202 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9204 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9205 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9206 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9207 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9208 if (i
.mask
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9209 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9210 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9211 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9212 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9213 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9214 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9215 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9216 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9217 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9219 if (x86_feature_2_used
9220 || i
.tm
.cpu_flags
.bitfield
.cpucmov
9221 || i
.tm
.cpu_flags
.bitfield
.cpusyscall
9222 || (i
.tm
.base_opcode
== 0xfc7
9223 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
9224 && i
.tm
.extension_opcode
== 1) /* cmpxchg8b */)
9225 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9226 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
9227 || i
.tm
.cpu_flags
.bitfield
.cpussse3
9228 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
9229 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
9230 || i
.tm
.cpu_flags
.bitfield
.cpucx16
9231 || i
.tm
.cpu_flags
.bitfield
.cpupopcnt
9232 /* LAHF-SAHF insns in 64-bit mode. */
9233 || (flag_code
== CODE_64BIT
9234 && (i
.tm
.base_opcode
| 1) == 0x9f
9235 && i
.tm
.opcode_modifier
.opcodespace
== SPACE_BASE
))
9236 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9237 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
9238 || i
.tm
.cpu_flags
.bitfield
.cpuavx2
9239 /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
9240 CpuAVX512DQ, LPW, TBM and AMX. */
9241 || (i
.tm
.opcode_modifier
.vex
9242 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9243 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9244 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9245 && !i
.tm
.cpu_flags
.bitfield
.cpulwp
9246 && !i
.tm
.cpu_flags
.bitfield
.cputbm
9247 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9248 || i
.tm
.cpu_flags
.bitfield
.cpuf16c
9249 || i
.tm
.cpu_flags
.bitfield
.cpufma
9250 || i
.tm
.cpu_flags
.bitfield
.cpulzcnt
9251 || i
.tm
.cpu_flags
.bitfield
.cpumovbe
9252 || i
.tm
.cpu_flags
.bitfield
.cpuxsaves
9253 || (x86_feature_2_used
9254 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9255 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9256 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9257 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9258 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
9259 || i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
9260 || i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
9261 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
9262 /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
9264 || (i
.tm
.opcode_modifier
.evex
9265 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512er
9266 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
9267 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
))
9268 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9272 /* Tie dwarf2 debug info to the address at the start of the insn.
9273 We can't do this after the insn has been output as the current
9274 frag may have been closed off. eg. by frag_var. */
9275 dwarf2_emit_insn (0);
9277 insn_start_frag
= frag_now
;
9278 insn_start_off
= frag_now_fix ();
9280 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9283 /* Branch can be 8 bytes. Leave some room for prefixes. */
9284 unsigned int max_branch_padding_size
= 14;
9286 /* Align section to boundary. */
9287 record_alignment (now_seg
, align_branch_power
);
9289 /* Make room for padding. */
9290 frag_grow (max_branch_padding_size
);
9292 /* Start of the padding. */
9297 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9298 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9301 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9302 fragP
->tc_frag_data
.branch_type
= branch
;
9303 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9307 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9309 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9310 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9312 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9313 output_interseg_jump ();
9316 /* Output normal instructions here. */
9320 enum mf_cmp_kind mf_cmp
;
9323 && (i
.tm
.base_opcode
== 0xfaee8
9324 || i
.tm
.base_opcode
== 0xfaef0
9325 || i
.tm
.base_opcode
== 0xfaef8))
9327 /* Encode lfence, mfence, and sfence as
9328 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9329 if (now_seg
!= absolute_section
)
9331 offsetT val
= 0x240483f0ULL
;
9334 md_number_to_chars (p
, val
, 5);
9337 abs_section_offset
+= 5;
9341 /* Some processors fail on LOCK prefix. This options makes
9342 assembler ignore LOCK prefix and serves as a workaround. */
9343 if (omit_lock_prefix
)
9345 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9346 && i
.tm
.opcode_modifier
.isprefix
)
9348 i
.prefix
[LOCK_PREFIX
] = 0;
9352 /* Skip if this is a branch. */
9354 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9356 /* Make room for padding. */
9357 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9362 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9363 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9366 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9367 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9368 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9370 else if (add_branch_prefix_frag_p ())
9372 unsigned int max_prefix_size
= align_branch_prefix_size
;
9374 /* Make room for padding. */
9375 frag_grow (max_prefix_size
);
9380 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9381 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9384 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9387 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9388 don't need the explicit prefix. */
9389 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9391 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9400 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9401 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9405 switch (i
.opcode_length
)
9411 /* Check for pseudo prefixes. */
9412 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9414 as_bad_where (insn_start_frag
->fr_file
,
9415 insn_start_frag
->fr_line
,
9416 _("pseudo prefix without instruction"));
9426 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9427 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9428 R_X86_64_GOTTPOFF relocation so that linker can safely
9429 perform IE->LE optimization. A dummy REX_OPCODE prefix
9430 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9431 relocation for GDesc -> IE/LE optimization. */
9432 if (x86_elf_abi
== X86_64_X32_ABI
9434 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9435 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9436 && i
.prefix
[REX_PREFIX
] == 0)
9437 add_prefix (REX_OPCODE
);
9440 /* The prefix bytes. */
9441 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9443 frag_opcode_byte (*q
);
9447 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9453 frag_opcode_byte (*q
);
9456 /* There should be no other prefixes for instructions
9461 /* For EVEX instructions i.vrex should become 0 after
9462 build_evex_prefix. For VEX instructions upper 16 registers
9463 aren't available, so VREX should be 0. */
9466 /* Now the VEX prefix. */
9467 if (now_seg
!= absolute_section
)
9469 p
= frag_more (i
.vex
.length
);
9470 for (j
= 0; j
< i
.vex
.length
; j
++)
9471 p
[j
] = i
.vex
.bytes
[j
];
9474 abs_section_offset
+= i
.vex
.length
;
9477 /* Now the opcode; be careful about word order here! */
9478 if (now_seg
== absolute_section
)
9479 abs_section_offset
+= i
.opcode_length
;
9480 else if (i
.opcode_length
== 1)
9482 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9486 switch (i
.opcode_length
)
9490 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9491 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9495 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9505 /* Put out high byte first: can't use md_number_to_chars! */
9506 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9507 *p
= i
.tm
.base_opcode
& 0xff;
9510 /* Now the modrm byte and sib byte (if present). */
9511 if (i
.tm
.opcode_modifier
.modrm
)
9513 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9515 | (i
.rm
.mode
<< 6));
9516 /* If i.rm.regmem == ESP (4)
9517 && i.rm.mode != (Register mode)
9519 ==> need second modrm byte. */
9520 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9522 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9523 frag_opcode_byte ((i
.sib
.base
<< 0)
9524 | (i
.sib
.index
<< 3)
9525 | (i
.sib
.scale
<< 6));
9528 if (i
.disp_operands
)
9529 output_disp (insn_start_frag
, insn_start_off
);
9532 output_imm (insn_start_frag
, insn_start_off
);
9535 * frag_now_fix () returning plain abs_section_offset when we're in the
9536 * absolute section, and abs_section_offset not getting updated as data
9537 * gets added to the frag breaks the logic below.
9539 if (now_seg
!= absolute_section
)
9541 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9543 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9547 /* NB: Don't add prefix with GOTPC relocation since
9548 output_disp() above depends on the fixed encoding
9549 length. Can't add prefix with TLS relocation since
9550 it breaks TLS linker optimization. */
9551 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9552 /* Prefix count on the current instruction. */
9553 unsigned int count
= i
.vex
.length
;
9555 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9556 /* REX byte is encoded in VEX/EVEX prefix. */
9557 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9560 /* Count prefixes for extended opcode maps. */
9562 switch (i
.opcode_length
)
9565 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9568 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9580 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9589 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9592 /* Set the maximum prefix size in BRANCH_PREFIX
9594 if (fragP
->tc_frag_data
.max_bytes
> max
)
9595 fragP
->tc_frag_data
.max_bytes
= max
;
9596 if (fragP
->tc_frag_data
.max_bytes
> count
)
9597 fragP
->tc_frag_data
.max_bytes
-= count
;
9599 fragP
->tc_frag_data
.max_bytes
= 0;
9603 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9605 unsigned int max_prefix_size
;
9606 if (align_branch_prefix_size
> max
)
9607 max_prefix_size
= max
;
9609 max_prefix_size
= align_branch_prefix_size
;
9610 if (max_prefix_size
> count
)
9611 fragP
->tc_frag_data
.max_prefix_length
9612 = max_prefix_size
- count
;
9615 /* Use existing segment prefix if possible. Use CS
9616 segment prefix in 64-bit mode. In 32-bit mode, use SS
9617 segment prefix with ESP/EBP base register and use DS
9618 segment prefix without ESP/EBP base register. */
9619 if (i
.prefix
[SEG_PREFIX
])
9620 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9621 else if (flag_code
== CODE_64BIT
)
9622 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9624 && (i
.base_reg
->reg_num
== 4
9625 || i
.base_reg
->reg_num
== 5))
9626 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9628 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9633 /* NB: Don't work with COND_JUMP86 without i386. */
9634 if (align_branch_power
9635 && now_seg
!= absolute_section
9636 && cpu_arch_flags
.bitfield
.cpui386
)
9638 /* Terminate each frag so that we can add prefix and check for
9640 frag_wane (frag_now
);
9647 pi ("" /*line*/, &i
);
9649 #endif /* DEBUG386 */
9652 /* Return the size of the displacement operand N. */
9655 disp_size (unsigned int n
)
9659 if (i
.types
[n
].bitfield
.disp64
)
9661 else if (i
.types
[n
].bitfield
.disp8
)
9663 else if (i
.types
[n
].bitfield
.disp16
)
9668 /* Return the size of the immediate operand N. */
9671 imm_size (unsigned int n
)
9674 if (i
.types
[n
].bitfield
.imm64
)
9676 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9678 else if (i
.types
[n
].bitfield
.imm16
)
9684 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9689 for (n
= 0; n
< i
.operands
; n
++)
9691 if (operand_type_check (i
.types
[n
], disp
))
9693 int size
= disp_size (n
);
9695 if (now_seg
== absolute_section
)
9696 abs_section_offset
+= size
;
9697 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9699 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9701 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9703 p
= frag_more (size
);
9704 md_number_to_chars (p
, val
, size
);
9708 enum bfd_reloc_code_real reloc_type
;
9709 int sign
= i
.types
[n
].bitfield
.disp32s
;
9710 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9713 /* We can't have 8 bit displacement here. */
9714 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9716 /* The PC relative address is computed relative
9717 to the instruction boundary, so in case immediate
9718 fields follows, we need to adjust the value. */
9719 if (pcrel
&& i
.imm_operands
)
9724 for (n1
= 0; n1
< i
.operands
; n1
++)
9725 if (operand_type_check (i
.types
[n1
], imm
))
9727 /* Only one immediate is allowed for PC
9728 relative address. */
9729 gas_assert (sz
== 0);
9731 i
.op
[n
].disps
->X_add_number
-= sz
;
9733 /* We should find the immediate. */
9734 gas_assert (sz
!= 0);
9737 p
= frag_more (size
);
9738 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9740 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9741 && (((reloc_type
== BFD_RELOC_32
9742 || reloc_type
== BFD_RELOC_X86_64_32S
9743 || (reloc_type
== BFD_RELOC_64
9745 && (i
.op
[n
].disps
->X_op
== O_symbol
9746 || (i
.op
[n
].disps
->X_op
== O_add
9747 && ((symbol_get_value_expression
9748 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9750 || reloc_type
== BFD_RELOC_32_PCREL
))
9754 reloc_type
= BFD_RELOC_386_GOTPC
;
9755 i
.has_gotpc_tls_reloc
= TRUE
;
9756 i
.op
[n
].imms
->X_add_number
+=
9757 encoding_length (insn_start_frag
, insn_start_off
, p
);
9759 else if (reloc_type
== BFD_RELOC_64
)
9760 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9762 /* Don't do the adjustment for x86-64, as there
9763 the pcrel addressing is relative to the _next_
9764 insn, and that is taken care of in other code. */
9765 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9767 else if (align_branch_power
)
9771 case BFD_RELOC_386_TLS_GD
:
9772 case BFD_RELOC_386_TLS_LDM
:
9773 case BFD_RELOC_386_TLS_IE
:
9774 case BFD_RELOC_386_TLS_IE_32
:
9775 case BFD_RELOC_386_TLS_GOTIE
:
9776 case BFD_RELOC_386_TLS_GOTDESC
:
9777 case BFD_RELOC_386_TLS_DESC_CALL
:
9778 case BFD_RELOC_X86_64_TLSGD
:
9779 case BFD_RELOC_X86_64_TLSLD
:
9780 case BFD_RELOC_X86_64_GOTTPOFF
:
9781 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9782 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9783 i
.has_gotpc_tls_reloc
= TRUE
;
9788 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9789 size
, i
.op
[n
].disps
, pcrel
,
9791 /* Check for "call/jmp *mem", "mov mem, %reg",
9792 "test %reg, mem" and "binop mem, %reg" where binop
9793 is one of adc, add, and, cmp, or, sbb, sub, xor
9794 instructions without data prefix. Always generate
9795 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9796 if (i
.prefix
[DATA_PREFIX
] == 0
9797 && (generate_relax_relocations
9800 && i
.rm
.regmem
== 5))
9802 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9803 && !is_any_vex_encoding(&i
.tm
)
9804 && ((i
.operands
== 1
9805 && i
.tm
.base_opcode
== 0xff
9806 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9808 && (i
.tm
.base_opcode
== 0x8b
9809 || i
.tm
.base_opcode
== 0x85
9810 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9814 fixP
->fx_tcbit
= i
.rex
!= 0;
9816 && (i
.base_reg
->reg_num
== RegIP
))
9817 fixP
->fx_tcbit2
= 1;
9820 fixP
->fx_tcbit2
= 1;
9828 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9833 for (n
= 0; n
< i
.operands
; n
++)
9835 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9836 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9839 if (operand_type_check (i
.types
[n
], imm
))
9841 int size
= imm_size (n
);
9843 if (now_seg
== absolute_section
)
9844 abs_section_offset
+= size
;
9845 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9849 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9851 p
= frag_more (size
);
9852 md_number_to_chars (p
, val
, size
);
9856 /* Not absolute_section.
9857 Need a 32-bit fixup (don't support 8bit
9858 non-absolute imms). Try to support other
9860 enum bfd_reloc_code_real reloc_type
;
9863 if (i
.types
[n
].bitfield
.imm32s
9864 && (i
.suffix
== QWORD_MNEM_SUFFIX
9865 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9870 p
= frag_more (size
);
9871 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9873 /* This is tough to explain. We end up with this one if we
9874 * have operands that look like
9875 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9876 * obtain the absolute address of the GOT, and it is strongly
9877 * preferable from a performance point of view to avoid using
9878 * a runtime relocation for this. The actual sequence of
9879 * instructions often look something like:
9884 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9886 * The call and pop essentially return the absolute address
9887 * of the label .L66 and store it in %ebx. The linker itself
9888 * will ultimately change the first operand of the addl so
9889 * that %ebx points to the GOT, but to keep things simple, the
9890 * .o file must have this operand set so that it generates not
9891 * the absolute address of .L66, but the absolute address of
9892 * itself. This allows the linker itself simply treat a GOTPC
9893 * relocation as asking for a pcrel offset to the GOT to be
9894 * added in, and the addend of the relocation is stored in the
9895 * operand field for the instruction itself.
9897 * Our job here is to fix the operand so that it would add
9898 * the correct offset so that %ebx would point to itself. The
9899 * thing that is tricky is that .-.L66 will point to the
9900 * beginning of the instruction, so we need to further modify
9901 * the operand so that it will point to itself. There are
9902 * other cases where you have something like:
9904 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9906 * and here no correction would be required. Internally in
9907 * the assembler we treat operands of this form as not being
9908 * pcrel since the '.' is explicitly mentioned, and I wonder
9909 * whether it would simplify matters to do it this way. Who
9910 * knows. In earlier versions of the PIC patches, the
9911 * pcrel_adjust field was used to store the correction, but
9912 * since the expression is not pcrel, I felt it would be
9913 * confusing to do it this way. */
9915 if ((reloc_type
== BFD_RELOC_32
9916 || reloc_type
== BFD_RELOC_X86_64_32S
9917 || reloc_type
== BFD_RELOC_64
)
9919 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9920 && (i
.op
[n
].imms
->X_op
== O_symbol
9921 || (i
.op
[n
].imms
->X_op
== O_add
9922 && ((symbol_get_value_expression
9923 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9927 reloc_type
= BFD_RELOC_386_GOTPC
;
9929 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9931 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9932 i
.has_gotpc_tls_reloc
= TRUE
;
9933 i
.op
[n
].imms
->X_add_number
+=
9934 encoding_length (insn_start_frag
, insn_start_off
, p
);
9936 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9937 i
.op
[n
].imms
, 0, reloc_type
);
9943 /* x86_cons_fix_new is called via the expression parsing code when a
9944 reloc is needed. We use this hook to get the correct .got reloc. */
9945 static int cons_sign
= -1;
9948 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9949 expressionS
*exp
, bfd_reloc_code_real_type r
)
9951 r
= reloc (len
, 0, cons_sign
, r
);
9954 if (exp
->X_op
== O_secrel
)
9956 exp
->X_op
= O_symbol
;
9957 r
= BFD_RELOC_32_SECREL
;
9961 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9964 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9965 purpose of the `.dc.a' internal pseudo-op. */
9968 x86_address_bytes (void)
9970 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9972 return stdoutput
->arch_info
->bits_per_address
/ 8;
9975 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9977 # define lex_got(reloc, adjust, types) NULL
9979 /* Parse operands of the form
9980 <symbol>@GOTOFF+<nnn>
9981 and similar .plt or .got references.
9983 If we find one, set up the correct relocation in RELOC and copy the
9984 input string, minus the `@GOTOFF' into a malloc'd buffer for
9985 parsing by the calling routine. Return this buffer, and if ADJUST
9986 is non-null set it to the length of the string we removed from the
9987 input line. Otherwise return NULL. */
9989 lex_got (enum bfd_reloc_code_real
*rel
,
9991 i386_operand_type
*types
)
9993 /* Some of the relocations depend on the size of what field is to
9994 be relocated. But in our callers i386_immediate and i386_displacement
9995 we don't yet know the operand size (this will be set by insn
9996 matching). Hence we record the word32 relocation here,
9997 and adjust the reloc according to the real size in reloc(). */
9998 static const struct {
10001 const enum bfd_reloc_code_real rel
[2];
10002 const i386_operand_type types64
;
10003 bfd_boolean need_GOT_symbol
;
10005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10006 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10007 BFD_RELOC_SIZE32
},
10008 OPERAND_TYPE_IMM32_64
, FALSE
},
10010 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10011 BFD_RELOC_X86_64_PLTOFF64
},
10012 OPERAND_TYPE_IMM64
, TRUE
},
10013 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10014 BFD_RELOC_X86_64_PLT32
},
10015 OPERAND_TYPE_IMM32_32S_DISP32
, FALSE
},
10016 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10017 BFD_RELOC_X86_64_GOTPLT64
},
10018 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10019 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10020 BFD_RELOC_X86_64_GOTOFF64
},
10021 OPERAND_TYPE_IMM64_DISP64
, TRUE
},
10022 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10023 BFD_RELOC_X86_64_GOTPCREL
},
10024 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10025 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10026 BFD_RELOC_X86_64_TLSGD
},
10027 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10028 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10029 _dummy_first_bfd_reloc_code_real
},
10030 OPERAND_TYPE_NONE
, TRUE
},
10031 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10032 BFD_RELOC_X86_64_TLSLD
},
10033 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10034 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10035 BFD_RELOC_X86_64_GOTTPOFF
},
10036 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10037 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10038 BFD_RELOC_X86_64_TPOFF32
},
10039 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10040 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10041 _dummy_first_bfd_reloc_code_real
},
10042 OPERAND_TYPE_NONE
, TRUE
},
10043 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10044 BFD_RELOC_X86_64_DTPOFF32
},
10045 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, TRUE
},
10046 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10047 _dummy_first_bfd_reloc_code_real
},
10048 OPERAND_TYPE_NONE
, TRUE
},
10049 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10050 _dummy_first_bfd_reloc_code_real
},
10051 OPERAND_TYPE_NONE
, TRUE
},
10052 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10053 BFD_RELOC_X86_64_GOT32
},
10054 OPERAND_TYPE_IMM32_32S_64_DISP32
, TRUE
},
10055 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10056 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10057 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10058 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10059 BFD_RELOC_X86_64_TLSDESC_CALL
},
10060 OPERAND_TYPE_IMM32_32S_DISP32
, TRUE
},
10065 #if defined (OBJ_MAYBE_ELF)
10070 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10071 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10074 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10076 int len
= gotrel
[j
].len
;
10077 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10079 if (gotrel
[j
].rel
[object_64bit
] != 0)
10082 char *tmpbuf
, *past_reloc
;
10084 *rel
= gotrel
[j
].rel
[object_64bit
];
10088 if (flag_code
!= CODE_64BIT
)
10090 types
->bitfield
.imm32
= 1;
10091 types
->bitfield
.disp32
= 1;
10094 *types
= gotrel
[j
].types64
;
10097 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10098 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10100 /* The length of the first part of our input line. */
10101 first
= cp
- input_line_pointer
;
10103 /* The second part goes from after the reloc token until
10104 (and including) an end_of_line char or comma. */
10105 past_reloc
= cp
+ 1 + len
;
10107 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10109 second
= cp
+ 1 - past_reloc
;
10111 /* Allocate and copy string. The trailing NUL shouldn't
10112 be necessary, but be safe. */
10113 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10114 memcpy (tmpbuf
, input_line_pointer
, first
);
10115 if (second
!= 0 && *past_reloc
!= ' ')
10116 /* Replace the relocation token with ' ', so that
10117 errors like foo@GOTOFF1 will be detected. */
10118 tmpbuf
[first
++] = ' ';
10120 /* Increment length by 1 if the relocation token is
10125 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10126 tmpbuf
[first
+ second
] = '\0';
10130 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10131 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10136 /* Might be a symbol version string. Don't as_bad here. */
10145 /* Parse operands of the form
10146 <symbol>@SECREL32+<nnn>
10148 If we find one, set up the correct relocation in RELOC and copy the
10149 input string, minus the `@SECREL32' into a malloc'd buffer for
10150 parsing by the calling routine. Return this buffer, and if ADJUST
10151 is non-null set it to the length of the string we removed from the
10152 input line. Otherwise return NULL.
10154 This function is copied from the ELF version above adjusted for PE targets. */
10157 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10158 int *adjust ATTRIBUTE_UNUSED
,
10159 i386_operand_type
*types
)
10161 static const struct
10165 const enum bfd_reloc_code_real rel
[2];
10166 const i386_operand_type types64
;
10170 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10171 BFD_RELOC_32_SECREL
},
10172 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10178 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10179 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10182 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10184 int len
= gotrel
[j
].len
;
10186 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10188 if (gotrel
[j
].rel
[object_64bit
] != 0)
10191 char *tmpbuf
, *past_reloc
;
10193 *rel
= gotrel
[j
].rel
[object_64bit
];
10199 if (flag_code
!= CODE_64BIT
)
10201 types
->bitfield
.imm32
= 1;
10202 types
->bitfield
.disp32
= 1;
10205 *types
= gotrel
[j
].types64
;
10208 /* The length of the first part of our input line. */
10209 first
= cp
- input_line_pointer
;
10211 /* The second part goes from after the reloc token until
10212 (and including) an end_of_line char or comma. */
10213 past_reloc
= cp
+ 1 + len
;
10215 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10217 second
= cp
+ 1 - past_reloc
;
10219 /* Allocate and copy string. The trailing NUL shouldn't
10220 be necessary, but be safe. */
10221 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10222 memcpy (tmpbuf
, input_line_pointer
, first
);
10223 if (second
!= 0 && *past_reloc
!= ' ')
10224 /* Replace the relocation token with ' ', so that
10225 errors like foo@SECLREL321 will be detected. */
10226 tmpbuf
[first
++] = ' ';
10227 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10228 tmpbuf
[first
+ second
] = '\0';
10232 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10233 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10238 /* Might be a symbol version string. Don't as_bad here. */
10244 bfd_reloc_code_real_type
10245 x86_cons (expressionS
*exp
, int size
)
10247 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10249 intel_syntax
= -intel_syntax
;
10252 if (size
== 4 || (object_64bit
&& size
== 8))
10254 /* Handle @GOTOFF and the like in an expression. */
10256 char *gotfree_input_line
;
10259 save
= input_line_pointer
;
10260 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10261 if (gotfree_input_line
)
10262 input_line_pointer
= gotfree_input_line
;
10266 if (gotfree_input_line
)
10268 /* expression () has merrily parsed up to the end of line,
10269 or a comma - in the wrong buffer. Transfer how far
10270 input_line_pointer has moved to the right buffer. */
10271 input_line_pointer
= (save
10272 + (input_line_pointer
- gotfree_input_line
)
10274 free (gotfree_input_line
);
10275 if (exp
->X_op
== O_constant
10276 || exp
->X_op
== O_absent
10277 || exp
->X_op
== O_illegal
10278 || exp
->X_op
== O_register
10279 || exp
->X_op
== O_big
)
10281 char c
= *input_line_pointer
;
10282 *input_line_pointer
= 0;
10283 as_bad (_("missing or invalid expression `%s'"), save
);
10284 *input_line_pointer
= c
;
10286 else if ((got_reloc
== BFD_RELOC_386_PLT32
10287 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10288 && exp
->X_op
!= O_symbol
)
10290 char c
= *input_line_pointer
;
10291 *input_line_pointer
= 0;
10292 as_bad (_("invalid PLT expression `%s'"), save
);
10293 *input_line_pointer
= c
;
10300 intel_syntax
= -intel_syntax
;
10303 i386_intel_simplify (exp
);
10309 signed_cons (int size
)
10311 if (flag_code
== CODE_64BIT
)
10319 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10326 if (exp
.X_op
== O_symbol
)
10327 exp
.X_op
= O_secrel
;
10329 emit_expr (&exp
, 4);
10331 while (*input_line_pointer
++ == ',');
10333 input_line_pointer
--;
10334 demand_empty_rest_of_line ();
10338 /* Handle Vector operations. */
10341 check_VecOperations (char *op_string
, char *op_end
)
10343 const reg_entry
*mask
;
10348 && (op_end
== NULL
|| op_string
< op_end
))
10351 if (*op_string
== '{')
10355 /* Check broadcasts. */
10356 if (strncmp (op_string
, "1to", 3) == 0)
10361 goto duplicated_vec_op
;
10364 if (*op_string
== '8')
10366 else if (*op_string
== '4')
10368 else if (*op_string
== '2')
10370 else if (*op_string
== '1'
10371 && *(op_string
+1) == '6')
10378 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10383 broadcast_op
.type
= bcst_type
;
10384 broadcast_op
.operand
= this_operand
;
10385 broadcast_op
.bytes
= 0;
10386 i
.broadcast
= &broadcast_op
;
10388 /* Check masking operation. */
10389 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10391 if (mask
== &bad_reg
)
10394 /* k0 can't be used for write mask. */
10395 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10397 as_bad (_("`%s%s' can't be used for write mask"),
10398 register_prefix
, mask
->reg_name
);
10404 mask_op
.mask
= mask
;
10405 mask_op
.zeroing
= 0;
10406 mask_op
.operand
= this_operand
;
10412 goto duplicated_vec_op
;
10414 i
.mask
->mask
= mask
;
10416 /* Only "{z}" is allowed here. No need to check
10417 zeroing mask explicitly. */
10418 if (i
.mask
->operand
!= this_operand
)
10420 as_bad (_("invalid write mask `%s'"), saved
);
10425 op_string
= end_op
;
10427 /* Check zeroing-flag for masking operation. */
10428 else if (*op_string
== 'z')
10432 mask_op
.mask
= NULL
;
10433 mask_op
.zeroing
= 1;
10434 mask_op
.operand
= this_operand
;
10439 if (i
.mask
->zeroing
)
10442 as_bad (_("duplicated `%s'"), saved
);
10446 i
.mask
->zeroing
= 1;
10448 /* Only "{%k}" is allowed here. No need to check mask
10449 register explicitly. */
10450 if (i
.mask
->operand
!= this_operand
)
10452 as_bad (_("invalid zeroing-masking `%s'"),
10461 goto unknown_vec_op
;
10463 if (*op_string
!= '}')
10465 as_bad (_("missing `}' in `%s'"), saved
);
10470 /* Strip whitespace since the addition of pseudo prefixes
10471 changed how the scrubber treats '{'. */
10472 if (is_space_char (*op_string
))
10478 /* We don't know this one. */
10479 as_bad (_("unknown vector operation: `%s'"), saved
);
10483 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10485 as_bad (_("zeroing-masking only allowed with write mask"));
10493 i386_immediate (char *imm_start
)
10495 char *save_input_line_pointer
;
10496 char *gotfree_input_line
;
10499 i386_operand_type types
;
10501 operand_type_set (&types
, ~0);
10503 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10505 as_bad (_("at most %d immediate operands are allowed"),
10506 MAX_IMMEDIATE_OPERANDS
);
10510 exp
= &im_expressions
[i
.imm_operands
++];
10511 i
.op
[this_operand
].imms
= exp
;
10513 if (is_space_char (*imm_start
))
10516 save_input_line_pointer
= input_line_pointer
;
10517 input_line_pointer
= imm_start
;
10519 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10520 if (gotfree_input_line
)
10521 input_line_pointer
= gotfree_input_line
;
10523 exp_seg
= expression (exp
);
10525 SKIP_WHITESPACE ();
10527 /* Handle vector operations. */
10528 if (*input_line_pointer
== '{')
10530 input_line_pointer
= check_VecOperations (input_line_pointer
,
10532 if (input_line_pointer
== NULL
)
10536 if (*input_line_pointer
)
10537 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10539 input_line_pointer
= save_input_line_pointer
;
10540 if (gotfree_input_line
)
10542 free (gotfree_input_line
);
10544 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10545 exp
->X_op
= O_illegal
;
10548 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10552 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10553 i386_operand_type types
, const char *imm_start
)
10555 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10558 as_bad (_("missing or invalid immediate expression `%s'"),
10562 else if (exp
->X_op
== O_constant
)
10564 /* Size it properly later. */
10565 i
.types
[this_operand
].bitfield
.imm64
= 1;
10566 /* If not 64bit, sign extend val. */
10567 if (flag_code
!= CODE_64BIT
10568 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10570 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10572 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10573 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10574 && exp_seg
!= absolute_section
10575 && exp_seg
!= text_section
10576 && exp_seg
!= data_section
10577 && exp_seg
!= bss_section
10578 && exp_seg
!= undefined_section
10579 && !bfd_is_com_section (exp_seg
))
10581 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10585 else if (!intel_syntax
&& exp_seg
== reg_section
)
10588 as_bad (_("illegal immediate register operand %s"), imm_start
);
10593 /* This is an address. The size of the address will be
10594 determined later, depending on destination register,
10595 suffix, or the default for the section. */
10596 i
.types
[this_operand
].bitfield
.imm8
= 1;
10597 i
.types
[this_operand
].bitfield
.imm16
= 1;
10598 i
.types
[this_operand
].bitfield
.imm32
= 1;
10599 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10600 i
.types
[this_operand
].bitfield
.imm64
= 1;
10601 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10609 i386_scale (char *scale
)
10612 char *save
= input_line_pointer
;
10614 input_line_pointer
= scale
;
10615 val
= get_absolute_expression ();
10620 i
.log2_scale_factor
= 0;
10623 i
.log2_scale_factor
= 1;
10626 i
.log2_scale_factor
= 2;
10629 i
.log2_scale_factor
= 3;
10633 char sep
= *input_line_pointer
;
10635 *input_line_pointer
= '\0';
10636 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10638 *input_line_pointer
= sep
;
10639 input_line_pointer
= save
;
10643 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10645 as_warn (_("scale factor of %d without an index register"),
10646 1 << i
.log2_scale_factor
);
10647 i
.log2_scale_factor
= 0;
10649 scale
= input_line_pointer
;
10650 input_line_pointer
= save
;
10655 i386_displacement (char *disp_start
, char *disp_end
)
10659 char *save_input_line_pointer
;
10660 char *gotfree_input_line
;
10662 i386_operand_type bigdisp
, types
= anydisp
;
10665 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10667 as_bad (_("at most %d displacement operands are allowed"),
10668 MAX_MEMORY_OPERANDS
);
10672 operand_type_set (&bigdisp
, 0);
10674 || i
.types
[this_operand
].bitfield
.baseindex
10675 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10676 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10678 i386_addressing_mode ();
10679 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10680 if (flag_code
== CODE_64BIT
)
10684 bigdisp
.bitfield
.disp32s
= 1;
10685 bigdisp
.bitfield
.disp64
= 1;
10688 bigdisp
.bitfield
.disp32
= 1;
10690 else if ((flag_code
== CODE_16BIT
) ^ override
)
10691 bigdisp
.bitfield
.disp16
= 1;
10693 bigdisp
.bitfield
.disp32
= 1;
10697 /* For PC-relative branches, the width of the displacement may be
10698 dependent upon data size, but is never dependent upon address size.
10699 Also make sure to not unintentionally match against a non-PC-relative
10700 branch template. */
10701 static templates aux_templates
;
10702 const insn_template
*t
= current_templates
->start
;
10703 bfd_boolean has_intel64
= FALSE
;
10705 aux_templates
.start
= t
;
10706 while (++t
< current_templates
->end
)
10708 if (t
->opcode_modifier
.jump
10709 != current_templates
->start
->opcode_modifier
.jump
)
10711 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10712 has_intel64
= TRUE
;
10714 if (t
< current_templates
->end
)
10716 aux_templates
.end
= t
;
10717 current_templates
= &aux_templates
;
10720 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10721 if (flag_code
== CODE_64BIT
)
10723 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10724 && (!intel64
|| !has_intel64
))
10725 bigdisp
.bitfield
.disp16
= 1;
10727 bigdisp
.bitfield
.disp32s
= 1;
10732 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10734 : LONG_MNEM_SUFFIX
));
10735 bigdisp
.bitfield
.disp32
= 1;
10736 if ((flag_code
== CODE_16BIT
) ^ override
)
10738 bigdisp
.bitfield
.disp32
= 0;
10739 bigdisp
.bitfield
.disp16
= 1;
10743 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10746 exp
= &disp_expressions
[i
.disp_operands
];
10747 i
.op
[this_operand
].disps
= exp
;
10749 save_input_line_pointer
= input_line_pointer
;
10750 input_line_pointer
= disp_start
;
10751 END_STRING_AND_SAVE (disp_end
);
10753 #ifndef GCC_ASM_O_HACK
10754 #define GCC_ASM_O_HACK 0
10757 END_STRING_AND_SAVE (disp_end
+ 1);
10758 if (i
.types
[this_operand
].bitfield
.baseIndex
10759 && displacement_string_end
[-1] == '+')
10761 /* This hack is to avoid a warning when using the "o"
10762 constraint within gcc asm statements.
10765 #define _set_tssldt_desc(n,addr,limit,type) \
10766 __asm__ __volatile__ ( \
10767 "movw %w2,%0\n\t" \
10768 "movw %w1,2+%0\n\t" \
10769 "rorl $16,%1\n\t" \
10770 "movb %b1,4+%0\n\t" \
10771 "movb %4,5+%0\n\t" \
10772 "movb $0,6+%0\n\t" \
10773 "movb %h1,7+%0\n\t" \
10775 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10777 This works great except that the output assembler ends
10778 up looking a bit weird if it turns out that there is
10779 no offset. You end up producing code that looks like:
10792 So here we provide the missing zero. */
10794 *displacement_string_end
= '0';
10797 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10798 if (gotfree_input_line
)
10799 input_line_pointer
= gotfree_input_line
;
10801 exp_seg
= expression (exp
);
10803 SKIP_WHITESPACE ();
10804 if (*input_line_pointer
)
10805 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10807 RESTORE_END_STRING (disp_end
+ 1);
10809 input_line_pointer
= save_input_line_pointer
;
10810 if (gotfree_input_line
)
10812 free (gotfree_input_line
);
10814 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10815 exp
->X_op
= O_illegal
;
10818 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10820 RESTORE_END_STRING (disp_end
);
10826 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10827 i386_operand_type types
, const char *disp_start
)
10829 i386_operand_type bigdisp
;
10832 /* We do this to make sure that the section symbol is in
10833 the symbol table. We will ultimately change the relocation
10834 to be relative to the beginning of the section. */
10835 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10836 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10837 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10839 if (exp
->X_op
!= O_symbol
)
10842 if (S_IS_LOCAL (exp
->X_add_symbol
)
10843 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10844 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10845 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10846 exp
->X_op
= O_subtract
;
10847 exp
->X_op_symbol
= GOT_symbol
;
10848 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10849 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10850 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10851 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10853 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10856 else if (exp
->X_op
== O_absent
10857 || exp
->X_op
== O_illegal
10858 || exp
->X_op
== O_big
)
10861 as_bad (_("missing or invalid displacement expression `%s'"),
10866 else if (flag_code
== CODE_64BIT
10867 && !i
.prefix
[ADDR_PREFIX
]
10868 && exp
->X_op
== O_constant
)
10870 /* Since displacement is signed extended to 64bit, don't allow
10871 disp32 and turn off disp32s if they are out of range. */
10872 i
.types
[this_operand
].bitfield
.disp32
= 0;
10873 if (!fits_in_signed_long (exp
->X_add_number
))
10875 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10876 if (i
.types
[this_operand
].bitfield
.baseindex
)
10878 as_bad (_("0x%lx out range of signed 32bit displacement"),
10879 (long) exp
->X_add_number
);
10885 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10886 else if (exp
->X_op
!= O_constant
10887 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10888 && exp_seg
!= absolute_section
10889 && exp_seg
!= text_section
10890 && exp_seg
!= data_section
10891 && exp_seg
!= bss_section
10892 && exp_seg
!= undefined_section
10893 && !bfd_is_com_section (exp_seg
))
10895 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10900 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10901 /* Constants get taken care of by optimize_disp(). */
10902 && exp
->X_op
!= O_constant
)
10903 i
.types
[this_operand
].bitfield
.disp8
= 1;
10905 /* Check if this is a displacement only operand. */
10906 bigdisp
= i
.types
[this_operand
];
10907 bigdisp
.bitfield
.disp8
= 0;
10908 bigdisp
.bitfield
.disp16
= 0;
10909 bigdisp
.bitfield
.disp32
= 0;
10910 bigdisp
.bitfield
.disp32s
= 0;
10911 bigdisp
.bitfield
.disp64
= 0;
10912 if (operand_type_all_zero (&bigdisp
))
10913 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10919 /* Return the active addressing mode, taking address override and
10920 registers forming the address into consideration. Update the
10921 address override prefix if necessary. */
10923 static enum flag_code
10924 i386_addressing_mode (void)
10926 enum flag_code addr_mode
;
10928 if (i
.prefix
[ADDR_PREFIX
])
10929 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10930 else if (flag_code
== CODE_16BIT
10931 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10932 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10933 from md_assemble() by "is not a valid base/index expression"
10934 when there is a base and/or index. */
10935 && !i
.types
[this_operand
].bitfield
.baseindex
)
10937 /* MPX insn memory operands with neither base nor index must be forced
10938 to use 32-bit addressing in 16-bit mode. */
10939 addr_mode
= CODE_32BIT
;
10940 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10942 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10943 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10947 addr_mode
= flag_code
;
10949 #if INFER_ADDR_PREFIX
10950 if (i
.mem_operands
== 0)
10952 /* Infer address prefix from the first memory operand. */
10953 const reg_entry
*addr_reg
= i
.base_reg
;
10955 if (addr_reg
== NULL
)
10956 addr_reg
= i
.index_reg
;
10960 if (addr_reg
->reg_type
.bitfield
.dword
)
10961 addr_mode
= CODE_32BIT
;
10962 else if (flag_code
!= CODE_64BIT
10963 && addr_reg
->reg_type
.bitfield
.word
)
10964 addr_mode
= CODE_16BIT
;
10966 if (addr_mode
!= flag_code
)
10968 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10970 /* Change the size of any displacement too. At most one
10971 of Disp16 or Disp32 is set.
10972 FIXME. There doesn't seem to be any real need for
10973 separate Disp16 and Disp32 flags. The same goes for
10974 Imm16 and Imm32. Removing them would probably clean
10975 up the code quite a lot. */
10976 if (flag_code
!= CODE_64BIT
10977 && (i
.types
[this_operand
].bitfield
.disp16
10978 || i
.types
[this_operand
].bitfield
.disp32
))
10979 i
.types
[this_operand
]
10980 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10990 /* Make sure the memory operand we've been dealt is valid.
10991 Return 1 on success, 0 on a failure. */
10994 i386_index_check (const char *operand_string
)
10996 const char *kind
= "base/index";
10997 enum flag_code addr_mode
= i386_addressing_mode ();
10998 const insn_template
*t
= current_templates
->start
;
11000 if (t
->opcode_modifier
.isstring
11001 && !t
->cpu_flags
.bitfield
.cpupadlock
11002 && (current_templates
->end
[-1].opcode_modifier
.isstring
11003 || i
.mem_operands
))
11005 /* Memory operands of string insns are special in that they only allow
11006 a single register (rDI, rSI, or rBX) as their memory address. */
11007 const reg_entry
*expected_reg
;
11008 static const char *di_si
[][2] =
11014 static const char *bx
[] = { "ebx", "bx", "rbx" };
11016 kind
= "string address";
11018 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
11020 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
11021 - IS_STRING_ES_OP0
;
11024 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
11025 || ((!i
.mem_operands
!= !intel_syntax
)
11026 && current_templates
->end
[-1].operand_types
[1]
11027 .bitfield
.baseindex
))
11030 = (const reg_entry
*) str_hash_find (reg_hash
,
11031 di_si
[addr_mode
][op
== es_op
]);
11035 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
11037 if (i
.base_reg
!= expected_reg
11039 || operand_type_check (i
.types
[this_operand
], disp
))
11041 /* The second memory operand must have the same size as
11045 && !((addr_mode
== CODE_64BIT
11046 && i
.base_reg
->reg_type
.bitfield
.qword
)
11047 || (addr_mode
== CODE_32BIT
11048 ? i
.base_reg
->reg_type
.bitfield
.dword
11049 : i
.base_reg
->reg_type
.bitfield
.word
)))
11052 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11054 intel_syntax
? '[' : '(',
11056 expected_reg
->reg_name
,
11057 intel_syntax
? ']' : ')');
11064 as_bad (_("`%s' is not a valid %s expression"),
11065 operand_string
, kind
);
11070 if (addr_mode
!= CODE_16BIT
)
11072 /* 32-bit/64-bit checks. */
11073 if (i
.disp_encoding
== disp_encoding_16bit
)
11076 as_bad (_("invalid `%s' prefix"),
11077 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11082 && ((addr_mode
== CODE_64BIT
11083 ? !i
.base_reg
->reg_type
.bitfield
.qword
11084 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11085 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11086 || i
.base_reg
->reg_num
== RegIZ
))
11088 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11089 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11090 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11091 && ((addr_mode
== CODE_64BIT
11092 ? !i
.index_reg
->reg_type
.bitfield
.qword
11093 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11094 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11097 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11098 if ((t
->opcode_modifier
.opcodeprefix
== PREFIX_0XF3
11099 && t
->base_opcode
== 0x0f1b)
11100 || (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11101 && (t
->base_opcode
& ~1) == 0x0f1a)
11102 || t
->opcode_modifier
.sib
== SIBMEM
)
11104 /* They cannot use RIP-relative addressing. */
11105 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11107 as_bad (_("`%s' cannot be used here"), operand_string
);
11111 /* bndldx and bndstx ignore their scale factor. */
11112 if (t
->opcode_modifier
.opcodeprefix
== PREFIX_NONE
11113 && (t
->base_opcode
& ~1) == 0x0f1a
11114 && i
.log2_scale_factor
)
11115 as_warn (_("register scaling is being ignored here"));
11120 /* 16-bit checks. */
11121 if (i
.disp_encoding
== disp_encoding_32bit
)
11125 && (!i
.base_reg
->reg_type
.bitfield
.word
11126 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11128 && (!i
.index_reg
->reg_type
.bitfield
.word
11129 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11131 && i
.base_reg
->reg_num
< 6
11132 && i
.index_reg
->reg_num
>= 6
11133 && i
.log2_scale_factor
== 0))))
11140 /* Handle vector immediates. */
11143 RC_SAE_immediate (const char *imm_start
)
11145 unsigned int match_found
, j
;
11146 const char *pstr
= imm_start
;
11154 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11156 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11160 rc_op
.type
= RC_NamesTable
[j
].type
;
11161 rc_op
.operand
= this_operand
;
11162 i
.rounding
= &rc_op
;
11166 as_bad (_("duplicated `%s'"), imm_start
);
11169 pstr
+= RC_NamesTable
[j
].len
;
11177 if (*pstr
++ != '}')
11179 as_bad (_("Missing '}': '%s'"), imm_start
);
11182 /* RC/SAE immediate string should contain nothing more. */;
11185 as_bad (_("Junk after '}': '%s'"), imm_start
);
11189 exp
= &im_expressions
[i
.imm_operands
++];
11190 i
.op
[this_operand
].imms
= exp
;
11192 exp
->X_op
= O_constant
;
11193 exp
->X_add_number
= 0;
11194 exp
->X_add_symbol
= (symbolS
*) 0;
11195 exp
->X_op_symbol
= (symbolS
*) 0;
11197 i
.types
[this_operand
].bitfield
.imm8
= 1;
11201 /* Only string instructions can have a second memory operand, so
11202 reduce current_templates to just those if it contains any. */
11204 maybe_adjust_templates (void)
11206 const insn_template
*t
;
11208 gas_assert (i
.mem_operands
== 1);
11210 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11211 if (t
->opcode_modifier
.isstring
)
11214 if (t
< current_templates
->end
)
11216 static templates aux_templates
;
11217 bfd_boolean recheck
;
11219 aux_templates
.start
= t
;
11220 for (; t
< current_templates
->end
; ++t
)
11221 if (!t
->opcode_modifier
.isstring
)
11223 aux_templates
.end
= t
;
11225 /* Determine whether to re-check the first memory operand. */
11226 recheck
= (aux_templates
.start
!= current_templates
->start
11227 || t
!= current_templates
->end
);
11229 current_templates
= &aux_templates
;
11233 i
.mem_operands
= 0;
11234 if (i
.memop1_string
!= NULL
11235 && i386_index_check (i
.memop1_string
) == 0)
11237 i
.mem_operands
= 1;
11244 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11248 i386_att_operand (char *operand_string
)
11250 const reg_entry
*r
;
11252 char *op_string
= operand_string
;
11254 if (is_space_char (*op_string
))
11257 /* We check for an absolute prefix (differentiating,
11258 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11259 if (*op_string
== ABSOLUTE_PREFIX
)
11262 if (is_space_char (*op_string
))
11264 i
.jumpabsolute
= TRUE
;
11267 /* Check if operand is a register. */
11268 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11270 i386_operand_type temp
;
11275 /* Check for a segment override by searching for ':' after a
11276 segment register. */
11277 op_string
= end_op
;
11278 if (is_space_char (*op_string
))
11280 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11282 switch (r
->reg_num
)
11285 i
.seg
[i
.mem_operands
] = &es
;
11288 i
.seg
[i
.mem_operands
] = &cs
;
11291 i
.seg
[i
.mem_operands
] = &ss
;
11294 i
.seg
[i
.mem_operands
] = &ds
;
11297 i
.seg
[i
.mem_operands
] = &fs
;
11300 i
.seg
[i
.mem_operands
] = &gs
;
11304 /* Skip the ':' and whitespace. */
11306 if (is_space_char (*op_string
))
11309 if (!is_digit_char (*op_string
)
11310 && !is_identifier_char (*op_string
)
11311 && *op_string
!= '('
11312 && *op_string
!= ABSOLUTE_PREFIX
)
11314 as_bad (_("bad memory operand `%s'"), op_string
);
11317 /* Handle case of %es:*foo. */
11318 if (*op_string
== ABSOLUTE_PREFIX
)
11321 if (is_space_char (*op_string
))
11323 i
.jumpabsolute
= TRUE
;
11325 goto do_memory_reference
;
11328 /* Handle vector operations. */
11329 if (*op_string
== '{')
11331 op_string
= check_VecOperations (op_string
, NULL
);
11332 if (op_string
== NULL
)
11338 as_bad (_("junk `%s' after register"), op_string
);
11341 temp
= r
->reg_type
;
11342 temp
.bitfield
.baseindex
= 0;
11343 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11345 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11346 i
.op
[this_operand
].regs
= r
;
11349 else if (*op_string
== REGISTER_PREFIX
)
11351 as_bad (_("bad register name `%s'"), op_string
);
11354 else if (*op_string
== IMMEDIATE_PREFIX
)
11357 if (i
.jumpabsolute
)
11359 as_bad (_("immediate operand illegal with absolute jump"));
11362 if (!i386_immediate (op_string
))
11365 else if (RC_SAE_immediate (operand_string
))
11367 /* If it is a RC or SAE immediate, do nothing. */
11370 else if (is_digit_char (*op_string
)
11371 || is_identifier_char (*op_string
)
11372 || *op_string
== '"'
11373 || *op_string
== '(')
11375 /* This is a memory reference of some sort. */
11378 /* Start and end of displacement string expression (if found). */
11379 char *displacement_string_start
;
11380 char *displacement_string_end
;
11383 do_memory_reference
:
11384 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11386 if ((i
.mem_operands
== 1
11387 && !current_templates
->start
->opcode_modifier
.isstring
)
11388 || i
.mem_operands
== 2)
11390 as_bad (_("too many memory references for `%s'"),
11391 current_templates
->start
->name
);
11395 /* Check for base index form. We detect the base index form by
11396 looking for an ')' at the end of the operand, searching
11397 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11399 base_string
= op_string
+ strlen (op_string
);
11401 /* Handle vector operations. */
11402 vop_start
= strchr (op_string
, '{');
11403 if (vop_start
&& vop_start
< base_string
)
11405 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11407 base_string
= vop_start
;
11411 if (is_space_char (*base_string
))
11414 /* If we only have a displacement, set-up for it to be parsed later. */
11415 displacement_string_start
= op_string
;
11416 displacement_string_end
= base_string
+ 1;
11418 if (*base_string
== ')')
11421 unsigned int parens_balanced
= 1;
11422 /* We've already checked that the number of left & right ()'s are
11423 equal, so this loop will not be infinite. */
11427 if (*base_string
== ')')
11429 if (*base_string
== '(')
11432 while (parens_balanced
);
11434 temp_string
= base_string
;
11436 /* Skip past '(' and whitespace. */
11438 if (is_space_char (*base_string
))
11441 if (*base_string
== ','
11442 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11445 displacement_string_end
= temp_string
;
11447 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11451 if (i
.base_reg
== &bad_reg
)
11453 base_string
= end_op
;
11454 if (is_space_char (*base_string
))
11458 /* There may be an index reg or scale factor here. */
11459 if (*base_string
== ',')
11462 if (is_space_char (*base_string
))
11465 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11468 if (i
.index_reg
== &bad_reg
)
11470 base_string
= end_op
;
11471 if (is_space_char (*base_string
))
11473 if (*base_string
== ',')
11476 if (is_space_char (*base_string
))
11479 else if (*base_string
!= ')')
11481 as_bad (_("expecting `,' or `)' "
11482 "after index register in `%s'"),
11487 else if (*base_string
== REGISTER_PREFIX
)
11489 end_op
= strchr (base_string
, ',');
11492 as_bad (_("bad register name `%s'"), base_string
);
11496 /* Check for scale factor. */
11497 if (*base_string
!= ')')
11499 char *end_scale
= i386_scale (base_string
);
11504 base_string
= end_scale
;
11505 if (is_space_char (*base_string
))
11507 if (*base_string
!= ')')
11509 as_bad (_("expecting `)' "
11510 "after scale factor in `%s'"),
11515 else if (!i
.index_reg
)
11517 as_bad (_("expecting index register or scale factor "
11518 "after `,'; got '%c'"),
11523 else if (*base_string
!= ')')
11525 as_bad (_("expecting `,' or `)' "
11526 "after base register in `%s'"),
11531 else if (*base_string
== REGISTER_PREFIX
)
11533 end_op
= strchr (base_string
, ',');
11536 as_bad (_("bad register name `%s'"), base_string
);
11541 /* If there's an expression beginning the operand, parse it,
11542 assuming displacement_string_start and
11543 displacement_string_end are meaningful. */
11544 if (displacement_string_start
!= displacement_string_end
)
11546 if (!i386_displacement (displacement_string_start
,
11547 displacement_string_end
))
11551 /* Special case for (%dx) while doing input/output op. */
11553 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11554 && i
.base_reg
->reg_type
.bitfield
.word
11555 && i
.index_reg
== 0
11556 && i
.log2_scale_factor
== 0
11557 && i
.seg
[i
.mem_operands
] == 0
11558 && !operand_type_check (i
.types
[this_operand
], disp
))
11560 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11564 if (i386_index_check (operand_string
) == 0)
11566 i
.flags
[this_operand
] |= Operand_Mem
;
11567 if (i
.mem_operands
== 0)
11568 i
.memop1_string
= xstrdup (operand_string
);
11573 /* It's not a memory operand; argh! */
11574 as_bad (_("invalid char %s beginning operand %d `%s'"),
11575 output_invalid (*op_string
),
11580 return 1; /* Normal return. */
11583 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11584 that an rs_machine_dependent frag may reach. */
11587 i386_frag_max_var (fragS
*frag
)
11589 /* The only relaxable frags are for jumps.
11590 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11591 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11592 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11595 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11597 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11599 /* STT_GNU_IFUNC symbol must go through PLT. */
11600 if ((symbol_get_bfdsym (fr_symbol
)->flags
11601 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11604 if (!S_IS_EXTERNAL (fr_symbol
))
11605 /* Symbol may be weak or local. */
11606 return !S_IS_WEAK (fr_symbol
);
11608 /* Global symbols with non-default visibility can't be preempted. */
11609 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11612 if (fr_var
!= NO_RELOC
)
11613 switch ((enum bfd_reloc_code_real
) fr_var
)
11615 case BFD_RELOC_386_PLT32
:
11616 case BFD_RELOC_X86_64_PLT32
:
11617 /* Symbol with PLT relocation may be preempted. */
11623 /* Global symbols with default visibility in a shared library may be
11624 preempted by another definition. */
11629 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11630 Note also work for Skylake and Cascadelake.
11631 ---------------------------------------------------------------------
11632 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11633 | ------ | ----------- | ------- | -------- |
11635 | Jno | N | N | Y |
11636 | Jc/Jb | Y | N | Y |
11637 | Jae/Jnb | Y | N | Y |
11638 | Je/Jz | Y | Y | Y |
11639 | Jne/Jnz | Y | Y | Y |
11640 | Jna/Jbe | Y | N | Y |
11641 | Ja/Jnbe | Y | N | Y |
11643 | Jns | N | N | Y |
11644 | Jp/Jpe | N | N | Y |
11645 | Jnp/Jpo | N | N | Y |
11646 | Jl/Jnge | Y | Y | Y |
11647 | Jge/Jnl | Y | Y | Y |
11648 | Jle/Jng | Y | Y | Y |
11649 | Jg/Jnle | Y | Y | Y |
11650 --------------------------------------------------------------------- */
11652 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11654 if (mf_cmp
== mf_cmp_alu_cmp
)
11655 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11656 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11657 if (mf_cmp
== mf_cmp_incdec
)
11658 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11659 || mf_jcc
== mf_jcc_jle
);
11660 if (mf_cmp
== mf_cmp_test_and
)
11665 /* Return the next non-empty frag. */
11668 i386_next_non_empty_frag (fragS
*fragP
)
11670 /* There may be a frag with a ".fill 0" when there is no room in
11671 the current frag for frag_grow in output_insn. */
11672 for (fragP
= fragP
->fr_next
;
11674 && fragP
->fr_type
== rs_fill
11675 && fragP
->fr_fix
== 0);
11676 fragP
= fragP
->fr_next
)
11681 /* Return the next jcc frag after BRANCH_PADDING. */
11684 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11686 fragS
*branch_fragP
;
11690 if (pad_fragP
->fr_type
== rs_machine_dependent
11691 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11692 == BRANCH_PADDING
))
11694 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11695 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11697 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11698 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11699 pad_fragP
->tc_frag_data
.mf_type
))
11700 return branch_fragP
;
11706 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11709 i386_classify_machine_dependent_frag (fragS
*fragP
)
11713 fragS
*branch_fragP
;
11715 unsigned int max_prefix_length
;
11717 if (fragP
->tc_frag_data
.classified
)
11720 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11721 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11722 for (next_fragP
= fragP
;
11723 next_fragP
!= NULL
;
11724 next_fragP
= next_fragP
->fr_next
)
11726 next_fragP
->tc_frag_data
.classified
= 1;
11727 if (next_fragP
->fr_type
== rs_machine_dependent
)
11728 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11730 case BRANCH_PADDING
:
11731 /* The BRANCH_PADDING frag must be followed by a branch
11733 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11734 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11736 case FUSED_JCC_PADDING
:
11737 /* Check if this is a fused jcc:
11739 CMP like instruction
11743 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11744 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11745 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11748 /* The BRANCH_PADDING frag is merged with the
11749 FUSED_JCC_PADDING frag. */
11750 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11751 /* CMP like instruction size. */
11752 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11753 frag_wane (pad_fragP
);
11754 /* Skip to branch_fragP. */
11755 next_fragP
= branch_fragP
;
11757 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11759 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11761 next_fragP
->fr_subtype
11762 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11763 next_fragP
->tc_frag_data
.max_bytes
11764 = next_fragP
->tc_frag_data
.max_prefix_length
;
11765 /* This will be updated in the BRANCH_PREFIX scan. */
11766 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11769 frag_wane (next_fragP
);
11774 /* Stop if there is no BRANCH_PREFIX. */
11775 if (!align_branch_prefix_size
)
11778 /* Scan for BRANCH_PREFIX. */
11779 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11781 if (fragP
->fr_type
!= rs_machine_dependent
11782 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11786 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11787 COND_JUMP_PREFIX. */
11788 max_prefix_length
= 0;
11789 for (next_fragP
= fragP
;
11790 next_fragP
!= NULL
;
11791 next_fragP
= next_fragP
->fr_next
)
11793 if (next_fragP
->fr_type
== rs_fill
)
11794 /* Skip rs_fill frags. */
11796 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11797 /* Stop for all other frags. */
11800 /* rs_machine_dependent frags. */
11801 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11804 /* Count BRANCH_PREFIX frags. */
11805 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11807 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11808 frag_wane (next_fragP
);
11812 += next_fragP
->tc_frag_data
.max_bytes
;
11814 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11816 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11817 == FUSED_JCC_PADDING
))
11819 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11820 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11824 /* Stop for other rs_machine_dependent frags. */
11828 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11830 /* Skip to the next frag. */
11831 fragP
= next_fragP
;
11835 /* Compute padding size for
11838 CMP like instruction
11840 COND_JUMP/UNCOND_JUMP
11845 COND_JUMP/UNCOND_JUMP
11849 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11851 unsigned int offset
, size
, padding_size
;
11852 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11854 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11856 address
= fragP
->fr_address
;
11857 address
+= fragP
->fr_fix
;
11859 /* CMP like instrunction size. */
11860 size
= fragP
->tc_frag_data
.cmp_size
;
11862 /* The base size of the branch frag. */
11863 size
+= branch_fragP
->fr_fix
;
11865 /* Add opcode and displacement bytes for the rs_machine_dependent
11867 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11868 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11870 /* Check if branch is within boundary and doesn't end at the last
11872 offset
= address
& ((1U << align_branch_power
) - 1);
11873 if ((offset
+ size
) >= (1U << align_branch_power
))
11874 /* Padding needed to avoid crossing boundary. */
11875 padding_size
= (1U << align_branch_power
) - offset
;
11877 /* No padding needed. */
11880 /* The return value may be saved in tc_frag_data.length which is
11882 if (!fits_in_unsigned_byte (padding_size
))
11885 return padding_size
;
11888 /* i386_generic_table_relax_frag()
11890 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11891 grow/shrink padding to align branch frags. Hand others to
11895 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11897 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11898 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11900 long padding_size
= i386_branch_padding_size (fragP
, 0);
11901 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11903 /* When the BRANCH_PREFIX frag is used, the computed address
11904 must match the actual address and there should be no padding. */
11905 if (fragP
->tc_frag_data
.padding_address
11906 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11910 /* Update the padding size. */
11912 fragP
->tc_frag_data
.length
= padding_size
;
11916 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11918 fragS
*padding_fragP
, *next_fragP
;
11919 long padding_size
, left_size
, last_size
;
11921 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11922 if (!padding_fragP
)
11923 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11924 return (fragP
->tc_frag_data
.length
11925 - fragP
->tc_frag_data
.last_length
);
11927 /* Compute the relative address of the padding frag in the very
11928 first time where the BRANCH_PREFIX frag sizes are zero. */
11929 if (!fragP
->tc_frag_data
.padding_address
)
11930 fragP
->tc_frag_data
.padding_address
11931 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11933 /* First update the last length from the previous interation. */
11934 left_size
= fragP
->tc_frag_data
.prefix_length
;
11935 for (next_fragP
= fragP
;
11936 next_fragP
!= padding_fragP
;
11937 next_fragP
= next_fragP
->fr_next
)
11938 if (next_fragP
->fr_type
== rs_machine_dependent
11939 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11944 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11948 if (max
> left_size
)
11953 next_fragP
->tc_frag_data
.last_length
= size
;
11957 next_fragP
->tc_frag_data
.last_length
= 0;
11960 /* Check the padding size for the padding frag. */
11961 padding_size
= i386_branch_padding_size
11962 (padding_fragP
, (fragP
->fr_address
11963 + fragP
->tc_frag_data
.padding_address
));
11965 last_size
= fragP
->tc_frag_data
.prefix_length
;
11966 /* Check if there is change from the last interation. */
11967 if (padding_size
== last_size
)
11969 /* Update the expected address of the padding frag. */
11970 padding_fragP
->tc_frag_data
.padding_address
11971 = (fragP
->fr_address
+ padding_size
11972 + fragP
->tc_frag_data
.padding_address
);
11976 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11978 /* No padding if there is no sufficient room. Clear the
11979 expected address of the padding frag. */
11980 padding_fragP
->tc_frag_data
.padding_address
= 0;
11984 /* Store the expected address of the padding frag. */
11985 padding_fragP
->tc_frag_data
.padding_address
11986 = (fragP
->fr_address
+ padding_size
11987 + fragP
->tc_frag_data
.padding_address
);
11989 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11991 /* Update the length for the current interation. */
11992 left_size
= padding_size
;
11993 for (next_fragP
= fragP
;
11994 next_fragP
!= padding_fragP
;
11995 next_fragP
= next_fragP
->fr_next
)
11996 if (next_fragP
->fr_type
== rs_machine_dependent
11997 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
12002 int max
= next_fragP
->tc_frag_data
.max_bytes
;
12006 if (max
> left_size
)
12011 next_fragP
->tc_frag_data
.length
= size
;
12015 next_fragP
->tc_frag_data
.length
= 0;
12018 return (fragP
->tc_frag_data
.length
12019 - fragP
->tc_frag_data
.last_length
);
12021 return relax_frag (segment
, fragP
, stretch
);
12024 /* md_estimate_size_before_relax()
12026 Called just before relax() for rs_machine_dependent frags. The x86
12027 assembler uses these frags to handle variable size jump
12030 Any symbol that is now undefined will not become defined.
12031 Return the correct fr_subtype in the frag.
12032 Return the initial "guess for variable size of frag" to caller.
12033 The guess is actually the growth beyond the fixed part. Whatever
12034 we do to grow the fixed or variable part contributes to our
12038 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
12040 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12041 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
12042 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
12044 i386_classify_machine_dependent_frag (fragP
);
12045 return fragP
->tc_frag_data
.length
;
12048 /* We've already got fragP->fr_subtype right; all we have to do is
12049 check for un-relaxable symbols. On an ELF system, we can't relax
12050 an externally visible symbol, because it may be overridden by a
12052 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12053 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12055 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12058 #if defined (OBJ_COFF) && defined (TE_PE)
12059 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12060 && S_IS_WEAK (fragP
->fr_symbol
))
12064 /* Symbol is undefined in this segment, or we need to keep a
12065 reloc so that weak symbols can be overridden. */
12066 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12067 enum bfd_reloc_code_real reloc_type
;
12068 unsigned char *opcode
;
12071 if (fragP
->fr_var
!= NO_RELOC
)
12072 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12073 else if (size
== 2)
12074 reloc_type
= BFD_RELOC_16_PCREL
;
12075 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12076 else if (need_plt32_p (fragP
->fr_symbol
))
12077 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12080 reloc_type
= BFD_RELOC_32_PCREL
;
12082 old_fr_fix
= fragP
->fr_fix
;
12083 opcode
= (unsigned char *) fragP
->fr_opcode
;
12085 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12088 /* Make jmp (0xeb) a (d)word displacement jump. */
12090 fragP
->fr_fix
+= size
;
12091 fix_new (fragP
, old_fr_fix
, size
,
12093 fragP
->fr_offset
, 1,
12099 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12101 /* Negate the condition, and branch past an
12102 unconditional jump. */
12105 /* Insert an unconditional jump. */
12107 /* We added two extra opcode bytes, and have a two byte
12109 fragP
->fr_fix
+= 2 + 2;
12110 fix_new (fragP
, old_fr_fix
+ 2, 2,
12112 fragP
->fr_offset
, 1,
12116 /* Fall through. */
12119 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12123 fragP
->fr_fix
+= 1;
12124 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12126 fragP
->fr_offset
, 1,
12127 BFD_RELOC_8_PCREL
);
12128 fixP
->fx_signed
= 1;
12132 /* This changes the byte-displacement jump 0x7N
12133 to the (d)word-displacement jump 0x0f,0x8N. */
12134 opcode
[1] = opcode
[0] + 0x10;
12135 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12136 /* We've added an opcode byte. */
12137 fragP
->fr_fix
+= 1 + size
;
12138 fix_new (fragP
, old_fr_fix
+ 1, size
,
12140 fragP
->fr_offset
, 1,
12145 BAD_CASE (fragP
->fr_subtype
);
12149 return fragP
->fr_fix
- old_fr_fix
;
12152 /* Guess size depending on current relax state. Initially the relax
12153 state will correspond to a short jump and we return 1, because
12154 the variable part of the frag (the branch offset) is one byte
12155 long. However, we can relax a section more than once and in that
12156 case we must either set fr_subtype back to the unrelaxed state,
12157 or return the value for the appropriate branch. */
12158 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12161 /* Called after relax() is finished.
12163 In: Address of frag.
12164 fr_type == rs_machine_dependent.
12165 fr_subtype is what the address relaxed to.
12167 Out: Any fixSs and constants are set up.
12168 Caller will turn frag into a ".space 0". */
12171 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12174 unsigned char *opcode
;
12175 unsigned char *where_to_put_displacement
= NULL
;
12176 offsetT target_address
;
12177 offsetT opcode_address
;
12178 unsigned int extension
= 0;
12179 offsetT displacement_from_opcode_start
;
12181 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12182 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12183 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12185 /* Generate nop padding. */
12186 unsigned int size
= fragP
->tc_frag_data
.length
;
12189 if (size
> fragP
->tc_frag_data
.max_bytes
)
12195 const char *branch
= "branch";
12196 const char *prefix
= "";
12197 fragS
*padding_fragP
;
12198 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12201 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12202 switch (fragP
->tc_frag_data
.default_prefix
)
12207 case CS_PREFIX_OPCODE
:
12210 case DS_PREFIX_OPCODE
:
12213 case ES_PREFIX_OPCODE
:
12216 case FS_PREFIX_OPCODE
:
12219 case GS_PREFIX_OPCODE
:
12222 case SS_PREFIX_OPCODE
:
12227 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12228 "%s within %d-byte boundary\n");
12230 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12231 "align %s within %d-byte boundary\n");
12235 padding_fragP
= fragP
;
12236 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12237 "%s within %d-byte boundary\n");
12241 switch (padding_fragP
->tc_frag_data
.branch_type
)
12243 case align_branch_jcc
:
12246 case align_branch_fused
:
12247 branch
= "fused jcc";
12249 case align_branch_jmp
:
12252 case align_branch_call
:
12255 case align_branch_indirect
:
12256 branch
= "indiret branch";
12258 case align_branch_ret
:
12265 fprintf (stdout
, msg
,
12266 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12267 (long long) fragP
->fr_address
, branch
,
12268 1 << align_branch_power
);
12270 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12271 memset (fragP
->fr_opcode
,
12272 fragP
->tc_frag_data
.default_prefix
, size
);
12274 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12276 fragP
->fr_fix
+= size
;
12281 opcode
= (unsigned char *) fragP
->fr_opcode
;
12283 /* Address we want to reach in file space. */
12284 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12286 /* Address opcode resides at in file space. */
12287 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12289 /* Displacement from opcode start to fill into instruction. */
12290 displacement_from_opcode_start
= target_address
- opcode_address
;
12292 if ((fragP
->fr_subtype
& BIG
) == 0)
12294 /* Don't have to change opcode. */
12295 extension
= 1; /* 1 opcode + 1 displacement */
12296 where_to_put_displacement
= &opcode
[1];
12300 if (no_cond_jump_promotion
12301 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12302 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12303 _("long jump required"));
12305 switch (fragP
->fr_subtype
)
12307 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12308 extension
= 4; /* 1 opcode + 4 displacement */
12310 where_to_put_displacement
= &opcode
[1];
12313 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12314 extension
= 2; /* 1 opcode + 2 displacement */
12316 where_to_put_displacement
= &opcode
[1];
12319 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12320 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12321 extension
= 5; /* 2 opcode + 4 displacement */
12322 opcode
[1] = opcode
[0] + 0x10;
12323 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12324 where_to_put_displacement
= &opcode
[2];
12327 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12328 extension
= 3; /* 2 opcode + 2 displacement */
12329 opcode
[1] = opcode
[0] + 0x10;
12330 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12331 where_to_put_displacement
= &opcode
[2];
12334 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12339 where_to_put_displacement
= &opcode
[3];
12343 BAD_CASE (fragP
->fr_subtype
);
12348 /* If size if less then four we are sure that the operand fits,
12349 but if it's 4, then it could be that the displacement is larger
12351 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12353 && ((addressT
) (displacement_from_opcode_start
- extension
12354 + ((addressT
) 1 << 31))
12355 > (((addressT
) 2 << 31) - 1)))
12357 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12358 _("jump target out of range"));
12359 /* Make us emit 0. */
12360 displacement_from_opcode_start
= extension
;
12362 /* Now put displacement after opcode. */
12363 md_number_to_chars ((char *) where_to_put_displacement
,
12364 (valueT
) (displacement_from_opcode_start
- extension
),
12365 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12366 fragP
->fr_fix
+= extension
;
12369 /* Apply a fixup (fixP) to segment data, once it has been determined
12370 by our caller that we have all the info we need to fix it up.
12372 Parameter valP is the pointer to the value of the bits.
12374 On the 386, immediates, displacements, and data pointers are all in
12375 the same (little-endian) format, so we don't need to care about which
12376 we are handling. */
12379 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12381 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12382 valueT value
= *valP
;
12384 #if !defined (TE_Mach)
12385 if (fixP
->fx_pcrel
)
12387 switch (fixP
->fx_r_type
)
12393 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12396 case BFD_RELOC_X86_64_32S
:
12397 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12400 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12403 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12408 if (fixP
->fx_addsy
!= NULL
12409 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12410 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12411 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12412 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12413 && !use_rela_relocations
)
12415 /* This is a hack. There should be a better way to handle this.
12416 This covers for the fact that bfd_install_relocation will
12417 subtract the current location (for partial_inplace, PC relative
12418 relocations); see more below. */
12422 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12425 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12427 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12430 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12432 if ((sym_seg
== seg
12433 || (symbol_section_p (fixP
->fx_addsy
)
12434 && sym_seg
!= absolute_section
))
12435 && !generic_force_reloc (fixP
))
12437 /* Yes, we add the values in twice. This is because
12438 bfd_install_relocation subtracts them out again. I think
12439 bfd_install_relocation is broken, but I don't dare change
12441 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12445 #if defined (OBJ_COFF) && defined (TE_PE)
12446 /* For some reason, the PE format does not store a
12447 section address offset for a PC relative symbol. */
12448 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12449 || S_IS_WEAK (fixP
->fx_addsy
))
12450 value
+= md_pcrel_from (fixP
);
12453 #if defined (OBJ_COFF) && defined (TE_PE)
12454 if (fixP
->fx_addsy
!= NULL
12455 && S_IS_WEAK (fixP
->fx_addsy
)
12456 /* PR 16858: Do not modify weak function references. */
12457 && ! fixP
->fx_pcrel
)
12459 #if !defined (TE_PEP)
12460 /* For x86 PE weak function symbols are neither PC-relative
12461 nor do they set S_IS_FUNCTION. So the only reliable way
12462 to detect them is to check the flags of their containing
12464 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12465 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12469 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12473 /* Fix a few things - the dynamic linker expects certain values here,
12474 and we must not disappoint it. */
12475 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12476 if (IS_ELF
&& fixP
->fx_addsy
)
12477 switch (fixP
->fx_r_type
)
12479 case BFD_RELOC_386_PLT32
:
12480 case BFD_RELOC_X86_64_PLT32
:
12481 /* Make the jump instruction point to the address of the operand.
12482 At runtime we merely add the offset to the actual PLT entry.
12483 NB: Subtract the offset size only for jump instructions. */
12484 if (fixP
->fx_pcrel
)
12488 case BFD_RELOC_386_TLS_GD
:
12489 case BFD_RELOC_386_TLS_LDM
:
12490 case BFD_RELOC_386_TLS_IE_32
:
12491 case BFD_RELOC_386_TLS_IE
:
12492 case BFD_RELOC_386_TLS_GOTIE
:
12493 case BFD_RELOC_386_TLS_GOTDESC
:
12494 case BFD_RELOC_X86_64_TLSGD
:
12495 case BFD_RELOC_X86_64_TLSLD
:
12496 case BFD_RELOC_X86_64_GOTTPOFF
:
12497 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12498 value
= 0; /* Fully resolved at runtime. No addend. */
12500 case BFD_RELOC_386_TLS_LE
:
12501 case BFD_RELOC_386_TLS_LDO_32
:
12502 case BFD_RELOC_386_TLS_LE_32
:
12503 case BFD_RELOC_X86_64_DTPOFF32
:
12504 case BFD_RELOC_X86_64_DTPOFF64
:
12505 case BFD_RELOC_X86_64_TPOFF32
:
12506 case BFD_RELOC_X86_64_TPOFF64
:
12507 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12510 case BFD_RELOC_386_TLS_DESC_CALL
:
12511 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12512 value
= 0; /* Fully resolved at runtime. No addend. */
12513 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12517 case BFD_RELOC_VTABLE_INHERIT
:
12518 case BFD_RELOC_VTABLE_ENTRY
:
12525 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12527 #endif /* !defined (TE_Mach) */
12529 /* Are we finished with this relocation now? */
12530 if (fixP
->fx_addsy
== NULL
)
12532 #if defined (OBJ_COFF) && defined (TE_PE)
12533 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12536 /* Remember value for tc_gen_reloc. */
12537 fixP
->fx_addnumber
= value
;
12538 /* Clear out the frag for now. */
12542 else if (use_rela_relocations
)
12544 fixP
->fx_no_overflow
= 1;
12545 /* Remember value for tc_gen_reloc. */
12546 fixP
->fx_addnumber
= value
;
12550 md_number_to_chars (p
, value
, fixP
->fx_size
);
12554 md_atof (int type
, char *litP
, int *sizeP
)
12556 /* This outputs the LITTLENUMs in REVERSE order;
12557 in accord with the bigendian 386. */
12558 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12561 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12564 output_invalid (int c
)
12567 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12570 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12571 "(0x%x)", (unsigned char) c
);
12572 return output_invalid_buf
;
12575 /* Verify that @r can be used in the current context. */
12577 static bfd_boolean
check_register (const reg_entry
*r
)
12579 if (allow_pseudo_reg
)
12582 if (operand_type_all_zero (&r
->reg_type
))
12585 if ((r
->reg_type
.bitfield
.dword
12586 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12587 || r
->reg_type
.bitfield
.class == RegCR
12588 || r
->reg_type
.bitfield
.class == RegDR
)
12589 && !cpu_arch_flags
.bitfield
.cpui386
)
12592 if (r
->reg_type
.bitfield
.class == RegTR
12593 && (flag_code
== CODE_64BIT
12594 || !cpu_arch_flags
.bitfield
.cpui386
12595 || cpu_arch_isa_flags
.bitfield
.cpui586
12596 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12599 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12602 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12604 if (r
->reg_type
.bitfield
.zmmword
12605 || r
->reg_type
.bitfield
.class == RegMask
)
12608 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12610 if (r
->reg_type
.bitfield
.ymmword
)
12613 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12618 if (r
->reg_type
.bitfield
.tmmword
12619 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12620 || flag_code
!= CODE_64BIT
))
12623 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12626 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12627 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12630 /* Upper 16 vector registers are only available with VREX in 64bit
12631 mode, and require EVEX encoding. */
12632 if (r
->reg_flags
& RegVRex
)
12634 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12635 || flag_code
!= CODE_64BIT
)
12638 if (i
.vec_encoding
== vex_encoding_default
)
12639 i
.vec_encoding
= vex_encoding_evex
;
12640 else if (i
.vec_encoding
!= vex_encoding_evex
)
12641 i
.vec_encoding
= vex_encoding_error
;
12644 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12645 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12646 && flag_code
!= CODE_64BIT
)
12649 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12656 /* REG_STRING starts *before* REGISTER_PREFIX. */
12658 static const reg_entry
*
12659 parse_real_register (char *reg_string
, char **end_op
)
12661 char *s
= reg_string
;
12663 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12664 const reg_entry
*r
;
12666 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12667 if (*s
== REGISTER_PREFIX
)
12670 if (is_space_char (*s
))
12673 p
= reg_name_given
;
12674 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12676 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12677 return (const reg_entry
*) NULL
;
12681 /* For naked regs, make sure that we are not dealing with an identifier.
12682 This prevents confusing an identifier like `eax_var' with register
12684 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12685 return (const reg_entry
*) NULL
;
12689 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
12691 /* Handle floating point regs, allowing spaces in the (i) part. */
12692 if (r
== i386_regtab
/* %st is first entry of table */)
12694 if (!cpu_arch_flags
.bitfield
.cpu8087
12695 && !cpu_arch_flags
.bitfield
.cpu287
12696 && !cpu_arch_flags
.bitfield
.cpu387
12697 && !allow_pseudo_reg
)
12698 return (const reg_entry
*) NULL
;
12700 if (is_space_char (*s
))
12705 if (is_space_char (*s
))
12707 if (*s
>= '0' && *s
<= '7')
12709 int fpr
= *s
- '0';
12711 if (is_space_char (*s
))
12716 r
= (const reg_entry
*) str_hash_find (reg_hash
, "st(0)");
12721 /* We have "%st(" then garbage. */
12722 return (const reg_entry
*) NULL
;
12726 return r
&& check_register (r
) ? r
: NULL
;
12729 /* REG_STRING starts *before* REGISTER_PREFIX. */
12731 static const reg_entry
*
12732 parse_register (char *reg_string
, char **end_op
)
12734 const reg_entry
*r
;
12736 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12737 r
= parse_real_register (reg_string
, end_op
);
12742 char *save
= input_line_pointer
;
12746 input_line_pointer
= reg_string
;
12747 c
= get_symbol_name (®_string
);
12748 symbolP
= symbol_find (reg_string
);
12749 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12751 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12753 know (e
->X_op
== O_register
);
12754 know (e
->X_add_number
>= 0
12755 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12756 r
= i386_regtab
+ e
->X_add_number
;
12757 if (!check_register (r
))
12759 as_bad (_("register '%s%s' cannot be used here"),
12760 register_prefix
, r
->reg_name
);
12763 *end_op
= input_line_pointer
;
12765 *input_line_pointer
= c
;
12766 input_line_pointer
= save
;
12772 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12774 const reg_entry
*r
;
12775 char *end
= input_line_pointer
;
12778 r
= parse_register (name
, &input_line_pointer
);
12779 if (r
&& end
<= input_line_pointer
)
12781 *nextcharP
= *input_line_pointer
;
12782 *input_line_pointer
= 0;
12785 e
->X_op
= O_register
;
12786 e
->X_add_number
= r
- i386_regtab
;
12789 e
->X_op
= O_illegal
;
12792 input_line_pointer
= end
;
12794 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12798 md_operand (expressionS
*e
)
12801 const reg_entry
*r
;
12803 switch (*input_line_pointer
)
12805 case REGISTER_PREFIX
:
12806 r
= parse_real_register (input_line_pointer
, &end
);
12809 e
->X_op
= O_register
;
12810 e
->X_add_number
= r
- i386_regtab
;
12811 input_line_pointer
= end
;
12816 gas_assert (intel_syntax
);
12817 end
= input_line_pointer
++;
12819 if (*input_line_pointer
== ']')
12821 ++input_line_pointer
;
12822 e
->X_op_symbol
= make_expr_symbol (e
);
12823 e
->X_add_symbol
= NULL
;
12824 e
->X_add_number
= 0;
12829 e
->X_op
= O_absent
;
12830 input_line_pointer
= end
;
12837 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12838 const char *md_shortopts
= "kVQ:sqnO::";
12840 const char *md_shortopts
= "qnO::";
12843 #define OPTION_32 (OPTION_MD_BASE + 0)
12844 #define OPTION_64 (OPTION_MD_BASE + 1)
12845 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12846 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12847 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12848 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12849 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12850 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12851 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12852 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12853 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12854 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12855 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12856 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12857 #define OPTION_X32 (OPTION_MD_BASE + 14)
12858 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12859 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12860 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12861 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12862 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12863 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12864 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12865 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12866 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12867 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12868 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12869 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12870 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12871 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12872 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12873 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12874 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12875 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12876 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12878 struct option md_longopts
[] =
12880 {"32", no_argument
, NULL
, OPTION_32
},
12881 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12882 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12883 {"64", no_argument
, NULL
, OPTION_64
},
12885 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12886 {"x32", no_argument
, NULL
, OPTION_X32
},
12887 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12888 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12890 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12891 {"march", required_argument
, NULL
, OPTION_MARCH
},
12892 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12893 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12894 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12895 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12896 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12897 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12898 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12899 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12900 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12901 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12902 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12903 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12904 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12905 # if defined (TE_PE) || defined (TE_PEP)
12906 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12908 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12909 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12910 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12911 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12912 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12913 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12914 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12915 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12916 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12917 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12918 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12919 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12920 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12921 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12922 {NULL
, no_argument
, NULL
, 0}
12924 size_t md_longopts_size
= sizeof (md_longopts
);
12927 md_parse_option (int c
, const char *arg
)
12930 char *arch
, *next
, *saved
, *type
;
12935 optimize_align_code
= 0;
12939 quiet_warnings
= 1;
12942 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12943 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12944 should be emitted or not. FIXME: Not implemented. */
12946 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12950 /* -V: SVR4 argument to print version ID. */
12952 print_version_id ();
12955 /* -k: Ignore for FreeBSD compatibility. */
12960 /* -s: On i386 Solaris, this tells the native assembler to use
12961 .stab instead of .stab.excl. We always use .stab anyhow. */
12964 case OPTION_MSHARED
:
12968 case OPTION_X86_USED_NOTE
:
12969 if (strcasecmp (arg
, "yes") == 0)
12971 else if (strcasecmp (arg
, "no") == 0)
12974 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12979 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12980 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12983 const char **list
, **l
;
12985 list
= bfd_target_list ();
12986 for (l
= list
; *l
!= NULL
; l
++)
12987 if (startswith (*l
, "elf64-x86-64")
12988 || strcmp (*l
, "coff-x86-64") == 0
12989 || strcmp (*l
, "pe-x86-64") == 0
12990 || strcmp (*l
, "pei-x86-64") == 0
12991 || strcmp (*l
, "mach-o-x86-64") == 0)
12993 default_arch
= "x86_64";
12997 as_fatal (_("no compiled in support for x86_64"));
13003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13007 const char **list
, **l
;
13009 list
= bfd_target_list ();
13010 for (l
= list
; *l
!= NULL
; l
++)
13011 if (startswith (*l
, "elf32-x86-64"))
13013 default_arch
= "x86_64:32";
13017 as_fatal (_("no compiled in support for 32bit x86_64"));
13021 as_fatal (_("32bit x86_64 is only supported for ELF"));
13026 default_arch
= "i386";
13029 case OPTION_DIVIDE
:
13030 #ifdef SVR4_COMMENT_CHARS
13035 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
13037 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
13041 i386_comment_chars
= n
;
13047 saved
= xstrdup (arg
);
13049 /* Allow -march=+nosse. */
13055 as_fatal (_("invalid -march= option: `%s'"), arg
);
13056 next
= strchr (arch
, '+');
13059 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13061 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13064 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13067 cpu_arch_name
= cpu_arch
[j
].name
;
13068 cpu_sub_arch_name
= NULL
;
13069 cpu_arch_flags
= cpu_arch
[j
].flags
;
13070 cpu_arch_isa
= cpu_arch
[j
].type
;
13071 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13072 if (!cpu_arch_tune_set
)
13074 cpu_arch_tune
= cpu_arch_isa
;
13075 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13079 else if (*cpu_arch
[j
].name
== '.'
13080 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13082 /* ISA extension. */
13083 i386_cpu_flags flags
;
13085 flags
= cpu_flags_or (cpu_arch_flags
,
13086 cpu_arch
[j
].flags
);
13088 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13090 if (cpu_sub_arch_name
)
13092 char *name
= cpu_sub_arch_name
;
13093 cpu_sub_arch_name
= concat (name
,
13095 (const char *) NULL
);
13099 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13100 cpu_arch_flags
= flags
;
13101 cpu_arch_isa_flags
= flags
;
13105 = cpu_flags_or (cpu_arch_isa_flags
,
13106 cpu_arch
[j
].flags
);
13111 if (j
>= ARRAY_SIZE (cpu_arch
))
13113 /* Disable an ISA extension. */
13114 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13115 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13117 i386_cpu_flags flags
;
13119 flags
= cpu_flags_and_not (cpu_arch_flags
,
13120 cpu_noarch
[j
].flags
);
13121 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13123 if (cpu_sub_arch_name
)
13125 char *name
= cpu_sub_arch_name
;
13126 cpu_sub_arch_name
= concat (arch
,
13127 (const char *) NULL
);
13131 cpu_sub_arch_name
= xstrdup (arch
);
13132 cpu_arch_flags
= flags
;
13133 cpu_arch_isa_flags
= flags
;
13138 if (j
>= ARRAY_SIZE (cpu_noarch
))
13139 j
= ARRAY_SIZE (cpu_arch
);
13142 if (j
>= ARRAY_SIZE (cpu_arch
))
13143 as_fatal (_("invalid -march= option: `%s'"), arg
);
13147 while (next
!= NULL
);
13153 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13154 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13156 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13158 cpu_arch_tune_set
= 1;
13159 cpu_arch_tune
= cpu_arch
[j
].type
;
13160 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13164 if (j
>= ARRAY_SIZE (cpu_arch
))
13165 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13168 case OPTION_MMNEMONIC
:
13169 if (strcasecmp (arg
, "att") == 0)
13170 intel_mnemonic
= 0;
13171 else if (strcasecmp (arg
, "intel") == 0)
13172 intel_mnemonic
= 1;
13174 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13177 case OPTION_MSYNTAX
:
13178 if (strcasecmp (arg
, "att") == 0)
13180 else if (strcasecmp (arg
, "intel") == 0)
13183 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13186 case OPTION_MINDEX_REG
:
13187 allow_index_reg
= 1;
13190 case OPTION_MNAKED_REG
:
13191 allow_naked_reg
= 1;
13194 case OPTION_MSSE2AVX
:
13198 case OPTION_MSSE_CHECK
:
13199 if (strcasecmp (arg
, "error") == 0)
13200 sse_check
= check_error
;
13201 else if (strcasecmp (arg
, "warning") == 0)
13202 sse_check
= check_warning
;
13203 else if (strcasecmp (arg
, "none") == 0)
13204 sse_check
= check_none
;
13206 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13209 case OPTION_MOPERAND_CHECK
:
13210 if (strcasecmp (arg
, "error") == 0)
13211 operand_check
= check_error
;
13212 else if (strcasecmp (arg
, "warning") == 0)
13213 operand_check
= check_warning
;
13214 else if (strcasecmp (arg
, "none") == 0)
13215 operand_check
= check_none
;
13217 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13220 case OPTION_MAVXSCALAR
:
13221 if (strcasecmp (arg
, "128") == 0)
13222 avxscalar
= vex128
;
13223 else if (strcasecmp (arg
, "256") == 0)
13224 avxscalar
= vex256
;
13226 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13229 case OPTION_MVEXWIG
:
13230 if (strcmp (arg
, "0") == 0)
13232 else if (strcmp (arg
, "1") == 0)
13235 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13238 case OPTION_MADD_BND_PREFIX
:
13239 add_bnd_prefix
= 1;
13242 case OPTION_MEVEXLIG
:
13243 if (strcmp (arg
, "128") == 0)
13244 evexlig
= evexl128
;
13245 else if (strcmp (arg
, "256") == 0)
13246 evexlig
= evexl256
;
13247 else if (strcmp (arg
, "512") == 0)
13248 evexlig
= evexl512
;
13250 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13253 case OPTION_MEVEXRCIG
:
13254 if (strcmp (arg
, "rne") == 0)
13256 else if (strcmp (arg
, "rd") == 0)
13258 else if (strcmp (arg
, "ru") == 0)
13260 else if (strcmp (arg
, "rz") == 0)
13263 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13266 case OPTION_MEVEXWIG
:
13267 if (strcmp (arg
, "0") == 0)
13269 else if (strcmp (arg
, "1") == 0)
13272 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13275 # if defined (TE_PE) || defined (TE_PEP)
13276 case OPTION_MBIG_OBJ
:
13281 case OPTION_MOMIT_LOCK_PREFIX
:
13282 if (strcasecmp (arg
, "yes") == 0)
13283 omit_lock_prefix
= 1;
13284 else if (strcasecmp (arg
, "no") == 0)
13285 omit_lock_prefix
= 0;
13287 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13290 case OPTION_MFENCE_AS_LOCK_ADD
:
13291 if (strcasecmp (arg
, "yes") == 0)
13293 else if (strcasecmp (arg
, "no") == 0)
13296 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13299 case OPTION_MLFENCE_AFTER_LOAD
:
13300 if (strcasecmp (arg
, "yes") == 0)
13301 lfence_after_load
= 1;
13302 else if (strcasecmp (arg
, "no") == 0)
13303 lfence_after_load
= 0;
13305 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13308 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13309 if (strcasecmp (arg
, "all") == 0)
13311 lfence_before_indirect_branch
= lfence_branch_all
;
13312 if (lfence_before_ret
== lfence_before_ret_none
)
13313 lfence_before_ret
= lfence_before_ret_shl
;
13315 else if (strcasecmp (arg
, "memory") == 0)
13316 lfence_before_indirect_branch
= lfence_branch_memory
;
13317 else if (strcasecmp (arg
, "register") == 0)
13318 lfence_before_indirect_branch
= lfence_branch_register
;
13319 else if (strcasecmp (arg
, "none") == 0)
13320 lfence_before_indirect_branch
= lfence_branch_none
;
13322 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13326 case OPTION_MLFENCE_BEFORE_RET
:
13327 if (strcasecmp (arg
, "or") == 0)
13328 lfence_before_ret
= lfence_before_ret_or
;
13329 else if (strcasecmp (arg
, "not") == 0)
13330 lfence_before_ret
= lfence_before_ret_not
;
13331 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13332 lfence_before_ret
= lfence_before_ret_shl
;
13333 else if (strcasecmp (arg
, "none") == 0)
13334 lfence_before_ret
= lfence_before_ret_none
;
13336 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13340 case OPTION_MRELAX_RELOCATIONS
:
13341 if (strcasecmp (arg
, "yes") == 0)
13342 generate_relax_relocations
= 1;
13343 else if (strcasecmp (arg
, "no") == 0)
13344 generate_relax_relocations
= 0;
13346 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13349 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13352 long int align
= strtoul (arg
, &end
, 0);
13357 align_branch_power
= 0;
13360 else if (align
>= 16)
13363 for (align_power
= 0;
13365 align
>>= 1, align_power
++)
13367 /* Limit alignment power to 31. */
13368 if (align
== 1 && align_power
< 32)
13370 align_branch_power
= align_power
;
13375 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13379 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13382 int align
= strtoul (arg
, &end
, 0);
13383 /* Some processors only support 5 prefixes. */
13384 if (*end
== '\0' && align
>= 0 && align
< 6)
13386 align_branch_prefix_size
= align
;
13389 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13394 case OPTION_MALIGN_BRANCH
:
13396 saved
= xstrdup (arg
);
13400 next
= strchr (type
, '+');
13403 if (strcasecmp (type
, "jcc") == 0)
13404 align_branch
|= align_branch_jcc_bit
;
13405 else if (strcasecmp (type
, "fused") == 0)
13406 align_branch
|= align_branch_fused_bit
;
13407 else if (strcasecmp (type
, "jmp") == 0)
13408 align_branch
|= align_branch_jmp_bit
;
13409 else if (strcasecmp (type
, "call") == 0)
13410 align_branch
|= align_branch_call_bit
;
13411 else if (strcasecmp (type
, "ret") == 0)
13412 align_branch
|= align_branch_ret_bit
;
13413 else if (strcasecmp (type
, "indirect") == 0)
13414 align_branch
|= align_branch_indirect_bit
;
13416 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13419 while (next
!= NULL
);
13423 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13424 align_branch_power
= 5;
13425 align_branch_prefix_size
= 5;
13426 align_branch
= (align_branch_jcc_bit
13427 | align_branch_fused_bit
13428 | align_branch_jmp_bit
);
13431 case OPTION_MAMD64
:
13435 case OPTION_MINTEL64
:
13443 /* Turn off -Os. */
13444 optimize_for_space
= 0;
13446 else if (*arg
== 's')
13448 optimize_for_space
= 1;
13449 /* Turn on all encoding optimizations. */
13450 optimize
= INT_MAX
;
13454 optimize
= atoi (arg
);
13455 /* Turn off -Os. */
13456 optimize_for_space
= 0;
13466 #define MESSAGE_TEMPLATE \
13470 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13471 int *left_p
, const char *name
, int len
)
13473 int size
= sizeof (MESSAGE_TEMPLATE
);
13474 int left
= *left_p
;
13476 /* Reserve 2 spaces for ", " or ",\0" */
13479 /* Check if there is any room. */
13487 p
= mempcpy (p
, name
, len
);
13491 /* Output the current message now and start a new one. */
13494 fprintf (stream
, "%s\n", message
);
13496 left
= size
- (start
- message
) - len
- 2;
13498 gas_assert (left
>= 0);
13500 p
= mempcpy (p
, name
, len
);
13508 show_arch (FILE *stream
, int ext
, int check
)
13510 static char message
[] = MESSAGE_TEMPLATE
;
13511 char *start
= message
+ 27;
13513 int size
= sizeof (MESSAGE_TEMPLATE
);
13520 left
= size
- (start
- message
);
13521 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13523 /* Should it be skipped? */
13524 if (cpu_arch
[j
].skip
)
13527 name
= cpu_arch
[j
].name
;
13528 len
= cpu_arch
[j
].len
;
13531 /* It is an extension. Skip if we aren't asked to show it. */
13542 /* It is an processor. Skip if we show only extension. */
13545 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13547 /* It is an impossible processor - skip. */
13551 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13554 /* Display disabled extensions. */
13556 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13558 name
= cpu_noarch
[j
].name
;
13559 len
= cpu_noarch
[j
].len
;
13560 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13565 fprintf (stream
, "%s\n", message
);
13569 md_show_usage (FILE *stream
)
13571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13572 fprintf (stream
, _("\
13573 -Qy, -Qn ignored\n\
13574 -V print assembler version number\n\
13577 fprintf (stream
, _("\
13578 -n Do not optimize code alignment\n\
13579 -q quieten some warnings\n"));
13580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13581 fprintf (stream
, _("\
13584 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13585 || defined (TE_PE) || defined (TE_PEP))
13586 fprintf (stream
, _("\
13587 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13589 #ifdef SVR4_COMMENT_CHARS
13590 fprintf (stream
, _("\
13591 --divide do not treat `/' as a comment character\n"));
13593 fprintf (stream
, _("\
13594 --divide ignored\n"));
13596 fprintf (stream
, _("\
13597 -march=CPU[,+EXTENSION...]\n\
13598 generate code for CPU and EXTENSION, CPU is one of:\n"));
13599 show_arch (stream
, 0, 1);
13600 fprintf (stream
, _("\
13601 EXTENSION is combination of:\n"));
13602 show_arch (stream
, 1, 0);
13603 fprintf (stream
, _("\
13604 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13605 show_arch (stream
, 0, 0);
13606 fprintf (stream
, _("\
13607 -msse2avx encode SSE instructions with VEX prefix\n"));
13608 fprintf (stream
, _("\
13609 -msse-check=[none|error|warning] (default: warning)\n\
13610 check SSE instructions\n"));
13611 fprintf (stream
, _("\
13612 -moperand-check=[none|error|warning] (default: warning)\n\
13613 check operand combinations for validity\n"));
13614 fprintf (stream
, _("\
13615 -mavxscalar=[128|256] (default: 128)\n\
13616 encode scalar AVX instructions with specific vector\n\
13618 fprintf (stream
, _("\
13619 -mvexwig=[0|1] (default: 0)\n\
13620 encode VEX instructions with specific VEX.W value\n\
13621 for VEX.W bit ignored instructions\n"));
13622 fprintf (stream
, _("\
13623 -mevexlig=[128|256|512] (default: 128)\n\
13624 encode scalar EVEX instructions with specific vector\n\
13626 fprintf (stream
, _("\
13627 -mevexwig=[0|1] (default: 0)\n\
13628 encode EVEX instructions with specific EVEX.W value\n\
13629 for EVEX.W bit ignored instructions\n"));
13630 fprintf (stream
, _("\
13631 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13632 encode EVEX instructions with specific EVEX.RC value\n\
13633 for SAE-only ignored instructions\n"));
13634 fprintf (stream
, _("\
13635 -mmnemonic=[att|intel] "));
13636 if (SYSV386_COMPAT
)
13637 fprintf (stream
, _("(default: att)\n"));
13639 fprintf (stream
, _("(default: intel)\n"));
13640 fprintf (stream
, _("\
13641 use AT&T/Intel mnemonic\n"));
13642 fprintf (stream
, _("\
13643 -msyntax=[att|intel] (default: att)\n\
13644 use AT&T/Intel syntax\n"));
13645 fprintf (stream
, _("\
13646 -mindex-reg support pseudo index registers\n"));
13647 fprintf (stream
, _("\
13648 -mnaked-reg don't require `%%' prefix for registers\n"));
13649 fprintf (stream
, _("\
13650 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13651 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13652 fprintf (stream
, _("\
13653 -mshared disable branch optimization for shared code\n"));
13654 fprintf (stream
, _("\
13655 -mx86-used-note=[no|yes] "));
13656 if (DEFAULT_X86_USED_NOTE
)
13657 fprintf (stream
, _("(default: yes)\n"));
13659 fprintf (stream
, _("(default: no)\n"));
13660 fprintf (stream
, _("\
13661 generate x86 used ISA and feature properties\n"));
13663 #if defined (TE_PE) || defined (TE_PEP)
13664 fprintf (stream
, _("\
13665 -mbig-obj generate big object files\n"));
13667 fprintf (stream
, _("\
13668 -momit-lock-prefix=[no|yes] (default: no)\n\
13669 strip all lock prefixes\n"));
13670 fprintf (stream
, _("\
13671 -mfence-as-lock-add=[no|yes] (default: no)\n\
13672 encode lfence, mfence and sfence as\n\
13673 lock addl $0x0, (%%{re}sp)\n"));
13674 fprintf (stream
, _("\
13675 -mrelax-relocations=[no|yes] "));
13676 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13677 fprintf (stream
, _("(default: yes)\n"));
13679 fprintf (stream
, _("(default: no)\n"));
13680 fprintf (stream
, _("\
13681 generate relax relocations\n"));
13682 fprintf (stream
, _("\
13683 -malign-branch-boundary=NUM (default: 0)\n\
13684 align branches within NUM byte boundary\n"));
13685 fprintf (stream
, _("\
13686 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13687 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13689 specify types of branches to align\n"));
13690 fprintf (stream
, _("\
13691 -malign-branch-prefix-size=NUM (default: 5)\n\
13692 align branches with NUM prefixes per instruction\n"));
13693 fprintf (stream
, _("\
13694 -mbranches-within-32B-boundaries\n\
13695 align branches within 32 byte boundary\n"));
13696 fprintf (stream
, _("\
13697 -mlfence-after-load=[no|yes] (default: no)\n\
13698 generate lfence after load\n"));
13699 fprintf (stream
, _("\
13700 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13701 generate lfence before indirect near branch\n"));
13702 fprintf (stream
, _("\
13703 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13704 generate lfence before ret\n"));
13705 fprintf (stream
, _("\
13706 -mamd64 accept only AMD64 ISA [default]\n"));
13707 fprintf (stream
, _("\
13708 -mintel64 accept only Intel64 ISA\n"));
13711 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13712 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13713 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13715 /* Pick the target format to use. */
13718 i386_target_format (void)
13720 if (!strncmp (default_arch
, "x86_64", 6))
13722 update_code_flag (CODE_64BIT
, 1);
13723 if (default_arch
[6] == '\0')
13724 x86_elf_abi
= X86_64_ABI
;
13726 x86_elf_abi
= X86_64_X32_ABI
;
13728 else if (!strcmp (default_arch
, "i386"))
13729 update_code_flag (CODE_32BIT
, 1);
13730 else if (!strcmp (default_arch
, "iamcu"))
13732 update_code_flag (CODE_32BIT
, 1);
13733 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13735 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13736 cpu_arch_name
= "iamcu";
13737 cpu_sub_arch_name
= NULL
;
13738 cpu_arch_flags
= iamcu_flags
;
13739 cpu_arch_isa
= PROCESSOR_IAMCU
;
13740 cpu_arch_isa_flags
= iamcu_flags
;
13741 if (!cpu_arch_tune_set
)
13743 cpu_arch_tune
= cpu_arch_isa
;
13744 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13747 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13748 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13752 as_fatal (_("unknown architecture"));
13754 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13755 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13756 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13757 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13759 switch (OUTPUT_FLAVOR
)
13761 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13762 case bfd_target_aout_flavour
:
13763 return AOUT_TARGET_FORMAT
;
13765 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13766 # if defined (TE_PE) || defined (TE_PEP)
13767 case bfd_target_coff_flavour
:
13768 if (flag_code
== CODE_64BIT
)
13769 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13771 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13772 # elif defined (TE_GO32)
13773 case bfd_target_coff_flavour
:
13774 return "coff-go32";
13776 case bfd_target_coff_flavour
:
13777 return "coff-i386";
13780 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13781 case bfd_target_elf_flavour
:
13783 const char *format
;
13785 switch (x86_elf_abi
)
13788 format
= ELF_TARGET_FORMAT
;
13790 tls_get_addr
= "___tls_get_addr";
13794 use_rela_relocations
= 1;
13797 tls_get_addr
= "__tls_get_addr";
13799 format
= ELF_TARGET_FORMAT64
;
13801 case X86_64_X32_ABI
:
13802 use_rela_relocations
= 1;
13805 tls_get_addr
= "__tls_get_addr";
13807 disallow_64bit_reloc
= 1;
13808 format
= ELF_TARGET_FORMAT32
;
13811 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13813 if (x86_elf_abi
!= X86_64_ABI
)
13814 as_fatal (_("Intel L1OM is 64bit only"));
13815 return ELF_TARGET_L1OM_FORMAT
;
13817 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13819 if (x86_elf_abi
!= X86_64_ABI
)
13820 as_fatal (_("Intel K1OM is 64bit only"));
13821 return ELF_TARGET_K1OM_FORMAT
;
13823 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13825 if (x86_elf_abi
!= I386_ABI
)
13826 as_fatal (_("Intel MCU is 32bit only"));
13827 return ELF_TARGET_IAMCU_FORMAT
;
13833 #if defined (OBJ_MACH_O)
13834 case bfd_target_mach_o_flavour
:
13835 if (flag_code
== CODE_64BIT
)
13837 use_rela_relocations
= 1;
13839 return "mach-o-x86-64";
13842 return "mach-o-i386";
13850 #endif /* OBJ_MAYBE_ more than one */
13853 md_undefined_symbol (char *name
)
13855 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13856 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13857 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13858 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13862 if (symbol_find (name
))
13863 as_bad (_("GOT already in symbol table"));
13864 GOT_symbol
= symbol_new (name
, undefined_section
,
13865 &zero_address_frag
, 0);
13872 /* Round up a section size to the appropriate boundary. */
13875 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13877 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13878 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13880 /* For a.out, force the section size to be aligned. If we don't do
13881 this, BFD will align it for us, but it will not write out the
13882 final bytes of the section. This may be a bug in BFD, but it is
13883 easier to fix it here since that is how the other a.out targets
13887 align
= bfd_section_alignment (segment
);
13888 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13895 /* On the i386, PC-relative offsets are relative to the start of the
13896 next instruction. That is, the address of the offset, plus its
13897 size, since the offset is always the last part of the insn. */
13900 md_pcrel_from (fixS
*fixP
)
13902 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13908 s_bss (int ignore ATTRIBUTE_UNUSED
)
13912 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13914 obj_elf_section_change_hook ();
13916 temp
= get_absolute_expression ();
13917 subseg_set (bss_section
, (subsegT
) temp
);
13918 demand_empty_rest_of_line ();
13923 /* Remember constant directive. */
13926 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13928 if (last_insn
.kind
!= last_insn_directive
13929 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13931 last_insn
.seg
= now_seg
;
13932 last_insn
.kind
= last_insn_directive
;
13933 last_insn
.name
= "constant directive";
13934 last_insn
.file
= as_where (&last_insn
.line
);
13935 if (lfence_before_ret
!= lfence_before_ret_none
)
13937 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13938 as_warn (_("constant directive skips -mlfence-before-ret "
13939 "and -mlfence-before-indirect-branch"));
13941 as_warn (_("constant directive skips -mlfence-before-ret"));
13943 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13944 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13949 i386_validate_fix (fixS
*fixp
)
13951 if (fixp
->fx_subsy
)
13953 if (fixp
->fx_subsy
== GOT_symbol
)
13955 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13959 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13960 if (fixp
->fx_tcbit2
)
13961 fixp
->fx_r_type
= (fixp
->fx_tcbit
13962 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13963 : BFD_RELOC_X86_64_GOTPCRELX
);
13966 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13971 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13973 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13975 fixp
->fx_subsy
= 0;
13978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13981 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13982 to section. Since PLT32 relocation must be against symbols,
13983 turn such PLT32 relocation into PC32 relocation. */
13985 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
13986 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
13987 && symbol_section_p (fixp
->fx_addsy
))
13988 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
13991 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13992 && fixp
->fx_tcbit2
)
13993 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
14000 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14003 bfd_reloc_code_real_type code
;
14005 switch (fixp
->fx_r_type
)
14007 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14008 case BFD_RELOC_SIZE32
:
14009 case BFD_RELOC_SIZE64
:
14010 if (S_IS_DEFINED (fixp
->fx_addsy
)
14011 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
14013 /* Resolve size relocation against local symbol to size of
14014 the symbol plus addend. */
14015 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
14016 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
14017 && !fits_in_unsigned_long (value
))
14018 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14019 _("symbol size computation overflow"));
14020 fixp
->fx_addsy
= NULL
;
14021 fixp
->fx_subsy
= NULL
;
14022 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
14026 /* Fall through. */
14028 case BFD_RELOC_X86_64_PLT32
:
14029 case BFD_RELOC_X86_64_GOT32
:
14030 case BFD_RELOC_X86_64_GOTPCREL
:
14031 case BFD_RELOC_X86_64_GOTPCRELX
:
14032 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14033 case BFD_RELOC_386_PLT32
:
14034 case BFD_RELOC_386_GOT32
:
14035 case BFD_RELOC_386_GOT32X
:
14036 case BFD_RELOC_386_GOTOFF
:
14037 case BFD_RELOC_386_GOTPC
:
14038 case BFD_RELOC_386_TLS_GD
:
14039 case BFD_RELOC_386_TLS_LDM
:
14040 case BFD_RELOC_386_TLS_LDO_32
:
14041 case BFD_RELOC_386_TLS_IE_32
:
14042 case BFD_RELOC_386_TLS_IE
:
14043 case BFD_RELOC_386_TLS_GOTIE
:
14044 case BFD_RELOC_386_TLS_LE_32
:
14045 case BFD_RELOC_386_TLS_LE
:
14046 case BFD_RELOC_386_TLS_GOTDESC
:
14047 case BFD_RELOC_386_TLS_DESC_CALL
:
14048 case BFD_RELOC_X86_64_TLSGD
:
14049 case BFD_RELOC_X86_64_TLSLD
:
14050 case BFD_RELOC_X86_64_DTPOFF32
:
14051 case BFD_RELOC_X86_64_DTPOFF64
:
14052 case BFD_RELOC_X86_64_GOTTPOFF
:
14053 case BFD_RELOC_X86_64_TPOFF32
:
14054 case BFD_RELOC_X86_64_TPOFF64
:
14055 case BFD_RELOC_X86_64_GOTOFF64
:
14056 case BFD_RELOC_X86_64_GOTPC32
:
14057 case BFD_RELOC_X86_64_GOT64
:
14058 case BFD_RELOC_X86_64_GOTPCREL64
:
14059 case BFD_RELOC_X86_64_GOTPC64
:
14060 case BFD_RELOC_X86_64_GOTPLT64
:
14061 case BFD_RELOC_X86_64_PLTOFF64
:
14062 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14063 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14064 case BFD_RELOC_RVA
:
14065 case BFD_RELOC_VTABLE_ENTRY
:
14066 case BFD_RELOC_VTABLE_INHERIT
:
14068 case BFD_RELOC_32_SECREL
:
14070 code
= fixp
->fx_r_type
;
14072 case BFD_RELOC_X86_64_32S
:
14073 if (!fixp
->fx_pcrel
)
14075 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14076 code
= fixp
->fx_r_type
;
14079 /* Fall through. */
14081 if (fixp
->fx_pcrel
)
14083 switch (fixp
->fx_size
)
14086 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14087 _("can not do %d byte pc-relative relocation"),
14089 code
= BFD_RELOC_32_PCREL
;
14091 case 1: code
= BFD_RELOC_8_PCREL
; break;
14092 case 2: code
= BFD_RELOC_16_PCREL
; break;
14093 case 4: code
= BFD_RELOC_32_PCREL
; break;
14095 case 8: code
= BFD_RELOC_64_PCREL
; break;
14101 switch (fixp
->fx_size
)
14104 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14105 _("can not do %d byte relocation"),
14107 code
= BFD_RELOC_32
;
14109 case 1: code
= BFD_RELOC_8
; break;
14110 case 2: code
= BFD_RELOC_16
; break;
14111 case 4: code
= BFD_RELOC_32
; break;
14113 case 8: code
= BFD_RELOC_64
; break;
14120 if ((code
== BFD_RELOC_32
14121 || code
== BFD_RELOC_32_PCREL
14122 || code
== BFD_RELOC_X86_64_32S
)
14124 && fixp
->fx_addsy
== GOT_symbol
)
14127 code
= BFD_RELOC_386_GOTPC
;
14129 code
= BFD_RELOC_X86_64_GOTPC32
;
14131 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14133 && fixp
->fx_addsy
== GOT_symbol
)
14135 code
= BFD_RELOC_X86_64_GOTPC64
;
14138 rel
= XNEW (arelent
);
14139 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14140 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14142 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14144 if (!use_rela_relocations
)
14146 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14147 vtable entry to be used in the relocation's section offset. */
14148 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14149 rel
->address
= fixp
->fx_offset
;
14150 #if defined (OBJ_COFF) && defined (TE_PE)
14151 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14152 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14157 /* Use the rela in 64bit mode. */
14160 if (disallow_64bit_reloc
)
14163 case BFD_RELOC_X86_64_DTPOFF64
:
14164 case BFD_RELOC_X86_64_TPOFF64
:
14165 case BFD_RELOC_64_PCREL
:
14166 case BFD_RELOC_X86_64_GOTOFF64
:
14167 case BFD_RELOC_X86_64_GOT64
:
14168 case BFD_RELOC_X86_64_GOTPCREL64
:
14169 case BFD_RELOC_X86_64_GOTPC64
:
14170 case BFD_RELOC_X86_64_GOTPLT64
:
14171 case BFD_RELOC_X86_64_PLTOFF64
:
14172 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14173 _("cannot represent relocation type %s in x32 mode"),
14174 bfd_get_reloc_code_name (code
));
14180 if (!fixp
->fx_pcrel
)
14181 rel
->addend
= fixp
->fx_offset
;
14185 case BFD_RELOC_X86_64_PLT32
:
14186 case BFD_RELOC_X86_64_GOT32
:
14187 case BFD_RELOC_X86_64_GOTPCREL
:
14188 case BFD_RELOC_X86_64_GOTPCRELX
:
14189 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14190 case BFD_RELOC_X86_64_TLSGD
:
14191 case BFD_RELOC_X86_64_TLSLD
:
14192 case BFD_RELOC_X86_64_GOTTPOFF
:
14193 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14194 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14195 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14198 rel
->addend
= (section
->vma
14200 + fixp
->fx_addnumber
14201 + md_pcrel_from (fixp
));
14206 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14207 if (rel
->howto
== NULL
)
14209 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14210 _("cannot represent relocation type %s"),
14211 bfd_get_reloc_code_name (code
));
14212 /* Set howto to a garbage value so that we can keep going. */
14213 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14214 gas_assert (rel
->howto
!= NULL
);
14220 #include "tc-i386-intel.c"
14223 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14225 int saved_naked_reg
;
14226 char saved_register_dot
;
14228 saved_naked_reg
= allow_naked_reg
;
14229 allow_naked_reg
= 1;
14230 saved_register_dot
= register_chars
['.'];
14231 register_chars
['.'] = '.';
14232 allow_pseudo_reg
= 1;
14233 expression_and_evaluate (exp
);
14234 allow_pseudo_reg
= 0;
14235 register_chars
['.'] = saved_register_dot
;
14236 allow_naked_reg
= saved_naked_reg
;
14238 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14240 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14242 exp
->X_op
= O_constant
;
14243 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14244 .dw2_regnum
[flag_code
>> 1];
14247 exp
->X_op
= O_illegal
;
14252 tc_x86_frame_initial_instructions (void)
14254 static unsigned int sp_regno
[2];
14256 if (!sp_regno
[flag_code
>> 1])
14258 char *saved_input
= input_line_pointer
;
14259 char sp
[][4] = {"esp", "rsp"};
14262 input_line_pointer
= sp
[flag_code
>> 1];
14263 tc_x86_parse_to_dw2regnum (&exp
);
14264 gas_assert (exp
.X_op
== O_constant
);
14265 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14266 input_line_pointer
= saved_input
;
14269 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14270 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14274 x86_dwarf2_addr_size (void)
14276 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14277 if (x86_elf_abi
== X86_64_X32_ABI
)
14280 return bfd_arch_bits_per_address (stdoutput
) / 8;
14284 i386_elf_section_type (const char *str
, size_t len
)
14286 if (flag_code
== CODE_64BIT
14287 && len
== sizeof ("unwind") - 1
14288 && strncmp (str
, "unwind", 6) == 0)
14289 return SHT_X86_64_UNWIND
;
14296 i386_solaris_fix_up_eh_frame (segT sec
)
14298 if (flag_code
== CODE_64BIT
)
14299 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14305 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14309 exp
.X_op
= O_secrel
;
14310 exp
.X_add_symbol
= symbol
;
14311 exp
.X_add_number
= 0;
14312 emit_expr (&exp
, size
);
14316 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14317 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14320 x86_64_section_letter (int letter
, const char **ptr_msg
)
14322 if (flag_code
== CODE_64BIT
)
14325 return SHF_X86_64_LARGE
;
14327 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14330 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14335 x86_64_section_word (char *str
, size_t len
)
14337 if (len
== 5 && flag_code
== CODE_64BIT
&& startswith (str
, "large"))
14338 return SHF_X86_64_LARGE
;
14344 handle_large_common (int small ATTRIBUTE_UNUSED
)
14346 if (flag_code
!= CODE_64BIT
)
14348 s_comm_internal (0, elf_common_parse
);
14349 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14353 static segT lbss_section
;
14354 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14355 asection
*saved_bss_section
= bss_section
;
14357 if (lbss_section
== NULL
)
14359 flagword applicable
;
14360 segT seg
= now_seg
;
14361 subsegT subseg
= now_subseg
;
14363 /* The .lbss section is for local .largecomm symbols. */
14364 lbss_section
= subseg_new (".lbss", 0);
14365 applicable
= bfd_applicable_section_flags (stdoutput
);
14366 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14367 seg_info (lbss_section
)->bss
= 1;
14369 subseg_set (seg
, subseg
);
14372 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14373 bss_section
= lbss_section
;
14375 s_comm_internal (0, elf_common_parse
);
14377 elf_com_section_ptr
= saved_com_section_ptr
;
14378 bss_section
= saved_bss_section
;
14381 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */