1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2020 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "gdbsupport/x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
49 #include "gdbsupport/byte-vector.h"
52 #include "amd64-ravenscar-thread.h"
54 /* Note that the AMD64 architecture was previously known as x86-64.
55 The latter is (forever) engraved into the canonical system name as
56 returned by config.guess, and used as the name for the AMD64 port
57 of GNU/Linux. The BSD's have renamed their ports to amd64; they
58 don't like to shout. For GDB we prefer the amd64_-prefix over the
59 x86_64_-prefix since it's so much easier to type. */
61 /* Register information. */
63 static const char * const amd64_register_names
[] =
65 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
67 /* %r8 is indeed register number 8. */
68 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
69 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
71 /* %st0 is register number 24. */
72 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
75 /* %xmm0 is register number 40. */
76 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
77 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
81 static const char * const amd64_ymm_names
[] =
83 "ymm0", "ymm1", "ymm2", "ymm3",
84 "ymm4", "ymm5", "ymm6", "ymm7",
85 "ymm8", "ymm9", "ymm10", "ymm11",
86 "ymm12", "ymm13", "ymm14", "ymm15"
89 static const char * const amd64_ymm_avx512_names
[] =
91 "ymm16", "ymm17", "ymm18", "ymm19",
92 "ymm20", "ymm21", "ymm22", "ymm23",
93 "ymm24", "ymm25", "ymm26", "ymm27",
94 "ymm28", "ymm29", "ymm30", "ymm31"
97 static const char * const amd64_ymmh_names
[] =
99 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
100 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
101 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
102 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
105 static const char * const amd64_ymmh_avx512_names
[] =
107 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
108 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
109 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
110 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
113 static const char * const amd64_mpx_names
[] =
115 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
118 static const char * const amd64_k_names
[] =
120 "k0", "k1", "k2", "k3",
121 "k4", "k5", "k6", "k7"
124 static const char * const amd64_zmmh_names
[] =
126 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
127 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
128 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
129 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
130 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
131 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
132 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
133 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
136 static const char * const amd64_zmm_names
[] =
138 "zmm0", "zmm1", "zmm2", "zmm3",
139 "zmm4", "zmm5", "zmm6", "zmm7",
140 "zmm8", "zmm9", "zmm10", "zmm11",
141 "zmm12", "zmm13", "zmm14", "zmm15",
142 "zmm16", "zmm17", "zmm18", "zmm19",
143 "zmm20", "zmm21", "zmm22", "zmm23",
144 "zmm24", "zmm25", "zmm26", "zmm27",
145 "zmm28", "zmm29", "zmm30", "zmm31"
148 static const char * const amd64_xmm_avx512_names
[] = {
149 "xmm16", "xmm17", "xmm18", "xmm19",
150 "xmm20", "xmm21", "xmm22", "xmm23",
151 "xmm24", "xmm25", "xmm26", "xmm27",
152 "xmm28", "xmm29", "xmm30", "xmm31"
155 static const char * const amd64_pkeys_names
[] = {
159 /* DWARF Register Number Mapping as defined in the System V psABI,
162 static int amd64_dwarf_regmap
[] =
164 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
165 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
166 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
167 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
169 /* Frame Pointer Register RBP. */
172 /* Stack Pointer Register RSP. */
175 /* Extended Integer Registers 8 - 15. */
176 AMD64_R8_REGNUM
, /* %r8 */
177 AMD64_R9_REGNUM
, /* %r9 */
178 AMD64_R10_REGNUM
, /* %r10 */
179 AMD64_R11_REGNUM
, /* %r11 */
180 AMD64_R12_REGNUM
, /* %r12 */
181 AMD64_R13_REGNUM
, /* %r13 */
182 AMD64_R14_REGNUM
, /* %r14 */
183 AMD64_R15_REGNUM
, /* %r15 */
185 /* Return Address RA. Mapped to RIP. */
188 /* SSE Registers 0 - 7. */
189 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
190 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
191 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
192 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
194 /* Extended SSE Registers 8 - 15. */
195 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
196 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
197 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
198 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
200 /* Floating Point Registers 0-7. */
201 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
202 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
203 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
204 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
206 /* MMX Registers 0 - 7.
207 We have to handle those registers specifically, as their register
208 number within GDB depends on the target (or they may even not be
209 available at all). */
210 -1, -1, -1, -1, -1, -1, -1, -1,
212 /* Control and Status Flags Register. */
215 /* Selector Registers. */
225 /* Segment Base Address Registers. */
231 /* Special Selector Registers. */
235 /* Floating Point Control Registers. */
241 static const int amd64_dwarf_regmap_len
=
242 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
244 /* Convert DWARF register number REG to the appropriate register
245 number used by GDB. */
248 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
250 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
251 int ymm0_regnum
= tdep
->ymm0_regnum
;
254 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
255 regnum
= amd64_dwarf_regmap
[reg
];
258 && i386_xmm_regnum_p (gdbarch
, regnum
))
259 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
264 /* Map architectural register numbers to gdb register numbers. */
266 static const int amd64_arch_regmap
[16] =
268 AMD64_RAX_REGNUM
, /* %rax */
269 AMD64_RCX_REGNUM
, /* %rcx */
270 AMD64_RDX_REGNUM
, /* %rdx */
271 AMD64_RBX_REGNUM
, /* %rbx */
272 AMD64_RSP_REGNUM
, /* %rsp */
273 AMD64_RBP_REGNUM
, /* %rbp */
274 AMD64_RSI_REGNUM
, /* %rsi */
275 AMD64_RDI_REGNUM
, /* %rdi */
276 AMD64_R8_REGNUM
, /* %r8 */
277 AMD64_R9_REGNUM
, /* %r9 */
278 AMD64_R10_REGNUM
, /* %r10 */
279 AMD64_R11_REGNUM
, /* %r11 */
280 AMD64_R12_REGNUM
, /* %r12 */
281 AMD64_R13_REGNUM
, /* %r13 */
282 AMD64_R14_REGNUM
, /* %r14 */
283 AMD64_R15_REGNUM
/* %r15 */
286 static const int amd64_arch_regmap_len
=
287 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
289 /* Convert architectural register number REG to the appropriate register
290 number used by GDB. */
293 amd64_arch_reg_to_regnum (int reg
)
295 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
297 return amd64_arch_regmap
[reg
];
300 /* Register names for byte pseudo-registers. */
302 static const char * const amd64_byte_names
[] =
304 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
305 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
306 "ah", "bh", "ch", "dh"
309 /* Number of lower byte registers. */
310 #define AMD64_NUM_LOWER_BYTE_REGS 16
312 /* Register names for word pseudo-registers. */
314 static const char * const amd64_word_names
[] =
316 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
317 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
320 /* Register names for dword pseudo-registers. */
322 static const char * const amd64_dword_names
[] =
324 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
325 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
329 /* Return the name of register REGNUM. */
332 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
334 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
335 if (i386_byte_regnum_p (gdbarch
, regnum
))
336 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
337 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
338 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
339 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
340 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
341 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
342 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
343 else if (i386_word_regnum_p (gdbarch
, regnum
))
344 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
345 else if (i386_dword_regnum_p (gdbarch
, regnum
))
346 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
348 return i386_pseudo_register_name (gdbarch
, regnum
);
351 static struct value
*
352 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
353 readable_regcache
*regcache
,
356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
358 value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
359 VALUE_LVAL (result_value
) = lval_register
;
360 VALUE_REGNUM (result_value
) = regnum
;
361 gdb_byte
*buf
= value_contents_raw (result_value
);
363 if (i386_byte_regnum_p (gdbarch
, regnum
))
365 int gpnum
= regnum
- tdep
->al_regnum
;
367 /* Extract (always little endian). */
368 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
370 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
371 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
373 /* Special handling for AH, BH, CH, DH. */
374 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
375 if (status
== REG_VALID
)
376 memcpy (buf
, raw_buf
+ 1, 1);
378 mark_value_bytes_unavailable (result_value
, 0,
379 TYPE_LENGTH (value_type (result_value
)));
383 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
384 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
385 if (status
== REG_VALID
)
386 memcpy (buf
, raw_buf
, 1);
388 mark_value_bytes_unavailable (result_value
, 0,
389 TYPE_LENGTH (value_type (result_value
)));
392 else if (i386_dword_regnum_p (gdbarch
, regnum
))
394 int gpnum
= regnum
- tdep
->eax_regnum
;
395 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
396 /* Extract (always little endian). */
397 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
398 if (status
== REG_VALID
)
399 memcpy (buf
, raw_buf
, 4);
401 mark_value_bytes_unavailable (result_value
, 0,
402 TYPE_LENGTH (value_type (result_value
)));
405 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
412 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
413 struct regcache
*regcache
,
414 int regnum
, const gdb_byte
*buf
)
416 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
418 if (i386_byte_regnum_p (gdbarch
, regnum
))
420 int gpnum
= regnum
- tdep
->al_regnum
;
422 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
424 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
425 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
427 /* Read ... AH, BH, CH, DH. */
428 regcache
->raw_read (gpnum
, raw_buf
);
429 /* ... Modify ... (always little endian). */
430 memcpy (raw_buf
+ 1, buf
, 1);
432 regcache
->raw_write (gpnum
, raw_buf
);
436 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
439 regcache
->raw_read (gpnum
, raw_buf
);
440 /* ... Modify ... (always little endian). */
441 memcpy (raw_buf
, buf
, 1);
443 regcache
->raw_write (gpnum
, raw_buf
);
446 else if (i386_dword_regnum_p (gdbarch
, regnum
))
448 int gpnum
= regnum
- tdep
->eax_regnum
;
449 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
452 regcache
->raw_read (gpnum
, raw_buf
);
453 /* ... Modify ... (always little endian). */
454 memcpy (raw_buf
, buf
, 4);
456 regcache
->raw_write (gpnum
, raw_buf
);
459 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
462 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
465 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
466 struct agent_expr
*ax
, int regnum
)
468 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
470 if (i386_byte_regnum_p (gdbarch
, regnum
))
472 int gpnum
= regnum
- tdep
->al_regnum
;
474 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
475 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
477 ax_reg_mask (ax
, gpnum
);
480 else if (i386_dword_regnum_p (gdbarch
, regnum
))
482 int gpnum
= regnum
- tdep
->eax_regnum
;
484 ax_reg_mask (ax
, gpnum
);
488 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
493 /* Register classes as defined in the psABI. */
507 /* Return the union class of CLASS1 and CLASS2. See the psABI for
510 static enum amd64_reg_class
511 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
513 /* Rule (a): If both classes are equal, this is the resulting class. */
514 if (class1
== class2
)
517 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
518 is the other class. */
519 if (class1
== AMD64_NO_CLASS
)
521 if (class2
== AMD64_NO_CLASS
)
524 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
525 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
528 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
529 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
530 return AMD64_INTEGER
;
532 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
533 MEMORY is used as class. */
534 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
535 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
536 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
539 /* Rule (f): Otherwise class SSE is used. */
543 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
545 /* Return true if TYPE is a structure or union with unaligned fields. */
548 amd64_has_unaligned_fields (struct type
*type
)
550 if (type
->code () == TYPE_CODE_STRUCT
551 || type
->code () == TYPE_CODE_UNION
)
553 for (int i
= 0; i
< type
->num_fields (); i
++)
555 struct type
*subtype
= check_typedef (type
->field (i
).type ());
556 int bitpos
= TYPE_FIELD_BITPOS (type
, i
);
557 int align
= type_align(subtype
);
559 /* Ignore static fields, empty fields (for example nested
560 empty structures), and bitfields (these are handled by
562 if (field_is_static (&type
->field (i
))
563 || (TYPE_FIELD_BITSIZE (type
, i
) == 0
564 && TYPE_LENGTH (subtype
) == 0)
565 || TYPE_FIELD_PACKED (type
, i
))
571 int bytepos
= bitpos
/ 8;
572 if (bytepos
% align
!= 0)
575 if (amd64_has_unaligned_fields (subtype
))
583 /* Classify field I of TYPE starting at BITOFFSET according to the rules for
584 structures and union types, and store the result in THECLASS. */
587 amd64_classify_aggregate_field (struct type
*type
, int i
,
588 enum amd64_reg_class theclass
[2],
589 unsigned int bitoffset
)
591 struct type
*subtype
= check_typedef (type
->field (i
).type ());
592 int bitpos
= bitoffset
+ TYPE_FIELD_BITPOS (type
, i
);
593 int pos
= bitpos
/ 64;
594 enum amd64_reg_class subclass
[2];
595 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
599 bitsize
= TYPE_LENGTH (subtype
) * 8;
600 endpos
= (bitpos
+ bitsize
- 1) / 64;
602 /* Ignore static fields, or empty fields, for example nested
604 if (field_is_static (&type
->field (i
)) || bitsize
== 0)
607 if (subtype
->code () == TYPE_CODE_STRUCT
608 || subtype
->code () == TYPE_CODE_UNION
)
610 /* Each field of an object is classified recursively. */
612 for (j
= 0; j
< subtype
->num_fields (); j
++)
613 amd64_classify_aggregate_field (subtype
, j
, theclass
, bitpos
);
617 gdb_assert (pos
== 0 || pos
== 1);
619 amd64_classify (subtype
, subclass
);
620 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
621 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
622 /* This is a bit of an odd case: We have a field that would
623 normally fit in one of the two eightbytes, except that
624 it is placed in a way that this field straddles them.
625 This has been seen with a structure containing an array.
627 The ABI is a bit unclear in this case, but we assume that
628 this field's class (stored in subclass[0]) must also be merged
629 into class[1]. In other words, our field has a piece stored
630 in the second eight-byte, and thus its class applies to
631 the second eight-byte as well.
633 In the case where the field length exceeds 8 bytes,
634 it should not be necessary to merge the field class
635 into class[1]. As LEN > 8, subclass[1] is necessarily
636 different from AMD64_NO_CLASS. If subclass[1] is equal
637 to subclass[0], then the normal class[1]/subclass[1]
638 merging will take care of everything. For subclass[1]
639 to be different from subclass[0], I can only see the case
640 where we have a SSE/SSEUP or X87/X87UP pair, which both
641 use up all 16 bytes of the aggregate, and are already
642 handled just fine (because each portion sits on its own
644 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
646 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
649 /* Classify TYPE according to the rules for aggregate (structures and
650 arrays) and union types, and store the result in CLASS. */
653 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
655 /* 1. If the size of an object is larger than two eightbytes, or it has
656 unaligned fields, it has class memory. */
657 if (TYPE_LENGTH (type
) > 16 || amd64_has_unaligned_fields (type
))
659 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
663 /* 2. Both eightbytes get initialized to class NO_CLASS. */
664 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
666 /* 3. Each field of an object is classified recursively so that
667 always two fields are considered. The resulting class is
668 calculated according to the classes of the fields in the
671 if (type
->code () == TYPE_CODE_ARRAY
)
673 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
675 /* All fields in an array have the same type. */
676 amd64_classify (subtype
, theclass
);
677 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
678 theclass
[1] = theclass
[0];
684 /* Structure or union. */
685 gdb_assert (type
->code () == TYPE_CODE_STRUCT
686 || type
->code () == TYPE_CODE_UNION
);
688 for (i
= 0; i
< type
->num_fields (); i
++)
689 amd64_classify_aggregate_field (type
, i
, theclass
, 0);
692 /* 4. Then a post merger cleanup is done: */
694 /* Rule (a): If one of the classes is MEMORY, the whole argument is
696 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
697 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
699 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
701 if (theclass
[0] == AMD64_SSEUP
)
702 theclass
[0] = AMD64_SSE
;
703 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
704 theclass
[1] = AMD64_SSE
;
707 /* Classify TYPE, and store the result in CLASS. */
710 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
712 enum type_code code
= type
->code ();
713 int len
= TYPE_LENGTH (type
);
715 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
717 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
718 long, long long, and pointers are in the INTEGER class. Similarly,
719 range types, used by languages such as Ada, are also in the INTEGER
721 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
722 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
723 || code
== TYPE_CODE_CHAR
724 || code
== TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type
))
725 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
726 theclass
[0] = AMD64_INTEGER
;
728 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
730 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
731 && (len
== 4 || len
== 8))
733 theclass
[0] = AMD64_SSE
;
735 /* Arguments of types __float128, _Decimal128 and __m128 are split into
736 two halves. The least significant ones belong to class SSE, the most
737 significant one to class SSEUP. */
738 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
739 /* FIXME: __float128, __m128. */
740 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
742 /* The 64-bit mantissa of arguments of type long double belongs to
743 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
745 else if (code
== TYPE_CODE_FLT
&& len
== 16)
746 /* Class X87 and X87UP. */
747 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
749 /* Arguments of complex T where T is one of the types float or
750 double get treated as if they are implemented as:
758 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
759 theclass
[0] = AMD64_SSE
;
760 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
761 theclass
[0] = theclass
[1] = AMD64_SSE
;
763 /* A variable of type complex long double is classified as type
765 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
766 theclass
[0] = AMD64_COMPLEX_X87
;
769 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
770 || code
== TYPE_CODE_UNION
)
771 amd64_classify_aggregate (type
, theclass
);
774 static enum return_value_convention
775 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
776 struct type
*type
, struct regcache
*regcache
,
777 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
779 enum amd64_reg_class theclass
[2];
780 int len
= TYPE_LENGTH (type
);
781 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
782 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
787 gdb_assert (!(readbuf
&& writebuf
));
789 /* 1. Classify the return type with the classification algorithm. */
790 amd64_classify (type
, theclass
);
792 /* 2. If the type has class MEMORY, then the caller provides space
793 for the return value and passes the address of this storage in
794 %rdi as if it were the first argument to the function. In effect,
795 this address becomes a hidden first argument.
797 On return %rax will contain the address that has been passed in
798 by the caller in %rdi. */
799 if (theclass
[0] == AMD64_MEMORY
)
801 /* As indicated by the comment above, the ABI guarantees that we
802 can always find the return value just after the function has
809 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
810 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
813 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
816 /* 8. If the class is COMPLEX_X87, the real part of the value is
817 returned in %st0 and the imaginary part in %st1. */
818 if (theclass
[0] == AMD64_COMPLEX_X87
)
822 regcache
->raw_read (AMD64_ST0_REGNUM
, readbuf
);
823 regcache
->raw_read (AMD64_ST1_REGNUM
, readbuf
+ 16);
828 i387_return_value (gdbarch
, regcache
);
829 regcache
->raw_write (AMD64_ST0_REGNUM
, writebuf
);
830 regcache
->raw_write (AMD64_ST1_REGNUM
, writebuf
+ 16);
832 /* Fix up the tag word such that both %st(0) and %st(1) are
834 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
837 return RETURN_VALUE_REGISTER_CONVENTION
;
840 gdb_assert (theclass
[1] != AMD64_MEMORY
);
841 gdb_assert (len
<= 16);
843 for (i
= 0; len
> 0; i
++, len
-= 8)
851 /* 3. If the class is INTEGER, the next available register
852 of the sequence %rax, %rdx is used. */
853 regnum
= integer_regnum
[integer_reg
++];
857 /* 4. If the class is SSE, the next available SSE register
858 of the sequence %xmm0, %xmm1 is used. */
859 regnum
= sse_regnum
[sse_reg
++];
863 /* 5. If the class is SSEUP, the eightbyte is passed in the
864 upper half of the last used SSE register. */
865 gdb_assert (sse_reg
> 0);
866 regnum
= sse_regnum
[sse_reg
- 1];
871 /* 6. If the class is X87, the value is returned on the X87
872 stack in %st0 as 80-bit x87 number. */
873 regnum
= AMD64_ST0_REGNUM
;
875 i387_return_value (gdbarch
, regcache
);
879 /* 7. If the class is X87UP, the value is returned together
880 with the previous X87 value in %st0. */
881 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
882 regnum
= AMD64_ST0_REGNUM
;
891 gdb_assert (!"Unexpected register class.");
894 gdb_assert (regnum
!= -1);
897 regcache
->raw_read_part (regnum
, offset
, std::min (len
, 8),
900 regcache
->raw_write_part (regnum
, offset
, std::min (len
, 8),
904 return RETURN_VALUE_REGISTER_CONVENTION
;
909 amd64_push_arguments (struct regcache
*regcache
, int nargs
, struct value
**args
,
910 CORE_ADDR sp
, function_call_return_method return_method
)
912 static int integer_regnum
[] =
914 AMD64_RDI_REGNUM
, /* %rdi */
915 AMD64_RSI_REGNUM
, /* %rsi */
916 AMD64_RDX_REGNUM
, /* %rdx */
917 AMD64_RCX_REGNUM
, /* %rcx */
918 AMD64_R8_REGNUM
, /* %r8 */
919 AMD64_R9_REGNUM
/* %r9 */
921 static int sse_regnum
[] =
923 /* %xmm0 ... %xmm7 */
924 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
925 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
926 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
927 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
929 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
930 int num_stack_args
= 0;
931 int num_elements
= 0;
937 /* Reserve a register for the "hidden" argument. */
938 if (return_method
== return_method_struct
)
941 for (i
= 0; i
< nargs
; i
++)
943 struct type
*type
= value_type (args
[i
]);
944 int len
= TYPE_LENGTH (type
);
945 enum amd64_reg_class theclass
[2];
946 int needed_integer_regs
= 0;
947 int needed_sse_regs
= 0;
950 /* Classify argument. */
951 amd64_classify (type
, theclass
);
953 /* Calculate the number of integer and SSE registers needed for
955 for (j
= 0; j
< 2; j
++)
957 if (theclass
[j
] == AMD64_INTEGER
)
958 needed_integer_regs
++;
959 else if (theclass
[j
] == AMD64_SSE
)
963 /* Check whether enough registers are available, and if the
964 argument should be passed in registers at all. */
965 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
966 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
967 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
969 /* The argument will be passed on the stack. */
970 num_elements
+= ((len
+ 7) / 8);
971 stack_args
[num_stack_args
++] = args
[i
];
975 /* The argument will be passed in registers. */
976 const gdb_byte
*valbuf
= value_contents (args
[i
]);
979 gdb_assert (len
<= 16);
981 for (j
= 0; len
> 0; j
++, len
-= 8)
989 regnum
= integer_regnum
[integer_reg
++];
993 regnum
= sse_regnum
[sse_reg
++];
997 gdb_assert (sse_reg
> 0);
998 regnum
= sse_regnum
[sse_reg
- 1];
1002 case AMD64_NO_CLASS
:
1006 gdb_assert (!"Unexpected register class.");
1009 gdb_assert (regnum
!= -1);
1010 memset (buf
, 0, sizeof buf
);
1011 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
1012 regcache
->raw_write_part (regnum
, offset
, 8, buf
);
1017 /* Allocate space for the arguments on the stack. */
1018 sp
-= num_elements
* 8;
1020 /* The psABI says that "The end of the input argument area shall be
1021 aligned on a 16 byte boundary." */
1024 /* Write out the arguments to the stack. */
1025 for (i
= 0; i
< num_stack_args
; i
++)
1027 struct type
*type
= value_type (stack_args
[i
]);
1028 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
1029 int len
= TYPE_LENGTH (type
);
1031 write_memory (sp
+ element
* 8, valbuf
, len
);
1032 element
+= ((len
+ 7) / 8);
1035 /* The psABI says that "For calls that may call functions that use
1036 varargs or stdargs (prototype-less calls or calls to functions
1037 containing ellipsis (...) in the declaration) %al is used as
1038 hidden argument to specify the number of SSE registers used. */
1039 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
1044 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1045 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1046 int nargs
, struct value
**args
, CORE_ADDR sp
,
1047 function_call_return_method return_method
,
1048 CORE_ADDR struct_addr
)
1050 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1053 /* BND registers can be in arbitrary values at the moment of the
1054 inferior call. This can cause boundary violations that are not
1055 due to a real bug or even desired by the user. The best to be done
1056 is set the BND registers to allow access to the whole memory, INIT
1057 state, before pushing the inferior call. */
1058 i387_reset_bnd_regs (gdbarch
, regcache
);
1060 /* Pass arguments. */
1061 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, return_method
);
1063 /* Pass "hidden" argument". */
1064 if (return_method
== return_method_struct
)
1066 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1067 regcache
->cooked_write (AMD64_RDI_REGNUM
, buf
);
1070 /* Store return address. */
1072 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1073 write_memory (sp
, buf
, 8);
1075 /* Finally, update the stack pointer... */
1076 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1077 regcache
->cooked_write (AMD64_RSP_REGNUM
, buf
);
1079 /* ...and fake a frame pointer. */
1080 regcache
->cooked_write (AMD64_RBP_REGNUM
, buf
);
1085 /* Displaced instruction handling. */
1087 /* A partially decoded instruction.
1088 This contains enough details for displaced stepping purposes. */
1092 /* The number of opcode bytes. */
1094 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1096 int enc_prefix_offset
;
1097 /* The offset to the first opcode byte. */
1099 /* The offset to the modrm byte or -1 if not present. */
1102 /* The raw instruction. */
1106 struct amd64_displaced_step_closure
: public displaced_step_closure
1108 amd64_displaced_step_closure (int insn_buf_len
)
1109 : insn_buf (insn_buf_len
, 0)
1112 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1117 /* Details of the instruction. */
1118 struct amd64_insn insn_details
;
1120 /* The possibly modified insn. */
1121 gdb::byte_vector insn_buf
;
1124 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1125 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1126 at which point delete these in favor of libopcodes' versions). */
1128 static const unsigned char onebyte_has_modrm
[256] = {
1129 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1130 /* ------------------------------- */
1131 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1132 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1133 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1134 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1135 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1136 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1137 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1138 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1139 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1140 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1141 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1142 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1143 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1144 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1145 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1146 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1147 /* ------------------------------- */
1148 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1151 static const unsigned char twobyte_has_modrm
[256] = {
1152 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1153 /* ------------------------------- */
1154 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1155 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1156 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1157 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1158 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1159 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1160 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1161 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1162 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1163 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1164 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1165 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1166 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1167 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1168 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1169 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1170 /* ------------------------------- */
1171 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1174 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1177 rex_prefix_p (gdb_byte pfx
)
1179 return REX_PREFIX_P (pfx
);
1182 /* True if PFX is the start of the 2-byte VEX prefix. */
1185 vex2_prefix_p (gdb_byte pfx
)
1190 /* True if PFX is the start of the 3-byte VEX prefix. */
1193 vex3_prefix_p (gdb_byte pfx
)
1198 /* Skip the legacy instruction prefixes in INSN.
1199 We assume INSN is properly sentineled so we don't have to worry
1200 about falling off the end of the buffer. */
1203 amd64_skip_prefixes (gdb_byte
*insn
)
1209 case DATA_PREFIX_OPCODE
:
1210 case ADDR_PREFIX_OPCODE
:
1211 case CS_PREFIX_OPCODE
:
1212 case DS_PREFIX_OPCODE
:
1213 case ES_PREFIX_OPCODE
:
1214 case FS_PREFIX_OPCODE
:
1215 case GS_PREFIX_OPCODE
:
1216 case SS_PREFIX_OPCODE
:
1217 case LOCK_PREFIX_OPCODE
:
1218 case REPE_PREFIX_OPCODE
:
1219 case REPNE_PREFIX_OPCODE
:
1231 /* Return an integer register (other than RSP) that is unused as an input
1233 In order to not require adding a rex prefix if the insn doesn't already
1234 have one, the result is restricted to RAX ... RDI, sans RSP.
1235 The register numbering of the result follows architecture ordering,
1239 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1241 /* 1 bit for each reg */
1242 int used_regs_mask
= 0;
1244 /* There can be at most 3 int regs used as inputs in an insn, and we have
1245 7 to choose from (RAX ... RDI, sans RSP).
1246 This allows us to take a conservative approach and keep things simple.
1247 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1248 that implicitly specify RAX. */
1251 used_regs_mask
|= 1 << EAX_REG_NUM
;
1252 /* Similarily avoid RDX, implicit operand in divides. */
1253 used_regs_mask
|= 1 << EDX_REG_NUM
;
1255 used_regs_mask
|= 1 << ESP_REG_NUM
;
1257 /* If the opcode is one byte long and there's no ModRM byte,
1258 assume the opcode specifies a register. */
1259 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1260 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1262 /* Mark used regs in the modrm/sib bytes. */
1263 if (details
->modrm_offset
!= -1)
1265 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1266 int mod
= MODRM_MOD_FIELD (modrm
);
1267 int reg
= MODRM_REG_FIELD (modrm
);
1268 int rm
= MODRM_RM_FIELD (modrm
);
1269 int have_sib
= mod
!= 3 && rm
== 4;
1271 /* Assume the reg field of the modrm byte specifies a register. */
1272 used_regs_mask
|= 1 << reg
;
1276 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1277 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1278 used_regs_mask
|= 1 << base
;
1279 used_regs_mask
|= 1 << idx
;
1283 used_regs_mask
|= 1 << rm
;
1287 gdb_assert (used_regs_mask
< 256);
1288 gdb_assert (used_regs_mask
!= 255);
1290 /* Finally, find a free reg. */
1294 for (i
= 0; i
< 8; ++i
)
1296 if (! (used_regs_mask
& (1 << i
)))
1300 /* We shouldn't get here. */
1301 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1305 /* Extract the details of INSN that we need. */
1308 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1310 gdb_byte
*start
= insn
;
1313 details
->raw_insn
= insn
;
1315 details
->opcode_len
= -1;
1316 details
->enc_prefix_offset
= -1;
1317 details
->opcode_offset
= -1;
1318 details
->modrm_offset
= -1;
1320 /* Skip legacy instruction prefixes. */
1321 insn
= amd64_skip_prefixes (insn
);
1323 /* Skip REX/VEX instruction encoding prefixes. */
1324 if (rex_prefix_p (*insn
))
1326 details
->enc_prefix_offset
= insn
- start
;
1329 else if (vex2_prefix_p (*insn
))
1331 /* Don't record the offset in this case because this prefix has
1332 no REX.B equivalent. */
1335 else if (vex3_prefix_p (*insn
))
1337 details
->enc_prefix_offset
= insn
- start
;
1341 details
->opcode_offset
= insn
- start
;
1343 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1345 /* Two or three-byte opcode. */
1347 need_modrm
= twobyte_has_modrm
[*insn
];
1349 /* Check for three-byte opcode. */
1359 details
->opcode_len
= 3;
1362 details
->opcode_len
= 2;
1368 /* One-byte opcode. */
1369 need_modrm
= onebyte_has_modrm
[*insn
];
1370 details
->opcode_len
= 1;
1376 details
->modrm_offset
= insn
- start
;
1380 /* Update %rip-relative addressing in INSN.
1382 %rip-relative addressing only uses a 32-bit displacement.
1383 32 bits is not enough to be guaranteed to cover the distance between where
1384 the real instruction is and where its copy is.
1385 Convert the insn to use base+disp addressing.
1386 We set base = pc + insn_length so we can leave disp unchanged. */
1389 fixup_riprel (struct gdbarch
*gdbarch
, amd64_displaced_step_closure
*dsc
,
1390 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1392 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1393 int modrm_offset
= insn_details
->modrm_offset
;
1394 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1397 int arch_tmp_regno
, tmp_regno
;
1398 ULONGEST orig_value
;
1400 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1403 /* Compute the rip-relative address. */
1404 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
.data (),
1405 dsc
->insn_buf
.size (), from
);
1406 rip_base
= from
+ insn_length
;
1408 /* We need a register to hold the address.
1409 Pick one not used in the insn.
1410 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1411 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1412 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1414 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1415 static constexpr gdb_byte VEX3_NOT_B
= 0x20;
1417 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1418 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1420 if (insn_details
->enc_prefix_offset
!= -1)
1422 gdb_byte
*pfx
= &dsc
->insn_buf
[insn_details
->enc_prefix_offset
];
1423 if (rex_prefix_p (pfx
[0]))
1425 else if (vex3_prefix_p (pfx
[0]))
1426 pfx
[1] |= VEX3_NOT_B
;
1428 gdb_assert_not_reached ("unhandled prefix");
1431 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1432 dsc
->tmp_regno
= tmp_regno
;
1433 dsc
->tmp_save
= orig_value
;
1436 /* Convert the ModRM field to be base+disp. */
1437 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1438 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1440 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1442 displaced_debug_printf ("%%rip-relative addressing used.");
1443 displaced_debug_printf ("using temp reg %d, old value %s, new value %s",
1444 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1445 paddress (gdbarch
, rip_base
));
1449 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1450 amd64_displaced_step_closure
*dsc
,
1451 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1453 const struct amd64_insn
*details
= &dsc
->insn_details
;
1455 if (details
->modrm_offset
!= -1)
1457 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1459 if ((modrm
& 0xc7) == 0x05)
1461 /* The insn uses rip-relative addressing.
1463 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1468 displaced_step_closure_up
1469 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1470 CORE_ADDR from
, CORE_ADDR to
,
1471 struct regcache
*regs
)
1473 int len
= gdbarch_max_insn_length (gdbarch
);
1474 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1475 continually watch for running off the end of the buffer. */
1476 int fixup_sentinel_space
= len
;
1477 std::unique_ptr
<amd64_displaced_step_closure
> dsc
1478 (new amd64_displaced_step_closure (len
+ fixup_sentinel_space
));
1479 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1480 struct amd64_insn
*details
= &dsc
->insn_details
;
1482 read_memory (from
, buf
, len
);
1484 /* Set up the sentinel space so we don't have to worry about running
1485 off the end of the buffer. An excessive number of leading prefixes
1486 could otherwise cause this. */
1487 memset (buf
+ len
, 0, fixup_sentinel_space
);
1489 amd64_get_insn_details (buf
, details
);
1491 /* GDB may get control back after the insn after the syscall.
1492 Presumably this is a kernel bug.
1493 If this is a syscall, make sure there's a nop afterwards. */
1497 if (amd64_syscall_p (details
, &syscall_length
))
1498 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1501 /* Modify the insn to cope with the address where it will be executed from.
1502 In particular, handle any rip-relative addressing. */
1503 fixup_displaced_copy (gdbarch
, dsc
.get (), from
, to
, regs
);
1505 write_memory (to
, buf
, len
);
1507 displaced_debug_printf ("copy %s->%s: %s",
1508 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1509 displaced_step_dump_bytes (buf
, len
).c_str ());
1511 /* This is a work around for a problem with g++ 4.8. */
1512 return displaced_step_closure_up (dsc
.release ());
1516 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1518 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1520 if (insn
[0] == 0xff)
1522 /* jump near, absolute indirect (/4) */
1523 if ((insn
[1] & 0x38) == 0x20)
1526 /* jump far, absolute indirect (/5) */
1527 if ((insn
[1] & 0x38) == 0x28)
1534 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1537 amd64_jmp_p (const struct amd64_insn
*details
)
1539 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1541 /* jump short, relative. */
1542 if (insn
[0] == 0xeb)
1545 /* jump near, relative. */
1546 if (insn
[0] == 0xe9)
1549 return amd64_absolute_jmp_p (details
);
1553 amd64_absolute_call_p (const struct amd64_insn
*details
)
1555 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1557 if (insn
[0] == 0xff)
1559 /* Call near, absolute indirect (/2) */
1560 if ((insn
[1] & 0x38) == 0x10)
1563 /* Call far, absolute indirect (/3) */
1564 if ((insn
[1] & 0x38) == 0x18)
1572 amd64_ret_p (const struct amd64_insn
*details
)
1574 /* NOTE: gcc can emit "repz ; ret". */
1575 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1579 case 0xc2: /* ret near, pop N bytes */
1580 case 0xc3: /* ret near */
1581 case 0xca: /* ret far, pop N bytes */
1582 case 0xcb: /* ret far */
1583 case 0xcf: /* iret */
1592 amd64_call_p (const struct amd64_insn
*details
)
1594 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1596 if (amd64_absolute_call_p (details
))
1599 /* call near, relative */
1600 if (insn
[0] == 0xe8)
1606 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1607 length in bytes. Otherwise, return zero. */
1610 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1612 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1614 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1623 /* Classify the instruction at ADDR using PRED.
1624 Throw an error if the memory can't be read. */
1627 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1628 int (*pred
) (const struct amd64_insn
*))
1630 struct amd64_insn details
;
1632 int len
, classification
;
1634 len
= gdbarch_max_insn_length (gdbarch
);
1635 buf
= (gdb_byte
*) alloca (len
);
1637 read_code (addr
, buf
, len
);
1638 amd64_get_insn_details (buf
, &details
);
1640 classification
= pred (&details
);
1642 return classification
;
1645 /* The gdbarch insn_is_call method. */
1648 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1650 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1653 /* The gdbarch insn_is_ret method. */
1656 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1658 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1661 /* The gdbarch insn_is_jump method. */
1664 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1666 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1669 /* Fix up the state of registers and memory after having single-stepped
1670 a displaced instruction. */
1673 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1674 struct displaced_step_closure
*dsc_
,
1675 CORE_ADDR from
, CORE_ADDR to
,
1676 struct regcache
*regs
)
1678 amd64_displaced_step_closure
*dsc
= (amd64_displaced_step_closure
*) dsc_
;
1679 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1680 /* The offset we applied to the instruction's address. */
1681 ULONGEST insn_offset
= to
- from
;
1682 gdb_byte
*insn
= dsc
->insn_buf
.data ();
1683 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1685 displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
1686 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1689 /* If we used a tmp reg, restore it. */
1693 displaced_debug_printf ("restoring reg %d to %s",
1694 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1695 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1698 /* The list of issues to contend with here is taken from
1699 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1700 Yay for Free Software! */
1702 /* Relocate the %rip back to the program's instruction stream,
1705 /* Except in the case of absolute or indirect jump or call
1706 instructions, or a return instruction, the new rip is relative to
1707 the displaced instruction; make it relative to the original insn.
1708 Well, signal handler returns don't need relocation either, but we use the
1709 value of %rip to recognize those; see below. */
1710 if (! amd64_absolute_jmp_p (insn_details
)
1711 && ! amd64_absolute_call_p (insn_details
)
1712 && ! amd64_ret_p (insn_details
))
1717 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1719 /* A signal trampoline system call changes the %rip, resuming
1720 execution of the main program after the signal handler has
1721 returned. That makes them like 'return' instructions; we
1722 shouldn't relocate %rip.
1724 But most system calls don't, and we do need to relocate %rip.
1726 Our heuristic for distinguishing these cases: if stepping
1727 over the system call instruction left control directly after
1728 the instruction, the we relocate --- control almost certainly
1729 doesn't belong in the displaced copy. Otherwise, we assume
1730 the instruction has put control where it belongs, and leave
1731 it unrelocated. Goodness help us if there are PC-relative
1733 if (amd64_syscall_p (insn_details
, &insn_len
)
1734 && orig_rip
!= to
+ insn_len
1735 /* GDB can get control back after the insn after the syscall.
1736 Presumably this is a kernel bug.
1737 Fixup ensures its a nop, we add one to the length for it. */
1738 && orig_rip
!= to
+ insn_len
+ 1)
1739 displaced_debug_printf ("syscall changed %%rip; not relocating");
1742 ULONGEST rip
= orig_rip
- insn_offset
;
1744 /* If we just stepped over a breakpoint insn, we don't backup
1745 the pc on purpose; this is to match behaviour without
1748 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1750 displaced_debug_printf ("relocated %%rip from %s to %s",
1751 paddress (gdbarch
, orig_rip
),
1752 paddress (gdbarch
, rip
));
1756 /* If the instruction was PUSHFL, then the TF bit will be set in the
1757 pushed value, and should be cleared. We'll leave this for later,
1758 since GDB already messes up the TF flag when stepping over a
1761 /* If the instruction was a call, the return address now atop the
1762 stack is the address following the copied instruction. We need
1763 to make it the address following the original instruction. */
1764 if (amd64_call_p (insn_details
))
1768 const ULONGEST retaddr_len
= 8;
1770 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1771 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1772 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1773 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1775 displaced_debug_printf ("relocated return addr at %s to %s",
1776 paddress (gdbarch
, rsp
),
1777 paddress (gdbarch
, retaddr
));
1781 /* If the instruction INSN uses RIP-relative addressing, return the
1782 offset into the raw INSN where the displacement to be adjusted is
1783 found. Returns 0 if the instruction doesn't use RIP-relative
1787 rip_relative_offset (struct amd64_insn
*insn
)
1789 if (insn
->modrm_offset
!= -1)
1791 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1793 if ((modrm
& 0xc7) == 0x05)
1795 /* The displacement is found right after the ModRM byte. */
1796 return insn
->modrm_offset
+ 1;
1804 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1806 target_write_memory (*to
, buf
, len
);
1811 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1812 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1814 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1815 int len
= gdbarch_max_insn_length (gdbarch
);
1816 /* Extra space for sentinels. */
1817 int fixup_sentinel_space
= len
;
1818 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1819 struct amd64_insn insn_details
;
1821 LONGEST rel32
, newrel
;
1825 read_memory (oldloc
, buf
, len
);
1827 /* Set up the sentinel space so we don't have to worry about running
1828 off the end of the buffer. An excessive number of leading prefixes
1829 could otherwise cause this. */
1830 memset (buf
+ len
, 0, fixup_sentinel_space
);
1833 amd64_get_insn_details (insn
, &insn_details
);
1835 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1837 /* Skip legacy instruction prefixes. */
1838 insn
= amd64_skip_prefixes (insn
);
1840 /* Adjust calls with 32-bit relative addresses as push/jump, with
1841 the address pushed being the location where the original call in
1842 the user program would return to. */
1843 if (insn
[0] == 0xe8)
1845 gdb_byte push_buf
[32];
1849 /* Where "ret" in the original code will return to. */
1850 ret_addr
= oldloc
+ insn_length
;
1852 /* If pushing an address higher than or equal to 0x80000000,
1853 avoid 'pushq', as that sign extends its 32-bit operand, which
1854 would be incorrect. */
1855 if (ret_addr
<= 0x7fffffff)
1857 push_buf
[0] = 0x68; /* pushq $... */
1858 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1863 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1864 push_buf
[i
++] = 0x83;
1865 push_buf
[i
++] = 0xec;
1866 push_buf
[i
++] = 0x08;
1868 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1869 push_buf
[i
++] = 0x04;
1870 push_buf
[i
++] = 0x24;
1871 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1872 ret_addr
& 0xffffffff);
1875 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1876 push_buf
[i
++] = 0x44;
1877 push_buf
[i
++] = 0x24;
1878 push_buf
[i
++] = 0x04;
1879 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1883 gdb_assert (i
<= sizeof (push_buf
));
1884 /* Push the push. */
1885 append_insns (to
, i
, push_buf
);
1887 /* Convert the relative call to a relative jump. */
1890 /* Adjust the destination offset. */
1891 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1892 newrel
= (oldloc
- *to
) + rel32
;
1893 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1895 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1896 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1897 hex_string (newrel
), paddress (gdbarch
, *to
));
1899 /* Write the adjusted jump into its displaced location. */
1900 append_insns (to
, 5, insn
);
1904 offset
= rip_relative_offset (&insn_details
);
1907 /* Adjust jumps with 32-bit relative addresses. Calls are
1908 already handled above. */
1909 if (insn
[0] == 0xe9)
1911 /* Adjust conditional jumps. */
1912 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1918 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1919 newrel
= (oldloc
- *to
) + rel32
;
1920 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1921 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1922 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1923 hex_string (newrel
), paddress (gdbarch
, *to
));
1926 /* Write the adjusted instruction into its displaced location. */
1927 append_insns (to
, insn_length
, buf
);
1931 /* The maximum number of saved registers. This should include %rip. */
1932 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1934 struct amd64_frame_cache
1939 CORE_ADDR sp_offset
;
1942 /* Saved registers. */
1943 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1947 /* Do we have a frame? */
1951 /* Initialize a frame cache. */
1954 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1961 cache
->sp_offset
= -8;
1964 /* Saved registers. We initialize these to -1 since zero is a valid
1965 offset (that's where %rbp is supposed to be stored).
1966 The values start out as being offsets, and are later converted to
1967 addresses (at which point -1 is interpreted as an address, still meaning
1969 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1970 cache
->saved_regs
[i
] = -1;
1971 cache
->saved_sp
= 0;
1972 cache
->saved_sp_reg
= -1;
1974 /* Frameless until proven otherwise. */
1975 cache
->frameless_p
= 1;
1978 /* Allocate and initialize a frame cache. */
1980 static struct amd64_frame_cache
*
1981 amd64_alloc_frame_cache (void)
1983 struct amd64_frame_cache
*cache
;
1985 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1986 amd64_init_frame_cache (cache
);
1990 /* GCC 4.4 and later, can put code in the prologue to realign the
1991 stack pointer. Check whether PC points to such code, and update
1992 CACHE accordingly. Return the first instruction after the code
1993 sequence or CURRENT_PC, whichever is smaller. If we don't
1994 recognize the code, return PC. */
1997 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1998 struct amd64_frame_cache
*cache
)
2000 /* There are 2 code sequences to re-align stack before the frame
2003 1. Use a caller-saved saved register:
2009 2. Use a callee-saved saved register:
2016 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2018 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2019 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2024 int offset
, offset_and
;
2026 if (target_read_code (pc
, buf
, sizeof buf
))
2029 /* Check caller-saved saved register. The first instruction has
2030 to be "leaq 8(%rsp), %reg". */
2031 if ((buf
[0] & 0xfb) == 0x48
2036 /* MOD must be binary 10 and R/M must be binary 100. */
2037 if ((buf
[2] & 0xc7) != 0x44)
2040 /* REG has register number. */
2041 reg
= (buf
[2] >> 3) & 7;
2043 /* Check the REX.R bit. */
2051 /* Check callee-saved saved register. The first instruction
2052 has to be "pushq %reg". */
2054 if ((buf
[0] & 0xf8) == 0x50)
2056 else if ((buf
[0] & 0xf6) == 0x40
2057 && (buf
[1] & 0xf8) == 0x50)
2059 /* Check the REX.B bit. */
2060 if ((buf
[0] & 1) != 0)
2069 reg
+= buf
[offset
] & 0x7;
2073 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2074 if ((buf
[offset
] & 0xfb) != 0x48
2075 || buf
[offset
+ 1] != 0x8d
2076 || buf
[offset
+ 3] != 0x24
2077 || buf
[offset
+ 4] != 0x10)
2080 /* MOD must be binary 10 and R/M must be binary 100. */
2081 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2084 /* REG has register number. */
2085 r
= (buf
[offset
+ 2] >> 3) & 7;
2087 /* Check the REX.R bit. */
2088 if (buf
[offset
] == 0x4c)
2091 /* Registers in pushq and leaq have to be the same. */
2098 /* Rigister can't be %rsp nor %rbp. */
2099 if (reg
== 4 || reg
== 5)
2102 /* The next instruction has to be "andq $-XXX, %rsp". */
2103 if (buf
[offset
] != 0x48
2104 || buf
[offset
+ 2] != 0xe4
2105 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2108 offset_and
= offset
;
2109 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2111 /* The next instruction has to be "pushq -8(%reg)". */
2113 if (buf
[offset
] == 0xff)
2115 else if ((buf
[offset
] & 0xf6) == 0x40
2116 && buf
[offset
+ 1] == 0xff)
2118 /* Check the REX.B bit. */
2119 if ((buf
[offset
] & 0x1) != 0)
2126 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2128 if (buf
[offset
+ 1] != 0xf8
2129 || (buf
[offset
] & 0xf8) != 0x70)
2132 /* R/M has register. */
2133 r
+= buf
[offset
] & 7;
2135 /* Registers in leaq and pushq have to be the same. */
2139 if (current_pc
> pc
+ offset_and
)
2140 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2142 return std::min (pc
+ offset
+ 2, current_pc
);
2145 /* Similar to amd64_analyze_stack_align for x32. */
2148 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2149 struct amd64_frame_cache
*cache
)
2151 /* There are 2 code sequences to re-align stack before the frame
2154 1. Use a caller-saved saved register:
2162 [addr32] leal 8(%rsp), %reg
2164 [addr32] pushq -8(%reg)
2166 2. Use a callee-saved saved register:
2176 [addr32] leal 16(%rsp), %reg
2178 [addr32] pushq -8(%reg)
2180 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2182 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2183 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2185 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2187 0x83 0xe4 0xf0 andl $-16, %esp
2188 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2193 int offset
, offset_and
;
2195 if (target_read_memory (pc
, buf
, sizeof buf
))
2198 /* Skip optional addr32 prefix. */
2199 offset
= buf
[0] == 0x67 ? 1 : 0;
2201 /* Check caller-saved saved register. The first instruction has
2202 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2203 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2204 && buf
[offset
+ 1] == 0x8d
2205 && buf
[offset
+ 3] == 0x24
2206 && buf
[offset
+ 4] == 0x8)
2208 /* MOD must be binary 10 and R/M must be binary 100. */
2209 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2212 /* REG has register number. */
2213 reg
= (buf
[offset
+ 2] >> 3) & 7;
2215 /* Check the REX.R bit. */
2216 if ((buf
[offset
] & 0x4) != 0)
2223 /* Check callee-saved saved register. The first instruction
2224 has to be "pushq %reg". */
2226 if ((buf
[offset
] & 0xf6) == 0x40
2227 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2229 /* Check the REX.B bit. */
2230 if ((buf
[offset
] & 1) != 0)
2235 else if ((buf
[offset
] & 0xf8) != 0x50)
2239 reg
+= buf
[offset
] & 0x7;
2243 /* Skip optional addr32 prefix. */
2244 if (buf
[offset
] == 0x67)
2247 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2248 "leal 16(%rsp), %reg". */
2249 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2250 || buf
[offset
+ 1] != 0x8d
2251 || buf
[offset
+ 3] != 0x24
2252 || buf
[offset
+ 4] != 0x10)
2255 /* MOD must be binary 10 and R/M must be binary 100. */
2256 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2259 /* REG has register number. */
2260 r
= (buf
[offset
+ 2] >> 3) & 7;
2262 /* Check the REX.R bit. */
2263 if ((buf
[offset
] & 0x4) != 0)
2266 /* Registers in pushq and leaq have to be the same. */
2273 /* Rigister can't be %rsp nor %rbp. */
2274 if (reg
== 4 || reg
== 5)
2277 /* The next instruction may be "andq $-XXX, %rsp" or
2278 "andl $-XXX, %esp". */
2279 if (buf
[offset
] != 0x48)
2282 if (buf
[offset
+ 2] != 0xe4
2283 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2286 offset_and
= offset
;
2287 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2289 /* Skip optional addr32 prefix. */
2290 if (buf
[offset
] == 0x67)
2293 /* The next instruction has to be "pushq -8(%reg)". */
2295 if (buf
[offset
] == 0xff)
2297 else if ((buf
[offset
] & 0xf6) == 0x40
2298 && buf
[offset
+ 1] == 0xff)
2300 /* Check the REX.B bit. */
2301 if ((buf
[offset
] & 0x1) != 0)
2308 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2310 if (buf
[offset
+ 1] != 0xf8
2311 || (buf
[offset
] & 0xf8) != 0x70)
2314 /* R/M has register. */
2315 r
+= buf
[offset
] & 7;
2317 /* Registers in leaq and pushq have to be the same. */
2321 if (current_pc
> pc
+ offset_and
)
2322 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2324 return std::min (pc
+ offset
+ 2, current_pc
);
2327 /* Do a limited analysis of the prologue at PC and update CACHE
2328 accordingly. Bail out early if CURRENT_PC is reached. Return the
2329 address where the analysis stopped.
2331 We will handle only functions beginning with:
2334 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2336 or (for the X32 ABI):
2339 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2341 The `endbr64` instruction can be found before these sequences, and will be
2344 Any function that doesn't start with one of these sequences will be
2345 assumed to have no prologue and thus no valid frame pointer in
2349 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2350 CORE_ADDR pc
, CORE_ADDR current_pc
,
2351 struct amd64_frame_cache
*cache
)
2353 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2354 /* The `endbr64` instruction. */
2355 static const gdb_byte endbr64
[4] = { 0xf3, 0x0f, 0x1e, 0xfa };
2356 /* There are two variations of movq %rsp, %rbp. */
2357 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2358 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2359 /* Ditto for movl %esp, %ebp. */
2360 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2361 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2366 if (current_pc
<= pc
)
2369 if (gdbarch_ptr_bit (gdbarch
) == 32)
2370 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2372 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2374 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2376 /* Check for the `endbr64` instruction, skip it if found. */
2377 if (op
== endbr64
[0])
2379 read_code (pc
+ 1, buf
, 3);
2381 if (memcmp (buf
, &endbr64
[1], 3) == 0)
2384 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2387 if (current_pc
<= pc
)
2390 if (op
== 0x55) /* pushq %rbp */
2392 /* Take into account that we've executed the `pushq %rbp' that
2393 starts this instruction sequence. */
2394 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2395 cache
->sp_offset
+= 8;
2397 /* If that's all, return now. */
2398 if (current_pc
<= pc
+ 1)
2401 read_code (pc
+ 1, buf
, 3);
2403 /* Check for `movq %rsp, %rbp'. */
2404 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2405 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2407 /* OK, we actually have a frame. */
2408 cache
->frameless_p
= 0;
2412 /* For X32, also check for `movl %esp, %ebp'. */
2413 if (gdbarch_ptr_bit (gdbarch
) == 32)
2415 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2416 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2418 /* OK, we actually have a frame. */
2419 cache
->frameless_p
= 0;
2430 /* Work around false termination of prologue - GCC PR debug/48827.
2432 START_PC is the first instruction of a function, PC is its minimal already
2433 determined advanced address. Function returns PC if it has nothing to do.
2437 <-- here is 0 lines advance - the false prologue end marker.
2438 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2439 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2440 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2441 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2442 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2443 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2444 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2445 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2449 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2451 struct symtab_and_line start_pc_sal
, next_sal
;
2452 gdb_byte buf
[4 + 8 * 7];
2458 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2459 if (start_pc_sal
.symtab
== NULL
2460 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2461 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2462 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2465 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2466 if (next_sal
.line
!= start_pc_sal
.line
)
2469 /* START_PC can be from overlayed memory, ignored here. */
2470 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2474 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2481 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2483 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2484 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2485 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2489 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2491 /* 8-bit displacement. */
2495 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2497 /* 32-bit displacement. */
2505 if (offset
- 4 != buf
[3])
2508 return next_sal
.end
;
2511 /* Return PC of first real instruction. */
2514 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2516 struct amd64_frame_cache cache
;
2518 CORE_ADDR func_addr
;
2520 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2522 CORE_ADDR post_prologue_pc
2523 = skip_prologue_using_sal (gdbarch
, func_addr
);
2524 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2526 /* LLVM backend (Clang/Flang) always emits a line note before the
2527 prologue and another one after. We trust clang to emit usable
2529 if (post_prologue_pc
2531 && COMPUNIT_PRODUCER (cust
) != NULL
2532 && producer_is_llvm (COMPUNIT_PRODUCER (cust
))))
2533 return std::max (start_pc
, post_prologue_pc
);
2536 amd64_init_frame_cache (&cache
);
2537 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2539 if (cache
.frameless_p
)
2542 return amd64_skip_xmm_prologue (pc
, start_pc
);
2546 /* Normal frames. */
2549 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2550 struct amd64_frame_cache
*cache
)
2552 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2553 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2557 cache
->pc
= get_frame_func (this_frame
);
2559 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2562 if (cache
->frameless_p
)
2564 /* We didn't find a valid frame. If we're at the start of a
2565 function, or somewhere half-way its prologue, the function's
2566 frame probably hasn't been fully setup yet. Try to
2567 reconstruct the base address for the stack frame by looking
2568 at the stack pointer. For truly "frameless" functions this
2571 if (cache
->saved_sp_reg
!= -1)
2573 /* Stack pointer has been saved. */
2574 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2575 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2577 /* We're halfway aligning the stack. */
2578 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2579 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2581 /* This will be added back below. */
2582 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2586 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2587 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2593 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2594 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2597 /* Now that we have the base address for the stack frame we can
2598 calculate the value of %rsp in the calling frame. */
2599 cache
->saved_sp
= cache
->base
+ 16;
2601 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2602 frame we find it at the same offset from the reconstructed base
2603 address. If we're halfway aligning the stack, %rip is handled
2604 differently (see above). */
2605 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2606 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2608 /* Adjust all the saved registers such that they contain addresses
2609 instead of offsets. */
2610 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2611 if (cache
->saved_regs
[i
] != -1)
2612 cache
->saved_regs
[i
] += cache
->base
;
2617 static struct amd64_frame_cache
*
2618 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2620 struct amd64_frame_cache
*cache
;
2623 return (struct amd64_frame_cache
*) *this_cache
;
2625 cache
= amd64_alloc_frame_cache ();
2626 *this_cache
= cache
;
2630 amd64_frame_cache_1 (this_frame
, cache
);
2632 catch (const gdb_exception_error
&ex
)
2634 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2641 static enum unwind_stop_reason
2642 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2645 struct amd64_frame_cache
*cache
=
2646 amd64_frame_cache (this_frame
, this_cache
);
2649 return UNWIND_UNAVAILABLE
;
2651 /* This marks the outermost frame. */
2652 if (cache
->base
== 0)
2653 return UNWIND_OUTERMOST
;
2655 return UNWIND_NO_REASON
;
2659 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2660 struct frame_id
*this_id
)
2662 struct amd64_frame_cache
*cache
=
2663 amd64_frame_cache (this_frame
, this_cache
);
2666 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2667 else if (cache
->base
== 0)
2669 /* This marks the outermost frame. */
2673 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2676 static struct value
*
2677 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2680 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2681 struct amd64_frame_cache
*cache
=
2682 amd64_frame_cache (this_frame
, this_cache
);
2684 gdb_assert (regnum
>= 0);
2686 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2687 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2689 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2690 return frame_unwind_got_memory (this_frame
, regnum
,
2691 cache
->saved_regs
[regnum
]);
2693 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2696 static const struct frame_unwind amd64_frame_unwind
=
2699 amd64_frame_unwind_stop_reason
,
2700 amd64_frame_this_id
,
2701 amd64_frame_prev_register
,
2703 default_frame_sniffer
2706 /* Generate a bytecode expression to get the value of the saved PC. */
2709 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2710 struct agent_expr
*ax
, struct axs_value
*value
,
2713 /* The following sequence assumes the traditional use of the base
2715 ax_reg (ax
, AMD64_RBP_REGNUM
);
2717 ax_simple (ax
, aop_add
);
2718 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2719 value
->kind
= axs_lvalue_memory
;
2723 /* Signal trampolines. */
2725 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2726 64-bit variants. This would require using identical frame caches
2727 on both platforms. */
2729 static struct amd64_frame_cache
*
2730 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2732 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2733 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2734 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2735 struct amd64_frame_cache
*cache
;
2741 return (struct amd64_frame_cache
*) *this_cache
;
2743 cache
= amd64_alloc_frame_cache ();
2747 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2748 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2750 addr
= tdep
->sigcontext_addr (this_frame
);
2751 gdb_assert (tdep
->sc_reg_offset
);
2752 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2753 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2754 if (tdep
->sc_reg_offset
[i
] != -1)
2755 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2759 catch (const gdb_exception_error
&ex
)
2761 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2765 *this_cache
= cache
;
2769 static enum unwind_stop_reason
2770 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2773 struct amd64_frame_cache
*cache
=
2774 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2777 return UNWIND_UNAVAILABLE
;
2779 return UNWIND_NO_REASON
;
2783 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2784 void **this_cache
, struct frame_id
*this_id
)
2786 struct amd64_frame_cache
*cache
=
2787 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2790 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2791 else if (cache
->base
== 0)
2793 /* This marks the outermost frame. */
2797 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2800 static struct value
*
2801 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2802 void **this_cache
, int regnum
)
2804 /* Make sure we've initialized the cache. */
2805 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2807 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2811 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2812 struct frame_info
*this_frame
,
2815 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2817 /* We shouldn't even bother if we don't have a sigcontext_addr
2819 if (tdep
->sigcontext_addr
== NULL
)
2822 if (tdep
->sigtramp_p
!= NULL
)
2824 if (tdep
->sigtramp_p (this_frame
))
2828 if (tdep
->sigtramp_start
!= 0)
2830 CORE_ADDR pc
= get_frame_pc (this_frame
);
2832 gdb_assert (tdep
->sigtramp_end
!= 0);
2833 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2840 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2843 amd64_sigtramp_frame_unwind_stop_reason
,
2844 amd64_sigtramp_frame_this_id
,
2845 amd64_sigtramp_frame_prev_register
,
2847 amd64_sigtramp_frame_sniffer
2852 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2854 struct amd64_frame_cache
*cache
=
2855 amd64_frame_cache (this_frame
, this_cache
);
2860 static const struct frame_base amd64_frame_base
=
2862 &amd64_frame_unwind
,
2863 amd64_frame_base_address
,
2864 amd64_frame_base_address
,
2865 amd64_frame_base_address
2868 /* Normal frames, but in a function epilogue. */
2870 /* Implement the stack_frame_destroyed_p gdbarch method.
2872 The epilogue is defined here as the 'ret' instruction, which will
2873 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2874 the function's stack frame. */
2877 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2880 struct compunit_symtab
*cust
;
2882 cust
= find_pc_compunit_symtab (pc
);
2883 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2886 if (target_read_memory (pc
, &insn
, 1))
2887 return 0; /* Can't read memory at pc. */
2889 if (insn
!= 0xc3) /* 'ret' instruction. */
2896 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2897 struct frame_info
*this_frame
,
2898 void **this_prologue_cache
)
2900 if (frame_relative_level (this_frame
) == 0)
2901 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2902 get_frame_pc (this_frame
));
2907 static struct amd64_frame_cache
*
2908 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2910 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2911 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2912 struct amd64_frame_cache
*cache
;
2916 return (struct amd64_frame_cache
*) *this_cache
;
2918 cache
= amd64_alloc_frame_cache ();
2919 *this_cache
= cache
;
2923 /* Cache base will be %esp plus cache->sp_offset (-8). */
2924 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2925 cache
->base
= extract_unsigned_integer (buf
, 8,
2926 byte_order
) + cache
->sp_offset
;
2928 /* Cache pc will be the frame func. */
2929 cache
->pc
= get_frame_pc (this_frame
);
2931 /* The saved %esp will be at cache->base plus 16. */
2932 cache
->saved_sp
= cache
->base
+ 16;
2934 /* The saved %eip will be at cache->base plus 8. */
2935 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2939 catch (const gdb_exception_error
&ex
)
2941 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2948 static enum unwind_stop_reason
2949 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2952 struct amd64_frame_cache
*cache
2953 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2956 return UNWIND_UNAVAILABLE
;
2958 return UNWIND_NO_REASON
;
2962 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2964 struct frame_id
*this_id
)
2966 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2970 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2972 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2975 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2978 amd64_epilogue_frame_unwind_stop_reason
,
2979 amd64_epilogue_frame_this_id
,
2980 amd64_frame_prev_register
,
2982 amd64_epilogue_frame_sniffer
2985 static struct frame_id
2986 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2990 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2992 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2995 /* 16 byte align the SP per frame requirements. */
2998 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3000 return sp
& -(CORE_ADDR
)16;
3004 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3005 in the floating-point register set REGSET to register cache
3006 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3009 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3010 int regnum
, const void *fpregs
, size_t len
)
3012 struct gdbarch
*gdbarch
= regcache
->arch ();
3013 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3015 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3016 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
3019 /* Collect register REGNUM from the register cache REGCACHE and store
3020 it in the buffer specified by FPREGS and LEN as described by the
3021 floating-point register set REGSET. If REGNUM is -1, do this for
3022 all registers in REGSET. */
3025 amd64_collect_fpregset (const struct regset
*regset
,
3026 const struct regcache
*regcache
,
3027 int regnum
, void *fpregs
, size_t len
)
3029 struct gdbarch
*gdbarch
= regcache
->arch ();
3030 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3032 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3033 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
3036 const struct regset amd64_fpregset
=
3038 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
3042 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
3043 %rdi. We expect its value to be a pointer to the jmp_buf structure
3044 from which we extract the address that we will land at. This
3045 address is copied into PC. This routine returns non-zero on
3049 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
3053 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3054 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
3055 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
3057 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3058 longjmp will land. */
3059 if (jb_pc_offset
== -1)
3062 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
3063 jb_addr
= extract_typed_address
3064 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
3065 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
3068 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
3073 static const int amd64_record_regmap
[] =
3075 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
3076 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
3077 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
3078 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
3079 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
3080 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
3083 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
3086 amd64_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3088 return x86_in_indirect_branch_thunk (pc
, amd64_register_names
,
3094 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3095 const target_desc
*default_tdesc
)
3097 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3098 const struct target_desc
*tdesc
= info
.target_desc
;
3099 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3100 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3101 static const char *const stap_register_indirection_prefixes
[] = { "(",
3103 static const char *const stap_register_indirection_suffixes
[] = { ")",
3106 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3107 floating-point registers. */
3108 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3109 tdep
->fpregset
= &amd64_fpregset
;
3111 if (! tdesc_has_registers (tdesc
))
3112 tdesc
= default_tdesc
;
3113 tdep
->tdesc
= tdesc
;
3115 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3116 tdep
->register_names
= amd64_register_names
;
3118 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3120 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3121 tdep
->k_register_names
= amd64_k_names
;
3122 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3123 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3125 tdep
->num_zmm_regs
= 32;
3126 tdep
->num_xmm_avx512_regs
= 16;
3127 tdep
->num_ymm_avx512_regs
= 16;
3129 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3130 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3131 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3132 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3135 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3137 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3138 tdep
->num_ymm_regs
= 16;
3139 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3142 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3144 tdep
->mpx_register_names
= amd64_mpx_names
;
3145 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3146 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3149 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3151 tdep
->fsbase_regnum
= AMD64_FSBASE_REGNUM
;
3154 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys") != NULL
)
3156 tdep
->pkeys_register_names
= amd64_pkeys_names
;
3157 tdep
->pkru_regnum
= AMD64_PKRU_REGNUM
;
3158 tdep
->num_pkeys_regs
= 1;
3161 tdep
->num_byte_regs
= 20;
3162 tdep
->num_word_regs
= 16;
3163 tdep
->num_dword_regs
= 16;
3164 /* Avoid wiring in the MMX registers for now. */
3165 tdep
->num_mmx_regs
= 0;
3167 set_gdbarch_pseudo_register_read_value (gdbarch
,
3168 amd64_pseudo_register_read_value
);
3169 set_gdbarch_pseudo_register_write (gdbarch
,
3170 amd64_pseudo_register_write
);
3171 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3172 amd64_ax_pseudo_register_collect
);
3174 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3176 /* AMD64 has an FPU and 16 SSE registers. */
3177 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3178 tdep
->num_xmm_regs
= 16;
3180 /* This is what all the fuss is about. */
3181 set_gdbarch_long_bit (gdbarch
, 64);
3182 set_gdbarch_long_long_bit (gdbarch
, 64);
3183 set_gdbarch_ptr_bit (gdbarch
, 64);
3185 /* In contrast to the i386, on AMD64 a `long double' actually takes
3186 up 128 bits, even though it's still based on the i387 extended
3187 floating-point format which has only 80 significant bits. */
3188 set_gdbarch_long_double_bit (gdbarch
, 128);
3190 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3192 /* Register numbers of various important registers. */
3193 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3194 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3195 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3196 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3198 /* The "default" register numbering scheme for AMD64 is referred to
3199 as the "DWARF Register Number Mapping" in the System V psABI.
3200 The preferred debugging format for all known AMD64 targets is
3201 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3202 DWARF-1), but we provide the same mapping just in case. This
3203 mapping is also used for stabs, which GCC does support. */
3204 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3205 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3207 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3208 be in use on any of the supported AMD64 targets. */
3210 /* Call dummy code. */
3211 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3212 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3213 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3215 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3216 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3217 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3219 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3221 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3223 tdep
->record_regmap
= amd64_record_regmap
;
3225 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3227 /* Hook the function epilogue frame unwinder. This unwinder is
3228 appended to the list first, so that it supercedes the other
3229 unwinders in function epilogues. */
3230 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3232 /* Hook the prologue-based frame unwinders. */
3233 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3234 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3235 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3237 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3239 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3241 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3243 /* SystemTap variables and functions. */
3244 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3245 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3246 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3247 stap_register_indirection_prefixes
);
3248 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3249 stap_register_indirection_suffixes
);
3250 set_gdbarch_stap_is_single_operand (gdbarch
,
3251 i386_stap_is_single_operand
);
3252 set_gdbarch_stap_parse_special_token (gdbarch
,
3253 i386_stap_parse_special_token
);
3254 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3255 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3256 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3258 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
3259 amd64_in_indirect_branch_thunk
);
3261 register_amd64_ravenscar_ops (gdbarch
);
3264 /* Initialize ARCH for x86-64, no osabi. */
3267 amd64_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3269 amd64_init_abi (info
, arch
, amd64_target_description (X86_XSTATE_SSE_MASK
,
3273 static struct type
*
3274 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3276 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3278 switch (regnum
- tdep
->eax_regnum
)
3280 case AMD64_RBP_REGNUM
: /* %ebp */
3281 case AMD64_RSP_REGNUM
: /* %esp */
3282 return builtin_type (gdbarch
)->builtin_data_ptr
;
3283 case AMD64_RIP_REGNUM
: /* %eip */
3284 return builtin_type (gdbarch
)->builtin_func_ptr
;
3287 return i386_pseudo_register_type (gdbarch
, regnum
);
3291 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3292 const target_desc
*default_tdesc
)
3294 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3296 amd64_init_abi (info
, gdbarch
, default_tdesc
);
3298 tdep
->num_dword_regs
= 17;
3299 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3301 set_gdbarch_long_bit (gdbarch
, 32);
3302 set_gdbarch_ptr_bit (gdbarch
, 32);
3305 /* Initialize ARCH for x64-32, no osabi. */
3308 amd64_x32_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3310 amd64_x32_init_abi (info
, arch
,
3311 amd64_target_description (X86_XSTATE_SSE_MASK
, true));
3314 /* Return the target description for a specified XSAVE feature mask. */
3316 const struct target_desc
*
3317 amd64_target_description (uint64_t xcr0
, bool segments
)
3319 static target_desc
*amd64_tdescs \
3320 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
3321 target_desc
**tdesc
;
3323 tdesc
= &amd64_tdescs
[(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
3324 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
3325 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
3326 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
3330 *tdesc
= amd64_create_target_description (xcr0
, false, false,
3336 void _initialize_amd64_tdep ();
3338 _initialize_amd64_tdep ()
3340 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x86_64
, GDB_OSABI_NONE
,
3341 amd64_none_init_abi
);
3342 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x64_32
, GDB_OSABI_NONE
,
3343 amd64_x32_none_init_abi
);
3347 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3348 sense that the instruction pointer and data pointer are simply
3349 64-bit offsets into the code segment and the data segment instead
3350 of a selector offset pair. The functions below store the upper 32
3351 bits of these pointers (instead of just the 16-bits of the segment
3354 /* Fill register REGNUM in REGCACHE with the appropriate
3355 floating-point or SSE register value from *FXSAVE. If REGNUM is
3356 -1, do this for all registers. This function masks off any of the
3357 reserved bits in *FXSAVE. */
3360 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3363 struct gdbarch
*gdbarch
= regcache
->arch ();
3364 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3366 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3369 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3371 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3373 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3374 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3375 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3376 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3380 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3383 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3386 struct gdbarch
*gdbarch
= regcache
->arch ();
3387 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3389 i387_supply_xsave (regcache
, regnum
, xsave
);
3392 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3394 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3397 clear_bv
= i387_xsave_get_clear_bv (gdbarch
, xsave
);
3399 /* If the FISEG and FOSEG registers have not been initialised yet
3400 (their CLEAR_BV bit is set) then their default values of zero will
3401 have already been setup by I387_SUPPLY_XSAVE. */
3402 if (!(clear_bv
& X86_XSTATE_X87
))
3404 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3405 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3406 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3407 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3412 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3413 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3414 all registers. This function doesn't touch any of the reserved
3418 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3421 struct gdbarch
*gdbarch
= regcache
->arch ();
3422 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3423 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3425 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3427 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3429 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3430 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3431 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3432 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3436 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3439 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3440 void *xsave
, int gcore
)
3442 struct gdbarch
*gdbarch
= regcache
->arch ();
3443 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3444 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3446 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3448 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3450 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3451 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
),
3453 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3454 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
),