1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
2 Contributed by Jon Beniston <jon@beniston.com>
4 Copyright (C) 2009-2021 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
30 #include "gdb/sim-lm32.h"
31 #include "arch-utils.h"
33 #include "trad-frame.h"
34 #include "reggroups.h"
35 #include "opcodes/lm32-desc.h"
38 /* Macros to extract fields from an instruction. */
39 #define LM32_OPCODE(insn) ((insn >> 26) & 0x3f)
40 #define LM32_REG0(insn) ((insn >> 21) & 0x1f)
41 #define LM32_REG1(insn) ((insn >> 16) & 0x1f)
42 #define LM32_REG2(insn) ((insn >> 11) & 0x1f)
43 #define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16)
47 /* gdbarch target dependent data here. Currently unused for LM32. */
50 struct lm32_frame_cache
52 /* The frame's base. Used when constructing a frame ID. */
57 /* Table indicating the location of each and every register. */
58 trad_frame_saved_reg
*saved_regs
;
61 /* Add the available register groups. */
64 lm32_add_reggroups (struct gdbarch
*gdbarch
)
66 reggroup_add (gdbarch
, general_reggroup
);
67 reggroup_add (gdbarch
, all_reggroup
);
68 reggroup_add (gdbarch
, system_reggroup
);
71 /* Return whether a given register is in a given group. */
74 lm32_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
75 struct reggroup
*group
)
77 if (group
== general_reggroup
)
78 return ((regnum
>= SIM_LM32_R0_REGNUM
) && (regnum
<= SIM_LM32_RA_REGNUM
))
79 || (regnum
== SIM_LM32_PC_REGNUM
);
80 else if (group
== system_reggroup
)
81 return ((regnum
>= SIM_LM32_BA_REGNUM
) && (regnum
<= SIM_LM32_EA_REGNUM
))
82 || ((regnum
>= SIM_LM32_EID_REGNUM
) && (regnum
<= SIM_LM32_IP_REGNUM
));
83 return default_register_reggroup_p (gdbarch
, regnum
, group
);
86 /* Return a name that corresponds to the given register number. */
89 lm32_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
91 static const char *register_names
[] = {
92 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
93 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
94 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
95 "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
96 "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
99 if ((reg_nr
< 0) || (reg_nr
>= ARRAY_SIZE (register_names
)))
102 return register_names
[reg_nr
];
105 /* Return type of register. */
108 lm32_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
110 return builtin_type (gdbarch
)->builtin_int32
;
113 /* Return non-zero if a register can't be written. */
116 lm32_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
118 return (regno
== SIM_LM32_R0_REGNUM
) || (regno
== SIM_LM32_EID_REGNUM
);
121 /* Analyze a function's prologue. */
124 lm32_analyze_prologue (struct gdbarch
*gdbarch
,
125 CORE_ADDR pc
, CORE_ADDR limit
,
126 struct lm32_frame_cache
*info
)
128 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
129 unsigned long instruction
;
131 /* Keep reading though instructions, until we come across an instruction
132 that isn't likely to be part of the prologue. */
134 for (; pc
< limit
; pc
+= 4)
137 /* Read an instruction. */
138 instruction
= read_memory_integer (pc
, 4, byte_order
);
140 if ((LM32_OPCODE (instruction
) == OP_SW
)
141 && (LM32_REG0 (instruction
) == SIM_LM32_SP_REGNUM
))
143 /* Any stack displaced store is likely part of the prologue.
144 Record that the register is being saved, and the offset
146 info
->saved_regs
[LM32_REG1 (instruction
)].set_addr (LM32_IMM16 (instruction
));
148 else if ((LM32_OPCODE (instruction
) == OP_ADDI
)
149 && (LM32_REG1 (instruction
) == SIM_LM32_SP_REGNUM
))
151 /* An add to the SP is likely to be part of the prologue.
152 Adjust stack size by whatever the instruction adds to the sp. */
153 info
->size
-= LM32_IMM16 (instruction
);
155 else if ( /* add fp,fp,sp */
156 ((LM32_OPCODE (instruction
) == OP_ADD
)
157 && (LM32_REG2 (instruction
) == SIM_LM32_FP_REGNUM
)
158 && (LM32_REG0 (instruction
) == SIM_LM32_FP_REGNUM
)
159 && (LM32_REG1 (instruction
) == SIM_LM32_SP_REGNUM
))
161 || ((LM32_OPCODE (instruction
) == OP_ADDI
)
162 && (LM32_REG1 (instruction
) == SIM_LM32_FP_REGNUM
)
163 && (LM32_REG0 (instruction
) == SIM_LM32_R0_REGNUM
)))
165 /* Likely to be in the prologue for functions that require
170 /* Any other instruction is likely not to be part of the
179 /* Return PC of first non prologue instruction, for the function at the
180 specified address. */
183 lm32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
185 CORE_ADDR func_addr
, limit_pc
;
186 struct lm32_frame_cache frame_info
;
187 trad_frame_saved_reg saved_regs
[SIM_LM32_NUM_REGS
];
189 /* See if we can determine the end of the prologue via the symbol table.
190 If so, then return either PC, or the PC after the prologue, whichever
192 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
194 CORE_ADDR post_prologue_pc
195 = skip_prologue_using_sal (gdbarch
, func_addr
);
196 if (post_prologue_pc
!= 0)
197 return std::max (pc
, post_prologue_pc
);
200 /* Can't determine prologue from the symbol table, need to examine
203 /* Find an upper limit on the function prologue using the debug
204 information. If the debug information could not be used to provide
205 that bound, then use an arbitrary large number as the upper bound. */
206 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
208 limit_pc
= pc
+ 100; /* Magic. */
210 frame_info
.saved_regs
= saved_regs
;
211 return lm32_analyze_prologue (gdbarch
, pc
, limit_pc
, &frame_info
);
214 /* Create a breakpoint instruction. */
215 constexpr gdb_byte lm32_break_insn
[4] = { OP_RAISE
<< 2, 0, 0, 2 };
217 typedef BP_MANIPULATION (lm32_break_insn
) lm32_breakpoint
;
220 /* Setup registers and stack for faking a call to a function in the
224 lm32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
225 struct regcache
*regcache
, CORE_ADDR bp_addr
,
226 int nargs
, struct value
**args
, CORE_ADDR sp
,
227 function_call_return_method return_method
,
228 CORE_ADDR struct_addr
)
230 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
231 int first_arg_reg
= SIM_LM32_R1_REGNUM
;
232 int num_arg_regs
= 8;
235 /* Set the return address. */
236 regcache_cooked_write_signed (regcache
, SIM_LM32_RA_REGNUM
, bp_addr
);
238 /* If we're returning a large struct, a pointer to the address to
239 store it at is passed as a first hidden parameter. */
240 if (return_method
== return_method_struct
)
242 regcache_cooked_write_unsigned (regcache
, first_arg_reg
, struct_addr
);
248 /* Setup parameters. */
249 for (i
= 0; i
< nargs
; i
++)
251 struct value
*arg
= args
[i
];
252 struct type
*arg_type
= check_typedef (value_type (arg
));
256 /* Promote small integer types to int. */
257 switch (arg_type
->code ())
262 case TYPE_CODE_RANGE
:
264 if (TYPE_LENGTH (arg_type
) < 4)
266 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
267 arg
= value_cast (arg_type
, arg
);
272 /* FIXME: Handle structures. */
274 contents
= (gdb_byte
*) value_contents (arg
);
275 val
= extract_unsigned_integer (contents
, TYPE_LENGTH (arg_type
),
278 /* First num_arg_regs parameters are passed by registers,
279 and the rest are passed on the stack. */
280 if (i
< num_arg_regs
)
281 regcache_cooked_write_unsigned (regcache
, first_arg_reg
+ i
, val
);
284 write_memory_unsigned_integer (sp
, TYPE_LENGTH (arg_type
), byte_order
,
290 /* Update stack pointer. */
291 regcache_cooked_write_signed (regcache
, SIM_LM32_SP_REGNUM
, sp
);
293 /* Return adjusted stack pointer. */
297 /* Extract return value after calling a function in the inferior. */
300 lm32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
303 struct gdbarch
*gdbarch
= regcache
->arch ();
304 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
306 CORE_ADDR return_buffer
;
308 if (type
->code () != TYPE_CODE_STRUCT
309 && type
->code () != TYPE_CODE_UNION
310 && type
->code () != TYPE_CODE_ARRAY
&& TYPE_LENGTH (type
) <= 4)
312 /* Return value is returned in a single register. */
313 regcache_cooked_read_unsigned (regcache
, SIM_LM32_R1_REGNUM
, &l
);
314 store_unsigned_integer (valbuf
, TYPE_LENGTH (type
), byte_order
, l
);
316 else if ((type
->code () == TYPE_CODE_INT
) && (TYPE_LENGTH (type
) == 8))
318 /* 64-bit values are returned in a register pair. */
319 regcache_cooked_read_unsigned (regcache
, SIM_LM32_R1_REGNUM
, &l
);
320 memcpy (valbuf
, &l
, 4);
321 regcache_cooked_read_unsigned (regcache
, SIM_LM32_R2_REGNUM
, &l
);
322 memcpy (valbuf
+ 4, &l
, 4);
326 /* Aggregate types greater than a single register are returned
327 in memory. FIXME: Unless they are only 2 regs?. */
328 regcache_cooked_read_unsigned (regcache
, SIM_LM32_R1_REGNUM
, &l
);
330 read_memory (return_buffer
, valbuf
, TYPE_LENGTH (type
));
334 /* Write into appropriate registers a function return value of type
335 TYPE, given in virtual format. */
337 lm32_store_return_value (struct type
*type
, struct regcache
*regcache
,
338 const gdb_byte
*valbuf
)
340 struct gdbarch
*gdbarch
= regcache
->arch ();
341 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
343 int len
= TYPE_LENGTH (type
);
347 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
348 regcache_cooked_write_unsigned (regcache
, SIM_LM32_R1_REGNUM
, val
);
352 val
= extract_unsigned_integer (valbuf
, 4, byte_order
);
353 regcache_cooked_write_unsigned (regcache
, SIM_LM32_R1_REGNUM
, val
);
354 val
= extract_unsigned_integer (valbuf
+ 4, len
- 4, byte_order
);
355 regcache_cooked_write_unsigned (regcache
, SIM_LM32_R2_REGNUM
, val
);
358 error (_("lm32_store_return_value: type length too large."));
361 /* Determine whether a functions return value is in a register or memory. */
362 static enum return_value_convention
363 lm32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
364 struct type
*valtype
, struct regcache
*regcache
,
365 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
367 enum type_code code
= valtype
->code ();
369 if (code
== TYPE_CODE_STRUCT
370 || code
== TYPE_CODE_UNION
371 || code
== TYPE_CODE_ARRAY
|| TYPE_LENGTH (valtype
) > 8)
372 return RETURN_VALUE_STRUCT_CONVENTION
;
375 lm32_extract_return_value (valtype
, regcache
, readbuf
);
377 lm32_store_return_value (valtype
, regcache
, writebuf
);
379 return RETURN_VALUE_REGISTER_CONVENTION
;
382 /* Put here the code to store, into fi->saved_regs, the addresses of
383 the saved registers of frame described by FRAME_INFO. This
384 includes special registers such as pc and fp saved in special ways
385 in the stack frame. sp is even more special: the address we return
386 for it IS the sp for the next frame. */
388 static struct lm32_frame_cache
*
389 lm32_frame_cache (struct frame_info
*this_frame
, void **this_prologue_cache
)
391 CORE_ADDR current_pc
;
394 struct lm32_frame_cache
*info
;
397 if ((*this_prologue_cache
))
398 return (struct lm32_frame_cache
*) (*this_prologue_cache
);
400 info
= FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache
);
401 (*this_prologue_cache
) = info
;
402 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
404 info
->pc
= get_frame_func (this_frame
);
405 current_pc
= get_frame_pc (this_frame
);
406 lm32_analyze_prologue (get_frame_arch (this_frame
),
407 info
->pc
, current_pc
, info
);
409 /* Compute the frame's base, and the previous frame's SP. */
410 this_base
= get_frame_register_unsigned (this_frame
, SIM_LM32_SP_REGNUM
);
411 prev_sp
= this_base
+ info
->size
;
412 info
->base
= this_base
;
414 /* Convert callee save offsets into addresses. */
415 for (i
= 0; i
< gdbarch_num_regs (get_frame_arch (this_frame
)) - 1; i
++)
417 if (info
->saved_regs
[i
].is_addr ())
418 info
->saved_regs
[i
].set_addr (this_base
+ info
->saved_regs
[i
].addr ());
421 /* The call instruction moves the caller's PC in the callee's RA register.
422 Since this is an unwind, do the reverse. Copy the location of RA register
423 into PC (the address / regnum) so that a request for PC will be
424 converted into a request for the RA register. */
425 info
->saved_regs
[SIM_LM32_PC_REGNUM
] = info
->saved_regs
[SIM_LM32_RA_REGNUM
];
427 /* The previous frame's SP needed to be computed. Save the computed
429 info
->saved_regs
[SIM_LM32_SP_REGNUM
].set_value (prev_sp
);
435 lm32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
436 struct frame_id
*this_id
)
438 struct lm32_frame_cache
*cache
= lm32_frame_cache (this_frame
, this_cache
);
440 /* This marks the outermost frame. */
441 if (cache
->base
== 0)
444 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
447 static struct value
*
448 lm32_frame_prev_register (struct frame_info
*this_frame
,
449 void **this_prologue_cache
, int regnum
)
451 struct lm32_frame_cache
*info
;
453 info
= lm32_frame_cache (this_frame
, this_prologue_cache
);
454 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
457 static const struct frame_unwind lm32_frame_unwind
= {
459 default_frame_unwind_stop_reason
,
461 lm32_frame_prev_register
,
463 default_frame_sniffer
467 lm32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
469 struct lm32_frame_cache
*info
= lm32_frame_cache (this_frame
, this_cache
);
474 static const struct frame_base lm32_frame_base
= {
476 lm32_frame_base_address
,
477 lm32_frame_base_address
,
478 lm32_frame_base_address
482 lm32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
484 /* Align to the size of an instruction (so that they can safely be
485 pushed onto the stack. */
489 static struct gdbarch
*
490 lm32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
492 struct gdbarch
*gdbarch
;
493 struct gdbarch_tdep
*tdep
;
495 /* If there is already a candidate, use it. */
496 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
498 return arches
->gdbarch
;
500 /* None found, create a new architecture from the information provided. */
501 tdep
= XCNEW (struct gdbarch_tdep
);
502 gdbarch
= gdbarch_alloc (&info
, tdep
);
505 set_gdbarch_short_bit (gdbarch
, 16);
506 set_gdbarch_int_bit (gdbarch
, 32);
507 set_gdbarch_long_bit (gdbarch
, 32);
508 set_gdbarch_long_long_bit (gdbarch
, 64);
509 set_gdbarch_float_bit (gdbarch
, 32);
510 set_gdbarch_double_bit (gdbarch
, 64);
511 set_gdbarch_long_double_bit (gdbarch
, 64);
512 set_gdbarch_ptr_bit (gdbarch
, 32);
515 set_gdbarch_num_regs (gdbarch
, SIM_LM32_NUM_REGS
);
516 set_gdbarch_sp_regnum (gdbarch
, SIM_LM32_SP_REGNUM
);
517 set_gdbarch_pc_regnum (gdbarch
, SIM_LM32_PC_REGNUM
);
518 set_gdbarch_register_name (gdbarch
, lm32_register_name
);
519 set_gdbarch_register_type (gdbarch
, lm32_register_type
);
520 set_gdbarch_cannot_store_register (gdbarch
, lm32_cannot_store_register
);
523 set_gdbarch_skip_prologue (gdbarch
, lm32_skip_prologue
);
524 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
525 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
526 set_gdbarch_frame_args_skip (gdbarch
, 0);
528 /* Frame unwinding. */
529 set_gdbarch_frame_align (gdbarch
, lm32_frame_align
);
530 frame_base_set_default (gdbarch
, &lm32_frame_base
);
531 frame_unwind_append_unwinder (gdbarch
, &lm32_frame_unwind
);
534 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, lm32_breakpoint::kind_from_pc
);
535 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, lm32_breakpoint::bp_from_kind
);
536 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
538 /* Calling functions in the inferior. */
539 set_gdbarch_push_dummy_call (gdbarch
, lm32_push_dummy_call
);
540 set_gdbarch_return_value (gdbarch
, lm32_return_value
);
542 lm32_add_reggroups (gdbarch
);
543 set_gdbarch_register_reggroup_p (gdbarch
, lm32_register_reggroup_p
);
548 void _initialize_lm32_tdep ();
550 _initialize_lm32_tdep ()
552 register_gdbarch_init (bfd_arch_lm32
, lm32_gdbarch_init
);