1 /* Target-dependent code for the NDS32 architecture, for GDB.
3 Copyright (C) 2013-2021 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
29 #include "reggroups.h"
32 #include "arch-utils.h"
35 #include "user-regs.h"
37 #include "dwarf2/frame.h"
39 #include "target-descriptions.h"
41 #include "nds32-tdep.h"
42 #include "elf/nds32.h"
43 #include "opcode/nds32.h"
46 #include "features/nds32.c"
48 /* Simple macros for instruction analysis. */
49 #define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50 #define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
58 /* Use an invalid address value as 'not available' marker. */
59 enum { REG_UNAVAIL
= (CORE_ADDR
) -1 };
61 /* Use an impossible value as invalid offset. */
62 enum { INVALID_OFFSET
= (CORE_ADDR
) -1 };
64 /* Instruction groups for NDS32 epilogue analysis. */
67 /* Instructions used everywhere, not only in epilogue. */
69 /* Instructions used to reset sp for local vars, arguments, etc. */
71 /* Instructions used to recover saved regs and to recover padding. */
73 /* Instructions used to return to the caller. */
75 /* Instructions used to recover saved regs and to return to the caller. */
79 static const char *const nds32_register_names
[] =
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
85 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
90 static const char *const nds32_fdr_register_names
[] =
92 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
93 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
94 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
95 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
98 static const char *const nds32_fsr_register_names
[] =
100 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
101 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
102 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
103 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
106 /* The number of registers for four FPU configuration options. */
107 const int num_fdr_map
[] = { 4, 8, 16, 32 };
108 const int num_fsr_map
[] = { 8, 16, 32, 32 };
110 /* Aliases for registers. */
115 } nds32_register_aliases
[] =
131 {"cr6", "fucop_exist"},
148 {"ir14", "int_mask"},
149 {"ir15", "int_pend"},
153 {"ir19", "int_ctrl"},
155 {"ir21", "sp_priv1"},
157 {"ir23", "sp_priv2"},
159 {"ir25", "sp_priv3"},
160 {"ir26", "int_mask2"},
161 {"ir27", "int_pend2"},
162 {"ir28", "int_pri2"},
163 {"ir29", "int_trigger"},
173 {"mr8", "cache_ctl"},
174 {"mr9", "hsmp_saddr"},
175 {"mr10", "hsmp_eaddr"},
176 {"mr11", "bg_region"},
227 {"hspr0", "hsp_ctl"},
228 {"hspr1", "sp_bound"},
229 {"hspr2", "sp_bound_priv"},
237 {"dmar0", "dma_cfg"},
238 {"dmar1", "dma_gcsw"},
239 {"dmar2", "dma_chnsel"},
240 {"dmar3", "dma_act"},
241 {"dmar4", "dma_setup"},
242 {"dmar5", "dma_isaddr"},
243 {"dmar6", "dma_esaddr"},
244 {"dmar7", "dma_tcnt"},
245 {"dmar8", "dma_status"},
246 {"dmar9", "dma_2dset"},
247 {"dmar10", "dma_2dsctl"},
248 {"dmar11", "dma_rcnt"},
249 {"dmar12", "dma_hstatus"},
251 {"racr0", "prusr_acc_ctl"},
252 {"fucpr", "fucop_ctl"},
255 {"idr1", "misc_ctl"},
256 {"idr2", "ecc_misc"},
261 {"secur3", "p_isign"},
264 /* Value of a register alias. BATON is the regnum of the corresponding
267 static struct value
*
268 value_of_nds32_reg (struct frame_info
*frame
, const void *baton
)
270 return value_of_register ((int) (intptr_t) baton
, frame
);
273 /* Implement the "frame_align" gdbarch method. */
276 nds32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
278 /* 8-byte aligned. */
279 return align_down (sp
, 8);
282 /* The same insn machine code is used for little-endian and big-endian. */
283 constexpr gdb_byte nds32_break_insn
[] = { 0xEA, 0x00 };
285 typedef BP_MANIPULATION (nds32_break_insn
) nds32_breakpoint
;
287 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
290 nds32_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
292 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
294 const int FDR
= FSR
+ 32;
296 if (num
>= 0 && num
< 32)
298 /* General-purpose registers (R0 - R31). */
301 else if (num
>= FSR
&& num
< FSR
+ 32)
303 /* Single precision floating-point registers (FS0 - FS31). */
304 return num
- FSR
+ tdep
->fs0_regnum
;
306 else if (num
>= FDR
&& num
< FDR
+ 32)
308 /* Double precision floating-point registers (FD0 - FD31). */
309 return num
- FDR
+ NDS32_FD0_REGNUM
;
312 /* No match, return a inaccessible register number. */
316 /* NDS32 register groups. */
317 static struct reggroup
*nds32_cr_reggroup
;
318 static struct reggroup
*nds32_ir_reggroup
;
319 static struct reggroup
*nds32_mr_reggroup
;
320 static struct reggroup
*nds32_dr_reggroup
;
321 static struct reggroup
*nds32_pfr_reggroup
;
322 static struct reggroup
*nds32_hspr_reggroup
;
323 static struct reggroup
*nds32_dmar_reggroup
;
324 static struct reggroup
*nds32_racr_reggroup
;
325 static struct reggroup
*nds32_idr_reggroup
;
326 static struct reggroup
*nds32_secur_reggroup
;
329 nds32_init_reggroups (void)
331 nds32_cr_reggroup
= reggroup_new ("cr", USER_REGGROUP
);
332 nds32_ir_reggroup
= reggroup_new ("ir", USER_REGGROUP
);
333 nds32_mr_reggroup
= reggroup_new ("mr", USER_REGGROUP
);
334 nds32_dr_reggroup
= reggroup_new ("dr", USER_REGGROUP
);
335 nds32_pfr_reggroup
= reggroup_new ("pfr", USER_REGGROUP
);
336 nds32_hspr_reggroup
= reggroup_new ("hspr", USER_REGGROUP
);
337 nds32_dmar_reggroup
= reggroup_new ("dmar", USER_REGGROUP
);
338 nds32_racr_reggroup
= reggroup_new ("racr", USER_REGGROUP
);
339 nds32_idr_reggroup
= reggroup_new ("idr", USER_REGGROUP
);
340 nds32_secur_reggroup
= reggroup_new ("secur", USER_REGGROUP
);
344 nds32_add_reggroups (struct gdbarch
*gdbarch
)
346 /* Add pre-defined register groups. */
347 reggroup_add (gdbarch
, general_reggroup
);
348 reggroup_add (gdbarch
, float_reggroup
);
349 reggroup_add (gdbarch
, system_reggroup
);
350 reggroup_add (gdbarch
, all_reggroup
);
351 reggroup_add (gdbarch
, save_reggroup
);
352 reggroup_add (gdbarch
, restore_reggroup
);
354 /* Add NDS32 register groups. */
355 reggroup_add (gdbarch
, nds32_cr_reggroup
);
356 reggroup_add (gdbarch
, nds32_ir_reggroup
);
357 reggroup_add (gdbarch
, nds32_mr_reggroup
);
358 reggroup_add (gdbarch
, nds32_dr_reggroup
);
359 reggroup_add (gdbarch
, nds32_pfr_reggroup
);
360 reggroup_add (gdbarch
, nds32_hspr_reggroup
);
361 reggroup_add (gdbarch
, nds32_dmar_reggroup
);
362 reggroup_add (gdbarch
, nds32_racr_reggroup
);
363 reggroup_add (gdbarch
, nds32_idr_reggroup
);
364 reggroup_add (gdbarch
, nds32_secur_reggroup
);
367 /* Implement the "register_reggroup_p" gdbarch method. */
370 nds32_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
371 struct reggroup
*reggroup
)
373 const char *reg_name
;
374 const char *group_name
;
377 if (reggroup
== all_reggroup
)
380 /* General reggroup contains only GPRs and PC. */
381 if (reggroup
== general_reggroup
)
382 return regnum
<= NDS32_PC_REGNUM
;
384 if (reggroup
== float_reggroup
|| reggroup
== save_reggroup
385 || reggroup
== restore_reggroup
)
387 ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
391 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
394 if (reggroup
== system_reggroup
)
395 return (regnum
> NDS32_PC_REGNUM
)
396 && !nds32_register_reggroup_p (gdbarch
, regnum
, float_reggroup
);
398 /* The NDS32 reggroup contains registers whose name is prefixed
400 reg_name
= gdbarch_register_name (gdbarch
, regnum
);
401 group_name
= reggroup_name (reggroup
);
402 return !strncmp (reg_name
, group_name
, strlen (group_name
));
405 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
408 nds32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
410 regnum
-= gdbarch_num_regs (gdbarch
);
412 /* Currently, only FSRs could be defined as pseudo registers. */
413 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
414 return arch_float_type (gdbarch
, -1, "builtin_type_ieee_single",
415 floatformats_ieee_single
);
417 warning (_("Unknown nds32 pseudo register %d."), regnum
);
421 /* Implement the "pseudo_register_name" tdesc_arch_data method. */
424 nds32_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
426 regnum
-= gdbarch_num_regs (gdbarch
);
428 /* Currently, only FSRs could be defined as pseudo registers. */
429 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
430 return nds32_fsr_register_names
[regnum
];
432 warning (_("Unknown nds32 pseudo register %d."), regnum
);
436 /* Implement the "pseudo_register_read" gdbarch method. */
438 static enum register_status
439 nds32_pseudo_register_read (struct gdbarch
*gdbarch
,
440 readable_regcache
*regcache
, int regnum
,
443 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
445 int offset
, fdr_regnum
;
446 enum register_status status
;
448 /* This function is registered in nds32_gdbarch_init only after these are
450 gdb_assert (tdep
->fpu_freg
!= -1);
451 gdb_assert (tdep
->use_pseudo_fsrs
!= 0);
453 regnum
-= gdbarch_num_regs (gdbarch
);
455 /* Currently, only FSRs could be defined as pseudo registers. */
456 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
458 /* fs0 is always the most significant half of fd0. */
459 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
460 offset
= (regnum
& 1) ? 4 : 0;
462 offset
= (regnum
& 1) ? 0 : 4;
464 fdr_regnum
= NDS32_FD0_REGNUM
+ (regnum
>> 1);
465 status
= regcache
->raw_read (fdr_regnum
, reg_buf
);
466 if (status
== REG_VALID
)
467 memcpy (buf
, reg_buf
+ offset
, 4);
472 gdb_assert_not_reached ("invalid pseudo register number");
475 /* Implement the "pseudo_register_write" gdbarch method. */
478 nds32_pseudo_register_write (struct gdbarch
*gdbarch
,
479 struct regcache
*regcache
, int regnum
,
482 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
484 int offset
, fdr_regnum
;
486 /* This function is registered in nds32_gdbarch_init only after these are
488 gdb_assert (tdep
->fpu_freg
!= -1);
489 gdb_assert (tdep
->use_pseudo_fsrs
!= 0);
491 regnum
-= gdbarch_num_regs (gdbarch
);
493 /* Currently, only FSRs could be defined as pseudo registers. */
494 if (regnum
< gdbarch_num_pseudo_regs (gdbarch
))
496 /* fs0 is always the most significant half of fd0. */
497 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
498 offset
= (regnum
& 1) ? 4 : 0;
500 offset
= (regnum
& 1) ? 0 : 4;
502 fdr_regnum
= NDS32_FD0_REGNUM
+ (regnum
>> 1);
503 regcache
->raw_read (fdr_regnum
, reg_buf
);
504 memcpy (reg_buf
+ offset
, buf
, 4);
505 regcache
->raw_write (fdr_regnum
, reg_buf
);
509 gdb_assert_not_reached ("invalid pseudo register number");
512 /* Helper function for NDS32 ABI. Return true if FPRs can be used
513 to pass function arguments and return value. */
516 nds32_abi_use_fpr (int elf_abi
)
518 return elf_abi
== E_NDS_ABI_V2FP_PLUS
;
521 /* Helper function for NDS32 ABI. Return true if GPRs and stack
522 can be used together to pass an argument. */
525 nds32_abi_split (int elf_abi
)
527 return elf_abi
== E_NDS_ABI_AABI
;
530 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
532 struct nds32_frame_cache
534 /* The previous frame's inner most stack address. Used as this
535 frame ID's stack_addr. */
538 /* The frame's base, optionally used by the high-level debug info. */
541 /* During prologue analysis, keep how far the SP and FP have been offset
542 from the start of the stack frame (as defined by the previous frame's
544 During epilogue analysis, keep how far the SP has been offset from the
545 current stack pointer. */
549 /* The address of the first instruction in this function. */
552 /* Saved registers. */
553 CORE_ADDR saved_regs
[NDS32_NUM_SAVED_REGS
];
556 /* Allocate and initialize a frame cache. */
558 static struct nds32_frame_cache
*
559 nds32_alloc_frame_cache (void)
561 struct nds32_frame_cache
*cache
;
564 cache
= FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache
);
566 /* Initialize fp_offset to check if FP is set in prologue. */
567 cache
->fp_offset
= INVALID_OFFSET
;
569 /* Saved registers. We initialize these to -1 since zero is a valid
571 for (i
= 0; i
< NDS32_NUM_SAVED_REGS
; i
++)
572 cache
->saved_regs
[i
] = REG_UNAVAIL
;
577 /* Helper function for instructions used to push multiple words. */
580 nds32_push_multiple_words (struct nds32_frame_cache
*cache
, int rb
, int re
,
583 CORE_ADDR sp_offset
= cache
->sp_offset
;
586 /* Check LP, GP, FP in enable4. */
587 for (i
= 1; i
<= 3; i
++)
589 if ((enable4
>> i
) & 0x1)
592 cache
->saved_regs
[NDS32_SP_REGNUM
- i
] = sp_offset
;
596 /* Skip case where re == rb == sp. */
597 if ((rb
< REG_FP
) && (re
< REG_FP
))
599 for (i
= re
; i
>= rb
; i
--)
602 cache
->saved_regs
[i
] = sp_offset
;
606 /* For sp, update the offset. */
607 cache
->sp_offset
= sp_offset
;
610 /* Analyze the instructions within the given address range. If CACHE
611 is non-NULL, fill it in. Return the first address beyond the given
612 address range. If CACHE is NULL, return the first address not
613 recognized as a prologue instruction. */
616 nds32_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
617 CORE_ADDR limit_pc
, struct nds32_frame_cache
*cache
)
619 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
620 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
621 /* Current scanning status. */
622 int in_prologue_bb
= 0;
624 uint32_t insn
, insn_len
;
626 for (; pc
< limit_pc
; pc
+= insn_len
)
628 insn
= read_memory_unsigned_integer (pc
, 4, BFD_ENDIAN_BIG
);
630 if ((insn
& 0x80000000) == 0)
632 /* 32-bit instruction */
635 if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_SP
, REG_SP
, 0))
637 /* addi $sp, $sp, imm15s */
638 int imm15s
= N32_IMM15S (insn
);
643 cache
->sp_offset
+= -imm15s
;
649 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_FP
, REG_SP
, 0))
651 /* addi $fp, $sp, imm15s */
652 int imm15s
= N32_IMM15S (insn
);
657 cache
->fp_offset
= cache
->sp_offset
- imm15s
;
663 else if ((insn
& ~(__MASK (19) << 6)) == N32_SMW_ADM
664 && N32_RA5 (insn
) == REG_SP
)
666 /* smw.adm Rb, [$sp], Re, enable4 */
668 nds32_push_multiple_words (cache
, N32_RT5 (insn
),
670 N32_LSMW_ENABLE4 (insn
));
674 else if (insn
== N32_ALU1 (ADD
, REG_SP
, REG_SP
, REG_TA
)
675 || insn
== N32_ALU1 (ADD
, REG_SP
, REG_TA
, REG_SP
))
677 /* add $sp, $sp, $ta */
678 /* add $sp, $ta, $sp */
682 cache
->sp_offset
+= -val_ta
;
688 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (MOVI
, REG_TA
, 0))
690 /* movi $ta, imm20s */
692 val_ta
= N32_IMM20S (insn
);
696 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (SETHI
, REG_TA
, 0))
698 /* sethi $ta, imm20u */
700 val_ta
= N32_IMM20U (insn
) << 12;
704 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ORI
, REG_TA
, REG_TA
, 0))
706 /* ori $ta, $ta, imm15u */
708 val_ta
|= N32_IMM15U (insn
);
712 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_TA
, REG_TA
, 0))
714 /* addi $ta, $ta, imm15s */
716 val_ta
+= N32_IMM15S (insn
);
720 if (insn
== N32_ALU1 (ADD
, REG_GP
, REG_TA
, REG_GP
)
721 || insn
== N32_ALU1 (ADD
, REG_GP
, REG_GP
, REG_TA
))
723 /* add $gp, $ta, $gp */
724 /* add $gp, $gp, $ta */
728 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (MOVI
, REG_GP
, 0))
730 /* movi $gp, imm20s */
734 else if (CHOP_BITS (insn
, 20) == N32_TYPE1 (SETHI
, REG_GP
, 0))
736 /* sethi $gp, imm20u */
740 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ORI
, REG_GP
, REG_GP
, 0))
742 /* ori $gp, $gp, imm15u */
748 /* Jump/Branch insns never appear in prologue basic block.
749 The loop can be escaped early when these insns are met. */
750 if (in_prologue_bb
== 1)
752 int op
= N32_OP6 (insn
);
755 || op
== N32_OP6_JREG
758 || op
== N32_OP6_BR3
)
763 if (abi_use_fpr
&& N32_OP6 (insn
) == N32_OP6_SDC
764 && __GF (insn
, 12, 3) == 0)
766 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
767 normal form (bit [12] == 0) is used. */
769 /* fsdi FDt, [$sp + (imm12s << 2)] */
770 if (N32_RA5 (insn
) == REG_SP
)
774 /* The optimizer might shove anything into the prologue, if
775 we build up cache (cache != NULL) from analyzing prologue,
776 we just skip what we don't recognize and analyze further to
777 make cache as complete as possible. However, if we skip
778 prologue, we'll stop immediately on unrecognized
785 /* 16-bit instruction */
790 if (CHOP_BITS (insn
, 10) == N16_TYPE10 (ADDI10S
, 0))
793 int imm10s
= N16_IMM10S (insn
);
798 cache
->sp_offset
+= -imm10s
;
804 else if (__GF (insn
, 7, 8) == N16_T25_PUSH25
)
809 int imm8u
= (insn
& 0x1f) << 3;
810 int re
= (insn
>> 5) & 0x3;
811 const int reg_map
[] = { 6, 8, 10, 14 };
813 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
814 nds32_push_multiple_words (cache
, 6, reg_map
[re
], 0xe);
816 /* Operation 2 -- sp = sp - (imm5u << 3) */
817 cache
->sp_offset
+= imm8u
;
823 else if (insn
== N16_TYPE5 (ADD5PC
, REG_GP
))
829 else if (CHOP_BITS (insn
, 5) == N16_TYPE55 (MOVI55
, REG_GP
, 0))
831 /* movi55 $gp, imm5s */
837 /* Jump/Branch insns never appear in prologue basic block.
838 The loop can be escaped early when these insns are met. */
839 if (in_prologue_bb
== 1)
841 uint32_t insn5
= CHOP_BITS (insn
, 5);
842 uint32_t insn8
= CHOP_BITS (insn
, 8);
843 uint32_t insn38
= CHOP_BITS (insn
, 11);
845 if (insn5
== N16_TYPE5 (JR5
, 0)
846 || insn5
== N16_TYPE5 (JRAL5
, 0)
847 || insn5
== N16_TYPE5 (RET5
, 0)
848 || insn8
== N16_TYPE8 (J8
, 0)
849 || insn8
== N16_TYPE8 (BEQZS8
, 0)
850 || insn8
== N16_TYPE8 (BNEZS8
, 0)
851 || insn38
== N16_TYPE38 (BEQZ38
, 0, 0)
852 || insn38
== N16_TYPE38 (BNEZ38
, 0, 0)
853 || insn38
== N16_TYPE38 (BEQS38
, 0, 0)
854 || insn38
== N16_TYPE38 (BNES38
, 0, 0))
859 /* The optimizer might shove anything into the prologue, if
860 we build up cache (cache != NULL) from analyzing prologue,
861 we just skip what we don't recognize and analyze further to
862 make cache as complete as possible. However, if we skip
863 prologue, we'll stop immediately on unrecognized
873 /* Implement the "skip_prologue" gdbarch method.
875 Find the end of function prologue. */
878 nds32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
880 CORE_ADDR func_addr
, limit_pc
;
882 /* See if we can determine the end of the prologue via the symbol table.
883 If so, then return either PC, or the PC after the prologue, whichever
885 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
887 CORE_ADDR post_prologue_pc
888 = skip_prologue_using_sal (gdbarch
, func_addr
);
889 if (post_prologue_pc
!= 0)
890 return std::max (pc
, post_prologue_pc
);
893 /* Can't determine prologue from the symbol table, need to examine
896 /* Find an upper limit on the function prologue using the debug
897 information. If the debug information could not be used to provide
898 that bound, then use an arbitrary large number as the upper bound. */
899 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
901 limit_pc
= pc
+ 128; /* Magic. */
903 /* Find the end of prologue. */
904 return nds32_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
907 /* Allocate and fill in *THIS_CACHE with information about the prologue of
908 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
909 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
911 static struct nds32_frame_cache
*
912 nds32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
914 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
915 struct nds32_frame_cache
*cache
;
916 CORE_ADDR current_pc
;
922 return (struct nds32_frame_cache
*) *this_cache
;
924 cache
= nds32_alloc_frame_cache ();
927 cache
->pc
= get_frame_func (this_frame
);
928 current_pc
= get_frame_pc (this_frame
);
929 nds32_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
);
931 /* Compute the previous frame's stack pointer (which is also the
932 frame's ID's stack address), and this frame's base pointer. */
933 if (cache
->fp_offset
!= INVALID_OFFSET
)
935 /* FP is set in prologue, so it can be used to calculate other info. */
936 this_base
= get_frame_register_unsigned (this_frame
, NDS32_FP_REGNUM
);
937 prev_sp
= this_base
+ cache
->fp_offset
;
941 this_base
= get_frame_register_unsigned (this_frame
, NDS32_SP_REGNUM
);
942 prev_sp
= this_base
+ cache
->sp_offset
;
945 cache
->prev_sp
= prev_sp
;
946 cache
->base
= this_base
;
948 /* Adjust all the saved registers such that they contain addresses
949 instead of offsets. */
950 for (i
= 0; i
< NDS32_NUM_SAVED_REGS
; i
++)
951 if (cache
->saved_regs
[i
] != REG_UNAVAIL
)
952 cache
->saved_regs
[i
] = cache
->prev_sp
- cache
->saved_regs
[i
];
957 /* Implement the "this_id" frame_unwind method.
959 Our frame ID for a normal frame is the current function's starting
960 PC and the caller's SP when we were called. */
963 nds32_frame_this_id (struct frame_info
*this_frame
,
964 void **this_cache
, struct frame_id
*this_id
)
966 struct nds32_frame_cache
*cache
= nds32_frame_cache (this_frame
, this_cache
);
968 /* This marks the outermost frame. */
969 if (cache
->prev_sp
== 0)
972 *this_id
= frame_id_build (cache
->prev_sp
, cache
->pc
);
975 /* Implement the "prev_register" frame_unwind method. */
977 static struct value
*
978 nds32_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
981 struct nds32_frame_cache
*cache
= nds32_frame_cache (this_frame
, this_cache
);
983 if (regnum
== NDS32_SP_REGNUM
)
984 return frame_unwind_got_constant (this_frame
, regnum
, cache
->prev_sp
);
986 /* The PC of the previous frame is stored in the LP register of
987 the current frame. */
988 if (regnum
== NDS32_PC_REGNUM
)
989 regnum
= NDS32_LP_REGNUM
;
991 if (regnum
< NDS32_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != REG_UNAVAIL
)
992 return frame_unwind_got_memory (this_frame
, regnum
,
993 cache
->saved_regs
[regnum
]);
995 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
998 static const struct frame_unwind nds32_frame_unwind
=
1002 default_frame_unwind_stop_reason
,
1003 nds32_frame_this_id
,
1004 nds32_frame_prev_register
,
1006 default_frame_sniffer
,
1009 /* Return the frame base address of *THIS_FRAME. */
1012 nds32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1014 struct nds32_frame_cache
*cache
= nds32_frame_cache (this_frame
, this_cache
);
1019 static const struct frame_base nds32_frame_base
=
1021 &nds32_frame_unwind
,
1022 nds32_frame_base_address
,
1023 nds32_frame_base_address
,
1024 nds32_frame_base_address
1027 /* Helper function for instructions used to pop multiple words. */
1030 nds32_pop_multiple_words (struct nds32_frame_cache
*cache
, int rb
, int re
,
1033 CORE_ADDR sp_offset
= cache
->sp_offset
;
1036 /* Skip case where re == rb == sp. */
1037 if ((rb
< REG_FP
) && (re
< REG_FP
))
1039 for (i
= rb
; i
<= re
; i
++)
1041 cache
->saved_regs
[i
] = sp_offset
;
1046 /* Check FP, GP, LP in enable4. */
1047 for (i
= 3; i
>= 1; i
--)
1049 if ((enable4
>> i
) & 0x1)
1051 cache
->saved_regs
[NDS32_SP_REGNUM
- i
] = sp_offset
;
1056 /* For sp, update the offset. */
1057 cache
->sp_offset
= sp_offset
;
1060 /* The instruction sequences in NDS32 epilogue are
1062 INSN_RESET_SP (optional)
1063 (If exists, this must be the first instruction in epilogue
1064 and the stack has not been destroyed.).
1065 INSN_RECOVER (optional).
1066 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1068 /* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1069 the necessary information will be recorded. */
1072 nds32_analyze_epilogue_insn32 (int abi_use_fpr
, uint32_t insn
,
1073 struct nds32_frame_cache
*cache
)
1075 if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_SP
, REG_SP
, 0)
1076 && N32_IMM15S (insn
) > 0)
1077 /* addi $sp, $sp, imm15s */
1078 return INSN_RESET_SP
;
1079 else if (CHOP_BITS (insn
, 15) == N32_TYPE2 (ADDI
, REG_SP
, REG_FP
, 0)
1080 && N32_IMM15S (insn
) < 0)
1081 /* addi $sp, $fp, imm15s */
1082 return INSN_RESET_SP
;
1083 else if ((insn
& ~(__MASK (19) << 6)) == N32_LMW_BIM
1084 && N32_RA5 (insn
) == REG_SP
)
1086 /* lmw.bim Rb, [$sp], Re, enable4 */
1088 nds32_pop_multiple_words (cache
, N32_RT5 (insn
),
1089 N32_RB5 (insn
), N32_LSMW_ENABLE4 (insn
));
1091 return INSN_RECOVER
;
1093 else if (insn
== N32_JREG (JR
, 0, REG_LP
, 0, 1))
1096 else if (insn
== N32_ALU1 (ADD
, REG_SP
, REG_SP
, REG_TA
)
1097 || insn
== N32_ALU1 (ADD
, REG_SP
, REG_TA
, REG_SP
))
1098 /* add $sp, $sp, $ta */
1099 /* add $sp, $ta, $sp */
1100 return INSN_RESET_SP
;
1101 else if (abi_use_fpr
1102 && (insn
& ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP
)
1104 if (__GF (insn
, 12, 1) == 0)
1105 /* fldi FDt, [$sp + (imm12s << 2)] */
1106 return INSN_RECOVER
;
1109 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1110 int offset
= N32_IMM12S (insn
) << 2;
1112 if (offset
== 8 || offset
== 12)
1115 cache
->sp_offset
+= offset
;
1117 return INSN_RECOVER
;
1125 /* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1126 the necessary information will be recorded. */
1129 nds32_analyze_epilogue_insn16 (uint32_t insn
, struct nds32_frame_cache
*cache
)
1131 if (insn
== N16_TYPE5 (RET5
, REG_LP
))
1134 else if (CHOP_BITS (insn
, 10) == N16_TYPE10 (ADDI10S
, 0))
1137 int imm10s
= N16_IMM10S (insn
);
1142 cache
->sp_offset
+= imm10s
;
1144 return INSN_RECOVER
;
1147 else if (__GF (insn
, 7, 8) == N16_T25_POP25
)
1152 int imm8u
= (insn
& 0x1f) << 3;
1153 int re
= (insn
>> 5) & 0x3;
1154 const int reg_map
[] = { 6, 8, 10, 14 };
1156 /* Operation 1 -- sp = sp + (imm5u << 3) */
1157 cache
->sp_offset
+= imm8u
;
1159 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1160 nds32_pop_multiple_words (cache
, 6, reg_map
[re
], 0xe);
1163 /* Operation 3 -- ret $lp */
1164 return INSN_RECOVER_RETURN
;
1170 /* Analyze a reasonable amount of instructions from the given PC to find
1171 the instruction used to return to the caller. Return 1 if the 'return'
1172 instruction could be found, 0 otherwise.
1174 If CACHE is non-NULL, fill it in. */
1177 nds32_analyze_epilogue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1178 struct nds32_frame_cache
*cache
)
1180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1181 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1183 uint32_t insn
, insn_len
;
1184 int insn_type
= INSN_NORMAL
;
1191 for (; pc
< limit_pc
; pc
+= insn_len
)
1193 insn
= read_memory_unsigned_integer (pc
, 4, BFD_ENDIAN_BIG
);
1195 if ((insn
& 0x80000000) == 0)
1197 /* 32-bit instruction */
1200 insn_type
= nds32_analyze_epilogue_insn32 (abi_use_fpr
, insn
, cache
);
1201 if (insn_type
== INSN_RETURN
)
1203 else if (insn_type
== INSN_RECOVER
)
1208 /* 16-bit instruction */
1212 insn_type
= nds32_analyze_epilogue_insn16 (insn
, cache
);
1213 if (insn_type
== INSN_RETURN
|| insn_type
== INSN_RECOVER_RETURN
)
1215 else if (insn_type
== INSN_RECOVER
)
1219 /* Stop the scan if this is an unexpected instruction. */
1226 /* Implement the "stack_frame_destroyed_p" gdbarch method. */
1229 nds32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1232 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1233 int insn_type
= INSN_NORMAL
;
1237 insn
= read_memory_unsigned_integer (addr
, 4, BFD_ENDIAN_BIG
);
1239 if ((insn
& 0x80000000) == 0)
1241 /* 32-bit instruction */
1243 insn_type
= nds32_analyze_epilogue_insn32 (abi_use_fpr
, insn
, NULL
);
1247 /* 16-bit instruction */
1250 insn_type
= nds32_analyze_epilogue_insn16 (insn
, NULL
);
1253 if (insn_type
== INSN_NORMAL
|| insn_type
== INSN_RESET_SP
)
1256 /* Search the required 'return' instruction within the following reasonable
1258 ret_found
= nds32_analyze_epilogue (gdbarch
, addr
, NULL
);
1262 /* Scan backwards to make sure that the last instruction has adjusted
1263 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1264 just a heuristic, so the false positives will be acceptable. */
1265 insn
= read_memory_unsigned_integer (addr
- 2, 4, BFD_ENDIAN_BIG
);
1267 /* Only 16-bit instructions are possible at addr - 2. */
1268 if ((insn
& 0x80000000) != 0)
1270 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1272 insn_type
= nds32_analyze_epilogue_insn16 (insn
>> 16, NULL
);
1273 if (insn_type
== INSN_RECOVER
)
1277 insn
= read_memory_unsigned_integer (addr
- 4, 4, BFD_ENDIAN_BIG
);
1279 /* If this is a 16-bit instruction at addr - 4, then there must be another
1280 16-bit instruction at addr - 2, so only 32-bit instructions need to
1281 be analyzed here. */
1282 if ((insn
& 0x80000000) == 0)
1284 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1286 insn_type
= nds32_analyze_epilogue_insn32 (abi_use_fpr
, insn
, NULL
);
1287 if (insn_type
== INSN_RECOVER
|| insn_type
== INSN_RESET_SP
)
1294 /* Implement the "sniffer" frame_unwind method. */
1297 nds32_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1298 struct frame_info
*this_frame
, void **this_cache
)
1300 if (frame_relative_level (this_frame
) == 0)
1301 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame
),
1302 get_frame_pc (this_frame
));
1307 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1308 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1309 allocated. Return a pointer to the current nds32_frame_cache in
1312 static struct nds32_frame_cache
*
1313 nds32_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1315 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1316 struct nds32_frame_cache
*cache
;
1317 CORE_ADDR current_pc
, current_sp
;
1321 return (struct nds32_frame_cache
*) *this_cache
;
1323 cache
= nds32_alloc_frame_cache ();
1324 *this_cache
= cache
;
1326 cache
->pc
= get_frame_func (this_frame
);
1327 current_pc
= get_frame_pc (this_frame
);
1328 nds32_analyze_epilogue (gdbarch
, current_pc
, cache
);
1330 current_sp
= get_frame_register_unsigned (this_frame
, NDS32_SP_REGNUM
);
1331 cache
->prev_sp
= current_sp
+ cache
->sp_offset
;
1333 /* Adjust all the saved registers such that they contain addresses
1334 instead of offsets. */
1335 for (i
= 0; i
< NDS32_NUM_SAVED_REGS
; i
++)
1336 if (cache
->saved_regs
[i
] != REG_UNAVAIL
)
1337 cache
->saved_regs
[i
] = current_sp
+ cache
->saved_regs
[i
];
1342 /* Implement the "this_id" frame_unwind method. */
1345 nds32_epilogue_frame_this_id (struct frame_info
*this_frame
,
1346 void **this_cache
, struct frame_id
*this_id
)
1348 struct nds32_frame_cache
*cache
1349 = nds32_epilogue_frame_cache (this_frame
, this_cache
);
1351 /* This marks the outermost frame. */
1352 if (cache
->prev_sp
== 0)
1355 *this_id
= frame_id_build (cache
->prev_sp
, cache
->pc
);
1358 /* Implement the "prev_register" frame_unwind method. */
1360 static struct value
*
1361 nds32_epilogue_frame_prev_register (struct frame_info
*this_frame
,
1362 void **this_cache
, int regnum
)
1364 struct nds32_frame_cache
*cache
1365 = nds32_epilogue_frame_cache (this_frame
, this_cache
);
1367 if (regnum
== NDS32_SP_REGNUM
)
1368 return frame_unwind_got_constant (this_frame
, regnum
, cache
->prev_sp
);
1370 /* The PC of the previous frame is stored in the LP register of
1371 the current frame. */
1372 if (regnum
== NDS32_PC_REGNUM
)
1373 regnum
= NDS32_LP_REGNUM
;
1375 if (regnum
< NDS32_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != REG_UNAVAIL
)
1376 return frame_unwind_got_memory (this_frame
, regnum
,
1377 cache
->saved_regs
[regnum
]);
1379 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1382 static const struct frame_unwind nds32_epilogue_frame_unwind
=
1386 default_frame_unwind_stop_reason
,
1387 nds32_epilogue_frame_this_id
,
1388 nds32_epilogue_frame_prev_register
,
1390 nds32_epilogue_frame_sniffer
1394 /* Floating type and struct type that has only one floating type member
1395 can pass value using FPU registers (when FPU ABI is used). */
1398 nds32_check_calling_use_fpr (struct type
*type
)
1401 enum type_code typecode
;
1406 t
= check_typedef (t
);
1407 typecode
= t
->code ();
1408 if (typecode
!= TYPE_CODE_STRUCT
)
1410 else if (t
->num_fields () != 1)
1413 t
= t
->field (0).type ();
1416 return typecode
== TYPE_CODE_FLT
;
1419 /* Implement the "push_dummy_call" gdbarch method. */
1422 nds32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1423 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1424 int nargs
, struct value
**args
, CORE_ADDR sp
,
1425 function_call_return_method return_method
,
1426 CORE_ADDR struct_addr
)
1428 const int REND
= 6; /* End for register offset. */
1429 int goff
= 0; /* Current gpr offset for argument. */
1430 int foff
= 0; /* Current fpr offset for argument. */
1431 int soff
= 0; /* Current stack offset for argument. */
1434 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1435 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1436 struct type
*func_type
= value_type (function
);
1437 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1438 int abi_split
= nds32_abi_split (tdep
->elf_abi
);
1440 /* Set the return address. For the NDS32, the return breakpoint is
1441 always at BP_ADDR. */
1442 regcache_cooked_write_unsigned (regcache
, NDS32_LP_REGNUM
, bp_addr
);
1444 /* If STRUCT_RETURN is true, then the struct return address (in
1445 STRUCT_ADDR) will consume the first argument-passing register.
1446 Both adjust the register count and store that value. */
1447 if (return_method
== return_method_struct
)
1449 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
, struct_addr
);
1453 /* Now make sure there's space on the stack */
1454 for (i
= 0; i
< nargs
; i
++)
1456 struct type
*type
= value_type (args
[i
]);
1457 int align
= type_align (type
);
1459 /* If align is zero, it may be an empty struct.
1460 Just ignore the argument of empty struct. */
1464 sp
-= TYPE_LENGTH (type
);
1465 sp
= align_down (sp
, align
);
1468 /* Stack must be 8-byte aligned. */
1469 sp
= align_down (sp
, 8);
1472 for (i
= 0; i
< nargs
; i
++)
1474 const gdb_byte
*val
;
1477 int calling_use_fpr
;
1480 type
= value_type (args
[i
]);
1481 calling_use_fpr
= nds32_check_calling_use_fpr (type
);
1482 len
= TYPE_LENGTH (type
);
1483 align
= type_align (type
);
1484 val
= value_contents (args
[i
]);
1486 /* The size of a composite type larger than 4 bytes will be rounded
1487 up to the nearest multiple of 4. */
1489 len
= align_up (len
, 4);
1491 /* Variadic functions are handled differently between AABI and ABI2FP+.
1493 For AABI, the caller pushes arguments in registers, callee stores
1494 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1495 Therefore, we don't have to handle variadic functions specially.
1497 For ABI2FP+, the caller pushes only named arguments in registers
1498 and pushes all unnamed arguments in stack. */
1500 if (abi_use_fpr
&& func_type
->has_varargs ()
1501 && i
>= func_type
->num_fields ())
1504 /* Try to use FPRs to pass arguments only when
1505 1. The program is built using toolchain with FPU support.
1506 2. The type of this argument can use FPR to pass value. */
1507 use_fpr
= abi_use_fpr
&& calling_use_fpr
;
1511 if (tdep
->fpu_freg
== -1)
1514 /* Adjust alignment. */
1515 if ((align
>> 2) > 0)
1516 foff
= align_up (foff
, align
>> 2);
1523 regcache
->cooked_write (tdep
->fs0_regnum
+ foff
, val
);
1527 regcache
->cooked_write (NDS32_FD0_REGNUM
+ (foff
>> 1), val
);
1532 internal_error (__FILE__
, __LINE__
,
1533 "Do not know how to handle %d-byte double.\n",
1543 When passing arguments using GPRs,
1545 * A composite type not larger than 4 bytes is passed in $rN.
1546 The format is as if the value is loaded with load instruction
1547 of corresponding size (e.g., LB, LH, LW).
1556 * Otherwise, a composite type is passed in consecutive registers.
1557 The size is rounded up to the nearest multiple of 4.
1558 The successive registers hold the parts of the argument as if
1559 were loaded using lmw instructions.
1565 LITTLE: [d c b a] [x x x e]
1566 BIG: [a b c d] [e x x x]
1569 /* Adjust alignment. */
1570 if ((align
>> 2) > 0)
1571 goff
= align_up (goff
, align
>> 2);
1573 if (len
<= (REND
- goff
) * 4)
1575 /* This argument can be passed wholly via GPRs. */
1578 regval
= extract_unsigned_integer (val
, (len
> 4) ? 4 : len
,
1580 regcache_cooked_write_unsigned (regcache
,
1581 NDS32_R0_REGNUM
+ goff
,
1591 /* Some parts of this argument can be passed via GPRs. */
1594 regval
= extract_unsigned_integer (val
, (len
> 4) ? 4 : len
,
1596 regcache_cooked_write_unsigned (regcache
,
1597 NDS32_R0_REGNUM
+ goff
,
1608 When pushing (split parts of) an argument into stack,
1610 * A composite type not larger than 4 bytes is copied to different
1612 In little-endian, the first byte of this argument is aligned
1613 at the low address of the next free word.
1614 In big-endian, the last byte of this argument is aligned
1615 at the high address of the next free word.
1626 /* Adjust alignment. */
1627 soff
= align_up (soff
, align
);
1631 int rlen
= (len
> 4) ? 4 : len
;
1633 if (byte_order
== BFD_ENDIAN_BIG
)
1634 write_memory (sp
+ soff
+ 4 - rlen
, val
, rlen
);
1636 write_memory (sp
+ soff
, val
, rlen
);
1644 /* Finally, update the SP register. */
1645 regcache_cooked_write_unsigned (regcache
, NDS32_SP_REGNUM
, sp
);
1650 /* If use_fpr, but no floating-point register exists,
1651 then it is an error. */
1652 error (_("Fail to call. FPU registers are required."));
1655 /* Read, for architecture GDBARCH, a function return value of TYPE
1656 from REGCACHE, and copy that into VALBUF. */
1659 nds32_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1660 struct regcache
*regcache
, gdb_byte
*valbuf
)
1662 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1663 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1664 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1665 int calling_use_fpr
;
1668 calling_use_fpr
= nds32_check_calling_use_fpr (type
);
1669 len
= TYPE_LENGTH (type
);
1671 if (abi_use_fpr
&& calling_use_fpr
)
1674 regcache
->cooked_read (tdep
->fs0_regnum
, valbuf
);
1676 regcache
->cooked_read (NDS32_FD0_REGNUM
, valbuf
);
1678 internal_error (__FILE__
, __LINE__
,
1679 _("Cannot extract return value of %d bytes "
1680 "long floating-point."), len
);
1685 When returning result,
1687 * A composite type not larger than 4 bytes is returned in $r0.
1688 The format is as if the result is loaded with load instruction
1689 of corresponding size (e.g., LB, LH, LW).
1698 * Otherwise, a composite type not larger than 8 bytes is returned
1700 In little-endian, the first word is loaded in $r0.
1701 In big-endian, the last word is loaded in $r1.
1707 LITTLE: [d c b a] [x x x e]
1708 BIG: [x x x a] [b c d e]
1715 /* By using store_unsigned_integer we avoid having to do
1716 anything special for small big-endian values. */
1717 regcache_cooked_read_unsigned (regcache
, NDS32_R0_REGNUM
, &tmp
);
1718 store_unsigned_integer (valbuf
, len
, byte_order
, tmp
);
1722 regcache
->cooked_read (NDS32_R0_REGNUM
, valbuf
);
1728 len1
= byte_order
== BFD_ENDIAN_BIG
? len
- 4 : 4;
1731 regcache_cooked_read_unsigned (regcache
, NDS32_R0_REGNUM
, &tmp
);
1732 store_unsigned_integer (valbuf
, len1
, byte_order
, tmp
);
1734 regcache_cooked_read_unsigned (regcache
, NDS32_R0_REGNUM
+ 1, &tmp
);
1735 store_unsigned_integer (valbuf
+ len1
, len2
, byte_order
, tmp
);
1739 regcache
->cooked_read (NDS32_R0_REGNUM
, valbuf
);
1740 regcache
->cooked_read (NDS32_R0_REGNUM
+ 1, valbuf
+ 4);
1745 /* Write, for architecture GDBARCH, a function return value of TYPE
1746 from VALBUF into REGCACHE. */
1749 nds32_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1750 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1752 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1753 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1754 int abi_use_fpr
= nds32_abi_use_fpr (tdep
->elf_abi
);
1755 int calling_use_fpr
;
1758 calling_use_fpr
= nds32_check_calling_use_fpr (type
);
1759 len
= TYPE_LENGTH (type
);
1761 if (abi_use_fpr
&& calling_use_fpr
)
1764 regcache
->cooked_write (tdep
->fs0_regnum
, valbuf
);
1766 regcache
->cooked_write (NDS32_FD0_REGNUM
, valbuf
);
1768 internal_error (__FILE__
, __LINE__
,
1769 _("Cannot store return value of %d bytes "
1770 "long floating-point."), len
);
1778 regval
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1779 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
, regval
);
1783 regcache
->cooked_write (NDS32_R0_REGNUM
, valbuf
);
1789 len1
= byte_order
== BFD_ENDIAN_BIG
? len
- 4 : 4;
1792 regval
= extract_unsigned_integer (valbuf
, len1
, byte_order
);
1793 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
, regval
);
1795 regval
= extract_unsigned_integer (valbuf
+ len1
, len2
, byte_order
);
1796 regcache_cooked_write_unsigned (regcache
, NDS32_R0_REGNUM
+ 1,
1801 regcache
->cooked_write (NDS32_R0_REGNUM
, valbuf
);
1802 regcache
->cooked_write (NDS32_R0_REGNUM
+ 1, valbuf
+ 4);
1807 /* Implement the "return_value" gdbarch method.
1809 Determine, for architecture GDBARCH, how a return value of TYPE
1810 should be returned. If it is supposed to be returned in registers,
1811 and READBUF is non-zero, read the appropriate value from REGCACHE,
1812 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1813 from WRITEBUF into REGCACHE. */
1815 static enum return_value_convention
1816 nds32_return_value (struct gdbarch
*gdbarch
, struct value
*func_type
,
1817 struct type
*type
, struct regcache
*regcache
,
1818 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1820 if (TYPE_LENGTH (type
) > 8)
1822 return RETURN_VALUE_STRUCT_CONVENTION
;
1826 if (readbuf
!= NULL
)
1827 nds32_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
1828 if (writebuf
!= NULL
)
1829 nds32_store_return_value (gdbarch
, type
, regcache
, writebuf
);
1831 return RETURN_VALUE_REGISTER_CONVENTION
;
1835 /* Implement the "get_longjmp_target" gdbarch method. */
1838 nds32_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1842 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1843 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1845 jb_addr
= get_frame_register_unsigned (frame
, NDS32_R0_REGNUM
);
1847 if (target_read_memory (jb_addr
+ 11 * 4, buf
, 4))
1850 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1854 /* Validate the given TDESC, and fixed-number some registers in it.
1855 Return 0 if the given TDESC does not contain the required feature
1856 or not contain required registers. */
1859 nds32_validate_tdesc_p (const struct target_desc
*tdesc
,
1860 struct tdesc_arch_data
*tdesc_data
,
1861 int *fpu_freg
, int *use_pseudo_fsrs
)
1863 const struct tdesc_feature
*feature
;
1866 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.nds32.core");
1867 if (feature
== NULL
)
1871 /* Validate and fixed-number R0-R10. */
1872 for (i
= NDS32_R0_REGNUM
; i
<= NDS32_R0_REGNUM
+ 10; i
++)
1873 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1874 nds32_register_names
[i
]);
1877 valid_p
&= tdesc_unnumbered_register (feature
,
1878 nds32_register_names
[NDS32_TA_REGNUM
]);
1880 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1881 for (i
= NDS32_FP_REGNUM
; i
<= NDS32_PC_REGNUM
; i
++)
1882 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1883 nds32_register_names
[i
]);
1888 /* Fixed-number R11-R27. */
1889 for (i
= NDS32_R0_REGNUM
+ 11; i
<= NDS32_R0_REGNUM
+ 27; i
++)
1890 tdesc_numbered_register (feature
, tdesc_data
, i
, nds32_register_names
[i
]);
1892 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.nds32.fpu");
1893 if (feature
!= NULL
)
1895 int num_fdr_regs
, num_fsr_regs
, fs0_regnum
, num_listed_fsr
;
1898 /* Guess FPU configuration via listed registers. */
1899 if (tdesc_unnumbered_register (feature
, "fd31"))
1901 else if (tdesc_unnumbered_register (feature
, "fd15"))
1903 else if (tdesc_unnumbered_register (feature
, "fd7"))
1905 else if (tdesc_unnumbered_register (feature
, "fd3"))
1909 /* Required FDR is not found. */
1914 /* Validate and fixed-number required FDRs. */
1915 num_fdr_regs
= num_fdr_map
[freg
];
1916 for (i
= 0; i
< num_fdr_regs
; i
++)
1917 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
1918 NDS32_FD0_REGNUM
+ i
,
1919 nds32_fdr_register_names
[i
]);
1923 /* Count the number of listed FSRs, and fixed-number them if present. */
1924 num_fsr_regs
= num_fsr_map
[freg
];
1925 fs0_regnum
= NDS32_FD0_REGNUM
+ num_fdr_regs
;
1927 for (i
= 0; i
< num_fsr_regs
; i
++)
1928 num_listed_fsr
+= tdesc_numbered_register (feature
, tdesc_data
,
1930 nds32_fsr_register_names
[i
]);
1932 if (num_listed_fsr
== 0)
1933 /* No required FSRs are listed explicitly, make them pseudo registers
1935 *use_pseudo_fsrs
= 1;
1936 else if (num_listed_fsr
== num_fsr_regs
)
1937 /* All required FSRs are listed explicitly. */
1938 *use_pseudo_fsrs
= 0;
1940 /* Some required FSRs are missing. */
1947 /* Initialize the current architecture based on INFO. If possible,
1948 re-use an architecture from ARCHES, which is a list of
1949 architectures already created during this debugging session.
1951 Called e.g. at program startup, when reading a core file, and when
1952 reading a binary file. */
1954 static struct gdbarch
*
1955 nds32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1957 struct gdbarch
*gdbarch
;
1958 struct gdbarch_tdep
*tdep
;
1959 struct gdbarch_list
*best_arch
;
1960 tdesc_arch_data_up tdesc_data
;
1961 const struct target_desc
*tdesc
= info
.target_desc
;
1962 int elf_abi
= E_NDS_ABI_AABI
;
1964 int use_pseudo_fsrs
= 0;
1965 int i
, num_regs
, maxregs
;
1967 /* Extract the elf_flags if available. */
1968 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
1969 elf_abi
= elf_elfheader (info
.abfd
)->e_flags
& EF_NDS_ABI
;
1971 /* If there is already a candidate, use it. */
1972 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
1974 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
1976 struct gdbarch_tdep
*idep
= gdbarch_tdep (best_arch
->gdbarch
);
1978 if (idep
->elf_abi
!= elf_abi
)
1981 /* Found a match. */
1985 if (best_arch
!= NULL
)
1986 return best_arch
->gdbarch
;
1988 if (!tdesc_has_registers (tdesc
))
1989 tdesc
= tdesc_nds32
;
1991 tdesc_data
= tdesc_data_alloc ();
1993 if (!nds32_validate_tdesc_p (tdesc
, tdesc_data
.get (), &fpu_freg
,
1997 /* Allocate space for the new architecture. */
1998 tdep
= XCNEW (struct gdbarch_tdep
);
1999 tdep
->fpu_freg
= fpu_freg
;
2000 tdep
->use_pseudo_fsrs
= use_pseudo_fsrs
;
2001 tdep
->fs0_regnum
= -1;
2002 tdep
->elf_abi
= elf_abi
;
2004 gdbarch
= gdbarch_alloc (&info
, tdep
);
2006 set_gdbarch_wchar_bit (gdbarch
, 16);
2007 set_gdbarch_wchar_signed (gdbarch
, 0);
2010 num_regs
= NDS32_NUM_REGS
;
2011 else if (use_pseudo_fsrs
== 1)
2013 set_gdbarch_pseudo_register_read (gdbarch
, nds32_pseudo_register_read
);
2014 set_gdbarch_pseudo_register_write (gdbarch
, nds32_pseudo_register_write
);
2015 set_tdesc_pseudo_register_name (gdbarch
, nds32_pseudo_register_name
);
2016 set_tdesc_pseudo_register_type (gdbarch
, nds32_pseudo_register_type
);
2017 set_gdbarch_num_pseudo_regs (gdbarch
, num_fsr_map
[fpu_freg
]);
2019 num_regs
= NDS32_NUM_REGS
+ num_fdr_map
[fpu_freg
];
2022 num_regs
= NDS32_NUM_REGS
+ num_fdr_map
[fpu_freg
] + num_fsr_map
[fpu_freg
];
2024 set_gdbarch_num_regs (gdbarch
, num_regs
);
2025 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
2027 /* Cache the register number of fs0. */
2029 tdep
->fs0_regnum
= user_reg_map_name_to_regnum (gdbarch
, "fs0", -1);
2031 /* Add NDS32 register aliases. To avoid search in user register name space,
2032 user_reg_map_name_to_regnum is not used. */
2033 maxregs
= gdbarch_num_cooked_regs (gdbarch
);
2034 for (i
= 0; i
< ARRAY_SIZE (nds32_register_aliases
); i
++)
2039 /* Search register name space. */
2040 for (j
= 0; j
< maxregs
; j
++)
2042 const char *regname
= gdbarch_register_name (gdbarch
, j
);
2045 && strcmp (regname
, nds32_register_aliases
[i
].name
) == 0)
2052 /* Try next alias entry if the given name can not be found in register
2057 user_reg_add (gdbarch
, nds32_register_aliases
[i
].alias
,
2058 value_of_nds32_reg
, (const void *) (intptr_t) regnum
);
2061 nds32_add_reggroups (gdbarch
);
2063 /* Hook in ABI-specific overrides, if they have been registered. */
2064 info
.tdesc_data
= tdesc_data
.get ();
2065 gdbarch_init_osabi (info
, gdbarch
);
2067 /* Override tdesc_register callbacks for system registers. */
2068 set_gdbarch_register_reggroup_p (gdbarch
, nds32_register_reggroup_p
);
2070 set_gdbarch_sp_regnum (gdbarch
, NDS32_SP_REGNUM
);
2071 set_gdbarch_pc_regnum (gdbarch
, NDS32_PC_REGNUM
);
2072 set_gdbarch_stack_frame_destroyed_p (gdbarch
, nds32_stack_frame_destroyed_p
);
2073 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, nds32_dwarf2_reg_to_regnum
);
2075 set_gdbarch_push_dummy_call (gdbarch
, nds32_push_dummy_call
);
2076 set_gdbarch_return_value (gdbarch
, nds32_return_value
);
2078 set_gdbarch_skip_prologue (gdbarch
, nds32_skip_prologue
);
2079 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2080 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
2081 nds32_breakpoint::kind_from_pc
);
2082 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
2083 nds32_breakpoint::bp_from_kind
);
2085 set_gdbarch_frame_align (gdbarch
, nds32_frame_align
);
2086 frame_base_set_default (gdbarch
, &nds32_frame_base
);
2088 /* Handle longjmp. */
2089 set_gdbarch_get_longjmp_target (gdbarch
, nds32_get_longjmp_target
);
2091 /* The order of appending is the order it check frame. */
2092 dwarf2_append_unwinders (gdbarch
);
2093 frame_unwind_append_unwinder (gdbarch
, &nds32_epilogue_frame_unwind
);
2094 frame_unwind_append_unwinder (gdbarch
, &nds32_frame_unwind
);
2099 void _initialize_nds32_tdep ();
2101 _initialize_nds32_tdep ()
2103 /* Initialize gdbarch. */
2104 register_gdbarch_init (bfd_arch_nds32
, nds32_gdbarch_init
);
2106 initialize_tdesc_nds32 ();
2107 nds32_init_reggroups ();