1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "arch-utils.h"
36 #include "floatformat.h"
40 #include "reggroups.h"
45 #include "sh64-tdep.h"
48 #include "solib-svr4.h"
53 /* registers numbers shared with the simulator. */
54 #include "gdb/sim-sh.h"
57 /* List of "set sh ..." and "show sh ..." commands. */
58 static struct cmd_list_element
*setshcmdlist
= NULL
;
59 static struct cmd_list_element
*showshcmdlist
= NULL
;
61 static const char sh_cc_gcc
[] = "gcc";
62 static const char sh_cc_renesas
[] = "renesas";
63 static const char *const sh_cc_enum
[] = {
69 static const char *sh_active_calling_convention
= sh_cc_gcc
;
71 #define SH_NUM_REGS 67
80 /* Flag showing that a frame has been created in the prologue code. */
83 /* Saved registers. */
84 CORE_ADDR saved_regs
[SH_NUM_REGS
];
89 sh_is_renesas_calling_convention (struct type
*func_type
)
95 func_type
= check_typedef (func_type
);
97 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
98 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
100 if (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
101 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
105 if (sh_active_calling_convention
== sh_cc_renesas
)
112 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
114 static char *register_names
[] = {
115 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
116 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
117 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
119 "", "", "", "", "", "", "", "",
120 "", "", "", "", "", "", "", "",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
128 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
130 return register_names
[reg_nr
];
134 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
136 static char *register_names
[] = {
137 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
138 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
139 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
141 "", "", "", "", "", "", "", "",
142 "", "", "", "", "", "", "", "",
144 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
145 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
146 "", "", "", "", "", "", "", "",
150 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
152 return register_names
[reg_nr
];
156 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
158 static char *register_names
[] = {
159 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
160 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
161 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
163 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
164 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
166 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
167 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
168 "", "", "", "", "", "", "", "",
172 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
174 return register_names
[reg_nr
];
178 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
180 static char *register_names
[] = {
181 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
182 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
183 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
185 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
186 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
188 "", "", "", "", "", "", "", "",
189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
194 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
196 return register_names
[reg_nr
];
200 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
202 static char *register_names
[] = {
203 /* general registers 0-15 */
204 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
205 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
207 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 /* floating point registers 25 - 40 */
211 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
212 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
215 /* 43 - 62. Banked registers. The bank number used is determined by
216 the bank register (63). */
217 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
218 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
219 "machb", "ivnb", "prb", "gbrb", "maclb",
220 /* 63: register bank number, not a real register but used to
221 communicate the register bank currently get/set. This register
222 is hidden to the user, who manipulates it using the pseudo
223 register called "bank" (67). See below. */
226 "ibcr", "ibnr", "tbr",
227 /* 67: register bank number, the user visible pseudo register. */
229 /* double precision (pseudo) 68 - 75 */
230 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
234 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
236 return register_names
[reg_nr
];
240 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
242 static char *register_names
[] = {
243 /* general registers 0-15 */
244 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
245 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
247 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
250 /* floating point registers 25 - 40 */
251 "", "", "", "", "", "", "", "",
252 "", "", "", "", "", "", "", "",
255 /* 43 - 62. Banked registers. The bank number used is determined by
256 the bank register (63). */
257 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
258 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
259 "machb", "ivnb", "prb", "gbrb", "maclb",
260 /* 63: register bank number, not a real register but used to
261 communicate the register bank currently get/set. This register
262 is hidden to the user, who manipulates it using the pseudo
263 register called "bank" (67). See below. */
266 "ibcr", "ibnr", "tbr",
267 /* 67: register bank number, the user visible pseudo register. */
269 /* double precision (pseudo) 68 - 75 */
270 "", "", "", "", "", "", "", "",
274 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
276 return register_names
[reg_nr
];
280 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
282 static char *register_names
[] = {
283 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
284 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
285 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
287 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
288 "y0", "y1", "", "", "", "", "", "mod",
290 "rs", "re", "", "", "", "", "", "",
291 "", "", "", "", "", "", "", "",
292 "", "", "", "", "", "", "", "",
296 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
298 return register_names
[reg_nr
];
302 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
304 static char *register_names
[] = {
305 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
306 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
307 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
309 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
310 "y0", "y1", "", "", "", "", "", "mod",
312 "rs", "re", "", "", "", "", "", "",
313 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
314 "", "", "", "", "", "", "", "",
315 "", "", "", "", "", "", "", "",
319 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
321 return register_names
[reg_nr
];
325 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
327 static char *register_names
[] = {
328 /* general registers 0-15 */
329 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
330 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
332 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
335 /* floating point registers 25 - 40 */
336 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
337 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
341 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
343 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
345 "", "", "", "", "", "", "", "",
346 /* pseudo bank register. */
348 /* double precision (pseudo) 68 - 75 */
349 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
350 /* vectors (pseudo) 76 - 79 */
351 "fv0", "fv4", "fv8", "fv12",
352 /* FIXME: missing XF */
353 /* FIXME: missing XD */
357 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
359 return register_names
[reg_nr
];
363 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
365 static char *register_names
[] = {
366 /* general registers 0-15 */
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
370 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
373 /* floating point registers 25 - 40 -- not for nofpu target */
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
379 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
381 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
383 "", "", "", "", "", "", "", "",
384 /* pseudo bank register. */
386 /* double precision (pseudo) 68 - 75 -- not for nofpu target */
387 "", "", "", "", "", "", "", "",
388 /* vectors (pseudo) 76 - 79 -- not for nofpu target */
393 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
395 return register_names
[reg_nr
];
399 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
401 static char *register_names
[] = {
402 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
403 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
404 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
406 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
407 "y0", "y1", "", "", "", "", "", "mod",
409 "rs", "re", "", "", "", "", "", "",
410 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "", "", "", "", "",
416 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
418 return register_names
[reg_nr
];
422 sh_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
427 static const gdb_byte
*
428 sh_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
432 /* For remote stub targets, trapa #20 is used. */
433 if (strcmp (target_shortname
, "remote") == 0)
435 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
436 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
438 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
439 return big_remote_breakpoint
;
441 return little_remote_breakpoint
;
445 /* 0xc3c3 is trapa #c3, and it works in big and little endian
447 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
453 GDBARCH_BREAKPOINT_FROM_PC (sh
)
455 /* Prologue looks like
459 sub <room_for_loca_vars>,r15
462 Actually it can be more complicated than this but that's it, basically. */
464 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
465 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
467 /* JSR @Rm 0100mmmm00001011 */
468 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
470 /* STS.L PR,@-r15 0100111100100010
471 r15-4-->r15, PR-->(r15) */
472 #define IS_STS(x) ((x) == 0x4f22)
474 /* STS.L MACL,@-r15 0100111100010010
475 r15-4-->r15, MACL-->(r15) */
476 #define IS_MACL_STS(x) ((x) == 0x4f12)
478 /* MOV.L Rm,@-r15 00101111mmmm0110
479 r15-4-->r15, Rm-->(R15) */
480 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
482 /* MOV r15,r14 0110111011110011
484 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
486 /* ADD #imm,r15 01111111iiiiiiii
488 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
490 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
491 #define IS_SHLL_R3(x) ((x) == 0x4300)
493 /* ADD r3,r15 0011111100111100
495 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
497 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
498 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
499 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
500 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
501 make this entirely clear. */
502 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
503 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
505 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
506 #define IS_MOV_ARG_TO_REG(x) \
507 (((x) & 0xf00f) == 0x6003 && \
508 ((x) & 0x00f0) >= 0x0040 && \
509 ((x) & 0x00f0) <= 0x0070)
510 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
511 #define IS_MOV_ARG_TO_IND_R14(x) \
512 (((x) & 0xff0f) == 0x2e02 && \
513 ((x) & 0x00f0) >= 0x0040 && \
514 ((x) & 0x00f0) <= 0x0070)
515 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
516 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
517 (((x) & 0xff00) == 0x1e00 && \
518 ((x) & 0x00f0) >= 0x0040 && \
519 ((x) & 0x00f0) <= 0x0070)
521 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
522 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
523 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
524 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
525 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
526 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
527 /* SUB Rn,R15 00111111nnnn1000 */
528 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
530 #define FPSCR_SZ (1 << 20)
532 /* The following instructions are used for epilogue testing. */
533 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
534 #define IS_RTS(x) ((x) == 0x000b)
535 #define IS_LDS(x) ((x) == 0x4f26)
536 #define IS_MACL_LDS(x) ((x) == 0x4f16)
537 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
538 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
539 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
542 sh_analyze_prologue (struct gdbarch
*gdbarch
,
543 CORE_ADDR pc
, CORE_ADDR limit_pc
,
544 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
546 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
551 int reg
, sav_reg
= -1;
554 for (; pc
< limit_pc
; pc
+= 2)
556 inst
= read_memory_unsigned_integer (pc
, 2, byte_order
);
557 /* See where the registers will be saved to. */
560 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
561 cache
->sp_offset
+= 4;
563 else if (IS_STS (inst
))
565 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
566 cache
->sp_offset
+= 4;
568 else if (IS_MACL_STS (inst
))
570 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
571 cache
->sp_offset
+= 4;
573 else if (IS_MOV_R3 (inst
))
575 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
577 else if (IS_SHLL_R3 (inst
))
581 else if (IS_ADD_R3SP (inst
))
583 cache
->sp_offset
+= -r3_val
;
585 else if (IS_ADD_IMM_SP (inst
))
587 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
588 cache
->sp_offset
-= offset
;
590 else if (IS_MOVW_PCREL_TO_REG (inst
))
594 reg
= GET_TARGET_REG (inst
);
598 offset
= (inst
& 0xff) << 1;
600 read_memory_integer ((pc
+ 4) + offset
, 2, byte_order
);
604 else if (IS_MOVL_PCREL_TO_REG (inst
))
608 reg
= GET_TARGET_REG (inst
);
612 offset
= (inst
& 0xff) << 2;
614 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
,
619 else if (IS_MOVI20 (inst
)
620 && (pc
+ 2 < limit_pc
))
624 reg
= GET_TARGET_REG (inst
);
628 sav_offset
= GET_SOURCE_REG (inst
) << 16;
629 /* MOVI20 is a 32 bit instruction! */
632 |= read_memory_unsigned_integer (pc
, 2, byte_order
);
633 /* Now sav_offset contains an unsigned 20 bit value.
634 It must still get sign extended. */
635 if (sav_offset
& 0x00080000)
636 sav_offset
|= 0xfff00000;
640 else if (IS_SUB_REG_FROM_SP (inst
))
642 reg
= GET_SOURCE_REG (inst
);
643 if (sav_reg
> 0 && reg
== sav_reg
)
647 cache
->sp_offset
+= sav_offset
;
649 else if (IS_FPUSH (inst
))
651 if (fpscr
& FPSCR_SZ
)
653 cache
->sp_offset
+= 8;
657 cache
->sp_offset
+= 4;
660 else if (IS_MOV_SP_FP (inst
))
663 /* Don't go any further than six more instructions. */
664 limit_pc
= std::min (limit_pc
, pc
+ (2 * 6));
667 /* At this point, only allow argument register moves to other
668 registers or argument register moves to @(X,fp) which are
669 moving the register arguments onto the stack area allocated
670 by a former add somenumber to SP call. Don't allow moving
671 to an fp indirect address above fp + cache->sp_offset. */
672 for (; pc
< limit_pc
; pc
+= 2)
674 inst
= read_memory_integer (pc
, 2, byte_order
);
675 if (IS_MOV_ARG_TO_IND_R14 (inst
))
677 reg
= GET_SOURCE_REG (inst
);
678 if (cache
->sp_offset
> 0)
679 cache
->saved_regs
[reg
] = cache
->sp_offset
;
681 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
683 reg
= GET_SOURCE_REG (inst
);
684 offset
= (inst
& 0xf) * 4;
685 if (cache
->sp_offset
> offset
)
686 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
688 else if (IS_MOV_ARG_TO_REG (inst
))
695 else if (IS_JSR (inst
))
697 /* We have found a jsr that has been scheduled into the prologue.
698 If we continue the scan and return a pc someplace after this,
699 then setting a breakpoint on this function will cause it to
700 appear to be called after the function it is calling via the
701 jsr, which will be very confusing. Most likely the next
702 instruction is going to be IS_MOV_SP_FP in the delay slot. If
703 so, note that before returning the current pc. */
704 if (pc
+ 2 < limit_pc
)
706 inst
= read_memory_integer (pc
+ 2, 2, byte_order
);
707 if (IS_MOV_SP_FP (inst
))
712 #if 0 /* This used to just stop when it found an instruction
713 that was not considered part of the prologue. Now,
714 we just keep going looking for likely
724 /* Skip any prologue before the guts of a function. */
726 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
728 CORE_ADDR post_prologue_pc
, func_addr
, func_end_addr
, limit_pc
;
729 struct sh_frame_cache cache
;
731 /* See if we can determine the end of the prologue via the symbol table.
732 If so, then return either PC, or the PC after the prologue, whichever
734 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
736 post_prologue_pc
= skip_prologue_using_sal (gdbarch
, func_addr
);
737 if (post_prologue_pc
!= 0)
738 return std::max (pc
, post_prologue_pc
);
741 /* Can't determine prologue from the symbol table, need to examine
744 /* Find an upper limit on the function prologue using the debug
745 information. If the debug information could not be used to provide
746 that bound, then use an arbitrary large number as the upper bound. */
747 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
749 /* Don't go any further than 28 instructions. */
750 limit_pc
= pc
+ (2 * 28);
752 /* Do not allow limit_pc to be past the function end, if we know
753 where that end is... */
754 if (func_end_addr
!= 0)
755 limit_pc
= std::min (limit_pc
, func_end_addr
);
757 cache
.sp_offset
= -4;
758 post_prologue_pc
= sh_analyze_prologue (gdbarch
, pc
, limit_pc
, &cache
, 0);
760 pc
= post_prologue_pc
;
767 Aggregate types not bigger than 8 bytes that have the same size and
768 alignment as one of the integer scalar types are returned in the
769 same registers as the integer type they match.
771 For example, a 2-byte aligned structure with size 2 bytes has the
772 same size and alignment as a short int, and will be returned in R0.
773 A 4-byte aligned structure with size 8 bytes has the same size and
774 alignment as a long long int, and will be returned in R0 and R1.
776 When an aggregate type is returned in R0 and R1, R0 contains the
777 first four bytes of the aggregate, and R1 contains the
778 remainder. If the size of the aggregate type is not a multiple of 4
779 bytes, the aggregate is tail-padded up to a multiple of 4
780 bytes. The value of the padding is undefined. For little-endian
781 targets the padding will appear at the most significant end of the
782 last element, for big-endian targets the padding appears at the
783 least significant end of the last element.
785 All other aggregate types are returned by address. The caller
786 function passes the address of an area large enough to hold the
787 aggregate value in R2. The called function stores the result in
790 To reiterate, structs smaller than 8 bytes could also be returned
791 in memory, if they don't pass the "same size and alignment as an
796 struct s { char c[3]; } wibble;
797 struct s foo(void) { return wibble; }
799 the return value from foo() will be in memory, not
800 in R0, because there is no 3-byte integer type.
804 struct s { char c[2]; } wibble;
805 struct s foo(void) { return wibble; }
807 because a struct containing two chars has alignment 1, that matches
808 type char, but size 2, that matches type short. There's no integer
809 type that has alignment 1 and size 2, so the struct is returned in
813 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
815 int len
= TYPE_LENGTH (type
);
816 int nelem
= TYPE_NFIELDS (type
);
818 /* The Renesas ABI returns aggregate types always on stack. */
819 if (renesas_abi
&& (TYPE_CODE (type
) == TYPE_CODE_STRUCT
820 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
823 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
824 fit in two registers anyway) use struct convention. */
825 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
828 /* Scalar types and aggregate types with exactly one field are aligned
829 by definition. They are returned in registers. */
833 /* If the first field in the aggregate has the same length as the entire
834 aggregate type, the type is returned in registers. */
835 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
838 /* If the size of the aggregate is 8 bytes and the first field is
839 of size 4 bytes its alignment is equal to long long's alignment,
840 so it's returned in registers. */
841 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
844 /* Otherwise use struct convention. */
849 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
851 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
852 if (renesas_abi
&& TYPE_NFIELDS (type
) == 0 && TYPE_LENGTH (type
) >= 8)
854 return sh_use_struct_convention (renesas_abi
, type
);
858 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
863 /* Function: push_dummy_call (formerly push_arguments)
864 Setup the function arguments for calling a function in the inferior.
866 On the Renesas SH architecture, there are four registers (R4 to R7)
867 which are dedicated for passing function arguments. Up to the first
868 four arguments (depending on size) may go into these registers.
869 The rest go on the stack.
871 MVS: Except on SH variants that have floating point registers.
872 In that case, float and double arguments are passed in the same
873 manner, but using FP registers instead of GP registers.
875 Arguments that are smaller than 4 bytes will still take up a whole
876 register or a whole 32-bit word on the stack, and will be
877 right-justified in the register or the stack word. This includes
878 chars, shorts, and small aggregate types.
880 Arguments that are larger than 4 bytes may be split between two or
881 more registers. If there are not enough registers free, an argument
882 may be passed partly in a register (or registers), and partly on the
883 stack. This includes doubles, long longs, and larger aggregates.
884 As far as I know, there is no upper limit to the size of aggregates
885 that will be passed in this way; in other words, the convention of
886 passing a pointer to a large aggregate instead of a copy is not used.
888 MVS: The above appears to be true for the SH variants that do not
889 have an FPU, however those that have an FPU appear to copy the
890 aggregate argument onto the stack (and not place it in registers)
891 if it is larger than 16 bytes (four GP registers).
893 An exceptional case exists for struct arguments (and possibly other
894 aggregates such as arrays) if the size is larger than 4 bytes but
895 not a multiple of 4 bytes. In this case the argument is never split
896 between the registers and the stack, but instead is copied in its
897 entirety onto the stack, AND also copied into as many registers as
898 there is room for. In other words, space in registers permitting,
899 two copies of the same argument are passed in. As far as I can tell,
900 only the one on the stack is used, although that may be a function
901 of the level of compiler optimization. I suspect this is a compiler
902 bug. Arguments of these odd sizes are left-justified within the
903 word (as opposed to arguments smaller than 4 bytes, which are
906 If the function is to return an aggregate type such as a struct, it
907 is either returned in the normal return value register R0 (if its
908 size is no greater than one byte), or else the caller must allocate
909 space into which the callee will copy the return value (if the size
910 is greater than one byte). In this case, a pointer to the return
911 value location is passed into the callee in register R2, which does
912 not displace any of the other arguments passed in via registers R4
915 /* Helper function to justify value in register according to endianess. */
916 static const gdb_byte
*
917 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
919 static gdb_byte valbuf
[4];
921 memset (valbuf
, 0, sizeof (valbuf
));
924 /* value gets right-justified in the register or stack word. */
925 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
926 memcpy (valbuf
+ (4 - len
), value_contents (val
), len
);
928 memcpy (valbuf
, value_contents (val
), len
);
931 return value_contents (val
);
934 /* Helper function to eval number of bytes to allocate on stack. */
936 sh_stack_allocsize (int nargs
, struct value
**args
)
940 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
944 /* Helper functions for getting the float arguments right. Registers usage
945 depends on the ABI and the endianess. The comments should enlighten how
946 it's intended to work. */
948 /* This array stores which of the float arg registers are already in use. */
949 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
951 /* This function just resets the above array to "no reg used so far". */
953 sh_init_flt_argreg (void)
955 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
958 /* This function returns the next register to use for float arg passing.
959 It returns either a valid value between FLOAT_ARG0_REGNUM and
960 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
961 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
963 Note that register number 0 in flt_argreg_array corresponds with the
964 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
965 29) the parity of the register number is preserved, which is important
966 for the double register passing test (see the "argreg & 1" test below). */
968 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
972 /* First search for the next free register. */
973 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
975 if (!flt_argreg_array
[argreg
])
978 /* No register left? */
979 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
980 return FLOAT_ARGLAST_REGNUM
+ 1;
984 /* Doubles are always starting in a even register number. */
987 /* In gcc ABI, the skipped register is lost for further argument
988 passing now. Not so in Renesas ABI. */
989 if (!sh_is_renesas_calling_convention (func_type
))
990 flt_argreg_array
[argreg
] = 1;
994 /* No register left? */
995 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
996 return FLOAT_ARGLAST_REGNUM
+ 1;
998 /* Also mark the next register as used. */
999 flt_argreg_array
[argreg
+ 1] = 1;
1001 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1002 && !sh_is_renesas_calling_convention (func_type
))
1004 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
1005 if (!flt_argreg_array
[argreg
+ 1])
1008 flt_argreg_array
[argreg
] = 1;
1009 return FLOAT_ARG0_REGNUM
+ argreg
;
1012 /* Helper function which figures out, if a type is treated like a float type.
1014 The FPU ABIs have a special way how to treat types as float types.
1015 Structures with exactly one member, which is of type float or double, are
1016 treated exactly as the base types float or double:
1026 are handled the same way as just
1032 As a result, arguments of these struct types are pushed into floating point
1033 registers exactly as floats or doubles, using the same decision algorithm.
1035 The same is valid if these types are used as function return types. The
1036 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1037 or even using struct convention as it is for other structs. */
1040 sh_treat_as_flt_p (struct type
*type
)
1042 /* Ordinary float types are obviously treated as float. */
1043 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1045 /* Otherwise non-struct types are not treated as float. */
1046 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
1048 /* Otherwise structs with more than one memeber are not treated as float. */
1049 if (TYPE_NFIELDS (type
) != 1)
1051 /* Otherwise if the type of that member is float, the whole type is
1052 treated as float. */
1053 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
1055 /* Otherwise it's not treated as float. */
1060 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1061 struct value
*function
,
1062 struct regcache
*regcache
,
1063 CORE_ADDR bp_addr
, int nargs
,
1064 struct value
**args
,
1065 CORE_ADDR sp
, int struct_return
,
1066 CORE_ADDR struct_addr
)
1068 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1069 int stack_offset
= 0;
1070 int argreg
= ARG0_REGNUM
;
1073 struct type
*func_type
= value_type (function
);
1076 const gdb_byte
*val
;
1077 int len
, reg_size
= 0;
1078 int pass_on_stack
= 0;
1080 int last_reg_arg
= INT_MAX
;
1082 /* The Renesas ABI expects all varargs arguments, plus the last
1083 non-vararg argument to be on the stack, no matter how many
1084 registers have been used so far. */
1085 if (sh_is_renesas_calling_convention (func_type
)
1086 && TYPE_VARARGS (func_type
))
1087 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1089 /* First force sp to a 4-byte alignment. */
1090 sp
= sh_frame_align (gdbarch
, sp
);
1092 /* Make room on stack for args. */
1093 sp
-= sh_stack_allocsize (nargs
, args
);
1095 /* Initialize float argument mechanism. */
1096 sh_init_flt_argreg ();
1098 /* Now load as many as possible of the first arguments into
1099 registers, and push the rest onto the stack. There are 16 bytes
1100 in four registers available. Loop thru args from first to last. */
1101 for (argnum
= 0; argnum
< nargs
; argnum
++)
1103 type
= value_type (args
[argnum
]);
1104 len
= TYPE_LENGTH (type
);
1105 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1107 /* Some decisions have to be made how various types are handled.
1108 This also differs in different ABIs. */
1111 /* Find out the next register to use for a floating point value. */
1112 treat_as_flt
= sh_treat_as_flt_p (type
);
1114 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1115 /* In Renesas ABI, long longs and aggregate types are always passed
1117 else if (sh_is_renesas_calling_convention (func_type
)
1118 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
== 8)
1119 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1120 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1122 /* In contrast to non-FPU CPUs, arguments are never split between
1123 registers and stack. If an argument doesn't fit in the remaining
1124 registers it's always pushed entirely on the stack. */
1125 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1130 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1131 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1133 || argnum
> last_reg_arg
)
1135 /* The data goes entirely on the stack, 4-byte aligned. */
1136 reg_size
= (len
+ 3) & ~3;
1137 write_memory (sp
+ stack_offset
, val
, reg_size
);
1138 stack_offset
+= reg_size
;
1140 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1142 /* Argument goes in a float argument register. */
1143 reg_size
= register_size (gdbarch
, flt_argreg
);
1144 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1145 /* In little endian mode, float types taking two registers
1146 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1147 be stored swapped in the argument registers. The below
1148 code first writes the first 32 bits in the next but one
1149 register, increments the val and len values accordingly
1150 and then proceeds as normal by writing the second 32 bits
1151 into the next register. */
1152 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1153 && TYPE_LENGTH (type
) == 2 * reg_size
)
1155 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1159 regval
= extract_unsigned_integer (val
, reg_size
,
1162 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1164 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1166 /* there's room in a register */
1167 reg_size
= register_size (gdbarch
, argreg
);
1168 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1169 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1171 /* Store the value one register at a time or in one step on
1180 if (sh_is_renesas_calling_convention (func_type
))
1181 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1182 the stack and store the struct return address there. */
1183 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1185 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1186 its own dedicated register. */
1187 regcache_cooked_write_unsigned (regcache
,
1188 STRUCT_RETURN_REGNUM
, struct_addr
);
1191 /* Store return address. */
1192 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1194 /* Update stack pointer. */
1195 regcache_cooked_write_unsigned (regcache
,
1196 gdbarch_sp_regnum (gdbarch
), sp
);
1202 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1203 struct value
*function
,
1204 struct regcache
*regcache
,
1206 int nargs
, struct value
**args
,
1207 CORE_ADDR sp
, int struct_return
,
1208 CORE_ADDR struct_addr
)
1210 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1211 int stack_offset
= 0;
1212 int argreg
= ARG0_REGNUM
;
1214 struct type
*func_type
= value_type (function
);
1217 const gdb_byte
*val
;
1218 int len
, reg_size
= 0;
1219 int pass_on_stack
= 0;
1220 int last_reg_arg
= INT_MAX
;
1222 /* The Renesas ABI expects all varargs arguments, plus the last
1223 non-vararg argument to be on the stack, no matter how many
1224 registers have been used so far. */
1225 if (sh_is_renesas_calling_convention (func_type
)
1226 && TYPE_VARARGS (func_type
))
1227 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1229 /* First force sp to a 4-byte alignment. */
1230 sp
= sh_frame_align (gdbarch
, sp
);
1232 /* Make room on stack for args. */
1233 sp
-= sh_stack_allocsize (nargs
, args
);
1235 /* Now load as many as possible of the first arguments into
1236 registers, and push the rest onto the stack. There are 16 bytes
1237 in four registers available. Loop thru args from first to last. */
1238 for (argnum
= 0; argnum
< nargs
; argnum
++)
1240 type
= value_type (args
[argnum
]);
1241 len
= TYPE_LENGTH (type
);
1242 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1244 /* Some decisions have to be made how various types are handled.
1245 This also differs in different ABIs. */
1247 /* Renesas ABI pushes doubles and long longs entirely on stack.
1248 Same goes for aggregate types. */
1249 if (sh_is_renesas_calling_convention (func_type
)
1250 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
>= 8)
1251 || (TYPE_CODE (type
) == TYPE_CODE_FLT
&& len
>= 8)
1252 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1253 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1257 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1258 || argnum
> last_reg_arg
)
1260 /* The remainder of the data goes entirely on the stack,
1262 reg_size
= (len
+ 3) & ~3;
1263 write_memory (sp
+ stack_offset
, val
, reg_size
);
1264 stack_offset
+= reg_size
;
1266 else if (argreg
<= ARGLAST_REGNUM
)
1268 /* There's room in a register. */
1269 reg_size
= register_size (gdbarch
, argreg
);
1270 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1271 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1273 /* Store the value reg_size bytes at a time. This means that things
1274 larger than reg_size bytes may go partly in registers and partly
1283 if (sh_is_renesas_calling_convention (func_type
))
1284 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1285 the stack and store the struct return address there. */
1286 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1288 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1289 its own dedicated register. */
1290 regcache_cooked_write_unsigned (regcache
,
1291 STRUCT_RETURN_REGNUM
, struct_addr
);
1294 /* Store return address. */
1295 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1297 /* Update stack pointer. */
1298 regcache_cooked_write_unsigned (regcache
,
1299 gdbarch_sp_regnum (gdbarch
), sp
);
1304 /* Find a function's return value in the appropriate registers (in
1305 regbuf), and copy it into valbuf. Extract from an array REGBUF
1306 containing the (raw) register state a function return value of type
1307 TYPE, and copy that, in virtual format, into VALBUF. */
1309 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1312 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1313 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1314 int len
= TYPE_LENGTH (type
);
1320 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1321 store_unsigned_integer (valbuf
, len
, byte_order
, c
);
1325 int i
, regnum
= R0_REGNUM
;
1326 for (i
= 0; i
< len
; i
+= 4)
1327 regcache_raw_read (regcache
, regnum
++, valbuf
+ i
);
1330 error (_("bad size for return value"));
1334 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1337 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1338 if (sh_treat_as_flt_p (type
))
1340 int len
= TYPE_LENGTH (type
);
1341 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1342 for (i
= 0; i
< len
; i
+= 4)
1343 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1344 regcache_raw_read (regcache
, regnum
++,
1345 valbuf
+ len
- 4 - i
);
1347 regcache_raw_read (regcache
, regnum
++, valbuf
+ i
);
1350 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1353 /* Write into appropriate registers a function return value
1354 of type TYPE, given in virtual format.
1355 If the architecture is sh4 or sh3e, store a function's return value
1356 in the R0 general register or in the FP0 floating point register,
1357 depending on the type of the return value. In all the other cases
1358 the result is stored in r0, left-justified. */
1360 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1361 const gdb_byte
*valbuf
)
1363 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1364 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1366 int len
= TYPE_LENGTH (type
);
1370 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1371 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1375 int i
, regnum
= R0_REGNUM
;
1376 for (i
= 0; i
< len
; i
+= 4)
1377 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1382 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1383 const gdb_byte
*valbuf
)
1385 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1386 if (sh_treat_as_flt_p (type
))
1388 int len
= TYPE_LENGTH (type
);
1389 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1390 for (i
= 0; i
< len
; i
+= 4)
1391 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1392 regcache_raw_write (regcache
, regnum
++,
1393 valbuf
+ len
- 4 - i
);
1395 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1398 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1401 static enum return_value_convention
1402 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct value
*function
,
1403 struct type
*type
, struct regcache
*regcache
,
1404 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1406 struct type
*func_type
= function
? value_type (function
) : NULL
;
1408 if (sh_use_struct_convention_nofpu (
1409 sh_is_renesas_calling_convention (func_type
), type
))
1410 return RETURN_VALUE_STRUCT_CONVENTION
;
1412 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1414 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1415 return RETURN_VALUE_REGISTER_CONVENTION
;
1418 static enum return_value_convention
1419 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct value
*function
,
1420 struct type
*type
, struct regcache
*regcache
,
1421 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1423 struct type
*func_type
= function
? value_type (function
) : NULL
;
1425 if (sh_use_struct_convention (
1426 sh_is_renesas_calling_convention (func_type
), type
))
1427 return RETURN_VALUE_STRUCT_CONVENTION
;
1429 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1431 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1432 return RETURN_VALUE_REGISTER_CONVENTION
;
1435 static struct type
*
1436 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1438 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1439 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1440 return builtin_type (gdbarch
)->builtin_float
;
1441 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1442 return builtin_type (gdbarch
)->builtin_double
;
1444 return builtin_type (gdbarch
)->builtin_int
;
1447 /* Return the GDB type object for the "standard" data type
1448 of data in register N. */
1449 static struct type
*
1450 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1452 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1453 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1454 return builtin_type (gdbarch
)->builtin_float
;
1456 return builtin_type (gdbarch
)->builtin_int
;
1459 static struct type
*
1460 sh_sh4_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1462 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1466 static struct type
*
1467 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1469 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1470 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1471 return builtin_type (gdbarch
)->builtin_float
;
1472 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1473 return builtin_type (gdbarch
)->builtin_double
;
1474 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1475 return sh_sh4_build_float_register_type (gdbarch
, 3);
1477 return builtin_type (gdbarch
)->builtin_int
;
1480 static struct type
*
1481 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1483 return builtin_type (gdbarch
)->builtin_int
;
1486 /* Is a register in a reggroup?
1487 The default code in reggroup.c doesn't identify system registers, some
1488 float registers or any of the vector registers.
1489 TODO: sh2a and dsp registers. */
1491 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1492 struct reggroup
*reggroup
)
1494 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1495 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
1498 if (reggroup
== float_reggroup
1499 && (regnum
== FPUL_REGNUM
1500 || regnum
== FPSCR_REGNUM
))
1503 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
1505 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
1507 if (reggroup
== general_reggroup
)
1511 if (regnum
== VBR_REGNUM
1512 || regnum
== SR_REGNUM
1513 || regnum
== FPSCR_REGNUM
1514 || regnum
== SSR_REGNUM
1515 || regnum
== SPC_REGNUM
)
1517 if (reggroup
== system_reggroup
)
1519 if (reggroup
== general_reggroup
)
1523 /* The default code can cope with any other registers. */
1524 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1527 /* On the sh4, the DRi pseudo registers are problematic if the target
1528 is little endian. When the user writes one of those registers, for
1529 instance with 'set var $dr0=1', we want the double to be stored
1531 fr0 = 0x00 0x00 0xf0 0x3f
1532 fr1 = 0x00 0x00 0x00 0x00
1534 This corresponds to little endian byte order & big endian word
1535 order. However if we let gdb write the register w/o conversion, it
1536 will write fr0 and fr1 this way:
1537 fr0 = 0x00 0x00 0x00 0x00
1538 fr1 = 0x00 0x00 0xf0 0x3f
1539 because it will consider fr0 and fr1 as a single LE stretch of memory.
1541 To achieve what we want we must force gdb to store things in
1542 floatformat_ieee_double_littlebyte_bigword (which is defined in
1543 include/floatformat.h and libiberty/floatformat.c.
1545 In case the target is big endian, there is no problem, the
1546 raw bytes will look like:
1547 fr0 = 0x3f 0xf0 0x00 0x00
1548 fr1 = 0x00 0x00 0x00 0x00
1550 The other pseudo registers (the FVs) also don't pose a problem
1551 because they are stored as 4 individual FP elements. */
1554 sh_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1555 struct type
*type
, gdb_byte
*from
, gdb_byte
*to
)
1557 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1559 /* It is a no-op. */
1560 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1564 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1567 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1569 store_typed_floating (to
, type
, val
);
1573 ("sh_register_convert_to_virtual called with non DR register number");
1577 sh_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1578 int regnum
, const gdb_byte
*from
, gdb_byte
*to
)
1580 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1582 /* It is a no-op. */
1583 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1587 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1589 DOUBLEST val
= extract_typed_floating (from
, type
);
1590 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1594 error (_("sh_register_convert_to_raw called with non DR register number"));
1597 /* For vectors of 4 floating point registers. */
1599 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
1603 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1604 + (fv_regnum
- FV0_REGNUM
) * 4;
1608 /* For double precision floating point registers, i.e 2 fp regs. */
1610 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
1614 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1615 + (dr_regnum
- DR0_REGNUM
) * 2;
1619 /* Concatenate PORTIONS contiguous raw registers starting at
1620 BASE_REGNUM into BUFFER. */
1622 static enum register_status
1623 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1624 struct regcache
*regcache
,
1626 int base_regnum
, gdb_byte
*buffer
)
1630 for (portion
= 0; portion
< portions
; portion
++)
1632 enum register_status status
;
1635 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1636 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1637 if (status
!= REG_VALID
)
1644 static enum register_status
1645 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1646 int reg_nr
, gdb_byte
*buffer
)
1649 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1650 enum register_status status
;
1652 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1653 return regcache_raw_read (regcache
, BANK_REGNUM
, buffer
);
1654 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1656 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1658 /* Build the value in the provided buffer. */
1659 /* Read the real regs for which this one is an alias. */
1660 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1661 2, base_regnum
, temp_buffer
);
1662 if (status
== REG_VALID
)
1664 /* We must pay attention to the endiannes. */
1665 sh_register_convert_to_virtual (gdbarch
, reg_nr
,
1666 register_type (gdbarch
, reg_nr
),
1667 temp_buffer
, buffer
);
1671 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1673 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1675 /* Read the real regs for which this one is an alias. */
1676 return pseudo_register_read_portions (gdbarch
, regcache
,
1677 4, base_regnum
, buffer
);
1680 gdb_assert_not_reached ("invalid pseudo register number");
1684 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1685 int reg_nr
, const gdb_byte
*buffer
)
1687 int base_regnum
, portion
;
1688 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1690 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1692 /* When the bank register is written to, the whole register bank
1693 is switched and all values in the bank registers must be read
1694 from the target/sim again. We're just invalidating the regcache
1695 so that a re-read happens next time it's necessary. */
1698 regcache_raw_write (regcache
, BANK_REGNUM
, buffer
);
1699 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
1700 regcache_invalidate (regcache
, bregnum
);
1702 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1704 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1706 /* We must pay attention to the endiannes. */
1707 sh_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1708 reg_nr
, buffer
, temp_buffer
);
1710 /* Write the real regs for which this one is an alias. */
1711 for (portion
= 0; portion
< 2; portion
++)
1712 regcache_raw_write (regcache
, base_regnum
+ portion
,
1714 + register_size (gdbarch
,
1715 base_regnum
) * portion
));
1717 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1719 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1721 /* Write the real regs for which this one is an alias. */
1722 for (portion
= 0; portion
< 4; portion
++)
1723 regcache_raw_write (regcache
, base_regnum
+ portion
,
1725 + register_size (gdbarch
,
1726 base_regnum
) * portion
));
1731 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1733 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
1734 return legacy_register_sim_regno (gdbarch
, nr
);
1735 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
1736 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
1737 if (nr
== MOD_REGNUM
)
1738 return SIM_SH_MOD_REGNUM
;
1739 if (nr
== RS_REGNUM
)
1740 return SIM_SH_RS_REGNUM
;
1741 if (nr
== RE_REGNUM
)
1742 return SIM_SH_RE_REGNUM
;
1743 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
1744 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
1749 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1754 return SIM_SH_TBR_REGNUM
;
1756 return SIM_SH_IBNR_REGNUM
;
1758 return SIM_SH_IBCR_REGNUM
;
1760 return SIM_SH_BANK_REGNUM
;
1762 return SIM_SH_BANK_MACL_REGNUM
;
1764 return SIM_SH_BANK_GBR_REGNUM
;
1766 return SIM_SH_BANK_PR_REGNUM
;
1768 return SIM_SH_BANK_IVN_REGNUM
;
1770 return SIM_SH_BANK_MACH_REGNUM
;
1774 return legacy_register_sim_regno (gdbarch
, nr
);
1777 /* Set up the register unwinding such that call-clobbered registers are
1778 not displayed in frames >0 because the true value is not certain.
1779 The 'undefined' registers will show up as 'not available' unless the
1782 This function is currently set up for SH4 and compatible only. */
1785 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1786 struct dwarf2_frame_state_reg
*reg
,
1787 struct frame_info
*this_frame
)
1789 /* Mark the PC as the destination for the return address. */
1790 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1791 reg
->how
= DWARF2_FRAME_REG_RA
;
1793 /* Mark the stack pointer as the call frame address. */
1794 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1795 reg
->how
= DWARF2_FRAME_REG_CFA
;
1797 /* The above was taken from the default init_reg in dwarf2-frame.c
1798 while the below is SH specific. */
1800 /* Caller save registers. */
1801 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
1802 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
1803 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
1804 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
1805 || (regnum
== MACH_REGNUM
)
1806 || (regnum
== MACL_REGNUM
)
1807 || (regnum
== FPUL_REGNUM
)
1808 || (regnum
== SR_REGNUM
))
1809 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1811 /* Callee save registers. */
1812 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
1813 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
1814 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
1815 || (regnum
== FV0_REGNUM
+3))
1816 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1818 /* Other registers. These are not in the ABI and may or may not
1819 mean anything in frames >0 so don't show them. */
1820 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
1821 || (regnum
== GBR_REGNUM
)
1822 || (regnum
== VBR_REGNUM
)
1823 || (regnum
== FPSCR_REGNUM
)
1824 || (regnum
== SSR_REGNUM
)
1825 || (regnum
== SPC_REGNUM
))
1826 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1829 static struct sh_frame_cache
*
1830 sh_alloc_frame_cache (void)
1832 struct sh_frame_cache
*cache
;
1835 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
1839 cache
->saved_sp
= 0;
1840 cache
->sp_offset
= 0;
1843 /* Frameless until proven otherwise. */
1846 /* Saved registers. We initialize these to -1 since zero is a valid
1847 offset (that's where fp is supposed to be stored). */
1848 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1850 cache
->saved_regs
[i
] = -1;
1856 static struct sh_frame_cache
*
1857 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1859 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1860 struct sh_frame_cache
*cache
;
1861 CORE_ADDR current_pc
;
1865 return (struct sh_frame_cache
*) *this_cache
;
1867 cache
= sh_alloc_frame_cache ();
1868 *this_cache
= cache
;
1870 /* In principle, for normal frames, fp holds the frame pointer,
1871 which holds the base address for the current stack frame.
1872 However, for functions that don't need it, the frame pointer is
1873 optional. For these "frameless" functions the frame pointer is
1874 actually the frame pointer of the calling frame. */
1875 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
1876 if (cache
->base
== 0)
1879 cache
->pc
= get_frame_func (this_frame
);
1880 current_pc
= get_frame_pc (this_frame
);
1885 /* Check for the existence of the FPSCR register. If it exists,
1886 fetch its value for use in prologue analysis. Passing a zero
1887 value is the best choice for architecture variants upon which
1888 there's no FPSCR register. */
1889 if (gdbarch_register_reggroup_p (gdbarch
, FPSCR_REGNUM
, all_reggroup
))
1890 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
1894 sh_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, fpscr
);
1897 if (!cache
->uses_fp
)
1899 /* We didn't find a valid frame, which means that CACHE->base
1900 currently holds the frame pointer for our calling frame. If
1901 we're at the start of a function, or somewhere half-way its
1902 prologue, the function's frame probably hasn't been fully
1903 setup yet. Try to reconstruct the base address for the stack
1904 frame by looking at the stack pointer. For truly "frameless"
1905 functions this might work too. */
1906 cache
->base
= get_frame_register_unsigned
1907 (this_frame
, gdbarch_sp_regnum (gdbarch
));
1910 /* Now that we have the base address for the stack frame we can
1911 calculate the value of sp in the calling frame. */
1912 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
1914 /* Adjust all the saved registers such that they contain addresses
1915 instead of offsets. */
1916 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1917 if (cache
->saved_regs
[i
] != -1)
1918 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
1923 static struct value
*
1924 sh_frame_prev_register (struct frame_info
*this_frame
,
1925 void **this_cache
, int regnum
)
1927 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1928 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1930 gdb_assert (regnum
>= 0);
1932 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
1933 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1935 /* The PC of the previous frame is stored in the PR register of
1936 the current frame. Frob regnum so that we pull the value from
1937 the correct place. */
1938 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1941 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
1942 return frame_unwind_got_memory (this_frame
, regnum
,
1943 cache
->saved_regs
[regnum
]);
1945 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1949 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1950 struct frame_id
*this_id
)
1952 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1954 /* This marks the outermost frame. */
1955 if (cache
->base
== 0)
1958 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
1961 static const struct frame_unwind sh_frame_unwind
= {
1963 default_frame_unwind_stop_reason
,
1965 sh_frame_prev_register
,
1967 default_frame_sniffer
1971 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1973 return frame_unwind_register_unsigned (next_frame
,
1974 gdbarch_sp_regnum (gdbarch
));
1978 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1980 return frame_unwind_register_unsigned (next_frame
,
1981 gdbarch_pc_regnum (gdbarch
));
1984 static struct frame_id
1985 sh_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1987 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
1988 gdbarch_sp_regnum (gdbarch
));
1989 return frame_id_build (sp
, get_frame_pc (this_frame
));
1993 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1995 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2000 static const struct frame_base sh_frame_base
= {
2002 sh_frame_base_address
,
2003 sh_frame_base_address
,
2004 sh_frame_base_address
2007 static struct sh_frame_cache
*
2008 sh_make_stub_cache (struct frame_info
*this_frame
)
2010 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2011 struct sh_frame_cache
*cache
;
2013 cache
= sh_alloc_frame_cache ();
2016 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2022 sh_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
2023 struct frame_id
*this_id
)
2025 struct sh_frame_cache
*cache
;
2027 if (*this_cache
== NULL
)
2028 *this_cache
= sh_make_stub_cache (this_frame
);
2029 cache
= (struct sh_frame_cache
*) *this_cache
;
2031 *this_id
= frame_id_build (cache
->saved_sp
, get_frame_pc (this_frame
));
2035 sh_stub_unwind_sniffer (const struct frame_unwind
*self
,
2036 struct frame_info
*this_frame
,
2037 void **this_prologue_cache
)
2039 CORE_ADDR addr_in_block
;
2041 addr_in_block
= get_frame_address_in_block (this_frame
);
2042 if (in_plt_section (addr_in_block
))
2048 static const struct frame_unwind sh_stub_unwind
=
2051 default_frame_unwind_stop_reason
,
2053 sh_frame_prev_register
,
2055 sh_stub_unwind_sniffer
2058 /* Implement the stack_frame_destroyed_p gdbarch method.
2060 The epilogue is defined here as the area at the end of a function,
2061 either on the `ret' instruction itself or after an instruction which
2062 destroys the function's stack frame. */
2065 sh_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2067 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2068 CORE_ADDR func_addr
= 0, func_end
= 0;
2070 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2073 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2074 for a nop and some fixed data (e.g. big offsets) which are
2075 unfortunately also treated as part of the function (which
2076 means, they are below func_end. */
2077 CORE_ADDR addr
= func_end
- 28;
2078 if (addr
< func_addr
+ 4)
2079 addr
= func_addr
+ 4;
2083 /* First search forward until hitting an rts. */
2084 while (addr
< func_end
2085 && !IS_RTS (read_memory_unsigned_integer (addr
, 2, byte_order
)))
2087 if (addr
>= func_end
)
2090 /* At this point we should find a mov.l @r15+,r14 instruction,
2091 either before or after the rts. If not, then the function has
2092 probably no "normal" epilogue and we bail out here. */
2093 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2094 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2,
2097 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2,
2101 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2103 /* Step over possible lds.l @r15+,macl. */
2104 if (IS_MACL_LDS (inst
))
2107 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2110 /* Step over possible lds.l @r15+,pr. */
2114 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2117 /* Step over possible mov r14,r15. */
2118 if (IS_MOV_FP_SP (inst
))
2121 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2124 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2126 while (addr
> func_addr
+ 4
2127 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2130 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2133 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2134 That's allowed for the epilogue. */
2135 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2136 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2137 && addr
> func_addr
+ 6
2138 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2,
2149 /* Supply register REGNUM from the buffer specified by REGS and LEN
2150 in the register set REGSET to register cache REGCACHE.
2151 REGTABLE specifies where each register can be found in REGS.
2152 If REGNUM is -1, do this for all registers in REGSET. */
2155 sh_corefile_supply_regset (const struct regset
*regset
,
2156 struct regcache
*regcache
,
2157 int regnum
, const void *regs
, size_t len
)
2159 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2160 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2161 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2162 ? tdep
->core_gregmap
2163 : tdep
->core_fpregmap
);
2166 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2168 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2169 && regmap
[i
].offset
+ 4 <= len
)
2170 regcache_raw_supply (regcache
, regmap
[i
].regnum
,
2171 (char *)regs
+ regmap
[i
].offset
);
2175 /* Collect register REGNUM in the register set REGSET from register cache
2176 REGCACHE into the buffer specified by REGS and LEN.
2177 REGTABLE specifies where each register can be found in REGS.
2178 If REGNUM is -1, do this for all registers in REGSET. */
2181 sh_corefile_collect_regset (const struct regset
*regset
,
2182 const struct regcache
*regcache
,
2183 int regnum
, void *regs
, size_t len
)
2185 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2187 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2188 ? tdep
->core_gregmap
2189 : tdep
->core_fpregmap
);
2192 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2194 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2195 && regmap
[i
].offset
+ 4 <= len
)
2196 regcache_raw_collect (regcache
, regmap
[i
].regnum
,
2197 (char *)regs
+ regmap
[i
].offset
);
2201 /* The following two regsets have the same contents, so it is tempting to
2202 unify them, but they are distiguished by their address, so don't. */
2204 const struct regset sh_corefile_gregset
=
2207 sh_corefile_supply_regset
,
2208 sh_corefile_collect_regset
2211 static const struct regset sh_corefile_fpregset
=
2214 sh_corefile_supply_regset
,
2215 sh_corefile_collect_regset
2219 sh_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
2220 iterate_over_regset_sections_cb
*cb
,
2222 const struct regcache
*regcache
)
2224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2226 if (tdep
->core_gregmap
!= NULL
)
2227 cb (".reg", tdep
->sizeof_gregset
, &sh_corefile_gregset
, NULL
, cb_data
);
2229 if (tdep
->core_fpregmap
!= NULL
)
2230 cb (".reg2", tdep
->sizeof_fpregset
, &sh_corefile_fpregset
, NULL
, cb_data
);
2233 /* This is the implementation of gdbarch method
2234 return_in_first_hidden_param_p. */
2237 sh_return_in_first_hidden_param_p (struct gdbarch
*gdbarch
,
2245 static struct gdbarch
*
2246 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2248 struct gdbarch
*gdbarch
;
2249 struct gdbarch_tdep
*tdep
;
2251 /* SH5 is handled entirely in sh64-tdep.c. */
2252 if (info
.bfd_arch_info
->mach
== bfd_mach_sh5
)
2253 return sh64_gdbarch_init (info
, arches
);
2255 /* If there is already a candidate, use it. */
2256 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2258 return arches
->gdbarch
;
2260 /* None found, create a new architecture from the information
2262 tdep
= XCNEW (struct gdbarch_tdep
);
2263 gdbarch
= gdbarch_alloc (&info
, tdep
);
2265 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2266 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2267 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2268 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2269 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2270 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2271 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2272 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2274 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2275 set_gdbarch_sp_regnum (gdbarch
, 15);
2276 set_gdbarch_pc_regnum (gdbarch
, 16);
2277 set_gdbarch_fp0_regnum (gdbarch
, -1);
2278 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2280 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2281 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2283 SET_GDBARCH_BREAKPOINT_MANIPULATION (sh
);
2285 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2286 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2288 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2290 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2291 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2293 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2294 set_gdbarch_return_in_first_hidden_param_p (gdbarch
,
2295 sh_return_in_first_hidden_param_p
);
2297 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2299 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2300 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2301 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2302 set_gdbarch_dummy_id (gdbarch
, sh_dummy_id
);
2303 frame_base_set_default (gdbarch
, &sh_frame_base
);
2305 set_gdbarch_stack_frame_destroyed_p (gdbarch
, sh_stack_frame_destroyed_p
);
2307 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
2309 set_gdbarch_iterate_over_regset_sections
2310 (gdbarch
, sh_iterate_over_regset_sections
);
2312 switch (info
.bfd_arch_info
->mach
)
2315 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2319 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2323 /* doubles on sh2e and sh3e are actually 4 byte. */
2324 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2325 set_gdbarch_double_format (gdbarch
, floatformats_ieee_single
);
2327 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2328 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2329 set_gdbarch_fp0_regnum (gdbarch
, 25);
2330 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2331 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2335 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
2336 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
2337 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2339 set_gdbarch_fp0_regnum (gdbarch
, 25);
2340 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
2341 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2342 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2343 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2344 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2347 case bfd_mach_sh2a_nofpu
:
2348 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
2349 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2351 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
2352 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2353 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2356 case bfd_mach_sh_dsp
:
2357 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2358 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2362 case bfd_mach_sh3_nommu
:
2363 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2364 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2368 case bfd_mach_sh2a_or_sh3e
:
2369 /* doubles on sh2e and sh3e are actually 4 byte. */
2370 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2371 set_gdbarch_double_format (gdbarch
, floatformats_ieee_single
);
2373 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2374 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2375 set_gdbarch_fp0_regnum (gdbarch
, 25);
2376 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2377 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2380 case bfd_mach_sh3_dsp
:
2381 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2382 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2387 case bfd_mach_sh2a_or_sh4
:
2388 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2389 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2390 set_gdbarch_fp0_regnum (gdbarch
, 25);
2391 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
2392 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2393 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2394 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2395 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2398 case bfd_mach_sh4_nofpu
:
2399 case bfd_mach_sh4a_nofpu
:
2400 case bfd_mach_sh4_nommu_nofpu
:
2401 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2402 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
2405 case bfd_mach_sh4al_dsp
:
2406 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
2407 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2411 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2415 /* Hook in ABI-specific overrides, if they have been registered. */
2416 gdbarch_init_osabi (info
, gdbarch
);
2418 dwarf2_append_unwinders (gdbarch
);
2419 frame_unwind_append_unwinder (gdbarch
, &sh_stub_unwind
);
2420 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
2426 show_sh_command (char *args
, int from_tty
)
2428 help_list (showshcmdlist
, "show sh ", all_commands
, gdb_stdout
);
2432 set_sh_command (char *args
, int from_tty
)
2435 ("\"set sh\" must be followed by an appropriate subcommand.\n");
2436 help_list (setshcmdlist
, "set sh ", all_commands
, gdb_stdout
);
2439 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
2442 _initialize_sh_tdep (void)
2444 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2446 add_prefix_cmd ("sh", no_class
, set_sh_command
, "SH specific commands.",
2447 &setshcmdlist
, "set sh ", 0, &setlist
);
2448 add_prefix_cmd ("sh", no_class
, show_sh_command
, "SH specific commands.",
2449 &showshcmdlist
, "show sh ", 0, &showlist
);
2451 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
2452 &sh_active_calling_convention
,
2453 _("Set calling convention used when calling target "
2454 "functions from GDB."),
2455 _("Show calling convention used when calling target "
2456 "functions from GDB."),
2457 _("gcc - Use GCC calling convention (default).\n"
2458 "renesas - Enforce Renesas calling convention."),
2460 &setshcmdlist
, &showshcmdlist
);