include/linux/mfd/db8500-prcmu.h

   1 /*
   2  * Copyright (C) STMicroelectronics 2009
   3  * Copyright (C) ST-Ericsson SA 2010
   4  *
   5  * License Terms: GNU General Public License v2
   6  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   7  *
   8  * PRCMU f/w APIs
   9  */
  10 #ifndef __MFD_DB8500_PRCMU_H
  11 #define __MFD_DB8500_PRCMU_H
  12
  13 #include <linux/interrupt.h>
  14 #include <linux/bitops.h>
  15
  16 /*
  17  * Registers
  18  */
  19 #define DB8500_PRCM_GPIOCR 0x138
  20 #define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0     BIT(0)
  21 #define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD      BIT(9)
  22 #define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1     BIT(11)
  23 #define DB8500_PRCM_GPIOCR_SPI2_SELECT          BIT(23)
  24
  25 #define DB8500_PRCM_LINE_VALUE 0x170
  26 #define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0      BIT(3)
  27
  28 #define DB8500_PRCM_DSI_SW_RESET 0x324
  29 #define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
  30 #define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
  31 #define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
  32
  33 /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
  34
  35 /**
  36  * enum state - ON/OFF state definition
  37  * @OFF: State is ON
  38  * @ON: State is OFF
  39  *
  40  */
  41 enum state {
  42         OFF = 0x0,
  43         ON  = 0x1,
  44 };
  45
  46 /**
  47  * enum ret_state - general purpose On/Off/Retention states
  48  *
  49  */
  50 enum ret_state {
  51         OFFST = 0,
  52         ONST  = 1,
  53         RETST = 2
  54 };
  55
  56 /**
  57  * enum clk_arm - ARM Cortex A9 clock schemes
  58  * @A9_OFF:
  59  * @A9_BOOT:
  60  * @A9_OPPT1:
  61  * @A9_OPPT2:
  62  * @A9_EXTCLK:
  63  */
  64 enum clk_arm {
  65         A9_OFF,
  66         A9_BOOT,
  67         A9_OPPT1,
  68         A9_OPPT2,
  69         A9_EXTCLK
  70 };
  71
  72 /**
  73  * enum clk_gen - GEN#0/GEN#1 clock schemes
  74  * @GEN_OFF:
  75  * @GEN_BOOT:
  76  * @GEN_OPPT1:
  77  */
  78 enum clk_gen {
  79         GEN_OFF,
  80         GEN_BOOT,
  81         GEN_OPPT1,
  82 };
  83
  84 /* some information between arm and xp70 */
  85
  86 /**
  87  * enum romcode_write - Romcode message written by A9 AND read by XP70
  88  * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
  89  * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
  90  *                 romcode. The xp70 will go into self-reset
  91  */
  92 enum romcode_write {
  93         RDY_2_DS = 0x09,
  94         RDY_2_XP70_RST = 0x10
  95 };
  96
  97 /**
  98  * enum romcode_read - Romcode message written by XP70 and read by A9
  99  * @INIT: Init value when romcode field is not used
 100  * @FS_2_DS: Value set when power state is going from ApExecute to
 101  *          ApDeepSleep
 102  * @END_DS: Value set when ApDeepSleep power state is reached coming from
 103  *         ApExecute state
 104  * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
 105  *           ApExecute
 106  * @END_FS: Value set when ApExecute power state is reached coming from
 107  *         ApDeepSleep state
 108  * @SWR: Value set when power state is going to ApReset
 109  * @END_SWR: Value set when the xp70 finished executing ApReset actions and
 110  *          waits for romcode acknowledgment to go to self-reset
 111  */
 112 enum romcode_read {
 113         INIT = 0x00,
 114         FS_2_DS = 0x0A,
 115         END_DS = 0x0B,
 116         DS_TO_FS = 0x0C,
 117         END_FS = 0x0D,
 118         SWR = 0x0E,
 119         END_SWR = 0x0F
 120 };
 121
 122 /**
 123  * enum ap_pwrst - current power states defined in PRCMU firmware
 124  * @NO_PWRST: Current power state init
 125  * @AP_BOOT: Current power state is apBoot
 126  * @AP_EXECUTE: Current power state is apExecute
 127  * @AP_DEEP_SLEEP: Current power state is apDeepSleep
 128  * @AP_SLEEP: Current power state is apSleep
 129  * @AP_IDLE: Current power state is apIdle
 130  * @AP_RESET: Current power state is apReset
 131  */
 132 enum ap_pwrst {
 133         NO_PWRST = 0x00,
 134         AP_BOOT = 0x01,
 135         AP_EXECUTE = 0x02,
 136         AP_DEEP_SLEEP = 0x03,
 137         AP_SLEEP = 0x04,
 138         AP_IDLE = 0x05,
 139         AP_RESET = 0x06
 140 };
 141
 142 /**
 143  * enum ap_pwrst_trans - Transition states defined in PRCMU firmware
 144  * @NO_TRANSITION: No power state transition
 145  * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
 146  * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
 147  * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
 148  * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
 149  *                          ApDeepSleep
 150  * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
 151  */
 152 enum ap_pwrst_trans {
 153         PRCMU_AP_NO_CHANGE              = 0x00,
 154         APEXECUTE_TO_APSLEEP            = 0x01,
 155         APIDLE_TO_APSLEEP               = 0x02, /* To be removed */
 156         PRCMU_AP_SLEEP                  = 0x01,
 157         APBOOT_TO_APEXECUTE             = 0x03,
 158         APEXECUTE_TO_APDEEPSLEEP        = 0x04, /* To be removed */
 159         PRCMU_AP_DEEP_SLEEP             = 0x04,
 160         APEXECUTE_TO_APIDLE             = 0x05, /* To be removed */
 161         PRCMU_AP_IDLE                   = 0x05,
 162         PRCMU_AP_DEEP_IDLE              = 0x07,
 163 };
 164
 165 /**
 166  * enum hw_acc_state - State definition for hardware accelerator
 167  * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
 168  * @HW_OFF: The hardware accelerator must be switched off
 169  * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
 170  *               internal RAM in retention
 171  * @HW_ON: The hwa hardware accelerator hwa must be switched on
 172  *
 173  * NOTE! Deprecated, to be removed when all users switched over to use the
 174  * regulator API.
 175  */
 176 enum hw_acc_state {
 177         HW_NO_CHANGE = 0x00,
 178         HW_OFF = 0x01,
 179         HW_OFF_RAMRET = 0x02,
 180         HW_ON = 0x04
 181 };
 182
 183 /**
 184  * enum  mbox_2_arm_stat - Status messages definition for mbox_arm
 185  * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
 186  *                    completed
 187  * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
 188  *              completed
 189  * @SLEEPOK: The apExecute to apSleep state transition has been completed
 190  * @IDLEOK: The apExecute to apIdle state transition has been completed
 191  * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
 192  * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
 193  * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
 194  * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
 195  *                       going
 196  * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
 197  *                       going
 198  * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
 199  *                         been completed
 200  * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
 201  * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
 202  * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
 203  *                     completed
 204  * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
 205  * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
 206  * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
 207  *                    completed
 208  * @INIT_STATUS: Status init
 209  */
 210 enum ap_pwrsttr_status {
 211         BOOT_TO_EXECUTEOK = 0xFF,
 212         DEEPSLEEPOK = 0xFE,
 213         SLEEPOK = 0xFD,
 214         IDLEOK = 0xFC,
 215         SOFTRESETOK = 0xFB,
 216         SOFTRESETGO = 0xFA,
 217         BOOT_TO_EXECUTE = 0xF9,
 218         EXECUTE_TO_DEEPSLEEP = 0xF8,
 219         DEEPSLEEP_TO_EXECUTE = 0xF7,
 220         DEEPSLEEP_TO_EXECUTEOK = 0xF6,
 221         EXECUTE_TO_SLEEP = 0xF5,
 222         SLEEP_TO_EXECUTE = 0xF4,
 223         SLEEP_TO_EXECUTEOK = 0xF3,
 224         EXECUTE_TO_IDLE = 0xF2,
 225         IDLE_TO_EXECUTE = 0xF1,
 226         IDLE_TO_EXECUTEOK = 0xF0,
 227         RDYTODS_RETURNTOEXE    = 0xEF,
 228         NORDYTODS_RETURNTOEXE  = 0xEE,
 229         EXETOSLEEP_RETURNTOEXE = 0xED,
 230         EXETOIDLE_RETURNTOEXE  = 0xEC,
 231         INIT_STATUS = 0xEB,
 232
 233         /*error messages */
 234         INITERROR                     = 0x00,
 235         PLLARMLOCKP_ER                = 0x01,
 236         PLLDDRLOCKP_ER                = 0x02,
 237         PLLSOCLOCKP_ER                = 0x03,
 238         PLLSOCK1LOCKP_ER              = 0x04,
 239         ARMWFI_ER                     = 0x05,
 240         SYSCLKOK_ER                   = 0x06,
 241         I2C_NACK_DATA_ER              = 0x07,
 242         BOOT_ER                       = 0x08,
 243         I2C_STATUS_ALWAYS_1           = 0x0A,
 244         I2C_NACK_REG_ADDR_ER          = 0x0B,
 245         I2C_NACK_DATA0123_ER          = 0x1B,
 246         I2C_NACK_ADDR_ER              = 0x1F,
 247         CURAPPWRSTISNOT_BOOT          = 0x20,
 248         CURAPPWRSTISNOT_EXECUTE       = 0x21,
 249         CURAPPWRSTISNOT_SLEEPMODE     = 0x22,
 250         CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
 251         FIFO4500WUISNOT_WUPEVENT      = 0x24,
 252         PLL32KLOCKP_ER                = 0x29,
 253         DDRDEEPSLEEPOK_ER             = 0x2A,
 254         ROMCODEREADY_ER               = 0x50,
 255         WUPBEFOREDS                   = 0x51,
 256         DDRCONFIG_ER                  = 0x52,
 257         WUPBEFORESLEEP                = 0x53,
 258         WUPBEFOREIDLE                 = 0x54
 259 };  /* earlier called as  mbox_2_arm_stat */
 260
 261 /**
 262  * enum dvfs_stat - DVFS status messages definition
 263  * @DVFS_GO: A state transition DVFS is on going
 264  * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
 265  * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
 266  * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
 267  * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
 268  *                   NOCHGCLK
 269  * @DVFS_INITSTATUS: Value init
 270  */
 271 enum dvfs_stat {
 272         DVFS_GO = 0xFF,
 273         DVFS_ARM100OPPOK = 0xFE,
 274         DVFS_ARM50OPPOK = 0xFD,
 275         DVFS_ARMEXTCLKOK = 0xFC,
 276         DVFS_NOCHGTCLKOK = 0xFB,
 277         DVFS_INITSTATUS = 0x00
 278 };
 279
 280 /**
 281  * enum sva_mmdsp_stat - SVA MMDSP status messages
 282  * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
 283  * @SVA_MMDSP_INIT: Status init
 284  */
 285 enum sva_mmdsp_stat {
 286         SVA_MMDSP_GO = 0xFF,
 287         SVA_MMDSP_INIT = 0x00
 288 };
 289
 290 /**
 291  * enum sia_mmdsp_stat - SIA MMDSP status messages
 292  * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
 293  * @SIA_MMDSP_INIT: Status init
 294  */
 295 enum sia_mmdsp_stat {
 296         SIA_MMDSP_GO = 0xFF,
 297         SIA_MMDSP_INIT = 0x00
 298 };
 299
 300 /**
 301  * enum  mbox_to_arm_err - Error messages definition
 302  * @INIT_ERR: Init value
 303  * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
 304  * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
 305  * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
 306  * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
 307  * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
 308  * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
 309  * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
 310  * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
 311  * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
 312  *          through I2C has not been correctly executed in the given time
 313  * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
 314  *             through I2C has not been correctly executed in the given time
 315  * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
 316  *                     I2C has not been correctly executed in the given time
 317  * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
 318  *             through I2C has not been correctly executed in the given time
 319  * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
 320  *                     I2C has not been correctly executed in the given time
 321  * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
 322  *             through I2C has not been correctly executed in the given time
 323  * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
 324  *                     I2C has not been correctly executed in the given time
 325  * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
 326  *                         has not been correctly executed in the given time
 327  * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
 328  *                             not been correctly executed in the given time
 329  * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
 330  *                             not been correctly executed in the given time
 331  * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
 332  *                     I2C has not been correctly executed in the given time
 333  * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
 334  *                     I2C has not been correctly executed in the given time
 335  * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
 336  *             through I2C has not been correctly executed in the given time
 337  * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
 338  *             ApBoot to ApExecute but the power current state is not Apboot
 339  * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
 340  *              transition from ApExecute to others power state but the
 341  *              power current state is not ApExecute
 342  * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
 343  *             but the power current state is not ApDeepSleep/ApSleep/ApIdle
 344  * @CURAPPWRSTISNOTCORRECTDBG:  Generated when wake up events are transmitted
 345  *              but the power current state is not correct
 346  * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
 347  *                    been correctly executed in the given time
 348  * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
 349  *                    been correctly executed in the given time
 350  * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
 351  *                    been correctly executed in the given time
 352  * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
 353  *                      been correctly executed in the given time
 354  * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
 355  *                    been correctly executed in the given time
 356  */
 357 enum mbox_to_arm_err {
 358         INIT_ERR = 0x00,
 359         PLLARMLOCKP_ERR = 0x01,
 360         PLLDDRLOCKP_ERR = 0x02,
 361         PLLSOC0LOCKP_ERR = 0x03,
 362         PLLSOC1LOCKP_ERR = 0x04,
 363         ARMWFI_ERR = 0x05,
 364         SYSCLKOK_ERR = 0x06,
 365         BOOT_ERR = 0x07,
 366         ROMCODESAVECONTEXT = 0x08,
 367         VARMHIGHSPEEDVALTO_ERR = 0x10,
 368         VARMHIGHSPEEDACCESS_ERR = 0x11,
 369         VARMLOWSPEEDVALTO_ERR = 0x12,
 370         VARMLOWSPEEDACCESS_ERR = 0x13,
 371         VARMRETENTIONVALTO_ERR = 0x14,
 372         VARMRETENTIONACCESS_ERR = 0x15,
 373         VAPEHIGHSPEEDVALTO_ERR = 0x16,
 374         VSAFEHPVALTO_ERR = 0x17,
 375         VMODSEL1VALTO_ERR = 0x18,
 376         VMODSEL2VALTO_ERR = 0x19,
 377         VARMOFFACCESS_ERR = 0x1A,
 378         VAPEOFFACCESS_ERR = 0x1B,
 379         VARMRETACCES_ERR = 0x1C,
 380         CURAPPWRSTISNOTBOOT = 0x20,
 381         CURAPPWRSTISNOTEXECUTE = 0x21,
 382         CURAPPWRSTISNOTSLEEPMODE = 0x22,
 383         CURAPPWRSTISNOTCORRECTDBG = 0x23,
 384         ARMREGU1VALTO_ERR = 0x24,
 385         ARMREGU2VALTO_ERR = 0x25,
 386         VAPEREGUVALTO_ERR = 0x26,
 387         VSMPS3REGUVALTO_ERR = 0x27,
 388         VMODREGUVALTO_ERR = 0x28
 389 };
 390
 391 enum hw_acc {
 392         SVAMMDSP = 0,
 393         SVAPIPE = 1,
 394         SIAMMDSP = 2,
 395         SIAPIPE = 3,
 396         SGA = 4,
 397         B2R2MCDE = 5,
 398         ESRAM12 = 6,
 399         ESRAM34 = 7,
 400 };
 401
 402 enum cs_pwrmgt {
 403         PWRDNCS0  = 0,
 404         WKUPCS0   = 1,
 405         PWRDNCS1  = 2,
 406         WKUPCS1   = 3
 407 };
 408
 409 /* Defs related to autonomous power management */
 410
 411 /**
 412  * enum sia_sva_pwr_policy - Power policy
 413  * @NO_CHGT:    No change
 414  * @DSPOFF_HWPOFF:
 415  * @DSPOFFRAMRET_HWPOFF:
 416  * @DSPCLKOFF_HWPOFF:
 417  * @DSPCLKOFF_HWPCLKOFF:
 418  *
 419  */
 420 enum sia_sva_pwr_policy {
 421         NO_CHGT                 = 0x0,
 422         DSPOFF_HWPOFF           = 0x1,
 423         DSPOFFRAMRET_HWPOFF     = 0x2,
 424         DSPCLKOFF_HWPOFF        = 0x3,
 425         DSPCLKOFF_HWPCLKOFF     = 0x4,
 426 };
 427
 428 /**
 429  * enum auto_enable - Auto Power enable
 430  * @AUTO_OFF:
 431  * @AUTO_ON:
 432  *
 433  */
 434 enum auto_enable {
 435         AUTO_OFF        = 0x0,
 436         AUTO_ON         = 0x1,
 437 };
 438
 439 /* End of file previously known as prcmu-fw-defs_v1.h */
 440
 441 /**
 442  * enum prcmu_power_status - results from set_power_state
 443  * @PRCMU_SLEEP_OK: Sleep went ok
 444  * @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
 445  * @PRCMU_IDLE_OK: Idle went ok
 446  * @PRCMU_DEEPIDLE_OK: DeepIdle went ok
 447  * @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
 448  * @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
 449  *
 450  */
 451 enum prcmu_power_status {
 452         PRCMU_SLEEP_OK                  = 0xf3,
 453         PRCMU_DEEP_SLEEP_OK             = 0xf6,
 454         PRCMU_IDLE_OK                   = 0xf0,
 455         PRCMU_DEEPIDLE_OK               = 0xe3,
 456         PRCMU_PRCMU2ARMPENDINGIT_ER     = 0x91,
 457         PRCMU_ARMPENDINGIT_ER           = 0x93,
 458 };
 459
 460 /*
 461  * Definitions for autonomous power management configuration.
 462  */
 463
 464 #define PRCMU_AUTO_PM_OFF 0
 465 #define PRCMU_AUTO_PM_ON 1
 466
 467 #define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
 468 #define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
 469
 470 enum prcmu_auto_pm_policy {
 471         PRCMU_AUTO_PM_POLICY_NO_CHANGE,
 472         PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
 473         PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
 474         PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
 475         PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
 476 };
 477
 478 /**
 479  * struct prcmu_auto_pm_config - Autonomous power management configuration.
 480  * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
 481  * @sia_power_on:       SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
 482  * @sia_policy:         SIA power policy. (enum prcmu_auto_pm_policy)
 483  * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
 484  * @sva_power_on:       SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
 485  * @sva_policy:         SVA power policy. (enum prcmu_auto_pm_policy)
 486  */
 487 struct prcmu_auto_pm_config {
 488         u8 sia_auto_pm_enable;
 489         u8 sia_power_on;
 490         u8 sia_policy;
 491         u8 sva_auto_pm_enable;
 492         u8 sva_power_on;
 493         u8 sva_policy;
 494 };
 495
 496 #define PRCMU_FW_PROJECT_U8500          2
 497 #define PRCMU_FW_PROJECT_U9500          4
 498 #define PRCMU_FW_PROJECT_U8500_C2       7
 499 #define PRCMU_FW_PROJECT_U9500_C2       11
 500 #define PRCMU_FW_PROJECT_U8520          13
 501 #define PRCMU_FW_PROJECT_U8420          14
 502
 503 struct prcmu_fw_version {
 504         u8 project;
 505         u8 api_version;
 506         u8 func_version;
 507         u8 errata;
 508 };
 509
 510 #ifdef CONFIG_MFD_DB8500_PRCMU
 511
 512 void db8500_prcmu_early_init(void);
 513 int prcmu_set_rc_a2p(enum romcode_write);
 514 enum romcode_read prcmu_get_rc_p2a(void);
 515 enum ap_pwrst prcmu_get_xp70_current_state(void);
 516 bool prcmu_has_arm_maxopp(void);
 517 struct prcmu_fw_version *prcmu_get_fw_version(void);
 518 int prcmu_request_ape_opp_100_voltage(bool enable);
 519 int prcmu_release_usb_wakeup_state(void);
 520 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
 521         struct prcmu_auto_pm_config *idle);
 522 bool prcmu_is_auto_pm_enabled(void);
 523
 524 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
 525 int prcmu_set_clock_divider(u8 clock, u8 divider);
 526 int db8500_prcmu_config_hotdog(u8 threshold);
 527 int db8500_prcmu_config_hotmon(u8 low, u8 high);
 528 int db8500_prcmu_start_temp_sense(u16 cycles32k);
 529 int db8500_prcmu_stop_temp_sense(void);
 530 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
 531 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
 532
 533 int prcmu_ac_wake_req(void);
 534 void prcmu_ac_sleep_req(void);
 535 void db8500_prcmu_modem_reset(void);
 536
 537 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
 538 int db8500_prcmu_enable_a9wdog(u8 id);
 539 int db8500_prcmu_disable_a9wdog(u8 id);
 540 int db8500_prcmu_kick_a9wdog(u8 id);
 541 int db8500_prcmu_load_a9wdog(u8 id, u32 val);
 542
 543 void db8500_prcmu_system_reset(u16 reset_code);
 544 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
 545 u8 db8500_prcmu_get_power_state_result(void);
 546 int db8500_prcmu_gic_decouple(void);
 547 int db8500_prcmu_gic_recouple(void);
 548 int db8500_prcmu_copy_gic_settings(void);
 549 bool db8500_prcmu_gic_pending_irq(void);
 550 bool db8500_prcmu_pending_irq(void);
 551 bool db8500_prcmu_is_cpu_in_wfi(int cpu);
 552 void db8500_prcmu_enable_wakeups(u32 wakeups);
 553 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
 554 int db8500_prcmu_request_clock(u8 clock, bool enable);
 555 int db8500_prcmu_set_display_clocks(void);
 556 int db8500_prcmu_disable_dsipll(void);
 557 int db8500_prcmu_enable_dsipll(void);
 558 void db8500_prcmu_config_abb_event_readout(u32 abb_events);
 559 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
 560 int db8500_prcmu_config_esram0_deep_sleep(u8 state);
 561 u16 db8500_prcmu_get_reset_code(void);
 562 bool db8500_prcmu_is_ac_wake_requested(void);
 563 int db8500_prcmu_set_arm_opp(u8 opp);
 564 int db8500_prcmu_get_arm_opp(void);
 565 int db8500_prcmu_set_ape_opp(u8 opp);
 566 int db8500_prcmu_get_ape_opp(void);
 567 int db8500_prcmu_set_ddr_opp(u8 opp);
 568 int db8500_prcmu_get_ddr_opp(void);
 569
 570 u32 db8500_prcmu_read(unsigned int reg);
 571 void db8500_prcmu_write(unsigned int reg, u32 value);
 572 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
 573
 574 #else /* !CONFIG_MFD_DB8500_PRCMU */
 575
 576 static inline void db8500_prcmu_early_init(void) {}
 577
 578 static inline int prcmu_set_rc_a2p(enum romcode_write code)
 579 {
 580         return 0;
 581 }
 582
 583 static inline enum romcode_read prcmu_get_rc_p2a(void)
 584 {
 585         return INIT;
 586 }
 587
 588 static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
 589 {
 590         return AP_EXECUTE;
 591 }
 592
 593 static inline bool prcmu_has_arm_maxopp(void)
 594 {
 595         return false;
 596 }
 597
 598 static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
 599 {
 600         return NULL;
 601 }
 602
 603 static inline int db8500_prcmu_set_ape_opp(u8 opp)
 604 {
 605         return 0;
 606 }
 607
 608 static inline int db8500_prcmu_get_ape_opp(void)
 609 {
 610         return APE_100_OPP;
 611 }
 612
 613 static inline int prcmu_request_ape_opp_100_voltage(bool enable)
 614 {
 615         return 0;
 616 }
 617
 618 static inline int prcmu_release_usb_wakeup_state(void)
 619 {
 620         return 0;
 621 }
 622
 623 static inline int db8500_prcmu_set_ddr_opp(u8 opp)
 624 {
 625         return 0;
 626 }
 627
 628 static inline int db8500_prcmu_get_ddr_opp(void)
 629 {
 630         return DDR_100_OPP;
 631 }
 632
 633 static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
 634         struct prcmu_auto_pm_config *idle)
 635 {
 636 }
 637
 638 static inline bool prcmu_is_auto_pm_enabled(void)
 639 {
 640         return false;
 641 }
 642
 643 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 644 {
 645         return 0;
 646 }
 647
 648 static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
 649 {
 650         return 0;
 651 }
 652
 653 static inline int db8500_prcmu_config_hotdog(u8 threshold)
 654 {
 655         return 0;
 656 }
 657
 658 static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
 659 {
 660         return 0;
 661 }
 662
 663 static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
 664 {
 665         return 0;
 666 }
 667
 668 static inline int db8500_prcmu_stop_temp_sense(void)
 669 {
 670         return 0;
 671 }
 672
 673 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
 674 {
 675         return -ENOSYS;
 676 }
 677
 678 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
 679 {
 680         return -ENOSYS;
 681 }
 682
 683 static inline int prcmu_ac_wake_req(void)
 684 {
 685         return 0;
 686 }
 687
 688 static inline void prcmu_ac_sleep_req(void) {}
 689
 690 static inline void db8500_prcmu_modem_reset(void) {}
 691
 692 static inline void db8500_prcmu_system_reset(u16 reset_code) {}
 693
 694 static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
 695         bool keep_ap_pll)
 696 {
 697         return 0;
 698 }
 699
 700 static inline u8 db8500_prcmu_get_power_state_result(void)
 701 {
 702         return 0;
 703 }
 704
 705 static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
 706
 707 static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
 708 {
 709         return 0;
 710 }
 711
 712 static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
 713 {
 714         return 0;
 715 }
 716
 717 static inline int db8500_prcmu_set_display_clocks(void)
 718 {
 719         return 0;
 720 }
 721
 722 static inline int db8500_prcmu_disable_dsipll(void)
 723 {
 724         return 0;
 725 }
 726
 727 static inline int db8500_prcmu_enable_dsipll(void)
 728 {
 729         return 0;
 730 }
 731
 732 static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
 733 {
 734         return 0;
 735 }
 736
 737 static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
 738
 739 static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
 740
 741 static inline u16 db8500_prcmu_get_reset_code(void)
 742 {
 743         return 0;
 744 }
 745
 746 static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
 747 {
 748         return 0;
 749 }
 750
 751 static inline int db8500_prcmu_enable_a9wdog(u8 id)
 752 {
 753         return 0;
 754 }
 755
 756 static inline int db8500_prcmu_disable_a9wdog(u8 id)
 757 {
 758         return 0;
 759 }
 760
 761 static inline int db8500_prcmu_kick_a9wdog(u8 id)
 762 {
 763         return 0;
 764 }
 765
 766 static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
 767 {
 768         return 0;
 769 }
 770
 771 static inline bool db8500_prcmu_is_ac_wake_requested(void)
 772 {
 773         return 0;
 774 }
 775
 776 static inline int db8500_prcmu_set_arm_opp(u8 opp)
 777 {
 778         return 0;
 779 }
 780
 781 static inline int db8500_prcmu_get_arm_opp(void)
 782 {
 783         return 0;
 784 }
 785
 786 static inline u32 db8500_prcmu_read(unsigned int reg)
 787 {
 788         return 0;
 789 }
 790
 791 static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
 792
 793 static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
 794         u32 value) {}
 795
 796 #endif /* !CONFIG_MFD_DB8500_PRCMU */
 797
 798 #endif /* __MFD_DB8500_PRCMU_H */