1 2021-07-03 Nick Clifton <nickc@redhat.com>
3 * configure: Regenerate.
4 * po/opcodes.pot: Regenerate.
6 2021-07-03 Nick Clifton <nickc@redhat.com>
8 * 2.37 release branch created.
10 2021-07-02 Alan Modra <amodra@gmail.com>
12 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
13 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
14 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
15 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
16 (nds32_keyword_gpr): Move declarations to..
17 * nds32-asm.h: ..here, constifying to match definitions.
19 2021-07-01 Mike Frysinger <vapier@gentoo.org>
21 * Makefile.am (GUILE): New variable.
23 * Makefile.in: Regenerate.
25 2021-07-01 Mike Frysinger <vapier@gentoo.org>
27 * mep-asm.c (macros): Mark static & const.
28 (lookup_macro): Change return & m to const.
29 (expand_macro): Change mac to const.
30 (expand_string): Change pmacro to const.
32 2021-07-01 Mike Frysinger <vapier@gentoo.org>
34 * nds32-asm.c (operand_fields): Rename to ...
35 (nds32_operand_fields): ... this.
36 (keyword_gpr): Rename to ...
37 (nds32_keyword_gpr): ... this.
38 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
39 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
40 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
41 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
42 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
44 (keywords): Rename to ...
45 (nds32_keywords): ... this.
46 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
47 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
49 2021-07-01 Mike Frysinger <vapier@gentoo.org>
51 * z80-dis.c (opc_ed): Make const.
52 (pref_ed): Make p const.
54 2021-07-01 Mike Frysinger <vapier@gentoo.org>
56 * microblaze-dis.c (get_field_special): Make op const.
57 (read_insn_microblaze): Make opr & op const. Rename opcodes to
59 (print_insn_microblaze): Make op & pop const.
60 (get_insn_microblaze): Make op const. Rename opcodes to
62 (microblaze_get_target_address): Likewise.
63 * microblaze-opc.h (struct op_code_struct): Make const.
64 Rename opcodes to microblaze_opcodes.
66 2021-07-01 Mike Frysinger <vapier@gentoo.org>
68 * aarch64-gen.c (aarch64_opcode_table): Add const.
69 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
71 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
73 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
76 2021-06-22 Alan Modra <amodra@gmail.com>
78 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
79 print separator for pcrel insns.
81 2021-06-19 Alan Modra <amodra@gmail.com>
83 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
85 2021-06-19 Alan Modra <amodra@gmail.com>
87 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
90 2021-06-17 Alan Modra <amodra@gmail.com>
92 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
95 2021-06-03 Alan Modra <amodra@gmail.com>
98 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
99 Use unsigned int for inst.
101 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
103 * arc-dis.c (arc_option_arg_t): New enumeration.
104 (arc_options): New variable.
105 (disassembler_options_arc): New function.
106 (print_arc_disassembler_options): Reimplement in terms of
107 "disassembler_options_arc".
109 2021-05-29 Alan Modra <amodra@gmail.com>
111 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
112 Don't special case PPC_OPCODE_RAW.
113 (lookup_prefix): Likewise.
114 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
115 (print_insn_powerpc): ..update caller.
116 * ppc-opc.c (EXT): Define.
117 (powerpc_opcodes): Mark extended mnemonics with EXT.
118 (prefix_opcodes, vle_opcodes): Likewise.
119 (XISEL, XISEL_MASK): Add cr field and simplify.
120 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
121 all isel variants to where the base mnemonic belongs. Sort dstt,
124 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
126 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
127 COP3 opcode instructions.
129 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
131 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
132 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
133 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
134 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
135 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
136 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
137 "cop2", and "cop3" entries.
139 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
141 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
142 entries and associated comments.
144 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
146 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
149 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
151 * mips-dis.c (mips_cp1_names_mips): New variable.
152 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
153 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
154 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
155 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
156 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
159 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
161 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
162 handling code over to...
163 <OP_REG_CONTROL>: ... this new case.
164 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
165 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
166 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
167 replacing the `G' operand code with `g'. Update "cftc1" and
168 "cftc2" entries replacing the `E' operand code with `y'.
169 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
170 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
171 entries replacing the `G' operand code with `g'.
173 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
175 * mips-dis.c (mips_cp0_names_r3900): New variable.
176 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
179 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
181 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
182 and "mtthc2" to using the `G' rather than `g' operand code for
183 the coprocessor control register referred.
185 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
187 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
188 entries with each other.
190 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
192 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
194 2021-05-25 Alan Modra <amodra@gmail.com>
196 * cris-desc.c: Regenerate.
197 * cris-desc.h: Regenerate.
198 * cris-opc.h: Regenerate.
199 * po/POTFILES.in: Regenerate.
201 2021-05-24 Mike Frysinger <vapier@gentoo.org>
203 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
204 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
205 (CGEN_CPUS): Add cris.
207 (stamp-cris): New rule.
208 * cgen.sh: Handle desc action.
209 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
210 * Makefile.in, configure: Regenerate.
212 2021-05-18 Job Noorman <mtvec@pm.me>
215 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
218 2021-05-17 Alex Coplan <alex.coplan@arm.com>
220 * arm-dis.c (mve_opcodes): Fix disassembly of
221 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
222 (is_mve_encoding_conflict): MVE vector loads should not match
224 (is_mve_unpredictable): It's not unpredictable to use the same
225 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
227 2021-05-11 Nick Clifton <nickc@redhat.com>
230 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
231 the end of the code buffer.
233 2021-05-06 Stafford Horne <shorne@gmail.com>
236 * or1k-asm.c: Regenerate.
238 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
240 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
241 info->insn_info_valid.
243 2021-04-26 Jan Beulich <jbeulich@suse.com>
245 * i386-opc.tbl (lea): Add Optimize.
246 * opcodes/i386-tbl.h: Re-generate.
248 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
250 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
251 of l32r fetch and display referenced literal value.
253 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
255 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
256 to 4 for literal disassembly.
258 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
260 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
261 for TLBI instruction.
263 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
265 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
268 2021-04-19 Jan Beulich <jbeulich@suse.com>
270 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
272 (convert_mov_to_movewide): Add initializer for "value".
274 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
276 * aarch64-opc.c: Add RME system registers.
278 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
280 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
281 "addi d,CV,z" to "c.mv d,CV".
283 2021-04-12 Alan Modra <amodra@gmail.com>
285 * configure.ac (--enable-checking): Add support.
286 * config.in: Regenerate.
287 * configure: Regenerate.
289 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
291 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
292 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
294 2021-04-09 Alan Modra <amodra@gmail.com>
296 * ppc-dis.c (struct dis_private): Add "special".
297 (POWERPC_DIALECT): Delete. Replace uses with..
298 (private_data): ..this. New inline function.
299 (disassemble_init_powerpc): Init "special" names.
300 (skip_optional_operands): Add is_pcrel arg, set when detecting R
301 field of prefix instructions.
302 (bsearch_reloc, print_got_plt): New functions.
303 (print_insn_powerpc): For pcrel instructions, print target address
304 and symbol if known, and decode plt and got loads too.
306 2021-04-08 Alan Modra <amodra@gmail.com>
309 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
311 2021-04-08 Alan Modra <amodra@gmail.com>
314 * ppc-opc.c (DCBT_EO): Move earlier.
315 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
316 (powerpc_operands): Add THCT and THDS entries.
317 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
319 2021-04-06 Alan Modra <amodra@gmail.com>
321 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
322 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
323 symbol_at_address_func.
325 2021-04-05 Alan Modra <amodra@gmail.com>
327 * configure.ac: Don't check for limits.h, string.h, strings.h or
329 (AC_ISC_POSIX): Don't invoke.
330 * sysdep.h: Include stdlib.h and string.h unconditionally.
331 * i386-opc.h: Include limits.h unconditionally.
332 * wasm32-dis.c: Likewise.
333 * cgen-opc.c: Don't include alloca-conf.h.
334 * config.in: Regenerate.
335 * configure: Regenerate.
337 2021-04-01 Martin Liska <mliska@suse.cz>
339 * arm-dis.c (strneq): Remove strneq and use startswith.
340 * cr16-dis.c (print_insn_cr16): Likewise.
341 * score-dis.c (streq): Likewise.
343 * score7-dis.c (strneq): Likewise.
345 2021-04-01 Alan Modra <amodra@gmail.com>
348 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
350 2021-03-31 Alan Modra <amodra@gmail.com>
352 * sysdep.h (POISON_BFD_BOOLEAN): Define.
353 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
354 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
355 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
356 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
357 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
358 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
359 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
360 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
361 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
362 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
363 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
364 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
365 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
366 and TRUE with true throughout.
368 2021-03-31 Alan Modra <amodra@gmail.com>
370 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
371 * aarch64-dis.h: Likewise.
372 * aarch64-opc.c: Likewise.
373 * avr-dis.c: Likewise.
374 * csky-dis.c: Likewise.
375 * nds32-asm.c: Likewise.
376 * nds32-dis.c: Likewise.
377 * nfp-dis.c: Likewise.
378 * riscv-dis.c: Likewise.
379 * s12z-dis.c: Likewise.
380 * wasm32-dis.c: Likewise.
382 2021-03-30 Jan Beulich <jbeulich@suse.com>
384 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
385 (i386_seg_prefixes): New.
386 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
387 (i386_seg_prefixes): Declare.
389 2021-03-30 Jan Beulich <jbeulich@suse.com>
391 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
393 2021-03-30 Jan Beulich <jbeulich@suse.com>
395 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
396 * i386-reg.tbl (st): Move down.
397 (st(0)): Delete. Extend comment.
398 * i386-tbl.h: Re-generate.
400 2021-03-29 Jan Beulich <jbeulich@suse.com>
402 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
403 (cmpsd): Move next to cmps.
404 (movsd): Move next to movs.
405 (cmpxchg16b): Move to separate section.
406 (fisttp, fisttpll): Likewise.
407 (monitor, mwait): Likewise.
408 * i386-tbl.h: Re-generate.
410 2021-03-29 Jan Beulich <jbeulich@suse.com>
412 * i386-opc.tbl (psadbw): Add <sse2:comm>.
414 * i386-tbl.h: Re-generate.
416 2021-03-29 Jan Beulich <jbeulich@suse.com>
418 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
419 pclmul, gfni): New templates. Use them wherever possible. Move
420 SSE4.1 pextrw into respective section.
421 * i386-tbl.h: Re-generate.
423 2021-03-29 Jan Beulich <jbeulich@suse.com>
425 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
426 strtoull(). Bump upper loop bound. Widen masks. Sanity check
428 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
429 Convert all of their uses to representation in opcode.
431 2021-03-29 Jan Beulich <jbeulich@suse.com>
433 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
434 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
435 value of None. Shrink operands to 3 bits.
437 2021-03-29 Jan Beulich <jbeulich@suse.com>
439 * i386-gen.c (process_i386_opcode_modifier): New parameter
441 (output_i386_opcode): New local variable "space". Adjust
442 process_i386_opcode_modifier() invocation.
443 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
445 * i386-tbl.h: Re-generate.
447 2021-03-29 Alan Modra <amodra@gmail.com>
449 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
450 (fp_qualifier_p, get_data_pattern): Likewise.
451 (aarch64_get_operand_modifier_from_value): Likewise.
452 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
453 (operand_variant_qualifier_p): Likewise.
454 (qualifier_value_in_range_constraint_p): Likewise.
455 (aarch64_get_qualifier_esize): Likewise.
456 (aarch64_get_qualifier_nelem): Likewise.
457 (aarch64_get_qualifier_standard_value): Likewise.
458 (get_lower_bound, get_upper_bound): Likewise.
459 (aarch64_find_best_match, match_operands_qualifier): Likewise.
460 (aarch64_print_operand): Likewise.
461 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
462 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
463 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
464 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
465 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
466 (print_insn_tic6x): Likewise.
468 2021-03-29 Alan Modra <amodra@gmail.com>
470 * arc-dis.c (extract_operand_value): Correct NULL cast.
471 * frv-opc.h: Regenerate.
473 2021-03-26 Jan Beulich <jbeulich@suse.com>
475 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
477 * i386-tbl.h: Re-generate.
479 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
481 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
482 immediate in br.n instruction.
484 2021-03-25 Jan Beulich <jbeulich@suse.com>
486 * i386-dis.c (XMGatherD, VexGatherD): New.
487 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
488 (print_insn): Check masking for S/G insns.
489 (OP_E_memory): New local variable check_gather. Extend mandatory
490 SIB check. Check register conflicts for (EVEX-encoded) gathers.
491 Extend check for disallowed 16-bit addressing.
492 (OP_VEX): New local variables modrm_reg and sib_index. Convert
493 if()s to switch(). Check register conflicts for (VEX-encoded)
494 gathers. Drop no longer reachable cases.
495 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
498 2021-03-25 Jan Beulich <jbeulich@suse.com>
500 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
501 zeroing-masking without masking.
503 2021-03-25 Jan Beulich <jbeulich@suse.com>
505 * i386-opc.tbl (invlpgb): Fix multi-operand form.
506 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
507 single-operand forms as deprecated.
508 * i386-tbl.h: Re-generate.
510 2021-03-25 Alan Modra <amodra@gmail.com>
513 * ppc-opc.c (XLOCB_MASK): Delete.
514 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
516 (powerpc_opcodes): Accept a BH field on all extended forms of
517 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
519 2021-03-24 Jan Beulich <jbeulich@suse.com>
521 * i386-gen.c (output_i386_opcode): Drop processing of
522 opcode_length. Calculate length from base_opcode. Adjust prefix
523 encoding determination.
524 (process_i386_opcodes): Drop output of fake opcode_length.
525 * i386-opc.h (struct insn_template): Drop opcode_length field.
526 * i386-opc.tbl: Drop opcode length field from all templates.
527 * i386-tbl.h: Re-generate.
529 2021-03-24 Jan Beulich <jbeulich@suse.com>
531 * i386-gen.c (process_i386_opcode_modifier): Return void. New
532 parameter "prefix". Drop local variable "regular_encoding".
533 Record prefix setting / check for consistency.
534 (output_i386_opcode): Parse opcode_length and base_opcode
535 earlier. Derive prefix encoding. Drop no longer applicable
536 consistency checking. Adjust process_i386_opcode_modifier()
538 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
540 * i386-tbl.h: Re-generate.
542 2021-03-24 Jan Beulich <jbeulich@suse.com>
544 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
546 * i386-opc.h (Prefix_*): Move #define-s.
547 * i386-opc.tbl: Move pseudo prefix enumerator values to
548 extension opcode field. Introduce pseudopfx template.
549 * i386-tbl.h: Re-generate.
551 2021-03-23 Jan Beulich <jbeulich@suse.com>
553 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
555 * i386-tbl.h: Re-generate.
557 2021-03-23 Jan Beulich <jbeulich@suse.com>
559 * i386-opc.h (struct insn_template): Move cpu_flags field past
561 * i386-tbl.h: Re-generate.
563 2021-03-23 Jan Beulich <jbeulich@suse.com>
565 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
566 * i386-opc.h (OpcodeSpace): New enumerator.
567 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
568 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
569 SPACE_XOP09, SPACE_XOP0A): ... respectively.
570 (struct i386_opcode_modifier): New field opcodespace. Shrink
572 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
573 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
575 * i386-tbl.h: Re-generate.
577 2021-03-22 Martin Liska <mliska@suse.cz>
579 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
580 * arc-dis.c (parse_option): Likewise.
581 * arm-dis.c (parse_arm_disassembler_options): Likewise.
582 * cris-dis.c (print_with_operands): Likewise.
583 * h8300-dis.c (bfd_h8_disassemble): Likewise.
584 * i386-dis.c (print_insn): Likewise.
585 * ia64-gen.c (fetch_insn_class): Likewise.
586 (parse_resource_users): Likewise.
587 (in_iclass): Likewise.
588 (lookup_specifier): Likewise.
589 (insert_opcode_dependencies): Likewise.
590 * mips-dis.c (parse_mips_ase_option): Likewise.
591 (parse_mips_dis_option): Likewise.
592 * s390-dis.c (disassemble_init_s390): Likewise.
593 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
595 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
597 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
599 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
601 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
602 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
604 2021-03-12 Alan Modra <amodra@gmail.com>
606 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
608 2021-03-11 Jan Beulich <jbeulich@suse.com>
610 * i386-dis.c (OP_XMM): Re-order checks.
612 2021-03-11 Jan Beulich <jbeulich@suse.com>
614 * i386-dis.c (putop): Drop need_vex check when also checking
616 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
619 2021-03-11 Jan Beulich <jbeulich@suse.com>
621 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
622 checks. Move case label past broadcast check.
624 2021-03-10 Jan Beulich <jbeulich@suse.com>
626 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
627 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
628 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
629 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
630 EVEX_W_0F38C7_M_0_L_2): Delete.
631 (REG_EVEX_0F38C7_M_0_L_2): New.
632 (intel_operand_size): Handle VEX and EVEX the same for
633 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
634 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
635 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
636 vex_vsib_q_w_d_mode uses.
637 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
638 0F38A1, and 0F38A3 entries.
639 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
641 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
642 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
645 2021-03-10 Jan Beulich <jbeulich@suse.com>
647 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
648 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
649 MOD_VEX_0FXOP_09_12): Rename to ...
650 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
651 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
652 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
653 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
654 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
655 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
656 (reg_table): Adjust comments.
657 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
658 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
659 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
660 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
661 (vex_len_table): Adjust opcode 0A_12 entry.
662 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
663 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
664 (rm_table): Move hreset entry.
666 2021-03-10 Jan Beulich <jbeulich@suse.com>
668 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
669 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
670 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
671 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
672 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
673 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
674 (get_valid_dis386): Also handle 512-bit vector length when
675 vectoring into vex_len_table[].
676 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
677 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
679 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
680 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
681 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
682 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
685 2021-03-10 Jan Beulich <jbeulich@suse.com>
687 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
688 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
689 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
690 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
692 * i386-dis-evex-len.h (evex_len_table): Likewise.
693 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
695 2021-03-10 Jan Beulich <jbeulich@suse.com>
697 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
698 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
699 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
700 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
701 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
702 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
703 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
704 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
705 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
706 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
707 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
708 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
709 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
710 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
711 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
712 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
713 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
714 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
715 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
716 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
717 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
718 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
719 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
720 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
721 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
722 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
723 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
724 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
725 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
726 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
727 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
728 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
729 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
730 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
731 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
732 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
733 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
734 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
735 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
736 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
737 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
738 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
739 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
740 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
741 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
742 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
743 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
744 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
745 EVEX_W_0F3A43_L_n): New.
746 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
747 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
748 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
749 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
750 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
751 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
752 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
753 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
754 0F385B, 0F38C6, and 0F38C7 entries.
755 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
757 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
758 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
759 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
760 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
762 2021-03-10 Jan Beulich <jbeulich@suse.com>
764 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
765 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
766 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
767 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
768 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
769 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
770 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
771 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
772 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
773 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
774 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
775 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
776 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
777 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
778 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
779 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
780 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
781 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
782 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
783 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
784 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
785 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
786 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
787 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
788 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
789 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
790 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
791 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
792 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
793 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
794 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
795 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
796 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
797 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
798 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
799 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
800 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
801 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
802 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
803 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
804 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
805 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
806 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
807 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
808 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
809 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
810 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
811 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
812 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
813 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
814 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
815 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
816 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
817 VEX_W_0F99_P_2_LEN_0): Delete.
818 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
819 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
820 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
821 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
822 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
823 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
824 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
825 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
826 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
827 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
828 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
829 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
830 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
831 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
832 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
833 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
834 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
835 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
836 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
837 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
838 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
839 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
840 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
841 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
842 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
843 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
844 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
845 (prefix_table): No longer link to vex_len_table[] for opcodes
846 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
847 0F92, 0F93, 0F98, and 0F99.
848 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
849 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
851 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
852 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
854 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
855 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
857 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
858 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
861 2021-03-10 Jan Beulich <jbeulich@suse.com>
863 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
864 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
865 REG_VEX_0F73_M_0 respectively.
866 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
867 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
868 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
869 MOD_VEX_0F73_REG_7): Delete.
870 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
871 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
872 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
873 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
874 PREFIX_VEX_0F3AF0_L_0 respectively.
875 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
876 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
877 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
878 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
879 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
880 VEX_LEN_0F38F7): New.
881 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
882 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
883 0F72, and 0F73. No longer link to vex_len_table[] for opcode
885 (prefix_table): No longer link to vex_len_table[] for opcodes
886 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
887 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
888 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
889 0F38F6, 0F38F7, and 0F3AF0.
890 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
891 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
892 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
895 2021-03-10 Jan Beulich <jbeulich@suse.com>
897 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
898 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
899 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
900 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
901 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
902 (MOD_0F71, MOD_0F72, MOD_0F73): New.
903 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
905 (reg_table): No longer link to mod_table[] for opcodes 0F71,
907 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
910 2021-03-10 Jan Beulich <jbeulich@suse.com>
912 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
913 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
914 (reg_table): Don't link to mod_table[] where not needed. Add
915 PREFIX_IGNORED to nop entries.
916 (prefix_table): Replace PREFIX_OPCODE in nop entries.
917 (mod_table): Add nop entries next to prefetch ones. Drop
918 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
919 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
920 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
921 PREFIX_OPCODE from endbr* entries.
922 (get_valid_dis386): Also consider entry's name when zapping
924 (print_insn): Handle PREFIX_IGNORED.
926 2021-03-09 Jan Beulich <jbeulich@suse.com>
928 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
929 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
931 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
932 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
933 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
934 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
935 (struct i386_opcode_modifier): Delete notrackprefixok,
936 islockable, hleprefixok, and repprefixok fields. Add prefixok
938 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
939 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
940 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
941 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
943 * opcodes/i386-tbl.h: Re-generate.
945 2021-03-09 Jan Beulich <jbeulich@suse.com>
947 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
948 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
950 * opcodes/i386-tbl.h: Re-generate.
952 2021-03-03 Jan Beulich <jbeulich@suse.com>
954 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
955 for {} instead of {0}. Don't look for '0'.
956 * i386-opc.tbl: Drop operand count field. Drop redundant operand
959 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
962 * riscv-dis.c (print_insn_args): Updated encoding macros.
963 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
964 (match_c_addi16sp): Updated encoding macros.
965 (match_c_lui): Likewise.
966 (match_c_lui_with_hint): Likewise.
967 (match_c_addi4spn): Likewise.
968 (match_c_slli): Likewise.
969 (match_slli_as_c_slli): Likewise.
970 (match_c_slli64): Likewise.
971 (match_srxi_as_c_srxi): Likewise.
972 (riscv_insn_types): Added .insn css/cl/cs.
974 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
976 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
977 (default_priv_spec): Updated type to riscv_spec_class.
978 (parse_riscv_dis_option): Updated.
979 * riscv-opc.c: Moved stuff and make the file tidy.
981 2021-02-17 Alan Modra <amodra@gmail.com>
983 * wasm32-dis.c: Include limits.h.
984 (CHAR_BIT): Provide backup define.
985 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
986 Correct signed overflow checking.
988 2021-02-16 Jan Beulich <jbeulich@suse.com>
990 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
991 * i386-tbl.h: Re-generate.
993 2021-02-16 Jan Beulich <jbeulich@suse.com>
995 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
997 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
999 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1001 * s390-mkopc.c (main): Accept arch14 as cpu string.
1002 * s390-opc.txt: Add new arch14 instructions.
1004 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1006 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1008 * configure: Regenerated.
1010 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1012 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1013 * tic54x-opc.c (regs): Rename to ...
1014 (tic54x_regs): ... this.
1015 (mmregs): Rename to ...
1016 (tic54x_mmregs): ... this.
1017 (condition_codes): Rename to ...
1018 (tic54x_condition_codes): ... this.
1019 (cc2_codes): Rename to ...
1020 (tic54x_cc2_codes): ... this.
1021 (cc3_codes): Rename to ...
1022 (tic54x_cc3_codes): ... this.
1023 (status_bits): Rename to ...
1024 (tic54x_status_bits): ... this.
1025 (misc_symbols): Rename to ...
1026 (tic54x_misc_symbols): ... this.
1028 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1030 * riscv-opc.c (MASK_RVB_IMM): Removed.
1031 (riscv_opcodes): Removed zb* instructions.
1032 (riscv_ext_version_table): Removed versions for zb*.
1034 2021-01-26 Alan Modra <amodra@gmail.com>
1036 * i386-gen.c (parse_template): Ensure entire template_instance
1039 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1041 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1042 (riscv_fpr_names_abi): Likewise.
1043 (riscv_opcodes): Likewise.
1044 (riscv_insn_types): Likewise.
1046 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1048 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1050 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1052 * riscv-dis.c: Comments tidy and improvement.
1053 * riscv-opc.c: Likewise.
1055 2021-01-13 Alan Modra <amodra@gmail.com>
1057 * Makefile.in: Regenerate.
1059 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1062 * configure.ac: Use GNU_MAKE_JOBSERVER.
1063 * aclocal.m4: Regenerated.
1064 * configure: Likewise.
1066 2021-01-12 Nick Clifton <nickc@redhat.com>
1068 * po/sr.po: Updated Serbian translation.
1070 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1073 * configure: Regenerated.
1075 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1077 * aarch64-asm-2.c: Regenerate.
1078 * aarch64-dis-2.c: Likewise.
1079 * aarch64-opc-2.c: Likewise.
1080 * aarch64-opc.c (aarch64_print_operand):
1081 Delete handling of AARCH64_OPND_CSRE_CSR.
1082 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1084 (_CSRE_INSN): Likewise.
1085 (aarch64_opcode_table): Delete csr.
1087 2021-01-11 Nick Clifton <nickc@redhat.com>
1089 * po/de.po: Updated German translation.
1090 * po/fr.po: Updated French translation.
1091 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1092 * po/sv.po: Updated Swedish translation.
1093 * po/uk.po: Updated Ukranian translation.
1095 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1097 * configure: Regenerated.
1099 2021-01-09 Nick Clifton <nickc@redhat.com>
1101 * configure: Regenerate.
1102 * po/opcodes.pot: Regenerate.
1104 2021-01-09 Nick Clifton <nickc@redhat.com>
1106 * 2.36 release branch crated.
1108 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1110 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1111 (DW, (XRC_MASK): Define.
1112 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1114 2021-01-09 Alan Modra <amodra@gmail.com>
1116 * configure: Regenerate.
1118 2021-01-08 Nick Clifton <nickc@redhat.com>
1120 * po/sv.po: Updated Swedish translation.
1122 2021-01-08 Nick Clifton <nickc@redhat.com>
1125 * aarch64-dis.c (determine_disassembling_preference): Move call to
1126 aarch64_match_operands_constraint outside of the assertion.
1127 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1128 Replace with a return of FALSE.
1131 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1132 core system register.
1134 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1136 * configure: Regenerate.
1138 2021-01-07 Nick Clifton <nickc@redhat.com>
1140 * po/fr.po: Updated French translation.
1142 2021-01-07 Fredrik Noring <noring@nocrew.org>
1144 * m68k-opc.c (chkl): Change minimum architecture requirement to
1147 2021-01-07 Philipp Tomsich <prt@gnu.org>
1149 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1151 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1152 Jim Wilson <jimw@sifive.com>
1153 Andrew Waterman <andrew@sifive.com>
1154 Maxim Blinov <maxim.blinov@embecosm.com>
1155 Kito Cheng <kito.cheng@sifive.com>
1156 Nelson Chu <nelson.chu@sifive.com>
1158 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1159 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1161 2021-01-01 Alan Modra <amodra@gmail.com>
1163 Update year range in copyright notice of all files.
1165 For older changes see ChangeLog-2020
1167 Copyright (C) 2021 Free Software Foundation, Inc.
1169 Copying and distribution of this file, with or without modification,
1170 are permitted in any medium without royalty provided the copyright
1171 notice and this notice are preserved.
1177 version-control: never