opcodes/ChangeLog

   1 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
   2
   3         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
   4         info->insn_info_valid.
   5
   6 2021-04-26  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-opc.tbl (lea): Add Optimize.
   9         * opcodes/i386-tbl.h: Re-generate.
  10
  11 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  12
  13         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
  14         of l32r fetch and display referenced literal value.
  15
  16 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  17
  18         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
  19         to 4 for literal disassembly.
  20
  21 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  22
  23         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
  24         for TLBI instruction.
  25
  26 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  27
  28         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
  29         DC instruction.
  30
  31 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  32
  33         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  34         "qualifier".
  35         (convert_mov_to_movewide): Add initializer for "value".
  36
  37 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  38
  39         * aarch64-opc.c: Add RME system registers.
  40
  41 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  42
  43         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  44         "addi d,CV,z" to "c.mv d,CV".
  45
  46 2021-04-12  Alan Modra  <amodra@gmail.com>
  47
  48         * configure.ac (--enable-checking): Add support.
  49         * config.in: Regenerate.
  50         * configure: Regenerate.
  51
  52 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
  53
  54         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
  55         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
  56
  57 2021-04-09  Alan Modra  <amodra@gmail.com>
  58
  59         * ppc-dis.c (struct dis_private): Add "special".
  60         (POWERPC_DIALECT): Delete.  Replace uses with..
  61         (private_data): ..this.  New inline function.
  62         (disassemble_init_powerpc): Init "special" names.
  63         (skip_optional_operands): Add is_pcrel arg, set when detecting R
  64         field of prefix instructions.
  65         (bsearch_reloc, print_got_plt): New functions.
  66         (print_insn_powerpc): For pcrel instructions, print target address
  67         and symbol if known, and decode plt and got loads too.
  68
  69 2021-04-08  Alan Modra  <amodra@gmail.com>
  70
  71         PR 27684
  72         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
  73
  74 2021-04-08  Alan Modra  <amodra@gmail.com>
  75
  76         PR 27676
  77         * ppc-opc.c (DCBT_EO): Move earlier.
  78         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
  79         (powerpc_operands): Add THCT and THDS entries.
  80         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
  81
  82 2021-04-06  Alan Modra  <amodra@gmail.com>
  83
  84         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
  85         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
  86         symbol_at_address_func.
  87
  88 2021-04-05  Alan Modra  <amodra@gmail.com>
  89
  90         * configure.ac: Don't check for limits.h, string.h, strings.h or
  91         stdlib.h.
  92         (AC_ISC_POSIX): Don't invoke.
  93         * sysdep.h: Include stdlib.h and string.h unconditionally.
  94         * i386-opc.h: Include limits.h unconditionally.
  95         * wasm32-dis.c: Likewise.
  96         * cgen-opc.c: Don't include alloca-conf.h.
  97         * config.in: Regenerate.
  98         * configure: Regenerate.
  99
 100 2021-04-01  Martin Liska  <mliska@suse.cz>
 101
 102         * arm-dis.c (strneq): Remove strneq and use startswith.
 103         * cr16-dis.c (print_insn_cr16): Likewise.
 104         * score-dis.c (streq): Likewise.
 105         (strneq): Likewise.
 106         * score7-dis.c (strneq): Likewise.
 107
 108 2021-04-01  Alan Modra  <amodra@gmail.com>
 109
 110         PR 27675
 111         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 112
 113 2021-03-31  Alan Modra  <amodra@gmail.com>
 114
 115         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 116         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 117         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 118         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 119         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 120         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 121         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 122         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 123         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 124         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 125         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 126         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 127         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 128         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 129         and TRUE with true throughout.
 130
 131 2021-03-31  Alan Modra  <amodra@gmail.com>
 132
 133         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 134         * aarch64-dis.h: Likewise.
 135         * aarch64-opc.c: Likewise.
 136         * avr-dis.c: Likewise.
 137         * csky-dis.c: Likewise.
 138         * nds32-asm.c: Likewise.
 139         * nds32-dis.c: Likewise.
 140         * nfp-dis.c: Likewise.
 141         * riscv-dis.c: Likewise.
 142         * s12z-dis.c: Likewise.
 143         * wasm32-dis.c: Likewise.
 144
 145 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 148         (i386_seg_prefixes): New.
 149         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 150         (i386_seg_prefixes): Declare.
 151
 152 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 155
 156 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 159         * i386-reg.tbl (st): Move down.
 160         (st(0)): Delete. Extend comment.
 161         * i386-tbl.h: Re-generate.
 162
 163 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 166         (cmpsd): Move next to cmps.
 167         (movsd): Move next to movs.
 168         (cmpxchg16b): Move to separate section.
 169         (fisttp, fisttpll): Likewise.
 170         (monitor, mwait): Likewise.
 171         * i386-tbl.h: Re-generate.
 172
 173 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 176         (vpsadbw): Add C.
 177         * i386-tbl.h: Re-generate.
 178
 179 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 182         pclmul, gfni): New templates. Use them wherever possible. Move
 183         SSE4.1 pextrw into respective section.
 184         * i386-tbl.h: Re-generate.
 185
 186 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 189         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 190         "length".
 191         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 192         Convert all of their uses to representation in opcode.
 193
 194 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 195
 196         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 197         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 198         value of None. Shrink operands to 3 bits.
 199
 200 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-gen.c (process_i386_opcode_modifier): New parameter
 203         "space".
 204         (output_i386_opcode): New local variable "space". Adjust
 205         process_i386_opcode_modifier() invocation.
 206         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 207         invocation.
 208         * i386-tbl.h: Re-generate.
 209
 210 2021-03-29  Alan Modra  <amodra@gmail.com>
 211
 212         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 213         (fp_qualifier_p, get_data_pattern): Likewise.
 214         (aarch64_get_operand_modifier_from_value): Likewise.
 215         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 216         (operand_variant_qualifier_p): Likewise.
 217         (qualifier_value_in_range_constraint_p): Likewise.
 218         (aarch64_get_qualifier_esize): Likewise.
 219         (aarch64_get_qualifier_nelem): Likewise.
 220         (aarch64_get_qualifier_standard_value): Likewise.
 221         (get_lower_bound, get_upper_bound): Likewise.
 222         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 223         (aarch64_print_operand): Likewise.
 224         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 225         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 226         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 227         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 228         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 229         (print_insn_tic6x): Likewise.
 230
 231 2021-03-29  Alan Modra  <amodra@gmail.com>
 232
 233         * arc-dis.c (extract_operand_value): Correct NULL cast.
 234         * frv-opc.h: Regenerate.
 235
 236 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 237
 238         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 239         MMX form.
 240         * i386-tbl.h: Re-generate.
 241
 242 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 243
 244         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 245         immediate in br.n instruction.
 246
 247 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-dis.c (XMGatherD, VexGatherD): New.
 250         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 251         (print_insn): Check masking for S/G insns.
 252         (OP_E_memory): New local variable check_gather. Extend mandatory
 253         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 254         Extend check for disallowed 16-bit addressing.
 255         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 256         if()s to switch(). Check register conflicts for (VEX-encoded)
 257         gathers. Drop no longer reachable cases.
 258         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 259         vgatherdp*.
 260
 261 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 262
 263         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 264         zeroing-masking without masking.
 265
 266 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 269         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 270         single-operand forms as deprecated.
 271         * i386-tbl.h: Re-generate.
 272
 273 2021-03-25  Alan Modra  <amodra@gmail.com>
 274
 275         PR 27647
 276         * ppc-opc.c (XLOCB_MASK): Delete.
 277         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 278         XLBH_MASK.
 279         (powerpc_opcodes): Accept a BH field on all extended forms of
 280         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 281
 282 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 283
 284         * i386-gen.c (output_i386_opcode): Drop processing of
 285         opcode_length. Calculate length from base_opcode. Adjust prefix
 286         encoding determination.
 287         (process_i386_opcodes): Drop output of fake opcode_length.
 288         * i386-opc.h (struct insn_template): Drop opcode_length field.
 289         * i386-opc.tbl: Drop opcode length field from all templates.
 290         * i386-tbl.h: Re-generate.
 291
 292 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 295         parameter "prefix". Drop local variable "regular_encoding".
 296         Record prefix setting / check for consistency.
 297         (output_i386_opcode): Parse opcode_length and base_opcode
 298         earlier. Derive prefix encoding. Drop no longer applicable
 299         consistency checking. Adjust process_i386_opcode_modifier()
 300         invocation.
 301         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 302         invocation.
 303         * i386-tbl.h: Re-generate.
 304
 305 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 308         check.
 309         * i386-opc.h (Prefix_*): Move #define-s.
 310         * i386-opc.tbl: Move pseudo prefix enumerator values to
 311         extension opcode field. Introduce pseudopfx template.
 312         * i386-tbl.h: Re-generate.
 313
 314 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 317         comment.
 318         * i386-tbl.h: Re-generate.
 319
 320 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-opc.h (struct insn_template): Move cpu_flags field past
 323         opcode_modifier one.
 324         * i386-tbl.h: Re-generate.
 325
 326 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 329         * i386-opc.h (OpcodeSpace): New enumerator.
 330         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 331         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 332         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 333         (struct i386_opcode_modifier): New field opcodespace. Shrink
 334         opcodeprefix field.
 335         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 336         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 337         OpcodePrefix uses.
 338         * i386-tbl.h: Re-generate.
 339
 340 2021-03-22  Martin Liska  <mliska@suse.cz>
 341
 342         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 343         * arc-dis.c (parse_option): Likewise.
 344         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 345         * cris-dis.c (print_with_operands): Likewise.
 346         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 347         * i386-dis.c (print_insn): Likewise.
 348         * ia64-gen.c (fetch_insn_class): Likewise.
 349         (parse_resource_users): Likewise.
 350         (in_iclass): Likewise.
 351         (lookup_specifier): Likewise.
 352         (insert_opcode_dependencies): Likewise.
 353         * mips-dis.c (parse_mips_ase_option): Likewise.
 354         (parse_mips_dis_option): Likewise.
 355         * s390-dis.c (disassemble_init_s390): Likewise.
 356         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 357
 358 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 359
 360         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 361
 362 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 363
 364         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 365         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 366
 367 2021-03-12  Alan Modra  <amodra@gmail.com>
 368
 369         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 370
 371 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-dis.c (OP_XMM): Re-order checks.
 374
 375 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 376
 377         * i386-dis.c (putop): Drop need_vex check when also checking
 378         vex.evex.
 379         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 380         checking vex.b.
 381
 382 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 385         checks. Move case label past broadcast check.
 386
 387 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 388
 389         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 390         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 391         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 392         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 393         EVEX_W_0F38C7_M_0_L_2): Delete.
 394         (REG_EVEX_0F38C7_M_0_L_2): New.
 395         (intel_operand_size): Handle VEX and EVEX the same for
 396         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 397         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 398         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 399         vex_vsib_q_w_d_mode uses.
 400         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 401         0F38A1, and 0F38A3 entries.
 402         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 403         entry.
 404         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 405         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 406         0F38A3 entries.
 407
 408 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 409
 410         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 411         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 412         MOD_VEX_0FXOP_09_12): Rename to ...
 413         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 414         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 415         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 416         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 417         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 418         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 419         (reg_table): Adjust comments.
 420         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 421         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 422         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 423         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 424         (vex_len_table): Adjust opcode 0A_12 entry.
 425         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 426         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 427         (rm_table): Move hreset entry.
 428
 429 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 430
 431         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 432         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 433         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 434         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 435         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 436         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 437         (get_valid_dis386): Also handle 512-bit vector length when
 438         vectoring into vex_len_table[].
 439         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 440         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 441         entries.
 442         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 443         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 444         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 445         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 446         entries.
 447
 448 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 449
 450         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 451         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 452         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 453         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 454         entries.
 455         * i386-dis-evex-len.h (evex_len_table): Likewise.
 456         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 457
 458 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 459
 460         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 461         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 462         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 463         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 464         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 465         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 466         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 467         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 468         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 469         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 470         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 471         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 472         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 473         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 474         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 475         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 476         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 477         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 478         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 479         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 480         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 481         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 482         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 483         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 484         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 485         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 486         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 487         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 488         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 489         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 490         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 491         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 492         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 493         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 494         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 495         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 496         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 497         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 498         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 499         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 500         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 501         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 502         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 503         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 504         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 505         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 506         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 507         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 508         EVEX_W_0F3A43_L_n): New.
 509         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 510         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 511         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 512         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 513         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 514         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 515         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 516         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 517         0F385B, 0F38C6, and 0F38C7 entries.
 518         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 519         0F38C6 and 0F38C7.
 520         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 521         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 522         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 523         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 524
 525 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 526
 527         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 528         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 529         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 530         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 531         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 532         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 533         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 534         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 535         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 536         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 537         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 538         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 539         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 540         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 541         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 542         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 543         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 544         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 545         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 546         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 547         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 548         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 549         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 550         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 551         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 552         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 553         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 554         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 555         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 556         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 557         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 558         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 559         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 560         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 561         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 562         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 563         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 564         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 565         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 566         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 567         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 568         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 569         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 570         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 571         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 572         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 573         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 574         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 575         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 576         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 577         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 578         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 579         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 580         VEX_W_0F99_P_2_LEN_0): Delete.
 581         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 582         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 583         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 584         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 585         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 586         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 587         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 588         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 589         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 590         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 591         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 592         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 593         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 594         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 595         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 596         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 597         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 598         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 599         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 600         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 601         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 602         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 603         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 604         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 605         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 606         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 607         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 608         (prefix_table): No longer link to vex_len_table[] for opcodes
 609         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 610         0F92, 0F93, 0F98, and 0F99.
 611         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 612         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 613         0F98, and 0F99.
 614         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 615         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 616         0F98, and 0F99.
 617         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 618         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 619         0F98, and 0F99.
 620         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 621         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 622         0F98, and 0F99.
 623
 624 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 625
 626         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 627         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 628         REG_VEX_0F73_M_0 respectively.
 629         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 630         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 631         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 632         MOD_VEX_0F73_REG_7): Delete.
 633         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 634         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 635         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 636         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 637         PREFIX_VEX_0F3AF0_L_0 respectively.
 638         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 639         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 640         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 641         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 642         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 643         VEX_LEN_0F38F7): New.
 644         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 645         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 646         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 647         0F38F3.
 648         (prefix_table): No longer link to vex_len_table[] for opcodes
 649         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 650         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 651         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 652         0F38F6, 0F38F7, and 0F3AF0.
 653         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 654         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 655         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 656         0F73.
 657
 658 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 659
 660         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 661         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 662         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 663         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 664         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 665         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 666         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 667         73.
 668         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 669         0F72, and 0F73.
 670         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 671         0F73.
 672
 673 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 674
 675         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 676         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 677         (reg_table): Don't link to mod_table[] where not needed. Add
 678         PREFIX_IGNORED to nop entries.
 679         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 680         (mod_table): Add nop entries next to prefetch ones. Drop
 681         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 682         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 683         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 684         PREFIX_OPCODE from endbr* entries.
 685         (get_valid_dis386): Also consider entry's name when zapping
 686         vindex.
 687         (print_insn): Handle PREFIX_IGNORED.
 688
 689 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 690
 691         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 692         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 693         element.
 694         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 695         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 696         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 697         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 698         (struct i386_opcode_modifier): Delete notrackprefixok,
 699         islockable, hleprefixok, and repprefixok fields. Add prefixok
 700         field.
 701         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 702         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 703         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 704         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 705         Replace HLEPrefixOk.
 706         * opcodes/i386-tbl.h: Re-generate.
 707
 708 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 709
 710         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 711         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 712         64-bit form.
 713         * opcodes/i386-tbl.h: Re-generate.
 714
 715 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 716
 717         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 718         for {} instead of {0}. Don't look for '0'.
 719         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 720         size specifiers.
 721
 722 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 723
 724         PR 27158
 725         * riscv-dis.c (print_insn_args): Updated encoding macros.
 726         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 727         (match_c_addi16sp): Updated encoding macros.
 728         (match_c_lui): Likewise.
 729         (match_c_lui_with_hint): Likewise.
 730         (match_c_addi4spn): Likewise.
 731         (match_c_slli): Likewise.
 732         (match_slli_as_c_slli): Likewise.
 733         (match_c_slli64): Likewise.
 734         (match_srxi_as_c_srxi): Likewise.
 735         (riscv_insn_types): Added .insn css/cl/cs.
 736
 737 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 738
 739         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 740         (default_priv_spec): Updated type to riscv_spec_class.
 741         (parse_riscv_dis_option): Updated.
 742         * riscv-opc.c: Moved stuff and make the file tidy.
 743
 744 2021-02-17  Alan Modra  <amodra@gmail.com>
 745
 746         * wasm32-dis.c: Include limits.h.
 747         (CHAR_BIT): Provide backup define.
 748         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 749         Correct signed overflow checking.
 750
 751 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 754         * i386-tbl.h: Re-generate.
 755
 756 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 759         Oword.
 760         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 761
 762 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 763
 764         * s390-mkopc.c (main): Accept arch14 as cpu string.
 765         * s390-opc.txt: Add new arch14 instructions.
 766
 767 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 768
 769         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 770         favour of LIBINTL.
 771         * configure: Regenerated.
 772
 773 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 774
 775         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 776         * tic54x-opc.c (regs): Rename to ...
 777         (tic54x_regs): ... this.
 778         (mmregs): Rename to ...
 779         (tic54x_mmregs): ... this.
 780         (condition_codes): Rename to ...
 781         (tic54x_condition_codes): ... this.
 782         (cc2_codes): Rename to ...
 783         (tic54x_cc2_codes): ... this.
 784         (cc3_codes): Rename to ...
 785         (tic54x_cc3_codes): ... this.
 786         (status_bits): Rename to ...
 787         (tic54x_status_bits): ... this.
 788         (misc_symbols): Rename to ...
 789         (tic54x_misc_symbols): ... this.
 790
 791 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 792
 793         * riscv-opc.c (MASK_RVB_IMM): Removed.
 794         (riscv_opcodes): Removed zb* instructions.
 795         (riscv_ext_version_table): Removed versions for zb*.
 796
 797 2021-01-26  Alan Modra  <amodra@gmail.com>
 798
 799         * i386-gen.c (parse_template): Ensure entire template_instance
 800         is initialised.
 801
 802 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 803
 804         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 805         (riscv_fpr_names_abi): Likewise.
 806         (riscv_opcodes): Likewise.
 807         (riscv_insn_types): Likewise.
 808
 809 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 810
 811         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 812
 813 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 814
 815         * riscv-dis.c: Comments tidy and improvement.
 816         * riscv-opc.c: Likewise.
 817
 818 2021-01-13  Alan Modra  <amodra@gmail.com>
 819
 820         * Makefile.in: Regenerate.
 821
 822 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 823
 824         PR binutils/26792
 825         * configure.ac: Use GNU_MAKE_JOBSERVER.
 826         * aclocal.m4: Regenerated.
 827         * configure: Likewise.
 828
 829 2021-01-12  Nick Clifton  <nickc@redhat.com>
 830
 831         * po/sr.po: Updated Serbian translation.
 832
 833 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 834
 835         PR ld/27173
 836         * configure: Regenerated.
 837
 838 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 839
 840         * aarch64-asm-2.c: Regenerate.
 841         * aarch64-dis-2.c: Likewise.
 842         * aarch64-opc-2.c: Likewise.
 843         * aarch64-opc.c (aarch64_print_operand):
 844         Delete handling of AARCH64_OPND_CSRE_CSR.
 845         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 846         (CSRE): Likewise.
 847         (_CSRE_INSN): Likewise.
 848         (aarch64_opcode_table): Delete csr.
 849
 850 2021-01-11  Nick Clifton  <nickc@redhat.com>
 851
 852         * po/de.po: Updated German translation.
 853         * po/fr.po: Updated French translation.
 854         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 855         * po/sv.po: Updated Swedish translation.
 856         * po/uk.po: Updated Ukranian translation.
 857
 858 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 859
 860         * configure: Regenerated.
 861
 862 2021-01-09  Nick Clifton  <nickc@redhat.com>
 863
 864         * configure: Regenerate.
 865         * po/opcodes.pot: Regenerate.
 866
 867 2021-01-09  Nick Clifton  <nickc@redhat.com>
 868
 869         * 2.36 release branch crated.
 870
 871 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 872
 873         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 874         (DW, (XRC_MASK): Define.
 875         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 876
 877 2021-01-09  Alan Modra  <amodra@gmail.com>
 878
 879         * configure: Regenerate.
 880
 881 2021-01-08  Nick Clifton  <nickc@redhat.com>
 882
 883         * po/sv.po: Updated Swedish translation.
 884
 885 2021-01-08  Nick Clifton  <nickc@redhat.com>
 886
 887         PR 27129
 888         * aarch64-dis.c (determine_disassembling_preference): Move call to
 889         aarch64_match_operands_constraint outside of the assertion.
 890         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 891         Replace with a return of FALSE.
 892
 893         PR 27139
 894         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 895         core system register.
 896
 897 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 898
 899         * configure: Regenerate.
 900
 901 2021-01-07  Nick Clifton  <nickc@redhat.com>
 902
 903         * po/fr.po: Updated French translation.
 904
 905 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 906
 907         * m68k-opc.c (chkl): Change minimum architecture requirement to
 908         m68020.
 909
 910 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 911
 912         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 913
 914 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 915             Jim Wilson  <jimw@sifive.com>
 916             Andrew Waterman  <andrew@sifive.com>
 917             Maxim Blinov  <maxim.blinov@embecosm.com>
 918             Kito Cheng  <kito.cheng@sifive.com>
 919             Nelson Chu  <nelson.chu@sifive.com>
 920
 921         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 922         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 923
 924 2021-01-01  Alan Modra  <amodra@gmail.com>
 925
 926         Update year range in copyright notice of all files.
 927
 928 For older changes see ChangeLog-2020
 929 \f
 930 Copyright (C) 2021 Free Software Foundation, Inc.
 931
 932 Copying and distribution of this file, with or without modification,
 933 are permitted in any medium without royalty provided the copyright
 934 notice and this notice are preserved.
 935
 936 Local Variables:
 937 mode: change-log
 938 left-margin: 8
 939 fill-column: 74
 940 version-control: never
 941 End: