opcodes/ChangeLog

   1 2021-03-10  Jan Beulich  <jbeulich@suse.com>
   2
   3         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
   4         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
   5         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
   6         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
   7         entries.
   8         * i386-dis-evex-len.h (evex_len_table): Likewise.
   9         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
  10
  11 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  12
  13         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
  14         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
  15         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
  16         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
  17         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
  18         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
  19         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
  20         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
  21         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
  22         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
  23         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
  24         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
  25         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
  26         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
  27         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
  28         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
  29         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
  30         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
  31         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
  32         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
  33         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
  34         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
  35         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
  36         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
  37         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
  38         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
  39         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
  40         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
  41         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
  42         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
  43         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
  44         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
  45         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
  46         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
  47         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
  48         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
  49         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
  50         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
  51         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
  52         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
  53         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
  54         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
  55         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
  56         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
  57         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
  58         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
  59         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
  60         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
  61         EVEX_W_0F3A43_L_n): New.
  62         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
  63         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
  64         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
  65         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
  66         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
  67         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
  68         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
  69         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
  70         0F385B, 0F38C6, and 0F38C7 entries.
  71         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
  72         0F38C6 and 0F38C7.
  73         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
  74         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
  75         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
  76         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
  77
  78 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  79
  80         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
  81         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
  82         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
  83         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
  84         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
  85         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
  86         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
  87         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
  88         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
  89         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
  90         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
  91         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
  92         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
  93         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
  94         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
  95         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
  96         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
  97         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
  98         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
  99         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 100         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 101         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 102         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 103         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 104         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 105         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 106         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 107         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 108         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 109         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 110         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 111         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 112         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 113         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 114         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 115         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 116         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 117         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 118         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 119         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 120         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 121         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 122         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 123         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 124         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 125         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 126         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 127         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 128         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 129         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 130         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 131         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 132         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 133         VEX_W_0F99_P_2_LEN_0): Delete.
 134         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 135         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 136         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 137         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 138         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 139         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 140         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 141         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 142         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 143         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 144         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 145         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 146         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 147         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 148         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 149         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 150         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 151         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 152         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 153         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 154         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 155         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 156         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 157         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 158         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 159         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 160         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 161         (prefix_table): No longer link to vex_len_table[] for opcodes
 162         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 163         0F92, 0F93, 0F98, and 0F99.
 164         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 165         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 166         0F98, and 0F99.
 167         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 168         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 169         0F98, and 0F99.
 170         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 171         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 172         0F98, and 0F99.
 173         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 174         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 175         0F98, and 0F99.
 176
 177 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 178
 179         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 180         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 181         REG_VEX_0F73_M_0 respectively.
 182         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 183         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 184         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 185         MOD_VEX_0F73_REG_7): Delete.
 186         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 187         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 188         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 189         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 190         PREFIX_VEX_0F3AF0_L_0 respectively.
 191         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 192         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 193         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 194         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 195         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 196         VEX_LEN_0F38F7): New.
 197         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 198         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 199         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 200         0F38F3.
 201         (prefix_table): No longer link to vex_len_table[] for opcodes
 202         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 203         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 204         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 205         0F38F6, 0F38F7, and 0F3AF0.
 206         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 207         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 208         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 209         0F73.
 210
 211 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 212
 213         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 214         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 215         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 216         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 217         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 218         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 219         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 220         73.
 221         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 222         0F72, and 0F73.
 223         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 224         0F73.
 225
 226 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 227
 228         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 229         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 230         (reg_table): Don't link to mod_table[] where not needed. Add
 231         PREFIX_IGNORED to nop entries.
 232         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 233         (mod_table): Add nop entries next to prefetch ones. Drop
 234         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 235         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 236         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 237         PREFIX_OPCODE from endbr* entries.
 238         (get_valid_dis386): Also consider entry's name when zapping
 239         vindex.
 240         (print_insn): Handle PREFIX_IGNORED.
 241
 242 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 243
 244         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 245         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 246         element.
 247         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 248         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 249         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 250         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 251         (struct i386_opcode_modifier): Delete notrackprefixok,
 252         islockable, hleprefixok, and repprefixok fields. Add prefixok
 253         field.
 254         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 255         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 256         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 257         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 258         Replace HLEPrefixOk.
 259         * opcodes/i386-tbl.h: Re-generate.
 260
 261 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 262
 263         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 264         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 265         64-bit form.
 266         * opcodes/i386-tbl.h: Re-generate.
 267
 268 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 269
 270         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 271         for {} instead of {0}. Don't look for '0'.
 272         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 273         size specifiers.
 274
 275 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 276
 277         PR 27158
 278         * riscv-dis.c (print_insn_args): Updated encoding macros.
 279         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 280         (match_c_addi16sp): Updated encoding macros.
 281         (match_c_lui): Likewise.
 282         (match_c_lui_with_hint): Likewise.
 283         (match_c_addi4spn): Likewise.
 284         (match_c_slli): Likewise.
 285         (match_slli_as_c_slli): Likewise.
 286         (match_c_slli64): Likewise.
 287         (match_srxi_as_c_srxi): Likewise.
 288         (riscv_insn_types): Added .insn css/cl/cs.
 289
 290 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 291
 292         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 293         (default_priv_spec): Updated type to riscv_spec_class.
 294         (parse_riscv_dis_option): Updated.
 295         * riscv-opc.c: Moved stuff and make the file tidy.
 296
 297 2021-02-17  Alan Modra  <amodra@gmail.com>
 298
 299         * wasm32-dis.c: Include limits.h.
 300         (CHAR_BIT): Provide backup define.
 301         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 302         Correct signed overflow checking.
 303
 304 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 305
 306         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 307         * i386-tbl.h: Re-generate.
 308
 309 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 312         Oword.
 313         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 314
 315 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 316
 317         * s390-mkopc.c (main): Accept arch14 as cpu string.
 318         * s390-opc.txt: Add new arch14 instructions.
 319
 320 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 321
 322         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 323         favour of LIBINTL.
 324         * configure: Regenerated.
 325
 326 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 327
 328         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 329         * tic54x-opc.c (regs): Rename to ...
 330         (tic54x_regs): ... this.
 331         (mmregs): Rename to ...
 332         (tic54x_mmregs): ... this.
 333         (condition_codes): Rename to ...
 334         (tic54x_condition_codes): ... this.
 335         (cc2_codes): Rename to ...
 336         (tic54x_cc2_codes): ... this.
 337         (cc3_codes): Rename to ...
 338         (tic54x_cc3_codes): ... this.
 339         (status_bits): Rename to ...
 340         (tic54x_status_bits): ... this.
 341         (misc_symbols): Rename to ...
 342         (tic54x_misc_symbols): ... this.
 343
 344 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 345
 346         * riscv-opc.c (MASK_RVB_IMM): Removed.
 347         (riscv_opcodes): Removed zb* instructions.
 348         (riscv_ext_version_table): Removed versions for zb*.
 349
 350 2021-01-26  Alan Modra  <amodra@gmail.com>
 351
 352         * i386-gen.c (parse_template): Ensure entire template_instance
 353         is initialised.
 354
 355 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 356
 357         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 358         (riscv_fpr_names_abi): Likewise.
 359         (riscv_opcodes): Likewise.
 360         (riscv_insn_types): Likewise.
 361
 362 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 363
 364         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 365
 366 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 367
 368         * riscv-dis.c: Comments tidy and improvement.
 369         * riscv-opc.c: Likewise.
 370
 371 2021-01-13  Alan Modra  <amodra@gmail.com>
 372
 373         * Makefile.in: Regenerate.
 374
 375 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 376
 377         PR binutils/26792
 378         * configure.ac: Use GNU_MAKE_JOBSERVER.
 379         * aclocal.m4: Regenerated.
 380         * configure: Likewise.
 381
 382 2021-01-12  Nick Clifton  <nickc@redhat.com>
 383
 384         * po/sr.po: Updated Serbian translation.
 385
 386 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 387
 388         PR ld/27173
 389         * configure: Regenerated.
 390
 391 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 392
 393         * aarch64-asm-2.c: Regenerate.
 394         * aarch64-dis-2.c: Likewise.
 395         * aarch64-opc-2.c: Likewise.
 396         * aarch64-opc.c (aarch64_print_operand):
 397         Delete handling of AARCH64_OPND_CSRE_CSR.
 398         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 399         (CSRE): Likewise.
 400         (_CSRE_INSN): Likewise.
 401         (aarch64_opcode_table): Delete csr.
 402
 403 2021-01-11  Nick Clifton  <nickc@redhat.com>
 404
 405         * po/de.po: Updated German translation.
 406         * po/fr.po: Updated French translation.
 407         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 408         * po/sv.po: Updated Swedish translation.
 409         * po/uk.po: Updated Ukranian translation.
 410
 411 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 412
 413         * configure: Regenerated.
 414
 415 2021-01-09  Nick Clifton  <nickc@redhat.com>
 416
 417         * configure: Regenerate.
 418         * po/opcodes.pot: Regenerate.
 419
 420 2021-01-09  Nick Clifton  <nickc@redhat.com>
 421
 422         * 2.36 release branch crated.
 423
 424 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 425
 426         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 427         (DW, (XRC_MASK): Define.
 428         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 429
 430 2021-01-09  Alan Modra  <amodra@gmail.com>
 431
 432         * configure: Regenerate.
 433
 434 2021-01-08  Nick Clifton  <nickc@redhat.com>
 435
 436         * po/sv.po: Updated Swedish translation.
 437
 438 2021-01-08  Nick Clifton  <nickc@redhat.com>
 439
 440         PR 27129
 441         * aarch64-dis.c (determine_disassembling_preference): Move call to
 442         aarch64_match_operands_constraint outside of the assertion.
 443         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 444         Replace with a return of FALSE.
 445
 446         PR 27139
 447         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 448         core system register.
 449
 450 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 451
 452         * configure: Regenerate.
 453
 454 2021-01-07  Nick Clifton  <nickc@redhat.com>
 455
 456         * po/fr.po: Updated French translation.
 457
 458 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 459
 460         * m68k-opc.c (chkl): Change minimum architecture requirement to
 461         m68020.
 462
 463 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 464
 465         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 466
 467 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 468             Jim Wilson  <jimw@sifive.com>
 469             Andrew Waterman  <andrew@sifive.com>
 470             Maxim Blinov  <maxim.blinov@embecosm.com>
 471             Kito Cheng  <kito.cheng@sifive.com>
 472             Nelson Chu  <nelson.chu@sifive.com>
 473
 474         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 475         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 476
 477 2021-01-01  Alan Modra  <amodra@gmail.com>
 478
 479         Update year range in copyright notice of all files.
 480
 481 For older changes see ChangeLog-2020
 482 \f
 483 Copyright (C) 2021 Free Software Foundation, Inc.
 484
 485 Copying and distribution of this file, with or without modification,
 486 are permitted in any medium without royalty provided the copyright
 487 notice and this notice are preserved.
 488
 489 Local Variables:
 490 mode: change-log
 491 left-margin: 8
 492 fill-column: 74
 493 version-control: never
 494 End: