opcodes/ChangeLog

   1 2021-03-24  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
   4         check.
   5         * i386-opc.h (Prefix_*): Move #define-s.
   6         * i386-opc.tbl: Move pseudo prefix enumerator values to
   7         extension opcode field. Introduce pseudopfx template.
   8         * i386-tbl.h: Re-generate.
   9
  10 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  11
  12         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
  13         comment.
  14         * i386-tbl.h: Re-generate.
  15
  16 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.h (struct insn_template): Move cpu_flags field past
  19         opcode_modifier one.
  20         * i386-tbl.h: Re-generate.
  21
  22 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
  25         * i386-opc.h (OpcodeSpace): New enumerator.
  26         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
  27         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
  28         SPACE_XOP09, SPACE_XOP0A): ... respectively.
  29         (struct i386_opcode_modifier): New field opcodespace. Shrink
  30         opcodeprefix field.
  31         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
  32         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
  33         OpcodePrefix uses.
  34         * i386-tbl.h: Re-generate.
  35
  36 2021-03-22  Martin Liska  <mliska@suse.cz>
  37
  38         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
  39         * arc-dis.c (parse_option): Likewise.
  40         * arm-dis.c (parse_arm_disassembler_options): Likewise.
  41         * cris-dis.c (print_with_operands): Likewise.
  42         * h8300-dis.c (bfd_h8_disassemble): Likewise.
  43         * i386-dis.c (print_insn): Likewise.
  44         * ia64-gen.c (fetch_insn_class): Likewise.
  45         (parse_resource_users): Likewise.
  46         (in_iclass): Likewise.
  47         (lookup_specifier): Likewise.
  48         (insert_opcode_dependencies): Likewise.
  49         * mips-dis.c (parse_mips_ase_option): Likewise.
  50         (parse_mips_dis_option): Likewise.
  51         * s390-dis.c (disassemble_init_s390): Likewise.
  52         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
  53
  54 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  55
  56         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
  57
  58 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  59
  60         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
  61         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
  62
  63 2021-03-12  Alan Modra  <amodra@gmail.com>
  64
  65         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
  66
  67 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-dis.c (OP_XMM): Re-order checks.
  70
  71 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-dis.c (putop): Drop need_vex check when also checking
  74         vex.evex.
  75         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
  76         checking vex.b.
  77
  78 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
  81         checks. Move case label past broadcast check.
  82
  83 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  84
  85         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
  86         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
  87         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
  88         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
  89         EVEX_W_0F38C7_M_0_L_2): Delete.
  90         (REG_EVEX_0F38C7_M_0_L_2): New.
  91         (intel_operand_size): Handle VEX and EVEX the same for
  92         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
  93         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
  94         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
  95         vex_vsib_q_w_d_mode uses.
  96         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
  97         0F38A1, and 0F38A3 entries.
  98         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
  99         entry.
 100         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 101         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 102         0F38A3 entries.
 103
 104 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 105
 106         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 107         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 108         MOD_VEX_0FXOP_09_12): Rename to ...
 109         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 110         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 111         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 112         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 113         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 114         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 115         (reg_table): Adjust comments.
 116         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 117         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 118         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 119         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 120         (vex_len_table): Adjust opcode 0A_12 entry.
 121         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 122         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 123         (rm_table): Move hreset entry.
 124
 125 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 126
 127         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 128         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 129         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 130         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 131         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 132         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 133         (get_valid_dis386): Also handle 512-bit vector length when
 134         vectoring into vex_len_table[].
 135         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 136         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 137         entries.
 138         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 139         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 140         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 141         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 142         entries.
 143
 144 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 145
 146         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 147         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 148         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 149         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 150         entries.
 151         * i386-dis-evex-len.h (evex_len_table): Likewise.
 152         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 153
 154 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 155
 156         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 157         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 158         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 159         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 160         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 161         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 162         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 163         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 164         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 165         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 166         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 167         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 168         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 169         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 170         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 171         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 172         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 173         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 174         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 175         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 176         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 177         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 178         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 179         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 180         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 181         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 182         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 183         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 184         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 185         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 186         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 187         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 188         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 189         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 190         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 191         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 192         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 193         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 194         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 195         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 196         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 197         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 198         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 199         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 200         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 201         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 202         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 203         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 204         EVEX_W_0F3A43_L_n): New.
 205         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 206         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 207         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 208         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 209         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 210         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 211         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 212         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 213         0F385B, 0F38C6, and 0F38C7 entries.
 214         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 215         0F38C6 and 0F38C7.
 216         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 217         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 218         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 219         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 220
 221 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 222
 223         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 224         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 225         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 226         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 227         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 228         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 229         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 230         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 231         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 232         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 233         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 234         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 235         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 236         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 237         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 238         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 239         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 240         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 241         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 242         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 243         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 244         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 245         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 246         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 247         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 248         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 249         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 250         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 251         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 252         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 253         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 254         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 255         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 256         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 257         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 258         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 259         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 260         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 261         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 262         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 263         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 264         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 265         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 266         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 267         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 268         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 269         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 270         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 271         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 272         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 273         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 274         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 275         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 276         VEX_W_0F99_P_2_LEN_0): Delete.
 277         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 278         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 279         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 280         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 281         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 282         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 283         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 284         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 285         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 286         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 287         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 288         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 289         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 290         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 291         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 292         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 293         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 294         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 295         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 296         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 297         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 298         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 299         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 300         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 301         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 302         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 303         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 304         (prefix_table): No longer link to vex_len_table[] for opcodes
 305         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 306         0F92, 0F93, 0F98, and 0F99.
 307         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 308         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 309         0F98, and 0F99.
 310         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 311         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 312         0F98, and 0F99.
 313         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 314         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 315         0F98, and 0F99.
 316         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 317         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 318         0F98, and 0F99.
 319
 320 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 321
 322         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 323         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 324         REG_VEX_0F73_M_0 respectively.
 325         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 326         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 327         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 328         MOD_VEX_0F73_REG_7): Delete.
 329         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 330         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 331         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 332         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 333         PREFIX_VEX_0F3AF0_L_0 respectively.
 334         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 335         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 336         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 337         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 338         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 339         VEX_LEN_0F38F7): New.
 340         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 341         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 342         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 343         0F38F3.
 344         (prefix_table): No longer link to vex_len_table[] for opcodes
 345         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 346         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 347         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 348         0F38F6, 0F38F7, and 0F3AF0.
 349         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 350         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 351         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 352         0F73.
 353
 354 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 355
 356         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 357         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 358         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 359         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 360         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 361         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 362         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 363         73.
 364         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 365         0F72, and 0F73.
 366         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 367         0F73.
 368
 369 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 370
 371         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 372         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 373         (reg_table): Don't link to mod_table[] where not needed. Add
 374         PREFIX_IGNORED to nop entries.
 375         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 376         (mod_table): Add nop entries next to prefetch ones. Drop
 377         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 378         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 379         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 380         PREFIX_OPCODE from endbr* entries.
 381         (get_valid_dis386): Also consider entry's name when zapping
 382         vindex.
 383         (print_insn): Handle PREFIX_IGNORED.
 384
 385 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 386
 387         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 388         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 389         element.
 390         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 391         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 392         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 393         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 394         (struct i386_opcode_modifier): Delete notrackprefixok,
 395         islockable, hleprefixok, and repprefixok fields. Add prefixok
 396         field.
 397         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 398         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 399         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 400         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 401         Replace HLEPrefixOk.
 402         * opcodes/i386-tbl.h: Re-generate.
 403
 404 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 405
 406         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 407         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 408         64-bit form.
 409         * opcodes/i386-tbl.h: Re-generate.
 410
 411 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 412
 413         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 414         for {} instead of {0}. Don't look for '0'.
 415         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 416         size specifiers.
 417
 418 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 419
 420         PR 27158
 421         * riscv-dis.c (print_insn_args): Updated encoding macros.
 422         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 423         (match_c_addi16sp): Updated encoding macros.
 424         (match_c_lui): Likewise.
 425         (match_c_lui_with_hint): Likewise.
 426         (match_c_addi4spn): Likewise.
 427         (match_c_slli): Likewise.
 428         (match_slli_as_c_slli): Likewise.
 429         (match_c_slli64): Likewise.
 430         (match_srxi_as_c_srxi): Likewise.
 431         (riscv_insn_types): Added .insn css/cl/cs.
 432
 433 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 434
 435         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 436         (default_priv_spec): Updated type to riscv_spec_class.
 437         (parse_riscv_dis_option): Updated.
 438         * riscv-opc.c: Moved stuff and make the file tidy.
 439
 440 2021-02-17  Alan Modra  <amodra@gmail.com>
 441
 442         * wasm32-dis.c: Include limits.h.
 443         (CHAR_BIT): Provide backup define.
 444         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 445         Correct signed overflow checking.
 446
 447 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 450         * i386-tbl.h: Re-generate.
 451
 452 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 455         Oword.
 456         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 457
 458 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 459
 460         * s390-mkopc.c (main): Accept arch14 as cpu string.
 461         * s390-opc.txt: Add new arch14 instructions.
 462
 463 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 464
 465         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 466         favour of LIBINTL.
 467         * configure: Regenerated.
 468
 469 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 470
 471         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 472         * tic54x-opc.c (regs): Rename to ...
 473         (tic54x_regs): ... this.
 474         (mmregs): Rename to ...
 475         (tic54x_mmregs): ... this.
 476         (condition_codes): Rename to ...
 477         (tic54x_condition_codes): ... this.
 478         (cc2_codes): Rename to ...
 479         (tic54x_cc2_codes): ... this.
 480         (cc3_codes): Rename to ...
 481         (tic54x_cc3_codes): ... this.
 482         (status_bits): Rename to ...
 483         (tic54x_status_bits): ... this.
 484         (misc_symbols): Rename to ...
 485         (tic54x_misc_symbols): ... this.
 486
 487 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 488
 489         * riscv-opc.c (MASK_RVB_IMM): Removed.
 490         (riscv_opcodes): Removed zb* instructions.
 491         (riscv_ext_version_table): Removed versions for zb*.
 492
 493 2021-01-26  Alan Modra  <amodra@gmail.com>
 494
 495         * i386-gen.c (parse_template): Ensure entire template_instance
 496         is initialised.
 497
 498 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 499
 500         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 501         (riscv_fpr_names_abi): Likewise.
 502         (riscv_opcodes): Likewise.
 503         (riscv_insn_types): Likewise.
 504
 505 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 506
 507         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 508
 509 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 510
 511         * riscv-dis.c: Comments tidy and improvement.
 512         * riscv-opc.c: Likewise.
 513
 514 2021-01-13  Alan Modra  <amodra@gmail.com>
 515
 516         * Makefile.in: Regenerate.
 517
 518 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 519
 520         PR binutils/26792
 521         * configure.ac: Use GNU_MAKE_JOBSERVER.
 522         * aclocal.m4: Regenerated.
 523         * configure: Likewise.
 524
 525 2021-01-12  Nick Clifton  <nickc@redhat.com>
 526
 527         * po/sr.po: Updated Serbian translation.
 528
 529 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 530
 531         PR ld/27173
 532         * configure: Regenerated.
 533
 534 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 535
 536         * aarch64-asm-2.c: Regenerate.
 537         * aarch64-dis-2.c: Likewise.
 538         * aarch64-opc-2.c: Likewise.
 539         * aarch64-opc.c (aarch64_print_operand):
 540         Delete handling of AARCH64_OPND_CSRE_CSR.
 541         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 542         (CSRE): Likewise.
 543         (_CSRE_INSN): Likewise.
 544         (aarch64_opcode_table): Delete csr.
 545
 546 2021-01-11  Nick Clifton  <nickc@redhat.com>
 547
 548         * po/de.po: Updated German translation.
 549         * po/fr.po: Updated French translation.
 550         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 551         * po/sv.po: Updated Swedish translation.
 552         * po/uk.po: Updated Ukranian translation.
 553
 554 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 555
 556         * configure: Regenerated.
 557
 558 2021-01-09  Nick Clifton  <nickc@redhat.com>
 559
 560         * configure: Regenerate.
 561         * po/opcodes.pot: Regenerate.
 562
 563 2021-01-09  Nick Clifton  <nickc@redhat.com>
 564
 565         * 2.36 release branch crated.
 566
 567 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 568
 569         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 570         (DW, (XRC_MASK): Define.
 571         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 572
 573 2021-01-09  Alan Modra  <amodra@gmail.com>
 574
 575         * configure: Regenerate.
 576
 577 2021-01-08  Nick Clifton  <nickc@redhat.com>
 578
 579         * po/sv.po: Updated Swedish translation.
 580
 581 2021-01-08  Nick Clifton  <nickc@redhat.com>
 582
 583         PR 27129
 584         * aarch64-dis.c (determine_disassembling_preference): Move call to
 585         aarch64_match_operands_constraint outside of the assertion.
 586         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 587         Replace with a return of FALSE.
 588
 589         PR 27139
 590         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 591         core system register.
 592
 593 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 594
 595         * configure: Regenerate.
 596
 597 2021-01-07  Nick Clifton  <nickc@redhat.com>
 598
 599         * po/fr.po: Updated French translation.
 600
 601 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 602
 603         * m68k-opc.c (chkl): Change minimum architecture requirement to
 604         m68020.
 605
 606 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 607
 608         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 609
 610 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 611             Jim Wilson  <jimw@sifive.com>
 612             Andrew Waterman  <andrew@sifive.com>
 613             Maxim Blinov  <maxim.blinov@embecosm.com>
 614             Kito Cheng  <kito.cheng@sifive.com>
 615             Nelson Chu  <nelson.chu@sifive.com>
 616
 617         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 618         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 619
 620 2021-01-01  Alan Modra  <amodra@gmail.com>
 621
 622         Update year range in copyright notice of all files.
 623
 624 For older changes see ChangeLog-2020
 625 \f
 626 Copyright (C) 2021 Free Software Foundation, Inc.
 627
 628 Copying and distribution of this file, with or without modification,
 629 are permitted in any medium without royalty provided the copyright
 630 notice and this notice are preserved.
 631
 632 Local Variables:
 633 mode: change-log
 634 left-margin: 8
 635 fill-column: 74
 636 version-control: never
 637 End: