1 2020-10-26 Lili Cui <lili.cui@intel.com>
3 * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
5 2020-10-22 H.J. Lu <hongjiu.lu@intel.com>
7 * po/es.po: Remove the duplicated entry.
9 2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com>
11 * po/es.po: Fix printf format.
13 2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
15 * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
16 * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
17 CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
19 (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
20 * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
21 * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
23 * i386-init.h: Re-generated.
24 * i386-tbl.h: Re-generated.
26 2020-10-16 Lili Cui <lili.cui@intel.com>
28 * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
29 and move it from cpu_flags to opcode_modifiers.
30 Use VexW0 and VexVVVV in the AVX-VNNI instructions.
31 * i386-gen.c: Likewise.
32 * i386-opc.h: Likewise.
33 * i386-opc.h: Likewise.
34 * i386-init.h: Regenerated.
35 * i386-tbl.h: Likewise.
37 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
38 Lili Cui <lili.cui@intel.com>
40 * i386-dis.c (PREFIX_VEX_0F3850): New.
41 (PREFIX_VEX_0F3851): Likewise.
42 (PREFIX_VEX_0F3852): Likewise.
43 (PREFIX_VEX_0F3853): Likewise.
44 (VEX_W_0F3850_P_2): Likewise.
45 (VEX_W_0F3851_P_2): Likewise.
46 (VEX_W_0F3852_P_2): Likewise.
47 (VEX_W_0F3853_P_2): Likewise.
48 (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
49 PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
50 (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
51 VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
52 (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
53 * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
54 CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
55 CPU_ANY_AVX_VNNI_FLAGS.
56 (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
57 * i386-opc.h (CpuAVX_VNNI): New.
58 (CpuVEX_PREFIX): Likewise.
59 (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
60 * i386-opc.tbl: Add Intel AVX VNNI instructions.
61 * i386-init.h: Regenerated.
62 * i386-tbl.h: Likewise.
64 2020-10-14 Lili Cui <lili.cui@intel.com>
65 H.J. Lu <hongjiu.lu@intel.com>
67 * i386-dis.c (PREFIX_0F3A0F): New.
68 (MOD_0F3A0F_PREFIX_1): Likewise.
69 (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
70 (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
71 (prefix_table): Add PREFIX_0F3A0F.
72 (mod_table): Add MOD_0F3A0F_PREFIX_1.
73 (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
74 (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
75 * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
77 (cpu_flags): Add CpuHRESET.
78 (output_i386_opcode): Allow 4 byte base_opcode.
79 * i386-opc.h (enum): Add CpuHRESET.
80 (i386_cpu_flags): Add cpuhreset.
81 * i386-opc.tbl: Add Intel HRESET instruction.
82 * i386-init.h: Regenerate.
83 * i386-tbl.h: Likewise.
85 2020-10-14 Lili Cui <lili.cui@intel.com>
87 * i386-dis.c (enum): Add
88 PREFIX_MOD_3_0F01_REG_5_RM_4,
89 PREFIX_MOD_3_0F01_REG_5_RM_5,
90 PREFIX_MOD_3_0F01_REG_5_RM_6,
91 PREFIX_MOD_3_0F01_REG_5_RM_7,
92 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
93 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
94 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
95 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
96 X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
97 (prefix_table): New instructions (see prefixes above).
99 * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
101 (cpu_flags): Add CpuUINTR.
102 * i386-opc.h (enum): Add CpuUINTR.
103 (i386_cpu_flags): Add cpuuintr.
104 * i386-opc.tbl: Add UINTR insns.
105 * i386-init.h: Regenerate.
106 * i386-tbl.h: Likewise.
108 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
110 * i386-gen.c (process_i386_opcode_modifier): Return 1 for
111 non-VEX/EVEX/prefix encoding.
112 (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
114 * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
115 base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
116 * i386-tbl.h: Regenerated.
118 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
120 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
122 * i386-opc.h (VexOpcode): Renamed to ...
123 (OpcodePrefix): This.
125 (PREFIX_0X66): Likewise.
126 (PREFIX_0XF2): Likewise.
127 (PREFIX_0XF3): Likewise.
128 * i386-opc.tbl (Prefix_0X66): New.
129 (Prefix_0XF2): Likewise.
130 (Prefix_0XF3): Likewise.
131 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
132 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
133 * i386-tbl.h: Regenerated.
135 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
137 * cgen-asm.c: Fix spelling mistakes.
138 * cgen-dis.c: Fix spelling mistakes.
139 * tic30-dis.c: Fix spelling mistakes.
141 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
144 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
146 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
149 * i386-dis.c (print_insn): Clear modrm if not needed.
150 (putop): Check need_modrm for modrm.mod != 3. Don't check
151 need_modrm for modrm.mod == 3.
153 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
155 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
156 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
157 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
158 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
159 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
160 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
161 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
162 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
163 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
164 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
165 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
166 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
167 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
168 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
170 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
172 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
174 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
176 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
177 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
179 2020-09-26 Alan Modra <amodra@gmail.com>
181 * csky-opc.h: Formatting.
182 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
183 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
185 (get_register_number): Likewise.
186 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
188 2020-09-24 Lili Cui <lili.cui@intel.com>
191 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
193 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
195 * csky-dis.c (csky_output_operand): Enclose body of if in curly
198 2020-09-24 Lili Cui <lili.cui@intel.com>
200 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
201 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
202 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
203 X86_64_0F01_REG_1_RM_7_P_2.
204 (prefix_table): Likewise.
205 (x86_64_table): Likewise.
206 (rm_table): Likewise.
207 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
208 and CPU_ANY_TDX_FLAGS.
209 (cpu_flags): Add CpuTDX.
210 * i386-opc.h (enum): Add CpuTDX.
211 (i386_cpu_flags): Add cputdx.
212 * i386-opc.tbl: Add TDX insns.
213 * i386-init.h: Regenerate.
214 * i386-tbl.h: Likewise.
216 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
218 * csky-dis.c (using_abi): New.
219 (parse_csky_dis_options): New function.
220 (get_gr_name): New function.
221 (get_cr_name): New function.
222 (csky_output_operand): Use get_gr_name and get_cr_name to
223 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
224 (print_insn_csky): Parse disassembler options.
225 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
226 (GENARAL_REG_BANK): Define.
227 (REG_SUPPORT_ALL): Define.
228 (REG_SUPPORT_ALL): New.
230 (REG_SUPPORT_A): Define.
231 (REG_SUPPORT_B): Define.
232 (REG_SUPPORT_C): Define.
233 (REG_SUPPORT_D): Define.
234 (REG_SUPPORT_E): Define.
235 (csky_abiv1_general_regs): New.
236 (csky_abiv1_control_regs): New.
237 (csky_abiv2_general_regs): New.
238 (csky_abiv2_control_regs): New.
239 (get_register_name): New function.
240 (get_register_number): New function.
241 (csky_get_general_reg_name): New function.
242 (csky_get_general_regno): New function.
243 (csky_get_control_reg_name): New function.
244 (csky_get_control_regno): New function.
245 (csky_v2_opcodes): Prefer two oprerans format for bclri and
246 bseti, strengthen the operands legality check of addc, zext
249 2020-09-23 Lili Cui <lili.cui@intel.com>
251 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
252 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
253 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
254 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
255 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
256 (reg_table): New instructions (see prefixes above).
257 (prefix_table): Likewise.
258 (three_byte_table): Likewise.
259 (mod_table): Likewise
260 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
261 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
262 (cpu_flags): Likewise.
263 (operand_type_init): Likewise.
264 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
265 (i386_cpu_flags): Add cpukl and cpuwide_kl.
266 * i386-opc.tbl: Add KL and WIDE_KL insns.
267 * i386-init.h: Regenerate.
268 * i386-tbl.h: Likewise.
270 2020-09-21 Alan Modra <amodra@gmail.com>
272 * rx-dis.c (flag_names): Add missing comma.
273 (register_names, flag_names, double_register_names),
274 (double_register_high_names, double_register_low_names),
275 (double_control_register_names, double_condition_names): Remove
278 2020-09-18 David Faust <david.faust@oracle.com>
280 * bpf-desc.c: Regenerate.
281 * bpf-desc.h: Likewise.
282 * bpf-opc.c: Likewise.
283 * bpf-opc.h: Likewise.
285 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
287 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
290 2020-09-16 Alan Modra <amodra@gmail.com>
292 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
294 2020-09-10 Nick Clifton <nickc@redhat.com>
296 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
297 for hidden, local, no-type symbols.
298 (disassemble_init_powerpc): Point the symbol_is_valid field in the
299 info structure at the new function.
301 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
303 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
304 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
307 2020-09-10 Nick Clifton <nickc@redhat.com>
309 * csky-dis.c (csky_output_operand): Coerce the immediate values to
310 long before printing.
312 2020-09-10 Alan Modra <amodra@gmail.com>
314 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
316 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
318 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
321 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
323 * csky-dis.c (csky_output_operand): Add handlers for
324 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
325 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
326 to support FPUV3 instructions.
327 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
328 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
329 OPRND_TYPE_DFLOAT_FMOVI.
330 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
331 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
332 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
333 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
334 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
335 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
336 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
337 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
338 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
339 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
340 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
341 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
342 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
343 (csky_v2_opcodes): Add FPUV3 instructions.
345 2020-09-08 Alex Coplan <alex.coplan@arm.com>
347 * aarch64-dis.c (print_operands): Pass CPU features to
348 aarch64_print_operand().
349 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
350 preferred disassembly of system registers.
351 (SR_RNG): Refactor to use new SR_FEAT2 macro.
357 (SR_EXPAND_ELx): New.
358 (SR_EXPAND_EL12): New.
359 (aarch64_sys_regs): Specify which registers are only on
360 A-profile, add R-profile system registers.
364 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
367 2020-09-08 Alex Coplan <alex.coplan@arm.com>
369 * aarch64-tbl.h (aarch64_feature_v8_r): New.
372 (aarch64_opcode_table): Add dfb.
373 * aarch64-opc-2.c: Regenerate.
374 * aarch64-asm-2.c: Regenerate.
375 * aarch64-dis-2.c: Regenerate.
377 2020-09-08 Alex Coplan <alex.coplan@arm.com>
379 * aarch64-dis.c (arch_variant): New.
380 (determine_disassembling_preference): Disassemble according to
382 (select_aarch64_variant): New.
383 (print_insn_aarch64): Set feature set.
385 2020-09-02 Alan Modra <amodra@gmail.com>
387 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
388 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
389 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
390 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
391 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
392 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
393 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
394 for value parameter and update code to suit.
395 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
396 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
398 2020-09-02 Alan Modra <amodra@gmail.com>
400 * i386-dis.c (OP_E_memory): Don't cast to signed type when
402 (get32, get32s): Use unsigned types in shift expressions.
404 2020-09-02 Alan Modra <amodra@gmail.com>
406 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
408 2020-09-02 Alan Modra <amodra@gmail.com>
410 * crx-dis.c: Whitespace.
411 (print_arg): Use unsigned type for longdisp and mask variables,
412 and for left shift constant.
414 2020-09-02 Alan Modra <amodra@gmail.com>
416 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
417 * bpf-ibld.c: Regenerate.
418 * epiphany-ibld.c: Regenerate.
419 * fr30-ibld.c: Regenerate.
420 * frv-ibld.c: Regenerate.
421 * ip2k-ibld.c: Regenerate.
422 * iq2000-ibld.c: Regenerate.
423 * lm32-ibld.c: Regenerate.
424 * m32c-ibld.c: Regenerate.
425 * m32r-ibld.c: Regenerate.
426 * mep-ibld.c: Regenerate.
427 * mt-ibld.c: Regenerate.
428 * or1k-ibld.c: Regenerate.
429 * xc16x-ibld.c: Regenerate.
430 * xstormy16-ibld.c: Regenerate.
432 2020-09-02 Alan Modra <amodra@gmail.com>
434 * bfin-dis.c (MASKBITS): Use SIGNBIT.
436 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
438 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
439 to CSKYV2_ISA_3E3R3 instruction set.
441 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
443 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
445 2020-09-01 Alan Modra <amodra@gmail.com>
447 * mep-ibld.c: Regenerate.
449 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
451 * csky-dis.c (csky_output_operand): Assign dis_info.value for
454 2020-08-30 Alan Modra <amodra@gmail.com>
456 * cr16-dis.c: Formatting.
457 (parameter): Delete struct typedef. Use dwordU instead
459 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
461 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
463 2020-08-29 Alan Modra <amodra@gmail.com>
466 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
467 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
469 2020-08-28 Alan Modra <amodra@gmail.com>
473 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
474 (extract_normal): Likewise.
475 (insert_normal): Likewise, and move past zero length test.
476 (put_insn_int_value): Handle mask for zero length, use 1UL.
477 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
478 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
479 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
480 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
482 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
484 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
485 (csky_dis_info): Add member isa.
486 (csky_find_inst_info): Skip instructions that do not belong to
488 (csky_get_disassembler): Get infomation from attribute section.
489 (print_insn_csky): Set defualt ISA flag.
490 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
491 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
492 isa_flag32'type to unsigned 64 bits.
494 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
496 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
498 2020-08-26 David Faust <david.faust@oracle.com>
500 * bpf-desc.c: Regenerate.
501 * bpf-desc.h: Likewise.
502 * bpf-opc.c: Likewise.
503 * bpf-opc.h: Likewise.
504 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
505 ISA when appropriate.
507 2020-08-25 Alan Modra <amodra@gmail.com>
510 * vax-dis.c (parse_disassembler_options): Always add at least one
511 to entry_addr_total_slots.
513 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
515 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
516 in other CPUs to speed up disassembling.
517 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
518 Change plsli.u16 to plsli.16, change sync's operand format.
520 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
522 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
524 2020-08-21 Nick Clifton <nickc@redhat.com>
526 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
529 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
531 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
533 2020-08-19 Alan Modra <amodra@gmail.com>
535 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
538 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
540 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
541 <xvcvbf16spn>: ...to this.
543 2020-08-12 Alex Coplan <alex.coplan@arm.com>
545 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
547 2020-08-12 Nick Clifton <nickc@redhat.com>
549 * po/sr.po: Updated Serbian translation.
551 2020-08-11 Alan Modra <amodra@gmail.com>
553 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
555 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
557 * aarch64-opc.c (aarch64_print_operand):
558 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
559 (aarch64_sys_reg_supported_p): Function removed.
560 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
561 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
564 2020-08-10 Alan Modra <amodra@gmail.com>
566 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
569 2020-08-10 Alan Modra <amodra@gmail.com>
571 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
572 Enable icbt for power5, miso for power8.
574 2020-08-10 Alan Modra <amodra@gmail.com>
576 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
577 mtvsrd, and similarly for mfvsrd.
579 2020-08-04 Christian Groessler <chris@groessler.org>
580 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
582 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
583 opcodes (special "out" to absolute address).
584 * z8k-opc.h: Regenerate.
586 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
589 * i386-opc.h (Prefix_Disp8): New.
590 (Prefix_Disp16): Likewise.
591 (Prefix_Disp32): Likewise.
592 (Prefix_Load): Likewise.
593 (Prefix_Store): Likewise.
594 (Prefix_VEX): Likewise.
595 (Prefix_VEX3): Likewise.
596 (Prefix_EVEX): Likewise.
597 (Prefix_REX): Likewise.
598 (Prefix_NoOptimize): Likewise.
599 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
600 * i386-tbl.h: Regenerated.
602 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
604 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
605 default case with abort() instead of printing an error message and
606 continuing, to avoid a maybe-uninitialized warning.
608 2020-07-24 Nick Clifton <nickc@redhat.com>
610 * po/de.po: Updated German translation.
612 2020-07-21 Jan Beulich <jbeulich@suse.com>
614 * i386-dis.c (OP_E_memory): Revert previous change.
616 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
619 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
620 without base nor index registers.
622 2020-07-15 Jan Beulich <jbeulich@suse.com>
624 * i386-dis.c (putop): Move 'V' and 'W' handling.
626 2020-07-15 Jan Beulich <jbeulich@suse.com>
628 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
629 construct for push/pop of register.
630 (putop): Honor cond when handling 'P'. Drop handling of plain
633 2020-07-15 Jan Beulich <jbeulich@suse.com>
635 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
636 description. Drop '&' description. Use P for push of immediate,
637 pushf/popf, enter, and leave. Use %LP for lret/retf.
638 (dis386_twobyte): Use P for push/pop of fs/gs.
639 (reg_table): Use P for push/pop. Use @ for near call/jmp.
640 (x86_64_table): Use P for far call/jmp.
641 (putop): Drop handling of 'U' and '&'. Move and adjust handling
642 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
644 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
645 and dqw_mode (unconditional).
647 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
650 * i386-dis.c (OP_E_memory): Without base nor index registers,
651 32-bit displacement to 64 bits.
653 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
655 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
656 faulty double register pair is detected.
658 2020-07-14 Jan Beulich <jbeulich@suse.com>
660 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
662 2020-07-14 Jan Beulich <jbeulich@suse.com>
664 * i386-dis.c (OP_R, Rm): Delete.
665 (MOD_0F24, MOD_0F26): Rename to ...
666 (X86_64_0F24, X86_64_0F26): ... respectively.
667 (dis386): Update 'L' and 'Z' comments.
668 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
670 (mod_table): Move opcode 0F24 and 0F26 entries ...
671 (x86_64_table): ... here.
672 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
675 2020-07-14 Jan Beulich <jbeulich@suse.com>
677 * i386-dis.c (Rd, Rdq, MaskR): Delete.
678 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
679 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
680 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
681 MOD_EVEX_0F387C): New enumerators.
682 (reg_table): Use Edq for rdssp.
683 (prefix_table): Use Edq for incssp.
684 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
685 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
686 ktest*, and kshift*. Use Edq / MaskE for kmov*.
687 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
688 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
689 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
690 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
691 0F3828_P_1 and 0F3838_P_1.
692 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
693 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
695 2020-07-14 Jan Beulich <jbeulich@suse.com>
697 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
698 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
699 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
700 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
701 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
702 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
703 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
704 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
705 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
706 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
707 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
708 (reg_table, prefix_table, three_byte_table, vex_table,
709 vex_len_table, mod_table, rm_table): Replace / remove respective
711 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
712 of PREFIX_DATA in used_prefixes.
714 2020-07-14 Jan Beulich <jbeulich@suse.com>
716 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
717 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
718 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
719 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
720 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
721 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
722 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
723 VEX_W_0F3A33_L_0): Delete.
724 (dis386): Adjust "BW" description.
725 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
726 0F3A31, 0F3A32, and 0F3A33.
727 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
729 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
732 2020-07-14 Jan Beulich <jbeulich@suse.com>
734 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
735 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
736 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
737 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
738 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
739 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
740 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
741 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
742 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
743 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
744 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
745 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
746 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
747 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
748 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
749 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
750 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
751 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
752 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
753 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
754 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
755 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
756 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
757 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
758 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
759 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
760 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
761 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
762 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
763 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
764 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
765 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
766 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
767 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
768 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
769 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
770 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
771 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
772 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
773 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
774 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
775 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
776 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
777 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
778 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
779 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
780 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
781 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
782 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
783 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
784 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
785 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
786 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
787 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
788 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
789 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
790 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
791 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
792 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
793 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
794 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
795 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
796 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
797 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
798 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
799 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
800 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
801 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
802 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
803 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
804 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
805 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
806 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
807 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
808 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
809 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
810 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
811 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
812 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
813 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
814 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
815 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
816 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
817 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
818 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
819 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
820 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
821 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
822 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
823 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
824 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
825 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
826 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
827 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
828 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
829 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
830 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
831 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
832 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
833 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
834 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
835 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
836 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
837 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
838 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
839 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
840 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
841 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
842 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
843 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
844 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
845 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
846 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
847 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
848 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
849 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
850 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
851 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
852 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
853 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
854 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
855 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
856 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
857 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
858 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
859 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
860 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
861 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
862 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
863 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
864 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
865 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
866 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
867 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
868 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
869 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
870 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
871 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
872 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
873 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
874 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
875 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
876 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
877 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
878 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
879 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
880 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
881 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
882 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
883 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
884 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
885 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
886 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
887 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
888 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
889 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
890 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
891 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
892 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
893 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
894 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
895 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
896 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
897 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
898 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
899 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
900 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
901 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
902 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
903 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
904 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
905 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
906 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
907 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
908 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
909 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
910 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
911 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
912 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
913 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
914 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
915 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
916 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
917 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
918 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
919 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
920 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
921 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
922 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
923 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
924 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
925 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
926 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
927 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
928 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
929 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
930 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
931 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
932 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
933 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
934 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
935 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
936 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
937 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
938 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
939 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
940 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
941 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
942 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
943 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
944 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
945 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
946 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
947 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
948 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
949 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
950 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
951 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
952 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
953 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
954 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
955 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
956 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
957 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
958 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
959 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
960 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
961 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
962 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
963 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
964 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
965 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
966 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
967 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
968 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
969 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
970 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
971 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
972 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
973 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
974 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
975 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
976 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
977 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
978 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
979 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
980 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
981 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
982 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
983 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
984 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
985 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
986 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
987 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
988 EVEX_W_0F3A72_P_2): Rename to ...
989 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
990 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
991 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
992 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
993 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
994 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
995 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
996 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
997 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
998 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
999 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1000 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1001 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1002 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1003 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1004 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1005 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1006 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1007 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1008 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1009 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1010 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1011 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1012 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1013 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1014 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1015 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1016 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1017 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1018 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1019 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1020 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1021 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1022 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1023 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1024 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1025 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1026 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1027 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1028 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1029 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1030 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1031 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1032 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1033 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1034 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1035 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1036 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1037 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1038 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1039 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1040 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1041 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1042 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1043 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1044 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1045 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1046 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1047 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1048 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1049 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1050 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1051 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1052 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1053 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1054 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1055 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1056 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1057 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1058 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1059 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1060 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1062 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1063 vex_w_table, mod_table): Replace / remove respective entries.
1064 (print_insn): Move up dp->prefix_requirement handling. Handle
1066 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1067 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1068 Replace / remove respective entries.
1070 2020-07-14 Jan Beulich <jbeulich@suse.com>
1072 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1073 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1074 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1075 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1076 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1078 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1079 0F2C, 0F2D, 0F2E, and 0F2F.
1080 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1083 2020-07-14 Jan Beulich <jbeulich@suse.com>
1085 * i386-dis.c (OP_VexR, VexScalarR): New.
1086 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1087 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1088 need_vex_reg): Delete.
1089 (prefix_table): Replace VexScalar by VexScalarR and
1090 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1091 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1092 (vex_len_table): Replace EXqVexScalarS by EXqS.
1093 (get_valid_dis386): Don't set need_vex_reg.
1094 (print_insn): Don't initialize need_vex_reg.
1095 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1096 q_scalar_swap_mode cases.
1097 (OP_EX): Don't check for d_scalar_swap_mode and
1099 (OP_VEX): Done check need_vex_reg.
1100 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1101 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1102 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1104 2020-07-14 Jan Beulich <jbeulich@suse.com>
1106 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1107 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1108 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1109 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1110 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1111 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1112 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1113 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1114 (vex_table): Replace Vex128 by Vex.
1115 (vex_len_table): Likewise. Adjust referenced enum names.
1116 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1117 referenced enum names.
1118 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1119 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1121 2020-07-14 Jan Beulich <jbeulich@suse.com>
1123 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1124 (putop): Handle "DQ". Don't handle "LW" anymore.
1125 (prefix_table, mod_table): Replace %LW by %DQ.
1126 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1128 2020-07-14 Jan Beulich <jbeulich@suse.com>
1130 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1131 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1132 d_scalar_swap_mode case handling. Move shift adjsutment into
1133 the case its applicable to.
1135 2020-07-14 Jan Beulich <jbeulich@suse.com>
1137 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1138 (EXbScalar, EXwScalar): Fold to ...
1139 (EXbwUnit): ... this.
1140 (b_scalar_mode, w_scalar_mode): Fold to ...
1141 (bw_unit_mode): ... this.
1142 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1143 w_scalar_mode handling by bw_unit_mode one.
1144 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1146 * i386-dis-evex-prefix.h: ... here.
1148 2020-07-14 Jan Beulich <jbeulich@suse.com>
1150 * i386-dis.c (PCMPESTR_Fixup): Delete.
1151 (dis386): Adjust "LQ" description.
1152 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1153 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1154 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1155 vpcmpestrm, and vpcmpestri.
1156 (putop): Honor "cond" when handling LQ.
1157 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1158 vcvtsi2ss and vcvtusi2ss.
1159 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1160 vcvtsi2sd and vcvtusi2sd.
1162 2020-07-14 Jan Beulich <jbeulich@suse.com>
1164 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1165 (simd_cmp_op): Add const.
1166 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1167 (CMP_Fixup): Handle VEX case.
1168 (prefix_table): Replace VCMP by CMP.
1169 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1171 2020-07-14 Jan Beulich <jbeulich@suse.com>
1173 * i386-dis.c (MOVBE_Fixup): Delete.
1175 (prefix_table): Use Mv for movbe entries.
1177 2020-07-14 Jan Beulich <jbeulich@suse.com>
1179 * i386-dis.c (CRC32_Fixup): Delete.
1180 (prefix_table): Use Eb/Ev for crc32 entries.
1182 2020-07-14 Jan Beulich <jbeulich@suse.com>
1184 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1185 Conditionalize invocations of "USED_REX (0)".
1187 2020-07-14 Jan Beulich <jbeulich@suse.com>
1189 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1190 CH, DH, BH, AX, DX): Delete.
1191 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1192 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1193 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1195 2020-07-10 Lili Cui <lili.cui@intel.com>
1197 * i386-dis.c (TMM): New.
1200 (MVexSIBMEM): Likewise.
1201 (tmm_mode): Likewise.
1202 (vex_sibmem_mode): Likewise.
1203 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1204 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1205 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1206 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1207 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1208 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1209 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1210 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1211 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1212 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1213 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1214 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1215 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1216 (PREFIX_VEX_0F3849_X86_64): Likewise.
1217 (PREFIX_VEX_0F384B_X86_64): Likewise.
1218 (PREFIX_VEX_0F385C_X86_64): Likewise.
1219 (PREFIX_VEX_0F385E_X86_64): Likewise.
1220 (X86_64_VEX_0F3849): Likewise.
1221 (X86_64_VEX_0F384B): Likewise.
1222 (X86_64_VEX_0F385C): Likewise.
1223 (X86_64_VEX_0F385E): Likewise.
1224 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1225 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1226 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1227 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1228 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1229 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1230 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1231 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1232 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1233 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1234 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1235 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1236 (VEX_W_0F3849_X86_64_P_0): Likewise.
1237 (VEX_W_0F3849_X86_64_P_2): Likewise.
1238 (VEX_W_0F3849_X86_64_P_3): Likewise.
1239 (VEX_W_0F384B_X86_64_P_1): Likewise.
1240 (VEX_W_0F384B_X86_64_P_2): Likewise.
1241 (VEX_W_0F384B_X86_64_P_3): Likewise.
1242 (VEX_W_0F385C_X86_64_P_1): Likewise.
1243 (VEX_W_0F385E_X86_64_P_0): Likewise.
1244 (VEX_W_0F385E_X86_64_P_1): Likewise.
1245 (VEX_W_0F385E_X86_64_P_2): Likewise.
1246 (VEX_W_0F385E_X86_64_P_3): Likewise.
1247 (names_tmm): Likewise.
1248 (att_names_tmm): Likewise.
1249 (intel_operand_size): Handle void_mode.
1250 (OP_XMM): Handle tmm_mode.
1253 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1254 CpuAMX_BF16 and CpuAMX_TILE.
1255 (operand_type_shorthands): Add RegTMM.
1256 (operand_type_init): Likewise.
1257 (operand_types): Add Tmmword.
1258 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1259 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1260 * i386-opc.h (CpuAMX_INT8): New.
1261 (CpuAMX_BF16): Likewise.
1262 (CpuAMX_TILE): Likewise.
1264 (Tmmword): Likewise.
1265 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1266 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1267 (i386_operand_type): Add tmmword.
1268 * i386-opc.tbl: Add AMX instructions.
1269 * i386-reg.tbl: Add AMX registers.
1270 * i386-init.h: Regenerated.
1271 * i386-tbl.h: Likewise.
1273 2020-07-08 Jan Beulich <jbeulich@suse.com>
1275 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1276 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1278 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1279 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1281 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1282 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1283 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1284 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1285 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1286 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1287 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1288 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1289 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1290 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1291 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1292 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1293 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1294 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1295 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1296 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1297 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1298 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1299 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1300 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1301 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1302 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1303 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1304 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1305 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1306 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1307 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1308 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1309 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1310 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1311 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1312 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1313 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1314 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1315 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1316 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1317 (reg_table): Re-order XOP entries. Adjust their operands.
1318 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1319 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1320 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1321 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1322 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1323 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1324 entries by references ...
1325 (vex_len_table): ... to resepctive new entries here. For several
1326 new and existing entries reference ...
1327 (vex_w_table): ... new entries here.
1328 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1330 2020-07-08 Jan Beulich <jbeulich@suse.com>
1332 * i386-dis.c (XMVexScalarI4): Define.
1333 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1334 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1335 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1336 (vex_len_table): Move scalar FMA4 entries ...
1337 (prefix_table): ... here.
1338 (OP_REG_VexI4): Handle scalar_mode.
1339 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1340 * i386-tbl.h: Re-generate.
1342 2020-07-08 Jan Beulich <jbeulich@suse.com>
1344 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1345 Vex_2src_2): Delete.
1346 (OP_VexW, VexW): New.
1347 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1348 for shifts and rotates by register.
1350 2020-07-08 Jan Beulich <jbeulich@suse.com>
1352 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1353 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1354 OP_EX_VexReg): Delete.
1355 (OP_VexI4, VexI4): New.
1356 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1357 (prefix_table): ... here.
1358 (print_insn): Drop setting of vex_w_done.
1360 2020-07-08 Jan Beulich <jbeulich@suse.com>
1362 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1363 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1364 (xop_table): Replace operands of 4-operand insns.
1365 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1367 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1369 * arc-opc.c (insert_rbd): New function.
1372 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1375 2020-07-07 Jan Beulich <jbeulich@suse.com>
1377 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1378 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1379 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1380 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1382 (putop): Handle "BW".
1383 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1384 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1386 * i386-dis-evex-prefix.h: ... here.
1388 2020-07-06 Jan Beulich <jbeulich@suse.com>
1390 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1391 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1392 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1393 VEX_W_0FXOP_09_83): New enumerators.
1394 (xop_table): Reference the above.
1395 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1396 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1397 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1398 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1400 2020-07-06 Jan Beulich <jbeulich@suse.com>
1402 * i386-dis.c (EVEX_W_0F3838_P_1,
1403 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1404 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1405 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1406 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1407 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1408 (putop): Centralize management of last[]. Delete SAVE_LAST.
1409 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1410 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1411 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1412 * i386-dis-evex-prefix.h: here.
1414 2020-07-06 Jan Beulich <jbeulich@suse.com>
1416 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1417 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1418 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1419 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1421 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1422 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1423 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1424 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1425 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1426 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1427 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1428 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1429 these, respectively.
1430 * i386-dis-evex-len.h: Adjust comments.
1431 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1432 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1433 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1434 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1435 MOD_EVEX_0F385B_P_2_W_1 table entries.
1436 * i386-dis-evex-w.h: Reference mod_table[] for
1437 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1440 2020-07-06 Jan Beulich <jbeulich@suse.com>
1442 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1443 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1445 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1446 Likewise. Mark 256-bit entries invalid.
1448 2020-07-06 Jan Beulich <jbeulich@suse.com>
1450 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1451 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1452 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1453 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1454 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1455 PREFIX_EVEX_0F382B): Delete.
1456 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1457 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1458 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1459 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1460 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1462 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1463 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1464 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1465 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1467 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1468 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1469 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1470 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1471 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1472 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1473 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1474 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1475 PREFIX_EVEX_0F382B): Remove table entries.
1476 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1477 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1478 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1480 2020-07-06 Jan Beulich <jbeulich@suse.com>
1482 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1483 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1485 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1486 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1487 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1488 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1491 2020-07-06 Jan Beulich <jbeulich@suse.com>
1493 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1494 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1495 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1496 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1497 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1498 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1499 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1500 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1501 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1504 2020-07-06 Jan Beulich <jbeulich@suse.com>
1506 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1507 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1508 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1510 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1512 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1514 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1516 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1518 2020-07-06 Jan Beulich <jbeulich@suse.com>
1520 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1521 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1522 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1523 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1524 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1525 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1526 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1527 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1528 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1529 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1530 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1531 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1532 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1533 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1534 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1535 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1536 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1537 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1538 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1539 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1540 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1541 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1542 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1543 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1544 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1545 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1546 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1547 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1548 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1549 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1550 (prefix_table): Add EXxEVexR to FMA table entries.
1551 (OP_Rounding): Move abort() invocation.
1552 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1553 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1554 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1555 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1556 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1557 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1558 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1559 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1560 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1561 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1563 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1564 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1565 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1566 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1567 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1568 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1569 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1570 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1571 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1572 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1573 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1574 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1575 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1576 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1577 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1578 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1579 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1580 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1581 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1582 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1583 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1584 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1585 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1586 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1587 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1588 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1589 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1590 Delete table entries.
1591 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1592 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1593 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1596 2020-07-06 Jan Beulich <jbeulich@suse.com>
1598 * i386-dis.c (EXqScalarS): Delete.
1599 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1600 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1602 2020-07-06 Jan Beulich <jbeulich@suse.com>
1604 * i386-dis.c (safe-ctype.h): Include.
1605 (EXdScalar, EXqScalar): Delete.
1606 (d_scalar_mode, q_scalar_mode): Delete.
1607 (prefix_table, vex_len_table): Use EXxmm_md in place of
1608 EXdScalar and EXxmm_mq in place of EXqScalar.
1609 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1610 d_scalar_mode and q_scalar_mode.
1611 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1612 (vmovsd): Use EXxmm_mq.
1614 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1617 * arc-dis.c: Fix spelling mistake.
1618 * po/opcodes.pot: Regenerate.
1620 2020-07-06 Nick Clifton <nickc@redhat.com>
1622 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1623 * po/uk.po: Updated Ukranian translation.
1625 2020-07-04 Nick Clifton <nickc@redhat.com>
1627 * configure: Regenerate.
1628 * po/opcodes.pot: Regenerate.
1630 2020-07-04 Nick Clifton <nickc@redhat.com>
1632 Binutils 2.35 branch created.
1634 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1636 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1637 * i386-opc.h (VexSwapSources): New.
1638 (i386_opcode_modifier): Add vexswapsources.
1639 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1640 with two source operands swapped.
1641 * i386-tbl.h: Regenerated.
1643 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1645 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1646 unprivileged CSR can also be initialized.
1648 2020-06-29 Alan Modra <amodra@gmail.com>
1650 * arm-dis.c: Use C style comments.
1651 * cr16-opc.c: Likewise.
1652 * ft32-dis.c: Likewise.
1653 * moxie-opc.c: Likewise.
1654 * tic54x-dis.c: Likewise.
1655 * s12z-opc.c: Remove useless comment.
1656 * xgate-dis.c: Likewise.
1658 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1660 * i386-opc.tbl: Add a blank line.
1662 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1664 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1665 (VecSIB128): Renamed to ...
1667 (VecSIB256): Renamed to ...
1669 (VecSIB512): Renamed to ...
1671 (VecSIB): Renamed to ...
1673 (i386_opcode_modifier): Replace vecsib with sib.
1674 * i386-opc.tbl (VecSIB128): New.
1675 (VecSIB256): Likewise.
1676 (VecSIB512): Likewise.
1677 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1678 and VecSIB512, respectively.
1680 2020-06-26 Jan Beulich <jbeulich@suse.com>
1682 * i386-dis.c: Adjust description of I macro.
1683 (x86_64_table): Drop use of I.
1684 (float_mem): Replace use of I.
1685 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1687 2020-06-26 Jan Beulich <jbeulich@suse.com>
1689 * i386-dis.c: (print_insn): Avoid straight assignment to
1690 priv.orig_sizeflag when processing -M sub-options.
1692 2020-06-25 Jan Beulich <jbeulich@suse.com>
1694 * i386-dis.c: Adjust description of J macro.
1695 (dis386, x86_64_table, mod_table): Replace J.
1696 (putop): Remove handling of J.
1698 2020-06-25 Jan Beulich <jbeulich@suse.com>
1700 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1702 2020-06-25 Jan Beulich <jbeulich@suse.com>
1704 * i386-dis.c: Adjust description of "LQ" macro.
1705 (dis386_twobyte): Use LQ for sysret.
1706 (putop): Adjust handling of LQ.
1708 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1710 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1711 * riscv-dis.c: Include elfxx-riscv.h.
1713 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1715 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1717 2020-06-17 Lili Cui <lili.cui@intel.com>
1719 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1721 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1724 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1725 * i386-opc.tbl: Likewise.
1726 * i386-tbl.h: Regenerated.
1728 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1730 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1732 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1734 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1735 (SR_CORE): Likewise.
1736 (SR_FEAT): Likewise.
1738 (SR_V8_1): Likewise.
1739 (SR_V8_2): Likewise.
1740 (SR_V8_3): Likewise.
1741 (SR_V8_4): Likewise.
1744 (SR_SSBS): Likewise.
1746 (SR_ID_PFR2): Likewise.
1747 (SR_PROFILE): Likewise.
1748 (SR_MEMTAG): Likewise.
1749 (SR_SCXTNUM): Likewise.
1750 (aarch64_sys_regs): Refactor to store feature information in the table.
1751 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1752 that now describe their own features.
1753 (aarch64_pstatefield_supported_p): Likewise.
1755 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1757 * i386-dis.c (prefix_table): Fix a typo in comments.
1759 2020-06-09 Jan Beulich <jbeulich@suse.com>
1761 * i386-dis.c (rex_ignored): Delete.
1762 (ckprefix): Drop rex_ignored initialization.
1763 (get_valid_dis386): Drop setting of rex_ignored.
1764 (print_insn): Drop checking of rex_ignored. Don't record data
1765 size prefix as used with VEX-and-alike encodings.
1767 2020-06-09 Jan Beulich <jbeulich@suse.com>
1769 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1770 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1771 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1772 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1773 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1774 VEX_0F12, and VEX_0F16.
1775 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1776 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1777 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1778 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1779 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1780 MOD_VEX_0F16_PREFIX_2 entries.
1782 2020-06-09 Jan Beulich <jbeulich@suse.com>
1784 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1785 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1786 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1787 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1788 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1789 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1790 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1791 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1792 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1793 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1794 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1795 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1796 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1797 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1798 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1799 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1800 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1801 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1802 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1803 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1804 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1805 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1806 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1807 EVEX_W_0FC6_P_2): Delete.
1808 (print_insn): Add EVEX.W vs embedded prefix consistency check
1809 to prefix validation.
1810 * i386-dis-evex.h (evex_table): Don't further descend for
1811 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1812 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1814 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1815 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1816 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1817 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1818 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1819 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1820 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1821 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1822 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1823 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1824 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1825 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1826 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1827 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1828 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1829 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1830 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1831 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1832 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1833 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1834 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1835 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1836 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1837 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1838 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1839 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1840 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1842 2020-06-09 Jan Beulich <jbeulich@suse.com>
1844 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1845 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1846 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1848 (print_insn): Drop pointless check against bad_opcode. Split
1849 prefix validation into legacy and VEX-and-alike parts.
1850 (putop): Re-work 'X' macro handling.
1852 2020-06-09 Jan Beulich <jbeulich@suse.com>
1854 * i386-dis.c (MOD_0F51): Rename to ...
1855 (MOD_0F50): ... this.
1857 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1859 * arm-dis.c (arm_opcodes): Add dfb.
1860 (thumb32_opcodes): Add dfb.
1862 2020-06-08 Jan Beulich <jbeulich@suse.com>
1864 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1866 2020-06-06 Alan Modra <amodra@gmail.com>
1868 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1870 2020-06-05 Alan Modra <amodra@gmail.com>
1872 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1873 size is large enough.
1875 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1877 * disassemble.c (disassemble_init_for_target): Set endian_code for
1879 * bpf-desc.c: Regenerate.
1880 * bpf-opc.c: Likewise.
1881 * bpf-dis.c: Likewise.
1883 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1885 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1886 (cgen_put_insn_value): Likewise.
1887 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1888 * cgen-dis.in (print_insn): Likewise.
1889 * cgen-ibld.in (insert_1): Likewise.
1890 (insert_1): Likewise.
1891 (insert_insn_normal): Likewise.
1892 (extract_1): Likewise.
1893 * bpf-dis.c: Regenerate.
1894 * bpf-ibld.c: Likewise.
1895 * bpf-ibld.c: Likewise.
1896 * cgen-dis.in: Likewise.
1897 * cgen-ibld.in: Likewise.
1898 * cgen-opc.c: Likewise.
1899 * epiphany-dis.c: Likewise.
1900 * epiphany-ibld.c: Likewise.
1901 * fr30-dis.c: Likewise.
1902 * fr30-ibld.c: Likewise.
1903 * frv-dis.c: Likewise.
1904 * frv-ibld.c: Likewise.
1905 * ip2k-dis.c: Likewise.
1906 * ip2k-ibld.c: Likewise.
1907 * iq2000-dis.c: Likewise.
1908 * iq2000-ibld.c: Likewise.
1909 * lm32-dis.c: Likewise.
1910 * lm32-ibld.c: Likewise.
1911 * m32c-dis.c: Likewise.
1912 * m32c-ibld.c: Likewise.
1913 * m32r-dis.c: Likewise.
1914 * m32r-ibld.c: Likewise.
1915 * mep-dis.c: Likewise.
1916 * mep-ibld.c: Likewise.
1917 * mt-dis.c: Likewise.
1918 * mt-ibld.c: Likewise.
1919 * or1k-dis.c: Likewise.
1920 * or1k-ibld.c: Likewise.
1921 * xc16x-dis.c: Likewise.
1922 * xc16x-ibld.c: Likewise.
1923 * xstormy16-dis.c: Likewise.
1924 * xstormy16-ibld.c: Likewise.
1926 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1928 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1929 (print_insn_): Handle instruction endian.
1930 * bpf-dis.c: Regenerate.
1931 * bpf-desc.c: Regenerate.
1932 * epiphany-dis.c: Likewise.
1933 * epiphany-desc.c: Likewise.
1934 * fr30-dis.c: Likewise.
1935 * fr30-desc.c: Likewise.
1936 * frv-dis.c: Likewise.
1937 * frv-desc.c: Likewise.
1938 * ip2k-dis.c: Likewise.
1939 * ip2k-desc.c: Likewise.
1940 * iq2000-dis.c: Likewise.
1941 * iq2000-desc.c: Likewise.
1942 * lm32-dis.c: Likewise.
1943 * lm32-desc.c: Likewise.
1944 * m32c-dis.c: Likewise.
1945 * m32c-desc.c: Likewise.
1946 * m32r-dis.c: Likewise.
1947 * m32r-desc.c: Likewise.
1948 * mep-dis.c: Likewise.
1949 * mep-desc.c: Likewise.
1950 * mt-dis.c: Likewise.
1951 * mt-desc.c: Likewise.
1952 * or1k-dis.c: Likewise.
1953 * or1k-desc.c: Likewise.
1954 * xc16x-dis.c: Likewise.
1955 * xc16x-desc.c: Likewise.
1956 * xstormy16-dis.c: Likewise.
1957 * xstormy16-desc.c: Likewise.
1959 2020-06-03 Nick Clifton <nickc@redhat.com>
1961 * po/sr.po: Updated Serbian translation.
1963 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1965 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1966 (riscv_get_priv_spec_class): Likewise.
1968 2020-06-01 Alan Modra <amodra@gmail.com>
1970 * bpf-desc.c: Regenerate.
1972 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1973 David Faust <david.faust@oracle.com>
1975 * bpf-desc.c: Regenerate.
1976 * bpf-opc.h: Likewise.
1977 * bpf-opc.c: Likewise.
1978 * bpf-dis.c: Likewise.
1980 2020-05-28 Alan Modra <amodra@gmail.com>
1982 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1985 2020-05-28 Alan Modra <amodra@gmail.com>
1987 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1989 (print_insn_ns32k): Revert last change.
1991 2020-05-28 Nick Clifton <nickc@redhat.com>
1993 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1996 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1998 Fix extraction of signed constants in nios2 disassembler (again).
2000 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2001 extractions of signed fields.
2003 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2005 * s390-opc.txt: Relocate vector load/store instructions with
2006 additional alignment parameter and change architecture level
2007 constraint from z14 to z13.
2009 2020-05-21 Alan Modra <amodra@gmail.com>
2011 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2012 * sparc-dis.c: Likewise.
2013 * tic4x-dis.c: Likewise.
2014 * xtensa-dis.c: Likewise.
2015 * bpf-desc.c: Regenerate.
2016 * epiphany-desc.c: Regenerate.
2017 * fr30-desc.c: Regenerate.
2018 * frv-desc.c: Regenerate.
2019 * ip2k-desc.c: Regenerate.
2020 * iq2000-desc.c: Regenerate.
2021 * lm32-desc.c: Regenerate.
2022 * m32c-desc.c: Regenerate.
2023 * m32r-desc.c: Regenerate.
2024 * mep-asm.c: Regenerate.
2025 * mep-desc.c: Regenerate.
2026 * mt-desc.c: Regenerate.
2027 * or1k-desc.c: Regenerate.
2028 * xc16x-desc.c: Regenerate.
2029 * xstormy16-desc.c: Regenerate.
2031 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
2033 * riscv-opc.c (riscv_ext_version_table): The table used to store
2034 all information about the supported spec and the corresponding ISA
2035 versions. Currently, only Zicsr is supported to verify the
2036 correctness of Z sub extension settings. Others will be supported
2037 in the future patches.
2038 (struct isa_spec_t, isa_specs): List for all supported ISA spec
2039 classes and the corresponding strings.
2040 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
2041 spec class by giving a ISA spec string.
2042 * riscv-opc.c (struct priv_spec_t): New structure.
2043 (struct priv_spec_t priv_specs): List for all supported privilege spec
2044 classes and the corresponding strings.
2045 (riscv_get_priv_spec_class): New function. Get the corresponding
2046 privilege spec class by giving a spec string.
2047 (riscv_get_priv_spec_name): New function. Get the corresponding
2048 privilege spec string by giving a CSR version class.
2049 * riscv-dis.c: Updated since DECLARE_CSR is changed.
2050 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2051 according to the chosen version. Build a hash table riscv_csr_hash to
2052 store the valid CSR for the chosen pirv verison. Dump the direct
2053 CSR address rather than it's name if it is invalid.
2054 (parse_riscv_dis_option_without_args): New function. Parse the options
2056 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2057 parse the options without arguments first, and then handle the options
2058 with arguments. Add the new option -Mpriv-spec, which has argument.
2059 * riscv-dis.c (print_riscv_disassembler_options): Add description
2060 about the new OBJDUMP option.
2062 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
2064 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2065 WC values on POWER10 sync, dcbf and wait instructions.
2066 (insert_pl, extract_pl): New functions.
2067 (L2OPT, LS, WC): Use insert_ls and extract_ls.
2068 (LS3): New , 3-bit L for sync.
2069 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2070 (SC2, PL): New, 2-bit SC and PL for sync and wait.
2071 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2072 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2073 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2074 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2075 <wait>: Enable PL operand on POWER10.
2076 <dcbf>: Enable L3OPT operand on POWER10.
2077 <sync>: Enable SC2 operand on POWER10.
2079 2020-05-19 Stafford Horne <shorne@gmail.com>
2082 * or1k-asm.c: Regenerate.
2083 * or1k-desc.c: Regenerate.
2084 * or1k-desc.h: Regenerate.
2085 * or1k-dis.c: Regenerate.
2086 * or1k-ibld.c: Regenerate.
2087 * or1k-opc.c: Regenerate.
2088 * or1k-opc.h: Regenerate.
2089 * or1k-opinst.c: Regenerate.
2091 2020-05-11 Alan Modra <amodra@gmail.com>
2093 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2096 2020-05-11 Alan Modra <amodra@gmail.com>
2098 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2099 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2101 2020-05-11 Alan Modra <amodra@gmail.com>
2103 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2105 2020-05-11 Alan Modra <amodra@gmail.com>
2107 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2108 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2110 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2112 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2115 2020-05-11 Alan Modra <amodra@gmail.com>
2117 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2118 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2119 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2120 (prefix_opcodes): Add xxeval.
2122 2020-05-11 Alan Modra <amodra@gmail.com>
2124 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2125 xxgenpcvwm, xxgenpcvdm.
2127 2020-05-11 Alan Modra <amodra@gmail.com>
2129 * ppc-opc.c (MP, VXVAM_MASK): Define.
2130 (VXVAPS_MASK): Use VXVA_MASK.
2131 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2132 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2133 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2134 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2136 2020-05-11 Alan Modra <amodra@gmail.com>
2137 Peter Bergner <bergner@linux.ibm.com>
2139 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2141 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2142 YMSK2, XA6a, XA6ap, XB6a entries.
2143 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2144 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2146 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2147 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2148 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2149 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2150 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2151 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2152 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2153 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2154 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2155 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2156 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2157 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2158 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2159 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2161 2020-05-11 Alan Modra <amodra@gmail.com>
2163 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2164 (insert_xts, extract_xts): New functions.
2165 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2166 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2167 (VXRC_MASK, VXSH_MASK): Define.
2168 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2169 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2170 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2171 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2172 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2173 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2174 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2176 2020-05-11 Alan Modra <amodra@gmail.com>
2178 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2179 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2180 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2181 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2182 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2184 2020-05-11 Alan Modra <amodra@gmail.com>
2186 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2187 (XTP, DQXP, DQXP_MASK): Define.
2188 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2189 (prefix_opcodes): Add plxvp and pstxvp.
2191 2020-05-11 Alan Modra <amodra@gmail.com>
2193 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2194 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2195 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2197 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2199 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2201 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2203 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2205 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2207 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2209 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2211 2020-05-11 Alan Modra <amodra@gmail.com>
2213 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2215 2020-05-11 Alan Modra <amodra@gmail.com>
2217 * ppc-dis.c (ppc_opts): Add "power10" entry.
2218 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2219 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2221 2020-05-11 Nick Clifton <nickc@redhat.com>
2223 * po/fr.po: Updated French translation.
2225 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2227 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2228 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2229 (operand_general_constraint_met_p): validate
2230 AARCH64_OPND_UNDEFINED.
2231 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2233 * aarch64-asm-2.c: Regenerated.
2234 * aarch64-dis-2.c: Regenerated.
2235 * aarch64-opc-2.c: Regenerated.
2237 2020-04-29 Nick Clifton <nickc@redhat.com>
2240 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2243 2020-04-29 Nick Clifton <nickc@redhat.com>
2245 * po/sv.po: Updated Swedish translation.
2247 2020-04-29 Nick Clifton <nickc@redhat.com>
2250 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2251 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2252 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2255 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2258 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2259 cmpi only on m68020up and cpu32.
2261 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2263 * aarch64-asm.c (aarch64_ins_none): New.
2264 * aarch64-asm.h (ins_none): New declaration.
2265 * aarch64-dis.c (aarch64_ext_none): New.
2266 * aarch64-dis.h (ext_none): New declaration.
2267 * aarch64-opc.c (aarch64_print_operand): Update case for
2268 AARCH64_OPND_BARRIER_PSB.
2269 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2270 (AARCH64_OPERANDS): Update inserter/extracter for
2271 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2272 * aarch64-asm-2.c: Regenerated.
2273 * aarch64-dis-2.c: Regenerated.
2274 * aarch64-opc-2.c: Regenerated.
2276 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2278 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2279 (aarch64_feature_ras, RAS): Likewise.
2280 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2281 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2282 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2283 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2284 * aarch64-asm-2.c: Regenerated.
2285 * aarch64-dis-2.c: Regenerated.
2286 * aarch64-opc-2.c: Regenerated.
2288 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2290 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2291 (print_insn_neon): Support disassembly of conditional
2294 2020-02-16 David Faust <david.faust@oracle.com>
2296 * bpf-desc.c: Regenerate.
2297 * bpf-desc.h: Likewise.
2298 * bpf-opc.c: Regenerate.
2299 * bpf-opc.h: Likewise.
2301 2020-04-07 Lili Cui <lili.cui@intel.com>
2303 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2304 (prefix_table): New instructions (see prefixes above).
2305 (rm_table): Likewise
2306 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2307 CPU_ANY_TSXLDTRK_FLAGS.
2308 (cpu_flags): Add CpuTSXLDTRK.
2309 * i386-opc.h (enum): Add CpuTSXLDTRK.
2310 (i386_cpu_flags): Add cputsxldtrk.
2311 * i386-opc.tbl: Add XSUSPLDTRK insns.
2312 * i386-init.h: Regenerate.
2313 * i386-tbl.h: Likewise.
2315 2020-04-02 Lili Cui <lili.cui@intel.com>
2317 * i386-dis.c (prefix_table): New instructions serialize.
2318 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2319 CPU_ANY_SERIALIZE_FLAGS.
2320 (cpu_flags): Add CpuSERIALIZE.
2321 * i386-opc.h (enum): Add CpuSERIALIZE.
2322 (i386_cpu_flags): Add cpuserialize.
2323 * i386-opc.tbl: Add SERIALIZE insns.
2324 * i386-init.h: Regenerate.
2325 * i386-tbl.h: Likewise.
2327 2020-03-26 Alan Modra <amodra@gmail.com>
2329 * disassemble.h (opcodes_assert): Declare.
2330 (OPCODES_ASSERT): Define.
2331 * disassemble.c: Don't include assert.h. Include opintl.h.
2332 (opcodes_assert): New function.
2333 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2334 (bfd_h8_disassemble): Reduce size of data array. Correctly
2335 calculate maxlen. Omit insn decoding when insn length exceeds
2336 maxlen. Exit from nibble loop when looking for E, before
2337 accessing next data byte. Move processing of E outside loop.
2338 Replace tests of maxlen in loop with assertions.
2340 2020-03-26 Alan Modra <amodra@gmail.com>
2342 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2344 2020-03-25 Alan Modra <amodra@gmail.com>
2346 * z80-dis.c (suffix): Init mybuf.
2348 2020-03-22 Alan Modra <amodra@gmail.com>
2350 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2351 successflly read from section.
2353 2020-03-22 Alan Modra <amodra@gmail.com>
2355 * arc-dis.c (find_format): Use ISO C string concatenation rather
2356 than line continuation within a string. Don't access needs_limm
2357 before testing opcode != NULL.
2359 2020-03-22 Alan Modra <amodra@gmail.com>
2361 * ns32k-dis.c (print_insn_arg): Update comment.
2362 (print_insn_ns32k): Reduce size of index_offset array, and
2363 initialize, passing -1 to print_insn_arg for args that are not
2364 an index. Don't exit arg loop early. Abort on bad arg number.
2366 2020-03-22 Alan Modra <amodra@gmail.com>
2368 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2369 * s12z-opc.c: Formatting.
2370 (operands_f): Return an int.
2371 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2372 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2373 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2374 (exg_sex_discrim): Likewise.
2375 (create_immediate_operand, create_bitfield_operand),
2376 (create_register_operand_with_size, create_register_all_operand),
2377 (create_register_all16_operand, create_simple_memory_operand),
2378 (create_memory_operand, create_memory_auto_operand): Don't
2379 segfault on malloc failure.
2380 (z_ext24_decode): Return an int status, negative on fail, zero
2382 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2383 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2384 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2385 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2386 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2387 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2388 (loop_primitive_decode, shift_decode, psh_pul_decode),
2389 (bit_field_decode): Similarly.
2390 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2391 to return value, update callers.
2392 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2393 Don't segfault on NULL operand.
2394 (decode_operation): Return OP_INVALID on first fail.
2395 (decode_s12z): Check all reads, returning -1 on fail.
2397 2020-03-20 Alan Modra <amodra@gmail.com>
2399 * metag-dis.c (print_insn_metag): Don't ignore status from
2402 2020-03-20 Alan Modra <amodra@gmail.com>
2404 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2405 Initialize parts of buffer not written when handling a possible
2406 2-byte insn at end of section. Don't attempt decoding of such
2407 an insn by the 4-byte machinery.
2409 2020-03-20 Alan Modra <amodra@gmail.com>
2411 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2412 partially filled buffer. Prevent lookup of 4-byte insns when
2413 only VLE 2-byte insns are possible due to section size. Print
2414 ".word" rather than ".long" for 2-byte leftovers.
2416 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2419 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2421 2020-03-13 Jan Beulich <jbeulich@suse.com>
2423 * i386-dis.c (X86_64_0D): Rename to ...
2424 (X86_64_0E): ... this.
2426 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2428 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2429 * Makefile.in: Regenerated.
2431 2020-03-09 Jan Beulich <jbeulich@suse.com>
2433 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2435 * i386-tbl.h: Re-generate.
2437 2020-03-09 Jan Beulich <jbeulich@suse.com>
2439 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2440 vprot*, vpsha*, and vpshl*.
2441 * i386-tbl.h: Re-generate.
2443 2020-03-09 Jan Beulich <jbeulich@suse.com>
2445 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2446 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2447 * i386-tbl.h: Re-generate.
2449 2020-03-09 Jan Beulich <jbeulich@suse.com>
2451 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2452 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2453 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2454 * i386-tbl.h: Re-generate.
2456 2020-03-09 Jan Beulich <jbeulich@suse.com>
2458 * i386-gen.c (struct template_arg, struct template_instance,
2459 struct template_param, struct template, templates,
2460 parse_template, expand_templates): New.
2461 (process_i386_opcodes): Various local variables moved to
2462 expand_templates. Call parse_template and expand_templates.
2463 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2464 * i386-tbl.h: Re-generate.
2466 2020-03-06 Jan Beulich <jbeulich@suse.com>
2468 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2469 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2470 register and memory source templates. Replace VexW= by VexW*
2472 * i386-tbl.h: Re-generate.
2474 2020-03-06 Jan Beulich <jbeulich@suse.com>
2476 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2477 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2478 * i386-tbl.h: Re-generate.
2480 2020-03-06 Jan Beulich <jbeulich@suse.com>
2482 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2483 * i386-tbl.h: Re-generate.
2485 2020-03-06 Jan Beulich <jbeulich@suse.com>
2487 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2488 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2489 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2490 VexW0 on SSE2AVX variants.
2491 (vmovq): Drop NoRex64 from XMM/XMM variants.
2492 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2493 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2494 applicable use VexW0.
2495 * i386-tbl.h: Re-generate.
2497 2020-03-06 Jan Beulich <jbeulich@suse.com>
2499 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2500 * i386-opc.h (Rex64): Delete.
2501 (struct i386_opcode_modifier): Remove rex64 field.
2502 * i386-opc.tbl (crc32): Drop Rex64.
2503 Replace Rex64 with Size64 everywhere else.
2504 * i386-tbl.h: Re-generate.
2506 2020-03-06 Jan Beulich <jbeulich@suse.com>
2508 * i386-dis.c (OP_E_memory): Exclude recording of used address
2509 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2510 addressed memory operands for MPX insns.
2512 2020-03-06 Jan Beulich <jbeulich@suse.com>
2514 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2515 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2516 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2517 (ptwrite): Split into non-64-bit and 64-bit forms.
2518 * i386-tbl.h: Re-generate.
2520 2020-03-06 Jan Beulich <jbeulich@suse.com>
2522 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2524 * i386-tbl.h: Re-generate.
2526 2020-03-04 Jan Beulich <jbeulich@suse.com>
2528 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2529 (prefix_table): Move vmmcall here. Add vmgexit.
2530 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2531 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2532 (cpu_flags): Add CpuSEV_ES entry.
2533 * i386-opc.h (CpuSEV_ES): New.
2534 (union i386_cpu_flags): Add cpusev_es field.
2535 * i386-opc.tbl (vmgexit): New.
2536 * i386-init.h, i386-tbl.h: Re-generate.
2538 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2540 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2542 * i386-opc.h (IGNORESIZE): New.
2543 (DEFAULTSIZE): Likewise.
2544 (IgnoreSize): Removed.
2545 (DefaultSize): Likewise.
2546 (MnemonicSize): New.
2547 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2549 * i386-opc.tbl (IgnoreSize): New.
2550 (DefaultSize): Likewise.
2551 * i386-tbl.h: Regenerated.
2553 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2556 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2559 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2562 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2563 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2564 * i386-tbl.h: Regenerated.
2566 2020-02-26 Alan Modra <amodra@gmail.com>
2568 * aarch64-asm.c: Indent labels correctly.
2569 * aarch64-dis.c: Likewise.
2570 * aarch64-gen.c: Likewise.
2571 * aarch64-opc.c: Likewise.
2572 * alpha-dis.c: Likewise.
2573 * i386-dis.c: Likewise.
2574 * nds32-asm.c: Likewise.
2575 * nfp-dis.c: Likewise.
2576 * visium-dis.c: Likewise.
2578 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2580 * arc-regs.h (int_vector_base): Make it available for all ARC
2583 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2585 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2588 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2590 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2591 c.mv/c.li if rs1 is zero.
2593 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2595 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2596 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2598 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2599 * i386-opc.h (CpuABM): Removed.
2601 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2602 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2603 popcnt. Remove CpuABM from lzcnt.
2604 * i386-init.h: Regenerated.
2605 * i386-tbl.h: Likewise.
2607 2020-02-17 Jan Beulich <jbeulich@suse.com>
2609 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2610 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2611 VexW1 instead of open-coding them.
2612 * i386-tbl.h: Re-generate.
2614 2020-02-17 Jan Beulich <jbeulich@suse.com>
2616 * i386-opc.tbl (AddrPrefixOpReg): Define.
2617 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2618 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2619 templates. Drop NoRex64.
2620 * i386-tbl.h: Re-generate.
2622 2020-02-17 Jan Beulich <jbeulich@suse.com>
2625 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2626 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2627 into Intel syntax instance (with Unpsecified) and AT&T one
2629 (vcvtneps2bf16): Likewise, along with folding the two so far
2631 * i386-tbl.h: Re-generate.
2633 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2635 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2636 CPU_ANY_SSE4A_FLAGS.
2638 2020-02-17 Alan Modra <amodra@gmail.com>
2640 * i386-gen.c (cpu_flag_init): Correct last change.
2642 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2644 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2647 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2649 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2652 2020-02-14 Jan Beulich <jbeulich@suse.com>
2655 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2656 destination for Cpu64-only variant.
2657 (movzx): Fold patterns.
2658 * i386-tbl.h: Re-generate.
2660 2020-02-13 Jan Beulich <jbeulich@suse.com>
2662 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2663 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2664 CPU_ANY_SSE4_FLAGS entry.
2665 * i386-init.h: Re-generate.
2667 2020-02-12 Jan Beulich <jbeulich@suse.com>
2669 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2670 with Unspecified, making the present one AT&T syntax only.
2671 * i386-tbl.h: Re-generate.
2673 2020-02-12 Jan Beulich <jbeulich@suse.com>
2675 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2676 * i386-tbl.h: Re-generate.
2678 2020-02-12 Jan Beulich <jbeulich@suse.com>
2681 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2682 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2683 Amd64 and Intel64 templates.
2684 (call, jmp): Likewise for far indirect variants. Dro
2686 * i386-tbl.h: Re-generate.
2688 2020-02-11 Jan Beulich <jbeulich@suse.com>
2690 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2691 * i386-opc.h (ShortForm): Delete.
2692 (struct i386_opcode_modifier): Remove shortform field.
2693 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2694 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2695 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2696 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2698 * i386-tbl.h: Re-generate.
2700 2020-02-11 Jan Beulich <jbeulich@suse.com>
2702 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2703 fucompi): Drop ShortForm from operand-less templates.
2704 * i386-tbl.h: Re-generate.
2706 2020-02-11 Alan Modra <amodra@gmail.com>
2708 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2709 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2710 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2711 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2712 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2714 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2716 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2717 (cde_opcodes): Add VCX* instructions.
2719 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2720 Matthew Malcomson <matthew.malcomson@arm.com>
2722 * arm-dis.c (struct cdeopcode32): New.
2723 (CDE_OPCODE): New macro.
2724 (cde_opcodes): New disassembly table.
2725 (regnames): New option to table.
2726 (cde_coprocs): New global variable.
2727 (print_insn_cde): New
2728 (print_insn_thumb32): Use print_insn_cde.
2729 (parse_arm_disassembler_options): Parse coprocN args.
2731 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2734 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2736 * i386-opc.h (AMD64): Removed.
2737 (Intel64): Likewose.
2739 (INTEL64): Likewise.
2740 (INTEL64ONLY): Likewise.
2741 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2742 * i386-opc.tbl (Amd64): New.
2743 (Intel64): Likewise.
2744 (Intel64Only): Likewise.
2745 Replace AMD64 with Amd64. Update sysenter/sysenter with
2746 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2747 * i386-tbl.h: Regenerated.
2749 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2752 * z80-dis.c: Add support for GBZ80 opcodes.
2754 2020-02-04 Alan Modra <amodra@gmail.com>
2756 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2758 2020-02-03 Alan Modra <amodra@gmail.com>
2760 * m32c-ibld.c: Regenerate.
2762 2020-02-01 Alan Modra <amodra@gmail.com>
2764 * frv-ibld.c: Regenerate.
2766 2020-01-31 Jan Beulich <jbeulich@suse.com>
2768 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2769 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2770 (OP_E_memory): Replace xmm_mdq_mode case label by
2771 vex_scalar_w_dq_mode one.
2772 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2774 2020-01-31 Jan Beulich <jbeulich@suse.com>
2776 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2777 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2778 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2779 (intel_operand_size): Drop vex_w_dq_mode case label.
2781 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2783 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2784 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2786 2020-01-30 Alan Modra <amodra@gmail.com>
2788 * m32c-ibld.c: Regenerate.
2790 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2792 * bpf-opc.c: Regenerate.
2794 2020-01-30 Jan Beulich <jbeulich@suse.com>
2796 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2797 (dis386): Use them to replace C2/C3 table entries.
2798 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2799 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2800 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2801 * i386-tbl.h: Re-generate.
2803 2020-01-30 Jan Beulich <jbeulich@suse.com>
2805 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2807 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2809 * i386-tbl.h: Re-generate.
2811 2020-01-30 Alan Modra <amodra@gmail.com>
2813 * tic4x-dis.c (tic4x_dp): Make unsigned.
2815 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2816 Jan Beulich <jbeulich@suse.com>
2819 * i386-dis.c (MOVSXD_Fixup): New function.
2820 (movsxd_mode): New enum.
2821 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2822 (intel_operand_size): Handle movsxd_mode.
2823 (OP_E_register): Likewise.
2825 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2826 register on movsxd. Add movsxd with 16-bit destination register
2827 for AMD64 and Intel64 ISAs.
2828 * i386-tbl.h: Regenerated.
2830 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2833 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2834 * aarch64-asm-2.c: Regenerate
2835 * aarch64-dis-2.c: Likewise.
2836 * aarch64-opc-2.c: Likewise.
2838 2020-01-21 Jan Beulich <jbeulich@suse.com>
2840 * i386-opc.tbl (sysret): Drop DefaultSize.
2841 * i386-tbl.h: Re-generate.
2843 2020-01-21 Jan Beulich <jbeulich@suse.com>
2845 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2847 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2848 * i386-tbl.h: Re-generate.
2850 2020-01-20 Nick Clifton <nickc@redhat.com>
2852 * po/de.po: Updated German translation.
2853 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2854 * po/uk.po: Updated Ukranian translation.
2856 2020-01-20 Alan Modra <amodra@gmail.com>
2858 * hppa-dis.c (fput_const): Remove useless cast.
2860 2020-01-20 Alan Modra <amodra@gmail.com>
2862 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2864 2020-01-18 Nick Clifton <nickc@redhat.com>
2866 * configure: Regenerate.
2867 * po/opcodes.pot: Regenerate.
2869 2020-01-18 Nick Clifton <nickc@redhat.com>
2871 Binutils 2.34 branch created.
2873 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2875 * opintl.h: Fix spelling error (seperate).
2877 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2879 * i386-opc.tbl: Add {vex} pseudo prefix.
2880 * i386-tbl.h: Regenerated.
2882 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2885 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2886 (neon_opcodes): Likewise.
2887 (select_arm_features): Make sure we enable MVE bits when selecting
2888 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2891 2020-01-16 Jan Beulich <jbeulich@suse.com>
2893 * i386-opc.tbl: Drop stale comment from XOP section.
2895 2020-01-16 Jan Beulich <jbeulich@suse.com>
2897 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2898 (extractps): Add VexWIG to SSE2AVX forms.
2899 * i386-tbl.h: Re-generate.
2901 2020-01-16 Jan Beulich <jbeulich@suse.com>
2903 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2904 Size64 from and use VexW1 on SSE2AVX forms.
2905 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2906 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2907 * i386-tbl.h: Re-generate.
2909 2020-01-15 Alan Modra <amodra@gmail.com>
2911 * tic4x-dis.c (tic4x_version): Make unsigned long.
2912 (optab, optab_special, registernames): New file scope vars.
2913 (tic4x_print_register): Set up registernames rather than
2914 malloc'd registertable.
2915 (tic4x_disassemble): Delete optable and optable_special. Use
2916 optab and optab_special instead. Throw away old optab,
2917 optab_special and registernames when info->mach changes.
2919 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2922 * z80-dis.c (suffix): Use .db instruction to generate double
2925 2020-01-14 Alan Modra <amodra@gmail.com>
2927 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2928 values to unsigned before shifting.
2930 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2932 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2934 (print_insn_thumb16, print_insn_thumb32): Likewise.
2935 (print_insn): Initialize the insn info.
2936 * i386-dis.c (print_insn): Initialize the insn info fields, and
2939 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2941 * arc-opc.c (C_NE): Make it required.
2943 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2945 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2946 reserved register name.
2948 2020-01-13 Alan Modra <amodra@gmail.com>
2950 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2951 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2953 2020-01-13 Alan Modra <amodra@gmail.com>
2955 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2956 result of wasm_read_leb128 in a uint64_t and check that bits
2957 are not lost when copying to other locals. Use uint32_t for
2958 most locals. Use PRId64 when printing int64_t.
2960 2020-01-13 Alan Modra <amodra@gmail.com>
2962 * score-dis.c: Formatting.
2963 * score7-dis.c: Formatting.
2965 2020-01-13 Alan Modra <amodra@gmail.com>
2967 * score-dis.c (print_insn_score48): Use unsigned variables for
2968 unsigned values. Don't left shift negative values.
2969 (print_insn_score32): Likewise.
2970 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2972 2020-01-13 Alan Modra <amodra@gmail.com>
2974 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2976 2020-01-13 Alan Modra <amodra@gmail.com>
2978 * fr30-ibld.c: Regenerate.
2980 2020-01-13 Alan Modra <amodra@gmail.com>
2982 * xgate-dis.c (print_insn): Don't left shift signed value.
2983 (ripBits): Formatting, use 1u.
2985 2020-01-10 Alan Modra <amodra@gmail.com>
2987 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2988 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2990 2020-01-10 Alan Modra <amodra@gmail.com>
2992 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2993 and XRREG value earlier to avoid a shift with negative exponent.
2994 * m10200-dis.c (disassemble): Similarly.
2996 2020-01-09 Nick Clifton <nickc@redhat.com>
2999 * z80-dis.c (ld_ii_ii): Use correct cast.
3001 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
3004 * z80-dis.c (ld_ii_ii): Use character constant when checking
3007 2020-01-09 Jan Beulich <jbeulich@suse.com>
3009 * i386-dis.c (SEP_Fixup): New.
3011 (dis386_twobyte): Use it for sysenter/sysexit.
3012 (enum x86_64_isa): Change amd64 enumerator to value 1.
3013 (OP_J): Compare isa64 against intel64 instead of amd64.
3014 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3016 * i386-tbl.h: Re-generate.
3018 2020-01-08 Alan Modra <amodra@gmail.com>
3020 * z8k-dis.c: Include libiberty.h
3021 (instr_data_s): Make max_fetched unsigned.
3022 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3023 Don't exceed byte_info bounds.
3024 (output_instr): Make num_bytes unsigned.
3025 (unpack_instr): Likewise for nibl_count and loop.
3026 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3028 * z8k-opc.h: Regenerate.
3030 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
3032 * arc-tbl.h (llock): Use 'LLOCK' as class.
3034 (scond): Use 'SCOND' as class.
3036 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3039 2020-01-06 Alan Modra <amodra@gmail.com>
3041 * m32c-ibld.c: Regenerate.
3043 2020-01-06 Alan Modra <amodra@gmail.com>
3046 * z80-dis.c (suffix): Don't use a local struct buffer copy.
3047 Peek at next byte to prevent recursion on repeated prefix bytes.
3048 Ensure uninitialised "mybuf" is not accessed.
3049 (print_insn_z80): Don't zero n_fetch and n_used here,..
3050 (print_insn_z80_buf): ..do it here instead.
3052 2020-01-04 Alan Modra <amodra@gmail.com>
3054 * m32r-ibld.c: Regenerate.
3056 2020-01-04 Alan Modra <amodra@gmail.com>
3058 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3060 2020-01-04 Alan Modra <amodra@gmail.com>
3062 * crx-dis.c (match_opcode): Avoid shift left of signed value.
3064 2020-01-04 Alan Modra <amodra@gmail.com>
3066 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3068 2020-01-03 Jan Beulich <jbeulich@suse.com>
3070 * aarch64-tbl.h (aarch64_opcode_table): Use
3071 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3073 2020-01-03 Jan Beulich <jbeulich@suse.com>
3075 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3076 forms of SUDOT and USDOT.
3078 2020-01-03 Jan Beulich <jbeulich@suse.com>
3080 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3082 * aarch64-dis-2.c: Re-generate.
3084 2020-01-03 Jan Beulich <jbeulich@suse.com>
3086 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3088 * aarch64-dis-2.c: Re-generate.
3090 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
3092 * z80-dis.c: Add support for eZ80 and Z80 instructions.
3094 2020-01-01 Alan Modra <amodra@gmail.com>
3096 Update year range in copyright notice of all files.
3098 For older changes see ChangeLog-2019
3100 Copyright (C) 2020 Free Software Foundation, Inc.
3102 Copying and distribution of this file, with or without modification,
3103 are permitted in any medium without royalty provided the copyright
3104 notice and this notice are preserved.
3110 version-control: never