1 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
3 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
4 (csky_dis_info): Add member isa.
5 (csky_find_inst_info): Skip instructions that do not belong to
7 (csky_get_disassembler): Get infomation from attribute section.
8 (print_insn_csky): Set defualt ISA flag.
9 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
10 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
11 isa_flag32'type to unsigned 64 bits.
13 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
15 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
17 2020-08-26 David Faust <david.faust@oracle.com>
19 * bpf-desc.c: Regenerate.
20 * bpf-desc.h: Likewise.
21 * bpf-opc.c: Likewise.
22 * bpf-opc.h: Likewise.
23 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
26 2020-08-25 Alan Modra <amodra@gmail.com>
29 * vax-dis.c (parse_disassembler_options): Always add at least one
30 to entry_addr_total_slots.
32 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
34 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
35 in other CPUs to speed up disassembling.
36 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
37 Change plsli.u16 to plsli.16, change sync's operand format.
39 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
41 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
43 2020-08-21 Nick Clifton <nickc@redhat.com>
45 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
48 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
50 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
52 2020-08-19 Alan Modra <amodra@gmail.com>
54 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
57 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
59 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
60 <xvcvbf16spn>: ...to this.
62 2020-08-12 Alex Coplan <alex.coplan@arm.com>
64 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
66 2020-08-12 Nick Clifton <nickc@redhat.com>
68 * po/sr.po: Updated Serbian translation.
70 2020-08-11 Alan Modra <amodra@gmail.com>
72 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
74 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
76 * aarch64-opc.c (aarch64_print_operand):
77 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
78 (aarch64_sys_reg_supported_p): Function removed.
79 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
80 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
83 2020-08-10 Alan Modra <amodra@gmail.com>
85 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
88 2020-08-10 Alan Modra <amodra@gmail.com>
90 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
91 Enable icbt for power5, miso for power8.
93 2020-08-10 Alan Modra <amodra@gmail.com>
95 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
96 mtvsrd, and similarly for mfvsrd.
98 2020-08-04 Christian Groessler <chris@groessler.org>
99 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
101 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
102 opcodes (special "out" to absolute address).
103 * z8k-opc.h: Regenerate.
105 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
108 * i386-opc.h (Prefix_Disp8): New.
109 (Prefix_Disp16): Likewise.
110 (Prefix_Disp32): Likewise.
111 (Prefix_Load): Likewise.
112 (Prefix_Store): Likewise.
113 (Prefix_VEX): Likewise.
114 (Prefix_VEX3): Likewise.
115 (Prefix_EVEX): Likewise.
116 (Prefix_REX): Likewise.
117 (Prefix_NoOptimize): Likewise.
118 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
119 * i386-tbl.h: Regenerated.
121 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
123 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
124 default case with abort() instead of printing an error message and
125 continuing, to avoid a maybe-uninitialized warning.
127 2020-07-24 Nick Clifton <nickc@redhat.com>
129 * po/de.po: Updated German translation.
131 2020-07-21 Jan Beulich <jbeulich@suse.com>
133 * i386-dis.c (OP_E_memory): Revert previous change.
135 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
138 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
139 without base nor index registers.
141 2020-07-15 Jan Beulich <jbeulich@suse.com>
143 * i386-dis.c (putop): Move 'V' and 'W' handling.
145 2020-07-15 Jan Beulich <jbeulich@suse.com>
147 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
148 construct for push/pop of register.
149 (putop): Honor cond when handling 'P'. Drop handling of plain
152 2020-07-15 Jan Beulich <jbeulich@suse.com>
154 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
155 description. Drop '&' description. Use P for push of immediate,
156 pushf/popf, enter, and leave. Use %LP for lret/retf.
157 (dis386_twobyte): Use P for push/pop of fs/gs.
158 (reg_table): Use P for push/pop. Use @ for near call/jmp.
159 (x86_64_table): Use P for far call/jmp.
160 (putop): Drop handling of 'U' and '&'. Move and adjust handling
161 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
163 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
164 and dqw_mode (unconditional).
166 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
169 * i386-dis.c (OP_E_memory): Without base nor index registers,
170 32-bit displacement to 64 bits.
172 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
174 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
175 faulty double register pair is detected.
177 2020-07-14 Jan Beulich <jbeulich@suse.com>
179 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
181 2020-07-14 Jan Beulich <jbeulich@suse.com>
183 * i386-dis.c (OP_R, Rm): Delete.
184 (MOD_0F24, MOD_0F26): Rename to ...
185 (X86_64_0F24, X86_64_0F26): ... respectively.
186 (dis386): Update 'L' and 'Z' comments.
187 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
189 (mod_table): Move opcode 0F24 and 0F26 entries ...
190 (x86_64_table): ... here.
191 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
194 2020-07-14 Jan Beulich <jbeulich@suse.com>
196 * i386-dis.c (Rd, Rdq, MaskR): Delete.
197 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
198 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
199 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
200 MOD_EVEX_0F387C): New enumerators.
201 (reg_table): Use Edq for rdssp.
202 (prefix_table): Use Edq for incssp.
203 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
204 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
205 ktest*, and kshift*. Use Edq / MaskE for kmov*.
206 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
207 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
208 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
209 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
210 0F3828_P_1 and 0F3838_P_1.
211 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
212 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
214 2020-07-14 Jan Beulich <jbeulich@suse.com>
216 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
217 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
218 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
219 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
220 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
221 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
222 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
223 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
224 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
225 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
226 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
227 (reg_table, prefix_table, three_byte_table, vex_table,
228 vex_len_table, mod_table, rm_table): Replace / remove respective
230 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
231 of PREFIX_DATA in used_prefixes.
233 2020-07-14 Jan Beulich <jbeulich@suse.com>
235 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
236 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
237 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
238 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
239 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
240 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
241 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
242 VEX_W_0F3A33_L_0): Delete.
243 (dis386): Adjust "BW" description.
244 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
245 0F3A31, 0F3A32, and 0F3A33.
246 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
248 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
251 2020-07-14 Jan Beulich <jbeulich@suse.com>
253 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
254 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
255 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
256 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
257 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
258 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
259 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
260 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
261 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
262 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
263 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
264 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
265 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
266 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
267 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
268 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
269 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
270 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
271 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
272 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
273 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
274 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
275 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
276 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
277 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
278 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
279 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
280 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
281 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
282 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
283 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
284 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
285 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
286 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
287 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
288 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
289 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
290 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
291 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
292 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
293 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
294 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
295 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
296 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
297 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
298 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
299 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
300 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
301 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
302 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
303 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
304 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
305 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
306 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
307 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
308 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
309 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
310 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
311 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
312 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
313 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
314 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
315 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
316 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
317 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
318 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
319 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
320 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
321 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
322 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
323 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
324 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
325 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
326 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
327 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
328 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
329 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
330 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
331 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
332 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
333 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
334 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
335 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
336 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
337 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
338 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
339 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
340 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
341 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
342 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
343 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
344 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
345 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
346 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
347 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
348 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
349 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
350 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
351 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
352 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
353 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
354 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
355 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
356 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
357 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
358 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
359 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
360 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
361 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
362 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
363 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
364 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
365 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
366 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
367 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
368 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
369 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
370 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
371 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
372 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
373 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
374 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
375 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
376 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
377 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
378 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
379 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
380 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
381 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
382 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
383 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
384 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
385 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
386 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
387 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
388 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
389 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
390 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
391 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
392 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
393 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
394 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
395 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
396 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
397 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
398 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
399 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
400 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
401 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
402 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
403 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
404 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
405 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
406 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
407 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
408 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
409 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
410 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
411 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
412 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
413 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
414 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
415 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
416 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
417 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
418 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
419 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
420 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
421 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
422 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
423 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
424 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
425 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
426 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
427 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
428 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
429 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
430 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
431 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
432 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
433 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
434 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
435 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
436 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
437 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
438 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
439 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
440 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
441 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
442 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
443 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
444 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
445 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
446 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
447 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
448 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
449 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
450 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
451 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
452 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
453 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
454 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
455 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
456 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
457 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
458 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
459 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
460 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
461 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
462 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
463 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
464 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
465 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
466 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
467 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
468 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
469 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
470 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
471 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
472 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
473 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
474 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
475 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
476 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
477 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
478 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
479 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
480 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
481 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
482 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
483 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
484 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
485 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
486 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
487 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
488 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
489 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
490 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
491 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
492 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
493 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
494 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
495 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
496 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
497 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
498 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
499 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
500 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
501 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
502 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
503 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
504 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
505 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
506 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
507 EVEX_W_0F3A72_P_2): Rename to ...
508 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
509 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
510 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
511 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
512 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
513 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
514 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
515 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
516 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
517 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
518 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
519 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
520 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
521 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
522 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
523 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
524 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
525 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
526 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
527 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
528 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
529 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
530 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
531 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
532 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
533 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
534 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
535 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
536 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
537 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
538 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
539 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
540 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
541 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
542 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
543 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
544 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
545 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
546 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
547 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
548 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
549 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
550 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
551 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
552 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
553 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
554 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
555 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
556 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
557 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
558 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
559 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
560 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
561 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
562 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
563 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
564 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
565 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
566 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
567 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
568 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
569 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
570 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
571 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
572 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
573 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
574 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
575 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
576 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
577 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
578 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
579 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
581 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
582 vex_w_table, mod_table): Replace / remove respective entries.
583 (print_insn): Move up dp->prefix_requirement handling. Handle
585 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
586 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
587 Replace / remove respective entries.
589 2020-07-14 Jan Beulich <jbeulich@suse.com>
591 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
592 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
593 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
594 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
595 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
597 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
598 0F2C, 0F2D, 0F2E, and 0F2F.
599 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
602 2020-07-14 Jan Beulich <jbeulich@suse.com>
604 * i386-dis.c (OP_VexR, VexScalarR): New.
605 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
606 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
607 need_vex_reg): Delete.
608 (prefix_table): Replace VexScalar by VexScalarR and
609 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
610 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
611 (vex_len_table): Replace EXqVexScalarS by EXqS.
612 (get_valid_dis386): Don't set need_vex_reg.
613 (print_insn): Don't initialize need_vex_reg.
614 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
615 q_scalar_swap_mode cases.
616 (OP_EX): Don't check for d_scalar_swap_mode and
618 (OP_VEX): Done check need_vex_reg.
619 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
620 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
621 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
623 2020-07-14 Jan Beulich <jbeulich@suse.com>
625 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
626 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
627 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
628 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
629 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
630 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
631 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
632 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
633 (vex_table): Replace Vex128 by Vex.
634 (vex_len_table): Likewise. Adjust referenced enum names.
635 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
636 referenced enum names.
637 (OP_VEX): Drop vex128_mode and vex256_mode cases.
638 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
640 2020-07-14 Jan Beulich <jbeulich@suse.com>
642 * i386-dis.c (dis386): "LW" description now applies to "DQ".
643 (putop): Handle "DQ". Don't handle "LW" anymore.
644 (prefix_table, mod_table): Replace %LW by %DQ.
645 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
647 2020-07-14 Jan Beulich <jbeulich@suse.com>
649 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
650 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
651 d_scalar_swap_mode case handling. Move shift adjsutment into
652 the case its applicable to.
654 2020-07-14 Jan Beulich <jbeulich@suse.com>
656 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
657 (EXbScalar, EXwScalar): Fold to ...
658 (EXbwUnit): ... this.
659 (b_scalar_mode, w_scalar_mode): Fold to ...
660 (bw_unit_mode): ... this.
661 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
662 w_scalar_mode handling by bw_unit_mode one.
663 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
665 * i386-dis-evex-prefix.h: ... here.
667 2020-07-14 Jan Beulich <jbeulich@suse.com>
669 * i386-dis.c (PCMPESTR_Fixup): Delete.
670 (dis386): Adjust "LQ" description.
671 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
672 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
673 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
674 vpcmpestrm, and vpcmpestri.
675 (putop): Honor "cond" when handling LQ.
676 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
677 vcvtsi2ss and vcvtusi2ss.
678 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
679 vcvtsi2sd and vcvtusi2sd.
681 2020-07-14 Jan Beulich <jbeulich@suse.com>
683 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
684 (simd_cmp_op): Add const.
685 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
686 (CMP_Fixup): Handle VEX case.
687 (prefix_table): Replace VCMP by CMP.
688 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
690 2020-07-14 Jan Beulich <jbeulich@suse.com>
692 * i386-dis.c (MOVBE_Fixup): Delete.
694 (prefix_table): Use Mv for movbe entries.
696 2020-07-14 Jan Beulich <jbeulich@suse.com>
698 * i386-dis.c (CRC32_Fixup): Delete.
699 (prefix_table): Use Eb/Ev for crc32 entries.
701 2020-07-14 Jan Beulich <jbeulich@suse.com>
703 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
704 Conditionalize invocations of "USED_REX (0)".
706 2020-07-14 Jan Beulich <jbeulich@suse.com>
708 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
709 CH, DH, BH, AX, DX): Delete.
710 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
711 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
712 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
714 2020-07-10 Lili Cui <lili.cui@intel.com>
716 * i386-dis.c (TMM): New.
719 (MVexSIBMEM): Likewise.
720 (tmm_mode): Likewise.
721 (vex_sibmem_mode): Likewise.
722 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
723 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
724 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
725 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
726 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
727 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
728 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
729 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
730 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
731 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
732 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
733 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
734 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
735 (PREFIX_VEX_0F3849_X86_64): Likewise.
736 (PREFIX_VEX_0F384B_X86_64): Likewise.
737 (PREFIX_VEX_0F385C_X86_64): Likewise.
738 (PREFIX_VEX_0F385E_X86_64): Likewise.
739 (X86_64_VEX_0F3849): Likewise.
740 (X86_64_VEX_0F384B): Likewise.
741 (X86_64_VEX_0F385C): Likewise.
742 (X86_64_VEX_0F385E): Likewise.
743 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
744 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
745 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
746 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
747 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
748 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
749 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
750 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
751 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
752 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
753 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
754 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
755 (VEX_W_0F3849_X86_64_P_0): Likewise.
756 (VEX_W_0F3849_X86_64_P_2): Likewise.
757 (VEX_W_0F3849_X86_64_P_3): Likewise.
758 (VEX_W_0F384B_X86_64_P_1): Likewise.
759 (VEX_W_0F384B_X86_64_P_2): Likewise.
760 (VEX_W_0F384B_X86_64_P_3): Likewise.
761 (VEX_W_0F385C_X86_64_P_1): Likewise.
762 (VEX_W_0F385E_X86_64_P_0): Likewise.
763 (VEX_W_0F385E_X86_64_P_1): Likewise.
764 (VEX_W_0F385E_X86_64_P_2): Likewise.
765 (VEX_W_0F385E_X86_64_P_3): Likewise.
766 (names_tmm): Likewise.
767 (att_names_tmm): Likewise.
768 (intel_operand_size): Handle void_mode.
769 (OP_XMM): Handle tmm_mode.
772 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
773 CpuAMX_BF16 and CpuAMX_TILE.
774 (operand_type_shorthands): Add RegTMM.
775 (operand_type_init): Likewise.
776 (operand_types): Add Tmmword.
777 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
778 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
779 * i386-opc.h (CpuAMX_INT8): New.
780 (CpuAMX_BF16): Likewise.
781 (CpuAMX_TILE): Likewise.
784 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
785 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
786 (i386_operand_type): Add tmmword.
787 * i386-opc.tbl: Add AMX instructions.
788 * i386-reg.tbl: Add AMX registers.
789 * i386-init.h: Regenerated.
790 * i386-tbl.h: Likewise.
792 2020-07-08 Jan Beulich <jbeulich@suse.com>
794 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
795 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
797 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
798 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
800 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
801 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
802 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
803 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
804 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
805 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
806 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
807 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
808 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
809 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
810 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
811 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
812 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
813 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
814 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
815 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
816 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
817 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
818 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
819 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
820 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
821 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
822 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
823 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
824 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
825 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
826 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
827 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
828 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
829 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
830 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
831 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
832 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
833 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
834 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
835 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
836 (reg_table): Re-order XOP entries. Adjust their operands.
837 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
838 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
839 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
840 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
841 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
842 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
843 entries by references ...
844 (vex_len_table): ... to resepctive new entries here. For several
845 new and existing entries reference ...
846 (vex_w_table): ... new entries here.
847 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
849 2020-07-08 Jan Beulich <jbeulich@suse.com>
851 * i386-dis.c (XMVexScalarI4): Define.
852 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
853 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
854 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
855 (vex_len_table): Move scalar FMA4 entries ...
856 (prefix_table): ... here.
857 (OP_REG_VexI4): Handle scalar_mode.
858 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
859 * i386-tbl.h: Re-generate.
861 2020-07-08 Jan Beulich <jbeulich@suse.com>
863 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
865 (OP_VexW, VexW): New.
866 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
867 for shifts and rotates by register.
869 2020-07-08 Jan Beulich <jbeulich@suse.com>
871 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
872 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
873 OP_EX_VexReg): Delete.
874 (OP_VexI4, VexI4): New.
875 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
876 (prefix_table): ... here.
877 (print_insn): Drop setting of vex_w_done.
879 2020-07-08 Jan Beulich <jbeulich@suse.com>
881 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
882 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
883 (xop_table): Replace operands of 4-operand insns.
884 (OP_REG_VexI4): Move VEX.W based operand swaping here.
886 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
888 * arc-opc.c (insert_rbd): New function.
891 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
894 2020-07-07 Jan Beulich <jbeulich@suse.com>
896 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
897 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
898 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
899 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
901 (putop): Handle "BW".
902 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
903 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
905 * i386-dis-evex-prefix.h: ... here.
907 2020-07-06 Jan Beulich <jbeulich@suse.com>
909 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
910 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
911 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
912 VEX_W_0FXOP_09_83): New enumerators.
913 (xop_table): Reference the above.
914 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
915 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
916 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
917 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
919 2020-07-06 Jan Beulich <jbeulich@suse.com>
921 * i386-dis.c (EVEX_W_0F3838_P_1,
922 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
923 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
924 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
925 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
926 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
927 (putop): Centralize management of last[]. Delete SAVE_LAST.
928 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
929 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
930 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
931 * i386-dis-evex-prefix.h: here.
933 2020-07-06 Jan Beulich <jbeulich@suse.com>
935 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
936 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
937 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
938 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
940 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
941 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
942 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
943 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
944 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
945 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
946 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
947 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
949 * i386-dis-evex-len.h: Adjust comments.
950 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
951 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
952 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
953 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
954 MOD_EVEX_0F385B_P_2_W_1 table entries.
955 * i386-dis-evex-w.h: Reference mod_table[] for
956 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
959 2020-07-06 Jan Beulich <jbeulich@suse.com>
961 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
962 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
964 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
965 Likewise. Mark 256-bit entries invalid.
967 2020-07-06 Jan Beulich <jbeulich@suse.com>
969 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
970 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
971 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
972 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
973 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
974 PREFIX_EVEX_0F382B): Delete.
975 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
976 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
977 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
978 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
979 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
981 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
982 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
983 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
984 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
986 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
987 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
988 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
989 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
990 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
991 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
992 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
993 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
994 PREFIX_EVEX_0F382B): Remove table entries.
995 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
996 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
997 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
999 2020-07-06 Jan Beulich <jbeulich@suse.com>
1001 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1002 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1004 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1005 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1006 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1007 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1010 2020-07-06 Jan Beulich <jbeulich@suse.com>
1012 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1013 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1014 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1015 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1016 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1017 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1018 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1019 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1020 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1023 2020-07-06 Jan Beulich <jbeulich@suse.com>
1025 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1026 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1027 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1029 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1031 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1033 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1035 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1037 2020-07-06 Jan Beulich <jbeulich@suse.com>
1039 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1040 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1041 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1042 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1043 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1044 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1045 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1046 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1047 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1048 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1049 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1050 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1051 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1052 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1053 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1054 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1055 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1056 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1057 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1058 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1059 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1060 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1061 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1062 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1063 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1064 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1065 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1066 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1067 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1068 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1069 (prefix_table): Add EXxEVexR to FMA table entries.
1070 (OP_Rounding): Move abort() invocation.
1071 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1072 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1073 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1074 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1075 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1076 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1077 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1078 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1079 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1080 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1082 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1083 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1084 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1085 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1086 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1087 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1088 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1089 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1090 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1091 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1092 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1093 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1094 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1095 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1096 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1097 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1098 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1099 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1100 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1101 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1102 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1103 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1104 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1105 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1106 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1107 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1108 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1109 Delete table entries.
1110 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1111 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1112 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1115 2020-07-06 Jan Beulich <jbeulich@suse.com>
1117 * i386-dis.c (EXqScalarS): Delete.
1118 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1119 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1121 2020-07-06 Jan Beulich <jbeulich@suse.com>
1123 * i386-dis.c (safe-ctype.h): Include.
1124 (EXdScalar, EXqScalar): Delete.
1125 (d_scalar_mode, q_scalar_mode): Delete.
1126 (prefix_table, vex_len_table): Use EXxmm_md in place of
1127 EXdScalar and EXxmm_mq in place of EXqScalar.
1128 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1129 d_scalar_mode and q_scalar_mode.
1130 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1131 (vmovsd): Use EXxmm_mq.
1133 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1136 * arc-dis.c: Fix spelling mistake.
1137 * po/opcodes.pot: Regenerate.
1139 2020-07-06 Nick Clifton <nickc@redhat.com>
1141 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1142 * po/uk.po: Updated Ukranian translation.
1144 2020-07-04 Nick Clifton <nickc@redhat.com>
1146 * configure: Regenerate.
1147 * po/opcodes.pot: Regenerate.
1149 2020-07-04 Nick Clifton <nickc@redhat.com>
1151 Binutils 2.35 branch created.
1153 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1155 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1156 * i386-opc.h (VexSwapSources): New.
1157 (i386_opcode_modifier): Add vexswapsources.
1158 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1159 with two source operands swapped.
1160 * i386-tbl.h: Regenerated.
1162 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1164 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1165 unprivileged CSR can also be initialized.
1167 2020-06-29 Alan Modra <amodra@gmail.com>
1169 * arm-dis.c: Use C style comments.
1170 * cr16-opc.c: Likewise.
1171 * ft32-dis.c: Likewise.
1172 * moxie-opc.c: Likewise.
1173 * tic54x-dis.c: Likewise.
1174 * s12z-opc.c: Remove useless comment.
1175 * xgate-dis.c: Likewise.
1177 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1179 * i386-opc.tbl: Add a blank line.
1181 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1183 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1184 (VecSIB128): Renamed to ...
1186 (VecSIB256): Renamed to ...
1188 (VecSIB512): Renamed to ...
1190 (VecSIB): Renamed to ...
1192 (i386_opcode_modifier): Replace vecsib with sib.
1193 * i386-opc.tbl (VecSIB128): New.
1194 (VecSIB256): Likewise.
1195 (VecSIB512): Likewise.
1196 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1197 and VecSIB512, respectively.
1199 2020-06-26 Jan Beulich <jbeulich@suse.com>
1201 * i386-dis.c: Adjust description of I macro.
1202 (x86_64_table): Drop use of I.
1203 (float_mem): Replace use of I.
1204 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1206 2020-06-26 Jan Beulich <jbeulich@suse.com>
1208 * i386-dis.c: (print_insn): Avoid straight assignment to
1209 priv.orig_sizeflag when processing -M sub-options.
1211 2020-06-25 Jan Beulich <jbeulich@suse.com>
1213 * i386-dis.c: Adjust description of J macro.
1214 (dis386, x86_64_table, mod_table): Replace J.
1215 (putop): Remove handling of J.
1217 2020-06-25 Jan Beulich <jbeulich@suse.com>
1219 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1221 2020-06-25 Jan Beulich <jbeulich@suse.com>
1223 * i386-dis.c: Adjust description of "LQ" macro.
1224 (dis386_twobyte): Use LQ for sysret.
1225 (putop): Adjust handling of LQ.
1227 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1229 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1230 * riscv-dis.c: Include elfxx-riscv.h.
1232 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1234 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1236 2020-06-17 Lili Cui <lili.cui@intel.com>
1238 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1240 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1243 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1244 * i386-opc.tbl: Likewise.
1245 * i386-tbl.h: Regenerated.
1247 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1249 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1251 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1253 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1254 (SR_CORE): Likewise.
1255 (SR_FEAT): Likewise.
1257 (SR_V8_1): Likewise.
1258 (SR_V8_2): Likewise.
1259 (SR_V8_3): Likewise.
1260 (SR_V8_4): Likewise.
1263 (SR_SSBS): Likewise.
1265 (SR_ID_PFR2): Likewise.
1266 (SR_PROFILE): Likewise.
1267 (SR_MEMTAG): Likewise.
1268 (SR_SCXTNUM): Likewise.
1269 (aarch64_sys_regs): Refactor to store feature information in the table.
1270 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1271 that now describe their own features.
1272 (aarch64_pstatefield_supported_p): Likewise.
1274 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1276 * i386-dis.c (prefix_table): Fix a typo in comments.
1278 2020-06-09 Jan Beulich <jbeulich@suse.com>
1280 * i386-dis.c (rex_ignored): Delete.
1281 (ckprefix): Drop rex_ignored initialization.
1282 (get_valid_dis386): Drop setting of rex_ignored.
1283 (print_insn): Drop checking of rex_ignored. Don't record data
1284 size prefix as used with VEX-and-alike encodings.
1286 2020-06-09 Jan Beulich <jbeulich@suse.com>
1288 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1289 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1290 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1291 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1292 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1293 VEX_0F12, and VEX_0F16.
1294 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1295 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1296 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1297 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1298 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1299 MOD_VEX_0F16_PREFIX_2 entries.
1301 2020-06-09 Jan Beulich <jbeulich@suse.com>
1303 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1304 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1305 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1306 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1307 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1308 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1309 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1310 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1311 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1312 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1313 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1314 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1315 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1316 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1317 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1318 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1319 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1320 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1321 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1322 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1323 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1324 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1325 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1326 EVEX_W_0FC6_P_2): Delete.
1327 (print_insn): Add EVEX.W vs embedded prefix consistency check
1328 to prefix validation.
1329 * i386-dis-evex.h (evex_table): Don't further descend for
1330 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1331 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1333 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1334 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1335 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1336 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1337 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1338 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1339 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1340 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1341 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1342 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1343 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1344 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1345 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1346 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1347 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1348 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1349 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1350 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1351 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1352 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1353 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1354 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1355 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1356 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1357 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1358 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1359 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1361 2020-06-09 Jan Beulich <jbeulich@suse.com>
1363 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1364 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1365 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1367 (print_insn): Drop pointless check against bad_opcode. Split
1368 prefix validation into legacy and VEX-and-alike parts.
1369 (putop): Re-work 'X' macro handling.
1371 2020-06-09 Jan Beulich <jbeulich@suse.com>
1373 * i386-dis.c (MOD_0F51): Rename to ...
1374 (MOD_0F50): ... this.
1376 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1378 * arm-dis.c (arm_opcodes): Add dfb.
1379 (thumb32_opcodes): Add dfb.
1381 2020-06-08 Jan Beulich <jbeulich@suse.com>
1383 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1385 2020-06-06 Alan Modra <amodra@gmail.com>
1387 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1389 2020-06-05 Alan Modra <amodra@gmail.com>
1391 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1392 size is large enough.
1394 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1396 * disassemble.c (disassemble_init_for_target): Set endian_code for
1398 * bpf-desc.c: Regenerate.
1399 * bpf-opc.c: Likewise.
1400 * bpf-dis.c: Likewise.
1402 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1404 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1405 (cgen_put_insn_value): Likewise.
1406 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1407 * cgen-dis.in (print_insn): Likewise.
1408 * cgen-ibld.in (insert_1): Likewise.
1409 (insert_1): Likewise.
1410 (insert_insn_normal): Likewise.
1411 (extract_1): Likewise.
1412 * bpf-dis.c: Regenerate.
1413 * bpf-ibld.c: Likewise.
1414 * bpf-ibld.c: Likewise.
1415 * cgen-dis.in: Likewise.
1416 * cgen-ibld.in: Likewise.
1417 * cgen-opc.c: Likewise.
1418 * epiphany-dis.c: Likewise.
1419 * epiphany-ibld.c: Likewise.
1420 * fr30-dis.c: Likewise.
1421 * fr30-ibld.c: Likewise.
1422 * frv-dis.c: Likewise.
1423 * frv-ibld.c: Likewise.
1424 * ip2k-dis.c: Likewise.
1425 * ip2k-ibld.c: Likewise.
1426 * iq2000-dis.c: Likewise.
1427 * iq2000-ibld.c: Likewise.
1428 * lm32-dis.c: Likewise.
1429 * lm32-ibld.c: Likewise.
1430 * m32c-dis.c: Likewise.
1431 * m32c-ibld.c: Likewise.
1432 * m32r-dis.c: Likewise.
1433 * m32r-ibld.c: Likewise.
1434 * mep-dis.c: Likewise.
1435 * mep-ibld.c: Likewise.
1436 * mt-dis.c: Likewise.
1437 * mt-ibld.c: Likewise.
1438 * or1k-dis.c: Likewise.
1439 * or1k-ibld.c: Likewise.
1440 * xc16x-dis.c: Likewise.
1441 * xc16x-ibld.c: Likewise.
1442 * xstormy16-dis.c: Likewise.
1443 * xstormy16-ibld.c: Likewise.
1445 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1447 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1448 (print_insn_): Handle instruction endian.
1449 * bpf-dis.c: Regenerate.
1450 * bpf-desc.c: Regenerate.
1451 * epiphany-dis.c: Likewise.
1452 * epiphany-desc.c: Likewise.
1453 * fr30-dis.c: Likewise.
1454 * fr30-desc.c: Likewise.
1455 * frv-dis.c: Likewise.
1456 * frv-desc.c: Likewise.
1457 * ip2k-dis.c: Likewise.
1458 * ip2k-desc.c: Likewise.
1459 * iq2000-dis.c: Likewise.
1460 * iq2000-desc.c: Likewise.
1461 * lm32-dis.c: Likewise.
1462 * lm32-desc.c: Likewise.
1463 * m32c-dis.c: Likewise.
1464 * m32c-desc.c: Likewise.
1465 * m32r-dis.c: Likewise.
1466 * m32r-desc.c: Likewise.
1467 * mep-dis.c: Likewise.
1468 * mep-desc.c: Likewise.
1469 * mt-dis.c: Likewise.
1470 * mt-desc.c: Likewise.
1471 * or1k-dis.c: Likewise.
1472 * or1k-desc.c: Likewise.
1473 * xc16x-dis.c: Likewise.
1474 * xc16x-desc.c: Likewise.
1475 * xstormy16-dis.c: Likewise.
1476 * xstormy16-desc.c: Likewise.
1478 2020-06-03 Nick Clifton <nickc@redhat.com>
1480 * po/sr.po: Updated Serbian translation.
1482 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1484 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1485 (riscv_get_priv_spec_class): Likewise.
1487 2020-06-01 Alan Modra <amodra@gmail.com>
1489 * bpf-desc.c: Regenerate.
1491 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1492 David Faust <david.faust@oracle.com>
1494 * bpf-desc.c: Regenerate.
1495 * bpf-opc.h: Likewise.
1496 * bpf-opc.c: Likewise.
1497 * bpf-dis.c: Likewise.
1499 2020-05-28 Alan Modra <amodra@gmail.com>
1501 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1504 2020-05-28 Alan Modra <amodra@gmail.com>
1506 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1508 (print_insn_ns32k): Revert last change.
1510 2020-05-28 Nick Clifton <nickc@redhat.com>
1512 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1515 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1517 Fix extraction of signed constants in nios2 disassembler (again).
1519 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1520 extractions of signed fields.
1522 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1524 * s390-opc.txt: Relocate vector load/store instructions with
1525 additional alignment parameter and change architecture level
1526 constraint from z14 to z13.
1528 2020-05-21 Alan Modra <amodra@gmail.com>
1530 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1531 * sparc-dis.c: Likewise.
1532 * tic4x-dis.c: Likewise.
1533 * xtensa-dis.c: Likewise.
1534 * bpf-desc.c: Regenerate.
1535 * epiphany-desc.c: Regenerate.
1536 * fr30-desc.c: Regenerate.
1537 * frv-desc.c: Regenerate.
1538 * ip2k-desc.c: Regenerate.
1539 * iq2000-desc.c: Regenerate.
1540 * lm32-desc.c: Regenerate.
1541 * m32c-desc.c: Regenerate.
1542 * m32r-desc.c: Regenerate.
1543 * mep-asm.c: Regenerate.
1544 * mep-desc.c: Regenerate.
1545 * mt-desc.c: Regenerate.
1546 * or1k-desc.c: Regenerate.
1547 * xc16x-desc.c: Regenerate.
1548 * xstormy16-desc.c: Regenerate.
1550 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1552 * riscv-opc.c (riscv_ext_version_table): The table used to store
1553 all information about the supported spec and the corresponding ISA
1554 versions. Currently, only Zicsr is supported to verify the
1555 correctness of Z sub extension settings. Others will be supported
1556 in the future patches.
1557 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1558 classes and the corresponding strings.
1559 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1560 spec class by giving a ISA spec string.
1561 * riscv-opc.c (struct priv_spec_t): New structure.
1562 (struct priv_spec_t priv_specs): List for all supported privilege spec
1563 classes and the corresponding strings.
1564 (riscv_get_priv_spec_class): New function. Get the corresponding
1565 privilege spec class by giving a spec string.
1566 (riscv_get_priv_spec_name): New function. Get the corresponding
1567 privilege spec string by giving a CSR version class.
1568 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1569 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1570 according to the chosen version. Build a hash table riscv_csr_hash to
1571 store the valid CSR for the chosen pirv verison. Dump the direct
1572 CSR address rather than it's name if it is invalid.
1573 (parse_riscv_dis_option_without_args): New function. Parse the options
1575 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1576 parse the options without arguments first, and then handle the options
1577 with arguments. Add the new option -Mpriv-spec, which has argument.
1578 * riscv-dis.c (print_riscv_disassembler_options): Add description
1579 about the new OBJDUMP option.
1581 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1583 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1584 WC values on POWER10 sync, dcbf and wait instructions.
1585 (insert_pl, extract_pl): New functions.
1586 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1587 (LS3): New , 3-bit L for sync.
1588 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1589 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1590 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1591 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1592 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1593 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1594 <wait>: Enable PL operand on POWER10.
1595 <dcbf>: Enable L3OPT operand on POWER10.
1596 <sync>: Enable SC2 operand on POWER10.
1598 2020-05-19 Stafford Horne <shorne@gmail.com>
1601 * or1k-asm.c: Regenerate.
1602 * or1k-desc.c: Regenerate.
1603 * or1k-desc.h: Regenerate.
1604 * or1k-dis.c: Regenerate.
1605 * or1k-ibld.c: Regenerate.
1606 * or1k-opc.c: Regenerate.
1607 * or1k-opc.h: Regenerate.
1608 * or1k-opinst.c: Regenerate.
1610 2020-05-11 Alan Modra <amodra@gmail.com>
1612 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1615 2020-05-11 Alan Modra <amodra@gmail.com>
1617 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1618 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1620 2020-05-11 Alan Modra <amodra@gmail.com>
1622 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1624 2020-05-11 Alan Modra <amodra@gmail.com>
1626 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1627 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1629 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1631 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1634 2020-05-11 Alan Modra <amodra@gmail.com>
1636 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1637 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1638 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1639 (prefix_opcodes): Add xxeval.
1641 2020-05-11 Alan Modra <amodra@gmail.com>
1643 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1644 xxgenpcvwm, xxgenpcvdm.
1646 2020-05-11 Alan Modra <amodra@gmail.com>
1648 * ppc-opc.c (MP, VXVAM_MASK): Define.
1649 (VXVAPS_MASK): Use VXVA_MASK.
1650 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1651 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1652 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1653 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1655 2020-05-11 Alan Modra <amodra@gmail.com>
1656 Peter Bergner <bergner@linux.ibm.com>
1658 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1660 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1661 YMSK2, XA6a, XA6ap, XB6a entries.
1662 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1663 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1665 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1666 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1667 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1668 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1669 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1670 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1671 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1672 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1673 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1674 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1675 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1676 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1677 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1678 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1680 2020-05-11 Alan Modra <amodra@gmail.com>
1682 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1683 (insert_xts, extract_xts): New functions.
1684 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1685 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1686 (VXRC_MASK, VXSH_MASK): Define.
1687 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1688 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1689 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1690 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1691 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1692 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1693 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1695 2020-05-11 Alan Modra <amodra@gmail.com>
1697 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1698 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1699 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1700 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1701 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1703 2020-05-11 Alan Modra <amodra@gmail.com>
1705 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1706 (XTP, DQXP, DQXP_MASK): Define.
1707 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1708 (prefix_opcodes): Add plxvp and pstxvp.
1710 2020-05-11 Alan Modra <amodra@gmail.com>
1712 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1713 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1714 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1716 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1718 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1720 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1722 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1724 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1726 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1728 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1730 2020-05-11 Alan Modra <amodra@gmail.com>
1732 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1734 2020-05-11 Alan Modra <amodra@gmail.com>
1736 * ppc-dis.c (ppc_opts): Add "power10" entry.
1737 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1738 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1740 2020-05-11 Nick Clifton <nickc@redhat.com>
1742 * po/fr.po: Updated French translation.
1744 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1746 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1747 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1748 (operand_general_constraint_met_p): validate
1749 AARCH64_OPND_UNDEFINED.
1750 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1752 * aarch64-asm-2.c: Regenerated.
1753 * aarch64-dis-2.c: Regenerated.
1754 * aarch64-opc-2.c: Regenerated.
1756 2020-04-29 Nick Clifton <nickc@redhat.com>
1759 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1762 2020-04-29 Nick Clifton <nickc@redhat.com>
1764 * po/sv.po: Updated Swedish translation.
1766 2020-04-29 Nick Clifton <nickc@redhat.com>
1769 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1770 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1771 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1774 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1777 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1778 cmpi only on m68020up and cpu32.
1780 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1782 * aarch64-asm.c (aarch64_ins_none): New.
1783 * aarch64-asm.h (ins_none): New declaration.
1784 * aarch64-dis.c (aarch64_ext_none): New.
1785 * aarch64-dis.h (ext_none): New declaration.
1786 * aarch64-opc.c (aarch64_print_operand): Update case for
1787 AARCH64_OPND_BARRIER_PSB.
1788 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1789 (AARCH64_OPERANDS): Update inserter/extracter for
1790 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1791 * aarch64-asm-2.c: Regenerated.
1792 * aarch64-dis-2.c: Regenerated.
1793 * aarch64-opc-2.c: Regenerated.
1795 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1797 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1798 (aarch64_feature_ras, RAS): Likewise.
1799 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1800 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1801 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1802 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1803 * aarch64-asm-2.c: Regenerated.
1804 * aarch64-dis-2.c: Regenerated.
1805 * aarch64-opc-2.c: Regenerated.
1807 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1809 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1810 (print_insn_neon): Support disassembly of conditional
1813 2020-02-16 David Faust <david.faust@oracle.com>
1815 * bpf-desc.c: Regenerate.
1816 * bpf-desc.h: Likewise.
1817 * bpf-opc.c: Regenerate.
1818 * bpf-opc.h: Likewise.
1820 2020-04-07 Lili Cui <lili.cui@intel.com>
1822 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1823 (prefix_table): New instructions (see prefixes above).
1824 (rm_table): Likewise
1825 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1826 CPU_ANY_TSXLDTRK_FLAGS.
1827 (cpu_flags): Add CpuTSXLDTRK.
1828 * i386-opc.h (enum): Add CpuTSXLDTRK.
1829 (i386_cpu_flags): Add cputsxldtrk.
1830 * i386-opc.tbl: Add XSUSPLDTRK insns.
1831 * i386-init.h: Regenerate.
1832 * i386-tbl.h: Likewise.
1834 2020-04-02 Lili Cui <lili.cui@intel.com>
1836 * i386-dis.c (prefix_table): New instructions serialize.
1837 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1838 CPU_ANY_SERIALIZE_FLAGS.
1839 (cpu_flags): Add CpuSERIALIZE.
1840 * i386-opc.h (enum): Add CpuSERIALIZE.
1841 (i386_cpu_flags): Add cpuserialize.
1842 * i386-opc.tbl: Add SERIALIZE insns.
1843 * i386-init.h: Regenerate.
1844 * i386-tbl.h: Likewise.
1846 2020-03-26 Alan Modra <amodra@gmail.com>
1848 * disassemble.h (opcodes_assert): Declare.
1849 (OPCODES_ASSERT): Define.
1850 * disassemble.c: Don't include assert.h. Include opintl.h.
1851 (opcodes_assert): New function.
1852 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1853 (bfd_h8_disassemble): Reduce size of data array. Correctly
1854 calculate maxlen. Omit insn decoding when insn length exceeds
1855 maxlen. Exit from nibble loop when looking for E, before
1856 accessing next data byte. Move processing of E outside loop.
1857 Replace tests of maxlen in loop with assertions.
1859 2020-03-26 Alan Modra <amodra@gmail.com>
1861 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1863 2020-03-25 Alan Modra <amodra@gmail.com>
1865 * z80-dis.c (suffix): Init mybuf.
1867 2020-03-22 Alan Modra <amodra@gmail.com>
1869 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1870 successflly read from section.
1872 2020-03-22 Alan Modra <amodra@gmail.com>
1874 * arc-dis.c (find_format): Use ISO C string concatenation rather
1875 than line continuation within a string. Don't access needs_limm
1876 before testing opcode != NULL.
1878 2020-03-22 Alan Modra <amodra@gmail.com>
1880 * ns32k-dis.c (print_insn_arg): Update comment.
1881 (print_insn_ns32k): Reduce size of index_offset array, and
1882 initialize, passing -1 to print_insn_arg for args that are not
1883 an index. Don't exit arg loop early. Abort on bad arg number.
1885 2020-03-22 Alan Modra <amodra@gmail.com>
1887 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1888 * s12z-opc.c: Formatting.
1889 (operands_f): Return an int.
1890 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1891 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1892 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1893 (exg_sex_discrim): Likewise.
1894 (create_immediate_operand, create_bitfield_operand),
1895 (create_register_operand_with_size, create_register_all_operand),
1896 (create_register_all16_operand, create_simple_memory_operand),
1897 (create_memory_operand, create_memory_auto_operand): Don't
1898 segfault on malloc failure.
1899 (z_ext24_decode): Return an int status, negative on fail, zero
1901 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1902 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1903 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1904 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1905 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1906 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1907 (loop_primitive_decode, shift_decode, psh_pul_decode),
1908 (bit_field_decode): Similarly.
1909 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1910 to return value, update callers.
1911 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1912 Don't segfault on NULL operand.
1913 (decode_operation): Return OP_INVALID on first fail.
1914 (decode_s12z): Check all reads, returning -1 on fail.
1916 2020-03-20 Alan Modra <amodra@gmail.com>
1918 * metag-dis.c (print_insn_metag): Don't ignore status from
1921 2020-03-20 Alan Modra <amodra@gmail.com>
1923 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1924 Initialize parts of buffer not written when handling a possible
1925 2-byte insn at end of section. Don't attempt decoding of such
1926 an insn by the 4-byte machinery.
1928 2020-03-20 Alan Modra <amodra@gmail.com>
1930 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1931 partially filled buffer. Prevent lookup of 4-byte insns when
1932 only VLE 2-byte insns are possible due to section size. Print
1933 ".word" rather than ".long" for 2-byte leftovers.
1935 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1938 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1940 2020-03-13 Jan Beulich <jbeulich@suse.com>
1942 * i386-dis.c (X86_64_0D): Rename to ...
1943 (X86_64_0E): ... this.
1945 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1947 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1948 * Makefile.in: Regenerated.
1950 2020-03-09 Jan Beulich <jbeulich@suse.com>
1952 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1954 * i386-tbl.h: Re-generate.
1956 2020-03-09 Jan Beulich <jbeulich@suse.com>
1958 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1959 vprot*, vpsha*, and vpshl*.
1960 * i386-tbl.h: Re-generate.
1962 2020-03-09 Jan Beulich <jbeulich@suse.com>
1964 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1965 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1966 * i386-tbl.h: Re-generate.
1968 2020-03-09 Jan Beulich <jbeulich@suse.com>
1970 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1971 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1972 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1973 * i386-tbl.h: Re-generate.
1975 2020-03-09 Jan Beulich <jbeulich@suse.com>
1977 * i386-gen.c (struct template_arg, struct template_instance,
1978 struct template_param, struct template, templates,
1979 parse_template, expand_templates): New.
1980 (process_i386_opcodes): Various local variables moved to
1981 expand_templates. Call parse_template and expand_templates.
1982 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1983 * i386-tbl.h: Re-generate.
1985 2020-03-06 Jan Beulich <jbeulich@suse.com>
1987 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1988 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1989 register and memory source templates. Replace VexW= by VexW*
1991 * i386-tbl.h: Re-generate.
1993 2020-03-06 Jan Beulich <jbeulich@suse.com>
1995 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1996 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1997 * i386-tbl.h: Re-generate.
1999 2020-03-06 Jan Beulich <jbeulich@suse.com>
2001 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2002 * i386-tbl.h: Re-generate.
2004 2020-03-06 Jan Beulich <jbeulich@suse.com>
2006 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2007 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2008 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2009 VexW0 on SSE2AVX variants.
2010 (vmovq): Drop NoRex64 from XMM/XMM variants.
2011 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2012 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2013 applicable use VexW0.
2014 * i386-tbl.h: Re-generate.
2016 2020-03-06 Jan Beulich <jbeulich@suse.com>
2018 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2019 * i386-opc.h (Rex64): Delete.
2020 (struct i386_opcode_modifier): Remove rex64 field.
2021 * i386-opc.tbl (crc32): Drop Rex64.
2022 Replace Rex64 with Size64 everywhere else.
2023 * i386-tbl.h: Re-generate.
2025 2020-03-06 Jan Beulich <jbeulich@suse.com>
2027 * i386-dis.c (OP_E_memory): Exclude recording of used address
2028 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2029 addressed memory operands for MPX insns.
2031 2020-03-06 Jan Beulich <jbeulich@suse.com>
2033 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2034 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2035 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2036 (ptwrite): Split into non-64-bit and 64-bit forms.
2037 * i386-tbl.h: Re-generate.
2039 2020-03-06 Jan Beulich <jbeulich@suse.com>
2041 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2043 * i386-tbl.h: Re-generate.
2045 2020-03-04 Jan Beulich <jbeulich@suse.com>
2047 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2048 (prefix_table): Move vmmcall here. Add vmgexit.
2049 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2050 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2051 (cpu_flags): Add CpuSEV_ES entry.
2052 * i386-opc.h (CpuSEV_ES): New.
2053 (union i386_cpu_flags): Add cpusev_es field.
2054 * i386-opc.tbl (vmgexit): New.
2055 * i386-init.h, i386-tbl.h: Re-generate.
2057 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2059 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2061 * i386-opc.h (IGNORESIZE): New.
2062 (DEFAULTSIZE): Likewise.
2063 (IgnoreSize): Removed.
2064 (DefaultSize): Likewise.
2065 (MnemonicSize): New.
2066 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2068 * i386-opc.tbl (IgnoreSize): New.
2069 (DefaultSize): Likewise.
2070 * i386-tbl.h: Regenerated.
2072 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2075 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2078 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2081 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2082 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2083 * i386-tbl.h: Regenerated.
2085 2020-02-26 Alan Modra <amodra@gmail.com>
2087 * aarch64-asm.c: Indent labels correctly.
2088 * aarch64-dis.c: Likewise.
2089 * aarch64-gen.c: Likewise.
2090 * aarch64-opc.c: Likewise.
2091 * alpha-dis.c: Likewise.
2092 * i386-dis.c: Likewise.
2093 * nds32-asm.c: Likewise.
2094 * nfp-dis.c: Likewise.
2095 * visium-dis.c: Likewise.
2097 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2099 * arc-regs.h (int_vector_base): Make it available for all ARC
2102 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2104 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2107 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2109 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2110 c.mv/c.li if rs1 is zero.
2112 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2114 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2115 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2117 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2118 * i386-opc.h (CpuABM): Removed.
2120 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2121 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2122 popcnt. Remove CpuABM from lzcnt.
2123 * i386-init.h: Regenerated.
2124 * i386-tbl.h: Likewise.
2126 2020-02-17 Jan Beulich <jbeulich@suse.com>
2128 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2129 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2130 VexW1 instead of open-coding them.
2131 * i386-tbl.h: Re-generate.
2133 2020-02-17 Jan Beulich <jbeulich@suse.com>
2135 * i386-opc.tbl (AddrPrefixOpReg): Define.
2136 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2137 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2138 templates. Drop NoRex64.
2139 * i386-tbl.h: Re-generate.
2141 2020-02-17 Jan Beulich <jbeulich@suse.com>
2144 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2145 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2146 into Intel syntax instance (with Unpsecified) and AT&T one
2148 (vcvtneps2bf16): Likewise, along with folding the two so far
2150 * i386-tbl.h: Re-generate.
2152 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2154 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2155 CPU_ANY_SSE4A_FLAGS.
2157 2020-02-17 Alan Modra <amodra@gmail.com>
2159 * i386-gen.c (cpu_flag_init): Correct last change.
2161 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2163 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2166 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2168 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2171 2020-02-14 Jan Beulich <jbeulich@suse.com>
2174 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2175 destination for Cpu64-only variant.
2176 (movzx): Fold patterns.
2177 * i386-tbl.h: Re-generate.
2179 2020-02-13 Jan Beulich <jbeulich@suse.com>
2181 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2182 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2183 CPU_ANY_SSE4_FLAGS entry.
2184 * i386-init.h: Re-generate.
2186 2020-02-12 Jan Beulich <jbeulich@suse.com>
2188 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2189 with Unspecified, making the present one AT&T syntax only.
2190 * i386-tbl.h: Re-generate.
2192 2020-02-12 Jan Beulich <jbeulich@suse.com>
2194 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2195 * i386-tbl.h: Re-generate.
2197 2020-02-12 Jan Beulich <jbeulich@suse.com>
2200 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2201 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2202 Amd64 and Intel64 templates.
2203 (call, jmp): Likewise for far indirect variants. Dro
2205 * i386-tbl.h: Re-generate.
2207 2020-02-11 Jan Beulich <jbeulich@suse.com>
2209 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2210 * i386-opc.h (ShortForm): Delete.
2211 (struct i386_opcode_modifier): Remove shortform field.
2212 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2213 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2214 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2215 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2217 * i386-tbl.h: Re-generate.
2219 2020-02-11 Jan Beulich <jbeulich@suse.com>
2221 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2222 fucompi): Drop ShortForm from operand-less templates.
2223 * i386-tbl.h: Re-generate.
2225 2020-02-11 Alan Modra <amodra@gmail.com>
2227 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2228 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2229 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2230 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2231 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2233 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2235 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2236 (cde_opcodes): Add VCX* instructions.
2238 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2239 Matthew Malcomson <matthew.malcomson@arm.com>
2241 * arm-dis.c (struct cdeopcode32): New.
2242 (CDE_OPCODE): New macro.
2243 (cde_opcodes): New disassembly table.
2244 (regnames): New option to table.
2245 (cde_coprocs): New global variable.
2246 (print_insn_cde): New
2247 (print_insn_thumb32): Use print_insn_cde.
2248 (parse_arm_disassembler_options): Parse coprocN args.
2250 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2253 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2255 * i386-opc.h (AMD64): Removed.
2256 (Intel64): Likewose.
2258 (INTEL64): Likewise.
2259 (INTEL64ONLY): Likewise.
2260 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2261 * i386-opc.tbl (Amd64): New.
2262 (Intel64): Likewise.
2263 (Intel64Only): Likewise.
2264 Replace AMD64 with Amd64. Update sysenter/sysenter with
2265 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2266 * i386-tbl.h: Regenerated.
2268 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2271 * z80-dis.c: Add support for GBZ80 opcodes.
2273 2020-02-04 Alan Modra <amodra@gmail.com>
2275 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2277 2020-02-03 Alan Modra <amodra@gmail.com>
2279 * m32c-ibld.c: Regenerate.
2281 2020-02-01 Alan Modra <amodra@gmail.com>
2283 * frv-ibld.c: Regenerate.
2285 2020-01-31 Jan Beulich <jbeulich@suse.com>
2287 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2288 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2289 (OP_E_memory): Replace xmm_mdq_mode case label by
2290 vex_scalar_w_dq_mode one.
2291 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2293 2020-01-31 Jan Beulich <jbeulich@suse.com>
2295 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2296 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2297 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2298 (intel_operand_size): Drop vex_w_dq_mode case label.
2300 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2302 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2303 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2305 2020-01-30 Alan Modra <amodra@gmail.com>
2307 * m32c-ibld.c: Regenerate.
2309 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2311 * bpf-opc.c: Regenerate.
2313 2020-01-30 Jan Beulich <jbeulich@suse.com>
2315 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2316 (dis386): Use them to replace C2/C3 table entries.
2317 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2318 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2319 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2320 * i386-tbl.h: Re-generate.
2322 2020-01-30 Jan Beulich <jbeulich@suse.com>
2324 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2326 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2328 * i386-tbl.h: Re-generate.
2330 2020-01-30 Alan Modra <amodra@gmail.com>
2332 * tic4x-dis.c (tic4x_dp): Make unsigned.
2334 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2335 Jan Beulich <jbeulich@suse.com>
2338 * i386-dis.c (MOVSXD_Fixup): New function.
2339 (movsxd_mode): New enum.
2340 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2341 (intel_operand_size): Handle movsxd_mode.
2342 (OP_E_register): Likewise.
2344 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2345 register on movsxd. Add movsxd with 16-bit destination register
2346 for AMD64 and Intel64 ISAs.
2347 * i386-tbl.h: Regenerated.
2349 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2352 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2353 * aarch64-asm-2.c: Regenerate
2354 * aarch64-dis-2.c: Likewise.
2355 * aarch64-opc-2.c: Likewise.
2357 2020-01-21 Jan Beulich <jbeulich@suse.com>
2359 * i386-opc.tbl (sysret): Drop DefaultSize.
2360 * i386-tbl.h: Re-generate.
2362 2020-01-21 Jan Beulich <jbeulich@suse.com>
2364 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2366 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2367 * i386-tbl.h: Re-generate.
2369 2020-01-20 Nick Clifton <nickc@redhat.com>
2371 * po/de.po: Updated German translation.
2372 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2373 * po/uk.po: Updated Ukranian translation.
2375 2020-01-20 Alan Modra <amodra@gmail.com>
2377 * hppa-dis.c (fput_const): Remove useless cast.
2379 2020-01-20 Alan Modra <amodra@gmail.com>
2381 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2383 2020-01-18 Nick Clifton <nickc@redhat.com>
2385 * configure: Regenerate.
2386 * po/opcodes.pot: Regenerate.
2388 2020-01-18 Nick Clifton <nickc@redhat.com>
2390 Binutils 2.34 branch created.
2392 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2394 * opintl.h: Fix spelling error (seperate).
2396 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2398 * i386-opc.tbl: Add {vex} pseudo prefix.
2399 * i386-tbl.h: Regenerated.
2401 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2404 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2405 (neon_opcodes): Likewise.
2406 (select_arm_features): Make sure we enable MVE bits when selecting
2407 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2410 2020-01-16 Jan Beulich <jbeulich@suse.com>
2412 * i386-opc.tbl: Drop stale comment from XOP section.
2414 2020-01-16 Jan Beulich <jbeulich@suse.com>
2416 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2417 (extractps): Add VexWIG to SSE2AVX forms.
2418 * i386-tbl.h: Re-generate.
2420 2020-01-16 Jan Beulich <jbeulich@suse.com>
2422 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2423 Size64 from and use VexW1 on SSE2AVX forms.
2424 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2425 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2426 * i386-tbl.h: Re-generate.
2428 2020-01-15 Alan Modra <amodra@gmail.com>
2430 * tic4x-dis.c (tic4x_version): Make unsigned long.
2431 (optab, optab_special, registernames): New file scope vars.
2432 (tic4x_print_register): Set up registernames rather than
2433 malloc'd registertable.
2434 (tic4x_disassemble): Delete optable and optable_special. Use
2435 optab and optab_special instead. Throw away old optab,
2436 optab_special and registernames when info->mach changes.
2438 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2441 * z80-dis.c (suffix): Use .db instruction to generate double
2444 2020-01-14 Alan Modra <amodra@gmail.com>
2446 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2447 values to unsigned before shifting.
2449 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2451 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2453 (print_insn_thumb16, print_insn_thumb32): Likewise.
2454 (print_insn): Initialize the insn info.
2455 * i386-dis.c (print_insn): Initialize the insn info fields, and
2458 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2460 * arc-opc.c (C_NE): Make it required.
2462 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2464 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2465 reserved register name.
2467 2020-01-13 Alan Modra <amodra@gmail.com>
2469 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2470 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2472 2020-01-13 Alan Modra <amodra@gmail.com>
2474 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2475 result of wasm_read_leb128 in a uint64_t and check that bits
2476 are not lost when copying to other locals. Use uint32_t for
2477 most locals. Use PRId64 when printing int64_t.
2479 2020-01-13 Alan Modra <amodra@gmail.com>
2481 * score-dis.c: Formatting.
2482 * score7-dis.c: Formatting.
2484 2020-01-13 Alan Modra <amodra@gmail.com>
2486 * score-dis.c (print_insn_score48): Use unsigned variables for
2487 unsigned values. Don't left shift negative values.
2488 (print_insn_score32): Likewise.
2489 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2491 2020-01-13 Alan Modra <amodra@gmail.com>
2493 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2495 2020-01-13 Alan Modra <amodra@gmail.com>
2497 * fr30-ibld.c: Regenerate.
2499 2020-01-13 Alan Modra <amodra@gmail.com>
2501 * xgate-dis.c (print_insn): Don't left shift signed value.
2502 (ripBits): Formatting, use 1u.
2504 2020-01-10 Alan Modra <amodra@gmail.com>
2506 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2507 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2509 2020-01-10 Alan Modra <amodra@gmail.com>
2511 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2512 and XRREG value earlier to avoid a shift with negative exponent.
2513 * m10200-dis.c (disassemble): Similarly.
2515 2020-01-09 Nick Clifton <nickc@redhat.com>
2518 * z80-dis.c (ld_ii_ii): Use correct cast.
2520 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2523 * z80-dis.c (ld_ii_ii): Use character constant when checking
2526 2020-01-09 Jan Beulich <jbeulich@suse.com>
2528 * i386-dis.c (SEP_Fixup): New.
2530 (dis386_twobyte): Use it for sysenter/sysexit.
2531 (enum x86_64_isa): Change amd64 enumerator to value 1.
2532 (OP_J): Compare isa64 against intel64 instead of amd64.
2533 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2535 * i386-tbl.h: Re-generate.
2537 2020-01-08 Alan Modra <amodra@gmail.com>
2539 * z8k-dis.c: Include libiberty.h
2540 (instr_data_s): Make max_fetched unsigned.
2541 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2542 Don't exceed byte_info bounds.
2543 (output_instr): Make num_bytes unsigned.
2544 (unpack_instr): Likewise for nibl_count and loop.
2545 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2547 * z8k-opc.h: Regenerate.
2549 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2551 * arc-tbl.h (llock): Use 'LLOCK' as class.
2553 (scond): Use 'SCOND' as class.
2555 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2558 2020-01-06 Alan Modra <amodra@gmail.com>
2560 * m32c-ibld.c: Regenerate.
2562 2020-01-06 Alan Modra <amodra@gmail.com>
2565 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2566 Peek at next byte to prevent recursion on repeated prefix bytes.
2567 Ensure uninitialised "mybuf" is not accessed.
2568 (print_insn_z80): Don't zero n_fetch and n_used here,..
2569 (print_insn_z80_buf): ..do it here instead.
2571 2020-01-04 Alan Modra <amodra@gmail.com>
2573 * m32r-ibld.c: Regenerate.
2575 2020-01-04 Alan Modra <amodra@gmail.com>
2577 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2579 2020-01-04 Alan Modra <amodra@gmail.com>
2581 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2583 2020-01-04 Alan Modra <amodra@gmail.com>
2585 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2587 2020-01-03 Jan Beulich <jbeulich@suse.com>
2589 * aarch64-tbl.h (aarch64_opcode_table): Use
2590 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2592 2020-01-03 Jan Beulich <jbeulich@suse.com>
2594 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2595 forms of SUDOT and USDOT.
2597 2020-01-03 Jan Beulich <jbeulich@suse.com>
2599 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2601 * opcodes/aarch64-dis-2.c: Re-generate.
2603 2020-01-03 Jan Beulich <jbeulich@suse.com>
2605 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2607 * opcodes/aarch64-dis-2.c: Re-generate.
2609 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2611 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2613 2020-01-01 Alan Modra <amodra@gmail.com>
2615 Update year range in copyright notice of all files.
2617 For older changes see ChangeLog-2019
2619 Copyright (C) 2020 Free Software Foundation, Inc.
2621 Copying and distribution of this file, with or without modification,
2622 are permitted in any medium without royalty provided the copyright
2623 notice and this notice are preserved.
2629 version-control: never