opcodes/ChangeLog

   1 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * Makefile.am (GUILE): New variable.
   4         (CGEN): Use $(GUILE).
   5         * Makefile.in: Regenerate.
   6
   7 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
   8
   9         * mep-asm.c (macros): Mark static & const.
  10         (lookup_macro): Change return & m to const.
  11         (expand_macro): Change mac to const.
  12         (expand_string): Change pmacro to const.
  13
  14 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  15
  16         * nds32-asm.c (operand_fields): Rename to ...
  17         (nds32_operand_fields): ... this.
  18         (keyword_gpr): Rename to ...
  19         (nds32_keyword_gpr): ... this.
  20         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
  21         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
  22         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
  23         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
  24         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
  25         Mark static.
  26         (keywords): Rename to ...
  27         (nds32_keywords): ... this.
  28         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
  29         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
  30
  31 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  32
  33         * z80-dis.c (opc_ed): Make const.
  34         (pref_ed): Make p const.
  35
  36 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  37
  38         * microblaze-dis.c (get_field_special): Make op const.
  39         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
  40         microblaze_opcodes.
  41         (print_insn_microblaze): Make op & pop const.
  42         (get_insn_microblaze): Make op const.  Rename opcodes to
  43         microblaze_opcodes.
  44         (microblaze_get_target_address): Likewise.
  45         * microblaze-opc.h (struct op_code_struct): Make const.
  46         Rename opcodes to microblaze_opcodes.
  47
  48 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  49
  50         * aarch64-gen.c (aarch64_opcode_table): Add const.
  51         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
  52
  53 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
  54
  55         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
  56         available.
  57
  58 2021-06-22  Alan Modra  <amodra@gmail.com>
  59
  60         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
  61         print separator for pcrel insns.
  62
  63 2021-06-19  Alan Modra  <amodra@gmail.com>
  64
  65         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
  66
  67 2021-06-19  Alan Modra  <amodra@gmail.com>
  68
  69         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
  70         entire buffer.
  71
  72 2021-06-17  Alan Modra  <amodra@gmail.com>
  73
  74         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
  75         in table.
  76
  77 2021-06-03  Alan Modra  <amodra@gmail.com>
  78
  79         PR 1202
  80         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
  81         Use unsigned int for inst.
  82
  83 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
  84
  85         * arc-dis.c (arc_option_arg_t): New enumeration.
  86         (arc_options): New variable.
  87         (disassembler_options_arc): New function.
  88         (print_arc_disassembler_options): Reimplement in terms of
  89         "disassembler_options_arc".
  90
  91 2021-05-29  Alan Modra  <amodra@gmail.com>
  92
  93         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
  94         Don't special case PPC_OPCODE_RAW.
  95         (lookup_prefix): Likewise.
  96         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
  97         (print_insn_powerpc): ..update caller.
  98         * ppc-opc.c (EXT): Define.
  99         (powerpc_opcodes): Mark extended mnemonics with EXT.
 100         (prefix_opcodes, vle_opcodes): Likewise.
 101         (XISEL, XISEL_MASK): Add cr field and simplify.
 102         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 103         all isel variants to where the base mnemonic belongs.  Sort dstt,
 104         dststt and dssall.
 105
 106 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 107
 108         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 109         COP3 opcode instructions.
 110
 111 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 112
 113         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 114         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 115         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 116         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 117         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 118         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 119         "cop2", and "cop3" entries.
 120
 121 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 122
 123         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 124         entries and associated comments.
 125
 126 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 127
 128         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 129         of "c0".
 130
 131 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 132
 133         * mips-dis.c (mips_cp1_names_mips): New variable.
 134         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 135         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 136         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 137         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 138         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 139         "loongson2f".
 140
 141 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 142
 143         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 144         handling code over to...
 145         <OP_REG_CONTROL>: ... this new case.
 146         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 147         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 148         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 149         replacing the `G' operand code with `g'.  Update "cftc1" and
 150         "cftc2" entries replacing the `E' operand code with `y'.
 151         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 152         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 153         entries replacing the `G' operand code with `g'.
 154
 155 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 156
 157         * mips-dis.c (mips_cp0_names_r3900): New variable.
 158         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 159         for "r3900".
 160
 161 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 162
 163         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 164         and "mtthc2" to using the `G' rather than `g' operand code for
 165         the coprocessor control register referred.
 166
 167 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 168
 169         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 170         entries with each other.
 171
 172 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 173
 174         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 175
 176 2021-05-25  Alan Modra  <amodra@gmail.com>
 177
 178         * cris-desc.c: Regenerate.
 179         * cris-desc.h: Regenerate.
 180         * cris-opc.h: Regenerate.
 181         * po/POTFILES.in: Regenerate.
 182
 183 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 184
 185         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 186         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 187         (CGEN_CPUS): Add cris.
 188         (CRIS_DEPS): Define.
 189         (stamp-cris): New rule.
 190         * cgen.sh: Handle desc action.
 191         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 192         * Makefile.in, configure: Regenerate.
 193
 194 2021-05-18  Job Noorman  <mtvec@pm.me>
 195
 196         PR 27814
 197         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 198         the elf objects.
 199
 200 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 201
 202         * arm-dis.c (mve_opcodes): Fix disassembly of
 203         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 204         (is_mve_encoding_conflict): MVE vector loads should not match
 205         when P = W = 0.
 206         (is_mve_unpredictable): It's not unpredictable to use the same
 207         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 208
 209 2021-05-11  Nick Clifton  <nickc@redhat.com>
 210
 211         PR 27840
 212         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 213         the end of the code buffer.
 214
 215 2021-05-06  Stafford Horne  <shorne@gmail.com>
 216
 217         PR 21464
 218         * or1k-asm.c: Regenerate.
 219
 220 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 221
 222         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 223         info->insn_info_valid.
 224
 225 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-opc.tbl (lea): Add Optimize.
 228         * opcodes/i386-tbl.h: Re-generate.
 229
 230 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 231
 232         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 233         of l32r fetch and display referenced literal value.
 234
 235 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 236
 237         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 238         to 4 for literal disassembly.
 239
 240 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 241
 242         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 243         for TLBI instruction.
 244
 245 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 246
 247         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 248         DC instruction.
 249
 250 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 251
 252         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 253         "qualifier".
 254         (convert_mov_to_movewide): Add initializer for "value".
 255
 256 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 257
 258         * aarch64-opc.c: Add RME system registers.
 259
 260 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 261
 262         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 263         "addi d,CV,z" to "c.mv d,CV".
 264
 265 2021-04-12  Alan Modra  <amodra@gmail.com>
 266
 267         * configure.ac (--enable-checking): Add support.
 268         * config.in: Regenerate.
 269         * configure: Regenerate.
 270
 271 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 272
 273         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 274         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 275
 276 2021-04-09  Alan Modra  <amodra@gmail.com>
 277
 278         * ppc-dis.c (struct dis_private): Add "special".
 279         (POWERPC_DIALECT): Delete.  Replace uses with..
 280         (private_data): ..this.  New inline function.
 281         (disassemble_init_powerpc): Init "special" names.
 282         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 283         field of prefix instructions.
 284         (bsearch_reloc, print_got_plt): New functions.
 285         (print_insn_powerpc): For pcrel instructions, print target address
 286         and symbol if known, and decode plt and got loads too.
 287
 288 2021-04-08  Alan Modra  <amodra@gmail.com>
 289
 290         PR 27684
 291         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 292
 293 2021-04-08  Alan Modra  <amodra@gmail.com>
 294
 295         PR 27676
 296         * ppc-opc.c (DCBT_EO): Move earlier.
 297         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 298         (powerpc_operands): Add THCT and THDS entries.
 299         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 300
 301 2021-04-06  Alan Modra  <amodra@gmail.com>
 302
 303         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 304         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 305         symbol_at_address_func.
 306
 307 2021-04-05  Alan Modra  <amodra@gmail.com>
 308
 309         * configure.ac: Don't check for limits.h, string.h, strings.h or
 310         stdlib.h.
 311         (AC_ISC_POSIX): Don't invoke.
 312         * sysdep.h: Include stdlib.h and string.h unconditionally.
 313         * i386-opc.h: Include limits.h unconditionally.
 314         * wasm32-dis.c: Likewise.
 315         * cgen-opc.c: Don't include alloca-conf.h.
 316         * config.in: Regenerate.
 317         * configure: Regenerate.
 318
 319 2021-04-01  Martin Liska  <mliska@suse.cz>
 320
 321         * arm-dis.c (strneq): Remove strneq and use startswith.
 322         * cr16-dis.c (print_insn_cr16): Likewise.
 323         * score-dis.c (streq): Likewise.
 324         (strneq): Likewise.
 325         * score7-dis.c (strneq): Likewise.
 326
 327 2021-04-01  Alan Modra  <amodra@gmail.com>
 328
 329         PR 27675
 330         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 331
 332 2021-03-31  Alan Modra  <amodra@gmail.com>
 333
 334         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 335         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 336         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 337         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 338         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 339         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 340         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 341         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 342         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 343         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 344         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 345         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 346         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 347         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 348         and TRUE with true throughout.
 349
 350 2021-03-31  Alan Modra  <amodra@gmail.com>
 351
 352         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 353         * aarch64-dis.h: Likewise.
 354         * aarch64-opc.c: Likewise.
 355         * avr-dis.c: Likewise.
 356         * csky-dis.c: Likewise.
 357         * nds32-asm.c: Likewise.
 358         * nds32-dis.c: Likewise.
 359         * nfp-dis.c: Likewise.
 360         * riscv-dis.c: Likewise.
 361         * s12z-dis.c: Likewise.
 362         * wasm32-dis.c: Likewise.
 363
 364 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 365
 366         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 367         (i386_seg_prefixes): New.
 368         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 369         (i386_seg_prefixes): Declare.
 370
 371 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 374
 375 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 376
 377         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 378         * i386-reg.tbl (st): Move down.
 379         (st(0)): Delete. Extend comment.
 380         * i386-tbl.h: Re-generate.
 381
 382 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 385         (cmpsd): Move next to cmps.
 386         (movsd): Move next to movs.
 387         (cmpxchg16b): Move to separate section.
 388         (fisttp, fisttpll): Likewise.
 389         (monitor, mwait): Likewise.
 390         * i386-tbl.h: Re-generate.
 391
 392 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 395         (vpsadbw): Add C.
 396         * i386-tbl.h: Re-generate.
 397
 398 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 399
 400         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 401         pclmul, gfni): New templates. Use them wherever possible. Move
 402         SSE4.1 pextrw into respective section.
 403         * i386-tbl.h: Re-generate.
 404
 405 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 408         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 409         "length".
 410         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 411         Convert all of their uses to representation in opcode.
 412
 413 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 414
 415         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 416         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 417         value of None. Shrink operands to 3 bits.
 418
 419 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-gen.c (process_i386_opcode_modifier): New parameter
 422         "space".
 423         (output_i386_opcode): New local variable "space". Adjust
 424         process_i386_opcode_modifier() invocation.
 425         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 426         invocation.
 427         * i386-tbl.h: Re-generate.
 428
 429 2021-03-29  Alan Modra  <amodra@gmail.com>
 430
 431         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 432         (fp_qualifier_p, get_data_pattern): Likewise.
 433         (aarch64_get_operand_modifier_from_value): Likewise.
 434         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 435         (operand_variant_qualifier_p): Likewise.
 436         (qualifier_value_in_range_constraint_p): Likewise.
 437         (aarch64_get_qualifier_esize): Likewise.
 438         (aarch64_get_qualifier_nelem): Likewise.
 439         (aarch64_get_qualifier_standard_value): Likewise.
 440         (get_lower_bound, get_upper_bound): Likewise.
 441         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 442         (aarch64_print_operand): Likewise.
 443         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 444         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 445         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 446         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 447         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 448         (print_insn_tic6x): Likewise.
 449
 450 2021-03-29  Alan Modra  <amodra@gmail.com>
 451
 452         * arc-dis.c (extract_operand_value): Correct NULL cast.
 453         * frv-opc.h: Regenerate.
 454
 455 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 456
 457         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 458         MMX form.
 459         * i386-tbl.h: Re-generate.
 460
 461 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 462
 463         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 464         immediate in br.n instruction.
 465
 466 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 467
 468         * i386-dis.c (XMGatherD, VexGatherD): New.
 469         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 470         (print_insn): Check masking for S/G insns.
 471         (OP_E_memory): New local variable check_gather. Extend mandatory
 472         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 473         Extend check for disallowed 16-bit addressing.
 474         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 475         if()s to switch(). Check register conflicts for (VEX-encoded)
 476         gathers. Drop no longer reachable cases.
 477         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 478         vgatherdp*.
 479
 480 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 481
 482         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 483         zeroing-masking without masking.
 484
 485 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 488         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 489         single-operand forms as deprecated.
 490         * i386-tbl.h: Re-generate.
 491
 492 2021-03-25  Alan Modra  <amodra@gmail.com>
 493
 494         PR 27647
 495         * ppc-opc.c (XLOCB_MASK): Delete.
 496         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 497         XLBH_MASK.
 498         (powerpc_opcodes): Accept a BH field on all extended forms of
 499         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 500
 501 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-gen.c (output_i386_opcode): Drop processing of
 504         opcode_length. Calculate length from base_opcode. Adjust prefix
 505         encoding determination.
 506         (process_i386_opcodes): Drop output of fake opcode_length.
 507         * i386-opc.h (struct insn_template): Drop opcode_length field.
 508         * i386-opc.tbl: Drop opcode length field from all templates.
 509         * i386-tbl.h: Re-generate.
 510
 511 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 514         parameter "prefix". Drop local variable "regular_encoding".
 515         Record prefix setting / check for consistency.
 516         (output_i386_opcode): Parse opcode_length and base_opcode
 517         earlier. Derive prefix encoding. Drop no longer applicable
 518         consistency checking. Adjust process_i386_opcode_modifier()
 519         invocation.
 520         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 521         invocation.
 522         * i386-tbl.h: Re-generate.
 523
 524 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 527         check.
 528         * i386-opc.h (Prefix_*): Move #define-s.
 529         * i386-opc.tbl: Move pseudo prefix enumerator values to
 530         extension opcode field. Introduce pseudopfx template.
 531         * i386-tbl.h: Re-generate.
 532
 533 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 536         comment.
 537         * i386-tbl.h: Re-generate.
 538
 539 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 540
 541         * i386-opc.h (struct insn_template): Move cpu_flags field past
 542         opcode_modifier one.
 543         * i386-tbl.h: Re-generate.
 544
 545 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 546
 547         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 548         * i386-opc.h (OpcodeSpace): New enumerator.
 549         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 550         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 551         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 552         (struct i386_opcode_modifier): New field opcodespace. Shrink
 553         opcodeprefix field.
 554         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 555         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 556         OpcodePrefix uses.
 557         * i386-tbl.h: Re-generate.
 558
 559 2021-03-22  Martin Liska  <mliska@suse.cz>
 560
 561         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 562         * arc-dis.c (parse_option): Likewise.
 563         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 564         * cris-dis.c (print_with_operands): Likewise.
 565         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 566         * i386-dis.c (print_insn): Likewise.
 567         * ia64-gen.c (fetch_insn_class): Likewise.
 568         (parse_resource_users): Likewise.
 569         (in_iclass): Likewise.
 570         (lookup_specifier): Likewise.
 571         (insert_opcode_dependencies): Likewise.
 572         * mips-dis.c (parse_mips_ase_option): Likewise.
 573         (parse_mips_dis_option): Likewise.
 574         * s390-dis.c (disassemble_init_s390): Likewise.
 575         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 576
 577 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 578
 579         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 580
 581 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 582
 583         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 584         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 585
 586 2021-03-12  Alan Modra  <amodra@gmail.com>
 587
 588         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 589
 590 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 591
 592         * i386-dis.c (OP_XMM): Re-order checks.
 593
 594 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 595
 596         * i386-dis.c (putop): Drop need_vex check when also checking
 597         vex.evex.
 598         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 599         checking vex.b.
 600
 601 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 602
 603         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 604         checks. Move case label past broadcast check.
 605
 606 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 607
 608         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 609         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 610         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 611         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 612         EVEX_W_0F38C7_M_0_L_2): Delete.
 613         (REG_EVEX_0F38C7_M_0_L_2): New.
 614         (intel_operand_size): Handle VEX and EVEX the same for
 615         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 616         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 617         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 618         vex_vsib_q_w_d_mode uses.
 619         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 620         0F38A1, and 0F38A3 entries.
 621         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 622         entry.
 623         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 624         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 625         0F38A3 entries.
 626
 627 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 628
 629         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 630         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 631         MOD_VEX_0FXOP_09_12): Rename to ...
 632         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 633         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 634         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 635         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 636         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 637         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 638         (reg_table): Adjust comments.
 639         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 640         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 641         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 642         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 643         (vex_len_table): Adjust opcode 0A_12 entry.
 644         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 645         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 646         (rm_table): Move hreset entry.
 647
 648 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 649
 650         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 651         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 652         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 653         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 654         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 655         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 656         (get_valid_dis386): Also handle 512-bit vector length when
 657         vectoring into vex_len_table[].
 658         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 659         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 660         entries.
 661         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 662         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 663         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 664         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 665         entries.
 666
 667 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 668
 669         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 670         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 671         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 672         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 673         entries.
 674         * i386-dis-evex-len.h (evex_len_table): Likewise.
 675         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 676
 677 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 678
 679         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 680         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 681         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 682         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 683         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 684         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 685         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 686         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 687         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 688         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 689         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 690         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 691         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 692         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 693         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 694         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 695         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 696         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 697         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 698         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 699         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 700         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 701         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 702         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 703         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 704         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 705         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 706         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 707         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 708         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 709         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 710         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 711         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 712         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 713         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 714         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 715         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 716         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 717         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 718         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 719         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 720         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 721         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 722         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 723         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 724         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 725         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 726         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 727         EVEX_W_0F3A43_L_n): New.
 728         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 729         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 730         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 731         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 732         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 733         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 734         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 735         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 736         0F385B, 0F38C6, and 0F38C7 entries.
 737         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 738         0F38C6 and 0F38C7.
 739         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 740         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 741         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 742         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 743
 744 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 745
 746         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 747         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 748         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 749         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 750         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 751         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 752         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 753         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 754         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 755         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 756         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 757         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 758         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 759         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 760         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 761         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 762         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 763         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 764         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 765         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 766         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 767         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 768         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 769         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 770         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 771         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 772         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 773         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 774         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 775         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 776         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 777         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 778         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 779         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 780         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 781         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 782         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 783         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 784         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 785         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 786         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 787         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 788         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 789         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 790         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 791         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 792         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 793         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 794         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 795         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 796         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 797         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 798         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 799         VEX_W_0F99_P_2_LEN_0): Delete.
 800         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 801         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 802         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 803         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 804         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 805         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 806         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 807         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 808         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 809         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 810         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 811         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 812         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 813         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 814         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 815         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 816         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 817         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 818         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 819         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 820         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 821         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 822         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 823         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 824         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 825         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 826         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 827         (prefix_table): No longer link to vex_len_table[] for opcodes
 828         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 829         0F92, 0F93, 0F98, and 0F99.
 830         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 831         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 832         0F98, and 0F99.
 833         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 834         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 835         0F98, and 0F99.
 836         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 837         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 838         0F98, and 0F99.
 839         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 840         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 841         0F98, and 0F99.
 842
 843 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 844
 845         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 846         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 847         REG_VEX_0F73_M_0 respectively.
 848         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 849         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 850         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 851         MOD_VEX_0F73_REG_7): Delete.
 852         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 853         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 854         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 855         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 856         PREFIX_VEX_0F3AF0_L_0 respectively.
 857         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 858         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 859         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 860         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 861         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 862         VEX_LEN_0F38F7): New.
 863         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 864         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 865         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 866         0F38F3.
 867         (prefix_table): No longer link to vex_len_table[] for opcodes
 868         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 869         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 870         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 871         0F38F6, 0F38F7, and 0F3AF0.
 872         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 873         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 874         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 875         0F73.
 876
 877 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 878
 879         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 880         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 881         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 882         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 883         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 884         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 885         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 886         73.
 887         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 888         0F72, and 0F73.
 889         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 890         0F73.
 891
 892 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 893
 894         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 895         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 896         (reg_table): Don't link to mod_table[] where not needed. Add
 897         PREFIX_IGNORED to nop entries.
 898         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 899         (mod_table): Add nop entries next to prefetch ones. Drop
 900         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 901         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 902         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 903         PREFIX_OPCODE from endbr* entries.
 904         (get_valid_dis386): Also consider entry's name when zapping
 905         vindex.
 906         (print_insn): Handle PREFIX_IGNORED.
 907
 908 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 909
 910         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 911         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 912         element.
 913         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 914         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 915         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 916         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 917         (struct i386_opcode_modifier): Delete notrackprefixok,
 918         islockable, hleprefixok, and repprefixok fields. Add prefixok
 919         field.
 920         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 921         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 922         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 923         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 924         Replace HLEPrefixOk.
 925         * opcodes/i386-tbl.h: Re-generate.
 926
 927 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 928
 929         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 930         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 931         64-bit form.
 932         * opcodes/i386-tbl.h: Re-generate.
 933
 934 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 937         for {} instead of {0}. Don't look for '0'.
 938         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 939         size specifiers.
 940
 941 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 942
 943         PR 27158
 944         * riscv-dis.c (print_insn_args): Updated encoding macros.
 945         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 946         (match_c_addi16sp): Updated encoding macros.
 947         (match_c_lui): Likewise.
 948         (match_c_lui_with_hint): Likewise.
 949         (match_c_addi4spn): Likewise.
 950         (match_c_slli): Likewise.
 951         (match_slli_as_c_slli): Likewise.
 952         (match_c_slli64): Likewise.
 953         (match_srxi_as_c_srxi): Likewise.
 954         (riscv_insn_types): Added .insn css/cl/cs.
 955
 956 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 957
 958         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 959         (default_priv_spec): Updated type to riscv_spec_class.
 960         (parse_riscv_dis_option): Updated.
 961         * riscv-opc.c: Moved stuff and make the file tidy.
 962
 963 2021-02-17  Alan Modra  <amodra@gmail.com>
 964
 965         * wasm32-dis.c: Include limits.h.
 966         (CHAR_BIT): Provide backup define.
 967         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 968         Correct signed overflow checking.
 969
 970 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 973         * i386-tbl.h: Re-generate.
 974
 975 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 976
 977         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 978         Oword.
 979         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 980
 981 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 982
 983         * s390-mkopc.c (main): Accept arch14 as cpu string.
 984         * s390-opc.txt: Add new arch14 instructions.
 985
 986 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 987
 988         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 989         favour of LIBINTL.
 990         * configure: Regenerated.
 991
 992 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 993
 994         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 995         * tic54x-opc.c (regs): Rename to ...
 996         (tic54x_regs): ... this.
 997         (mmregs): Rename to ...
 998         (tic54x_mmregs): ... this.
 999         (condition_codes): Rename to ...
1000         (tic54x_condition_codes): ... this.
1001         (cc2_codes): Rename to ...
1002         (tic54x_cc2_codes): ... this.
1003         (cc3_codes): Rename to ...
1004         (tic54x_cc3_codes): ... this.
1005         (status_bits): Rename to ...
1006         (tic54x_status_bits): ... this.
1007         (misc_symbols): Rename to ...
1008         (tic54x_misc_symbols): ... this.
1009
1010 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1011
1012         * riscv-opc.c (MASK_RVB_IMM): Removed.
1013         (riscv_opcodes): Removed zb* instructions.
1014         (riscv_ext_version_table): Removed versions for zb*.
1015
1016 2021-01-26  Alan Modra  <amodra@gmail.com>
1017
1018         * i386-gen.c (parse_template): Ensure entire template_instance
1019         is initialised.
1020
1021 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1022
1023         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1024         (riscv_fpr_names_abi): Likewise.
1025         (riscv_opcodes): Likewise.
1026         (riscv_insn_types): Likewise.
1027
1028 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1029
1030         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1031
1032 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1033
1034         * riscv-dis.c: Comments tidy and improvement.
1035         * riscv-opc.c: Likewise.
1036
1037 2021-01-13  Alan Modra  <amodra@gmail.com>
1038
1039         * Makefile.in: Regenerate.
1040
1041 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1042
1043         PR binutils/26792
1044         * configure.ac: Use GNU_MAKE_JOBSERVER.
1045         * aclocal.m4: Regenerated.
1046         * configure: Likewise.
1047
1048 2021-01-12  Nick Clifton  <nickc@redhat.com>
1049
1050         * po/sr.po: Updated Serbian translation.
1051
1052 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1053
1054         PR ld/27173
1055         * configure: Regenerated.
1056
1057 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1058
1059         * aarch64-asm-2.c: Regenerate.
1060         * aarch64-dis-2.c: Likewise.
1061         * aarch64-opc-2.c: Likewise.
1062         * aarch64-opc.c (aarch64_print_operand):
1063         Delete handling of AARCH64_OPND_CSRE_CSR.
1064         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1065         (CSRE): Likewise.
1066         (_CSRE_INSN): Likewise.
1067         (aarch64_opcode_table): Delete csr.
1068
1069 2021-01-11  Nick Clifton  <nickc@redhat.com>
1070
1071         * po/de.po: Updated German translation.
1072         * po/fr.po: Updated French translation.
1073         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1074         * po/sv.po: Updated Swedish translation.
1075         * po/uk.po: Updated Ukranian translation.
1076
1077 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1078
1079         * configure: Regenerated.
1080
1081 2021-01-09  Nick Clifton  <nickc@redhat.com>
1082
1083         * configure: Regenerate.
1084         * po/opcodes.pot: Regenerate.
1085
1086 2021-01-09  Nick Clifton  <nickc@redhat.com>
1087
1088         * 2.36 release branch crated.
1089
1090 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1091
1092         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1093         (DW, (XRC_MASK): Define.
1094         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1095
1096 2021-01-09  Alan Modra  <amodra@gmail.com>
1097
1098         * configure: Regenerate.
1099
1100 2021-01-08  Nick Clifton  <nickc@redhat.com>
1101
1102         * po/sv.po: Updated Swedish translation.
1103
1104 2021-01-08  Nick Clifton  <nickc@redhat.com>
1105
1106         PR 27129
1107         * aarch64-dis.c (determine_disassembling_preference): Move call to
1108         aarch64_match_operands_constraint outside of the assertion.
1109         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1110         Replace with a return of FALSE.
1111
1112         PR 27139
1113         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1114         core system register.
1115
1116 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1117
1118         * configure: Regenerate.
1119
1120 2021-01-07  Nick Clifton  <nickc@redhat.com>
1121
1122         * po/fr.po: Updated French translation.
1123
1124 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1125
1126         * m68k-opc.c (chkl): Change minimum architecture requirement to
1127         m68020.
1128
1129 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1130
1131         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1132
1133 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1134             Jim Wilson  <jimw@sifive.com>
1135             Andrew Waterman  <andrew@sifive.com>
1136             Maxim Blinov  <maxim.blinov@embecosm.com>
1137             Kito Cheng  <kito.cheng@sifive.com>
1138             Nelson Chu  <nelson.chu@sifive.com>
1139
1140         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1141         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1142
1143 2021-01-01  Alan Modra  <amodra@gmail.com>
1144
1145         Update year range in copyright notice of all files.
1146
1147 For older changes see ChangeLog-2020
1148 \f
1149 Copyright (C) 2021 Free Software Foundation, Inc.
1150
1151 Copying and distribution of this file, with or without modification,
1152 are permitted in any medium without royalty provided the copyright
1153 notice and this notice are preserved.
1154
1155 Local Variables:
1156 mode: change-log
1157 left-margin: 8
1158 fill-column: 74
1159 version-control: never
1160 End: