opcodes/ChangeLog

   1 2020-10-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
   2
   3         * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
   4         * aarch64-asm-2.c: Regenerated.
   5         * aarch64-dis-2.c: Regenerated.
   6         * aarch64-opc-2.c: Regenerated.
   7
   8 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
   9
  10         * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
  11         * aarch64-tbl.h (CSRE): New CSRE feature handler.
  12         (_CSRE_INSN): New CSRE instruction type.
  13         (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
  14         * aarch64-asm-2.c: Regenerated.
  15         * aarch64-dis-2.c: Regenerated.
  16         * aarch64-opc-2.c: Regenerated.
  17
  18 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  19
  20         * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
  21         and operand description.
  22         * aarch64-asm-2.c: Regenerated.
  23         * aarch64-dis-2.c: Regenerated.
  24         * aarch64-opc-2.c: Regenerated.
  25
  26 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
  27
  28         * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
  29
  30 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
  31
  32         * csky-dis.c (csky_output_operand): Add handler for
  33         OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
  34         * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
  35         (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
  36         some instructions for VDSPV1.
  37
  38 2020-10-26  Lili Cui  <lili.cui@intel.com>
  39
  40         * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
  41
  42 2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  43
  44         * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
  45         * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
  46         ins_barrier_dsb_nx.
  47         * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
  48         * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
  49         ext_barrier_dsb_nx.
  50         * aarch64-opc.c (aarch64_print_operand): New options table
  51         aarch64_barrier_dsb_nxs_options.
  52         * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
  53         * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
  54         Armv8.7-a instruction.
  55         * aarch64-asm-2.c: Regenerated.
  56         * aarch64-dis-2.c: Regenerated.
  57         * aarch64-opc-2.c: Regenerated.
  58
  59 2020-10-22  H.J. Lu  <hongjiu.lu@intel.com>
  60
  61         * po/es.po: Remove the duplicated entry.
  62
  63 2020-10-20  Dr. David Alan Gilbert  <dgilbert@redhat.com>
  64
  65         * po/es.po: Fix printf format.
  66
  67 2020-10-20  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
  68
  69         * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
  70         * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
  71         CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
  72         Add CPU_ZNVER3_FLAGS.
  73         (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
  74         * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
  75         * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
  76         rmpupdate, rmpadjust.
  77         * i386-init.h: Re-generated.
  78         * i386-tbl.h: Re-generated.
  79
  80 2020-10-16  Lili Cui  <lili.cui@intel.com>
  81
  82         * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
  83         and move it from cpu_flags to opcode_modifiers.
  84         Use VexW0 and VexVVVV in the AVX-VNNI instructions.
  85         * i386-gen.c: Likewise.
  86         * i386-opc.h: Likewise.
  87         * i386-opc.h: Likewise.
  88         * i386-init.h: Regenerated.
  89         * i386-tbl.h: Likewise.
  90
  91 2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  92
  93         * aarch64-tbl.h (ARMV8_7): New macro.
  94
  95 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  96             Lili Cui  <lili.cui@intel.com>
  97
  98         * i386-dis.c (PREFIX_VEX_0F3850): New.
  99         (PREFIX_VEX_0F3851): Likewise.
 100         (PREFIX_VEX_0F3852): Likewise.
 101         (PREFIX_VEX_0F3853): Likewise.
 102         (VEX_W_0F3850_P_2): Likewise.
 103         (VEX_W_0F3851_P_2): Likewise.
 104         (VEX_W_0F3852_P_2): Likewise.
 105         (VEX_W_0F3853_P_2): Likewise.
 106         (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
 107         PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
 108         (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
 109         VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
 110         (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
 111         * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
 112         CPU_UNKNOWN_FLAGS.  Add CPU_AVX_VNNI_FLAGS and
 113         CPU_ANY_AVX_VNNI_FLAGS.
 114         (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
 115         * i386-opc.h (CpuAVX_VNNI): New.
 116         (CpuVEX_PREFIX): Likewise.
 117         (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
 118         * i386-opc.tbl: Add Intel AVX VNNI instructions.
 119         * i386-init.h: Regenerated.
 120         * i386-tbl.h: Likewise.
 121
 122 2020-10-14  Lili Cui  <lili.cui@intel.com>
 123             H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         * i386-dis.c (PREFIX_0F3A0F): New.
 126         (MOD_0F3A0F_PREFIX_1): Likewise.
 127         (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
 128         (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
 129         (prefix_table): Add PREFIX_0F3A0F.
 130         (mod_table): Add MOD_0F3A0F_PREFIX_1.
 131         (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
 132         (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
 133         * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
 134         CPU_ANY_HRESET_FLAGS.
 135         (cpu_flags): Add CpuHRESET.
 136         (output_i386_opcode): Allow 4 byte base_opcode.
 137         * i386-opc.h (enum): Add CpuHRESET.
 138         (i386_cpu_flags): Add cpuhreset.
 139         * i386-opc.tbl: Add Intel HRESET instruction.
 140         * i386-init.h: Regenerate.
 141         * i386-tbl.h: Likewise.
 142
 143 2020-10-14  Lili Cui  <lili.cui@intel.com>
 144
 145         * i386-dis.c (enum): Add
 146         PREFIX_MOD_3_0F01_REG_5_RM_4,
 147         PREFIX_MOD_3_0F01_REG_5_RM_5,
 148         PREFIX_MOD_3_0F01_REG_5_RM_6,
 149         PREFIX_MOD_3_0F01_REG_5_RM_7,
 150         X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
 151         X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
 152         X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
 153         X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
 154         X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
 155         (prefix_table): New instructions (see prefixes above).
 156         (rm_table): Likewise
 157         * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
 158         CPU_ANY_UINTR_FLAGS.
 159         (cpu_flags): Add CpuUINTR.
 160         * i386-opc.h (enum): Add CpuUINTR.
 161         (i386_cpu_flags): Add cpuuintr.
 162         * i386-opc.tbl: Add UINTR insns.
 163         * i386-init.h: Regenerate.
 164         * i386-tbl.h: Likewise.
 165
 166 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 167
 168         * i386-gen.c (process_i386_opcode_modifier): Return 1 for
 169         non-VEX/EVEX/prefix encoding.
 170         (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
 171         has a prefix byte.
 172         * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
 173         base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
 174         * i386-tbl.h: Regenerated.
 175
 176 2020-10-13  H.J. Lu  <hongjiu.lu@intel.com>
 177
 178         * i386-gen.c (opcode_modifiers): Replace VexOpcode with
 179         OpcodePrefix.
 180         * i386-opc.h (VexOpcode): Renamed to ...
 181         (OpcodePrefix): This.
 182         (PREFIX_NONE): New.
 183         (PREFIX_0X66): Likewise.
 184         (PREFIX_0XF2): Likewise.
 185         (PREFIX_0XF3): Likewise.
 186         * i386-opc.tbl (Prefix_0X66): New.
 187         (Prefix_0XF2): Likewise.
 188         (Prefix_0XF3): Likewise.
 189         Replace VexOpcode= with OpcodePrefix=.  Use Prefix_0X66 on xorpd.
 190         Use Prefix_0XF3 on cvtdq2pd.  Use Prefix_0XF2 on cvtpd2dq.
 191         * i386-tbl.h: Regenerated.
 192
 193 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 194
 195         * aarch64-opc.c: Add BRBE system registers.
 196
 197 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 198
 199         * aarch64-opc.c: New CSRE system registers defined.
 200
 201 2020-10-05  Samanta Navarro  <ferivoz@riseup.net>
 202
 203         * cgen-asm.c: Fix spelling mistakes.
 204         * cgen-dis.c: Fix spelling mistakes.
 205         * tic30-dis.c: Fix spelling mistakes.
 206
 207 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 208
 209         PR binutils/26704
 210         * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
 211
 212 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         PR binutils/26705
 215         * i386-dis.c (print_insn): Clear modrm if not needed.
 216         (putop): Check need_modrm for modrm.mod != 3.  Don't check
 217         need_modrm for modrm.mod == 3.
 218
 219 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 220
 221         * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
 222         TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
 223         TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
 224         TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
 225         TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
 226         TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
 227         TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
 228         TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
 229         WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
 230         TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
 231         TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
 232         TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR, TRCVDARCCTLR,
 233         TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
 234         TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
 235
 236 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 237
 238         * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
 239
 240 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 241
 242         * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
 243         TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
 244
 245 2020-09-26  Alan Modra  <amodra@gmail.com>
 246
 247         * csky-opc.h: Formatting.
 248         (GENERAL_REG_BANK): Correct spelling.  Update use throughout file.
 249         (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
 250         and shift 1u.
 251         (get_register_number): Likewise.
 252         * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
 253
 254 2020-09-24  Lili Cui  <lili.cui@intel.com>
 255
 256         PR 26654
 257         * i386-dis.c (enum): Put MOD_VEX_0F38* together.
 258
 259 2020-09-24  Andrew Burgess <andrew.burgess@embecosm.com>
 260
 261         * csky-dis.c (csky_output_operand): Enclose body of if in curly
 262         braces.
 263
 264 2020-09-24  Lili Cui  <lili.cui@intel.com>
 265
 266         * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
 267         PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
 268         X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
 269         X86_64_0F01_REG_1_RM_7_P_2.
 270         (prefix_table): Likewise.
 271         (x86_64_table): Likewise.
 272         (rm_table): Likewise.
 273         * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
 274         and CPU_ANY_TDX_FLAGS.
 275         (cpu_flags): Add CpuTDX.
 276         * i386-opc.h (enum): Add CpuTDX.
 277         (i386_cpu_flags): Add cputdx.
 278         * i386-opc.tbl: Add TDX insns.
 279         * i386-init.h: Regenerate.
 280         * i386-tbl.h: Likewise.
 281
 282 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
 283
 284         * csky-dis.c (using_abi): New.
 285         (parse_csky_dis_options): New function.
 286         (get_gr_name): New function.
 287         (get_cr_name): New function.
 288         (csky_output_operand): Use get_gr_name and get_cr_name to
 289         disassemble and add handle of OPRND_TYPE_IMM5b_LS.
 290         (print_insn_csky): Parse disassembler options.
 291         * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
 292         (GENARAL_REG_BANK): Define.
 293         (REG_SUPPORT_ALL): Define.
 294         (REG_SUPPORT_ALL): New.
 295         (ASH): Define.
 296         (REG_SUPPORT_A): Define.
 297         (REG_SUPPORT_B): Define.
 298         (REG_SUPPORT_C): Define.
 299         (REG_SUPPORT_D): Define.
 300         (REG_SUPPORT_E): Define.
 301         (csky_abiv1_general_regs): New.
 302         (csky_abiv1_control_regs): New.
 303         (csky_abiv2_general_regs): New.
 304         (csky_abiv2_control_regs): New.
 305         (get_register_name): New function.
 306         (get_register_number): New function.
 307         (csky_get_general_reg_name): New function.
 308         (csky_get_general_regno): New function.
 309         (csky_get_control_reg_name): New function.
 310         (csky_get_control_regno): New function.
 311         (csky_v2_opcodes): Prefer two oprerans format for bclri and
 312         bseti, strengthen the operands legality check of addc, zext
 313         and sext.
 314
 315 2020-09-23  Lili Cui  <lili.cui@intel.com>
 316
 317         * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
 318         MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
 319         MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
 320         MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
 321         PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
 322         (reg_table): New instructions (see prefixes above).
 323         (prefix_table): Likewise.
 324         (three_byte_table): Likewise.
 325         (mod_table): Likewise
 326         * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
 327         CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
 328         (cpu_flags): Likewise.
 329         (operand_type_init): Likewise.
 330         * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
 331         (i386_cpu_flags): Add cpukl and cpuwide_kl.
 332         * i386-opc.tbl: Add KL and WIDE_KL insns.
 333         * i386-init.h: Regenerate.
 334         * i386-tbl.h: Likewise.
 335
 336 2020-09-21  Alan Modra  <amodra@gmail.com>
 337
 338         * rx-dis.c (flag_names): Add missing comma.
 339         (register_names, flag_names, double_register_names),
 340         (double_register_high_names, double_register_low_names),
 341         (double_control_register_names, double_condition_names): Remove
 342         trailing commas.
 343
 344 2020-09-18  David Faust  <david.faust@oracle.com>
 345
 346         * bpf-desc.c: Regenerate.
 347         * bpf-desc.h: Likewise.
 348         * bpf-opc.c: Likewise.
 349         * bpf-opc.h: Likewise.
 350
 351 2020-09-16  Andrew Burgess <andrew.burgess@embecosm.com>
 352
 353         * csky-dis.c (csky_get_disassembler): Don't return NULL when there
 354         is no BFD.
 355
 356 2020-09-16  Alan Modra  <amodra@gmail.com>
 357
 358         * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
 359
 360 2020-09-10  Nick Clifton  <nickc@redhat.com>
 361
 362         * ppc-dis.c (ppc_symbol_is_valid): New function.  Returns false
 363         for hidden, local, no-type symbols.
 364         (disassemble_init_powerpc): Point the symbol_is_valid field in the
 365         info structure at the new function.
 366
 367 2020-09-10  Cooper Qu  <cooper.qu@linux.alibaba.com>
 368
 369         * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
 370         * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
 371         opcode fixing.
 372
 373 2020-09-10  Nick Clifton  <nickc@redhat.com>
 374
 375         * csky-dis.c (csky_output_operand): Coerce the immediate values to
 376         long before printing.
 377
 378 2020-09-10  Alan Modra  <amodra@gmail.com>
 379
 380         * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
 381
 382 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 383
 384         * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
 385         ISA flag.
 386
 387 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 388
 389         * csky-dis.c (csky_output_operand): Add handlers for
 390         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 391         OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
 392         to support FPUV3 instructions.
 393         * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
 394         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 395         OPRND_TYPE_DFLOAT_FMOVI.
 396         (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
 397          OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
 398          OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
 399          OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
 400          OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
 401          OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
 402          OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
 403          OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
 404          OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
 405          OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
 406          OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
 407          OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
 408          OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
 409         (csky_v2_opcodes): Add FPUV3 instructions.
 410
 411 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 412
 413         * aarch64-dis.c (print_operands): Pass CPU features to
 414         aarch64_print_operand().
 415         * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
 416         preferred disassembly of system registers.
 417         (SR_RNG): Refactor to use new SR_FEAT2 macro.
 418         (SR_FEAT2): New.
 419         (SR_V8_1_A): New.
 420         (SR_V8_4_A): New.
 421         (SR_V8_A): New.
 422         (SR_V8_R): New.
 423         (SR_EXPAND_ELx): New.
 424         (SR_EXPAND_EL12): New.
 425         (aarch64_sys_regs): Specify which registers are only on
 426         A-profile, add R-profile system registers.
 427         (ENC_BARLAR): New.
 428         (PRBARn_ELx): New.
 429         (PRLARn_ELx): New.
 430         (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
 431         Armv8-R AArch64.
 432
 433 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 434
 435         * aarch64-tbl.h (aarch64_feature_v8_r): New.
 436         (ARMV8_R): New.
 437         (V8_R_INSN): New.
 438         (aarch64_opcode_table): Add dfb.
 439         * aarch64-opc-2.c: Regenerate.
 440         * aarch64-asm-2.c: Regenerate.
 441         * aarch64-dis-2.c: Regenerate.
 442
 443 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 444
 445         * aarch64-dis.c (arch_variant): New.
 446         (determine_disassembling_preference): Disassemble according to
 447         arch variant.
 448         (select_aarch64_variant): New.
 449         (print_insn_aarch64): Set feature set.
 450
 451 2020-09-02  Alan Modra  <amodra@gmail.com>
 452
 453         * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
 454         (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
 455         (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
 456         (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
 457         (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
 458         (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
 459         (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
 460         for value parameter and update code to suit.
 461         (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
 462         (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
 463
 464 2020-09-02  Alan Modra  <amodra@gmail.com>
 465
 466         * i386-dis.c (OP_E_memory): Don't cast to signed type when
 467         negating.
 468         (get32, get32s): Use unsigned types in shift expressions.
 469
 470 2020-09-02  Alan Modra  <amodra@gmail.com>
 471
 472         * csky-dis.c (print_insn_csky): Use unsigned type for "given".
 473
 474 2020-09-02  Alan Modra  <amodra@gmail.com>
 475
 476         * crx-dis.c: Whitespace.
 477         (print_arg): Use unsigned type for longdisp and mask variables,
 478         and for left shift constant.
 479
 480 2020-09-02  Alan Modra  <amodra@gmail.com>
 481
 482         * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
 483         * bpf-ibld.c: Regenerate.
 484         * epiphany-ibld.c: Regenerate.
 485         * fr30-ibld.c: Regenerate.
 486         * frv-ibld.c: Regenerate.
 487         * ip2k-ibld.c: Regenerate.
 488         * iq2000-ibld.c: Regenerate.
 489         * lm32-ibld.c: Regenerate.
 490         * m32c-ibld.c: Regenerate.
 491         * m32r-ibld.c: Regenerate.
 492         * mep-ibld.c: Regenerate.
 493         * mt-ibld.c: Regenerate.
 494         * or1k-ibld.c: Regenerate.
 495         * xc16x-ibld.c: Regenerate.
 496         * xstormy16-ibld.c: Regenerate.
 497
 498 2020-09-02  Alan Modra  <amodra@gmail.com>
 499
 500         * bfin-dis.c (MASKBITS): Use SIGNBIT.
 501
 502 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 503
 504         * csky-opc.h (csky_v2_opcodes): Move divul and divsl
 505         to CSKYV2_ISA_3E3R3 instruction set.
 506
 507 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 508
 509         * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
 510
 511 2020-09-01  Alan Modra  <amodra@gmail.com>
 512
 513         * mep-ibld.c: Regenerate.
 514
 515 2020-08-31  Cooper Qu  <cooper.qu@linux.alibaba.com>
 516
 517         * csky-dis.c (csky_output_operand): Assign dis_info.value for
 518         OPRND_TYPE_VREG.
 519
 520 2020-08-30  Alan Modra  <amodra@gmail.com>
 521
 522         * cr16-dis.c: Formatting.
 523         (parameter): Delete struct typedef.  Use dwordU instead
 524         throughout file.
 525         (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
 526         and tbitb.
 527         (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
 528
 529 2020-08-29  Alan Modra  <amodra@gmail.com>
 530
 531         PR 26446
 532         * csky-opc.h (MAX_OPRND_NUM): Define to 5.
 533         (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
 534
 535 2020-08-28  Alan Modra  <amodra@gmail.com>
 536
 537         PR 26449
 538         PR 26450
 539         * cgen-ibld.in (insert_1): Use 1UL in forming mask.
 540         (extract_normal): Likewise.
 541         (insert_normal): Likewise, and move past zero length test.
 542         (put_insn_int_value): Handle mask for zero length, use 1UL.
 543         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 544         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 545         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 546         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 547
 548 2020-08-28  Cooper Qu  <cooper.qu@linux.alibaba.com>
 549
 550         * csky-dis.c (CSKY_DEFAULT_ISA): Define.
 551         (csky_dis_info): Add member isa.
 552         (csky_find_inst_info): Skip instructions that do not belong to
 553         current CPU.
 554         (csky_get_disassembler): Get infomation from attribute section.
 555         (print_insn_csky): Set defualt ISA flag.
 556         * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
 557         * csky-opc.h (struct csky_opcode): Change isa_flag16 and
 558         isa_flag32'type to unsigned 64 bits.
 559
 560 2020-08-26  Jose E. Marchesi  <jemarch@gnu.org>
 561
 562         * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
 563
 564 2020-08-26  David Faust  <david.faust@oracle.com>
 565
 566         * bpf-desc.c: Regenerate.
 567         * bpf-desc.h: Likewise.
 568         * bpf-opc.c: Likewise.
 569         * bpf-opc.h: Likewise.
 570         * disassemble.c (disassemble_init_for_target): Set bits for xBPF
 571         ISA when appropriate.
 572
 573 2020-08-25  Alan Modra  <amodra@gmail.com>
 574
 575         PR 26504
 576         * vax-dis.c (parse_disassembler_options): Always add at least one
 577         to entry_addr_total_slots.
 578
 579 2020-08-24  Cooper Qu  <cooper.qu@linux.alibaba.com>
 580
 581         * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
 582         in other CPUs to speed up disassembling.
 583         * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
 584         Change plsli.u16 to plsli.16, change sync's operand format.
 585
 586 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 587
 588         * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
 589
 590 2020-08-21  Nick Clifton  <nickc@redhat.com>
 591
 592         * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
 593         symbols.
 594
 595 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 596
 597         * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
 598
 599 2020-08-19  Alan Modra  <amodra@gmail.com>
 600
 601         * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
 602         vcmpuq and xvtlsbb.
 603
 604 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
 605
 606         * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
 607         <xvcvbf16spn>: ...to this.
 608
 609 2020-08-12  Alex Coplan  <alex.coplan@arm.com>
 610
 611         * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
 612
 613 2020-08-12  Nick Clifton  <nickc@redhat.com>
 614
 615         * po/sr.po: Updated Serbian translation.
 616
 617 2020-08-11  Alan Modra  <amodra@gmail.com>
 618
 619         * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
 620
 621 2020-08-10  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 622
 623         * aarch64-opc.c (aarch64_print_operand):
 624         (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
 625         (aarch64_sys_reg_supported_p): Function removed.
 626         (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
 627         (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
 628         into this function.
 629
 630 2020-08-10  Alan Modra  <amodra@gmail.com>
 631
 632         * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
 633         instructions.
 634
 635 2020-08-10  Alan Modra  <amodra@gmail.com>
 636
 637         * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
 638         Enable icbt for power5, miso for power8.
 639
 640 2020-08-10  Alan Modra  <amodra@gmail.com>
 641
 642         * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
 643         mtvsrd, and similarly for mfvsrd.
 644
 645 2020-08-04  Christian Groessler  <chris@groessler.org>
 646             Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
 647
 648         * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
 649         opcodes (special "out" to absolute address).
 650         * z8k-opc.h: Regenerate.
 651
 652 2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 653
 654         PR gas/26305
 655         * i386-opc.h (Prefix_Disp8): New.
 656         (Prefix_Disp16): Likewise.
 657         (Prefix_Disp32): Likewise.
 658         (Prefix_Load): Likewise.
 659         (Prefix_Store): Likewise.
 660         (Prefix_VEX): Likewise.
 661         (Prefix_VEX3): Likewise.
 662         (Prefix_EVEX): Likewise.
 663         (Prefix_REX): Likewise.
 664         (Prefix_NoOptimize): Likewise.
 665         * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
 666         * i386-tbl.h: Regenerated.
 667
 668 2020-07-29  Andreas Arnez  <arnez@linux.ibm.com>
 669
 670         * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
 671         default case with abort() instead of printing an error message and
 672         continuing, to avoid a maybe-uninitialized warning.
 673
 674 2020-07-24  Nick Clifton  <nickc@redhat.com>
 675
 676         * po/de.po: Updated German translation.
 677
 678 2020-07-21  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-dis.c (OP_E_memory): Revert previous change.
 681
 682 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 683
 684         PR gas/26237
 685         * i386-dis.c (OP_E_memory): Don't display eiz with no scale
 686         without base nor index registers.
 687
 688 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 689
 690         * i386-dis.c (putop): Move 'V' and 'W' handling.
 691
 692 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-dis.c (dis386): Adjust 'V' description. Use P-based
 695         construct for push/pop of register.
 696         (putop): Honor cond when handling 'P'. Drop handling of plain
 697         'V'.
 698
 699 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 700
 701         * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
 702         description. Drop '&' description. Use P for push of immediate,
 703         pushf/popf, enter, and leave. Use %LP for lret/retf.
 704         (dis386_twobyte): Use P for push/pop of fs/gs.
 705         (reg_table): Use P for push/pop. Use @ for near call/jmp.
 706         (x86_64_table): Use P for far call/jmp.
 707         (putop): Drop handling of 'U' and '&'. Move and adjust handling
 708         of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
 709         labels.
 710         (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
 711         and dqw_mode (unconditional).
 712
 713 2020-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 714
 715         PR gas/26237
 716         * i386-dis.c (OP_E_memory): Without base nor index registers,
 717         32-bit displacement to 64 bits.
 718
 719 2020-07-14  Claudiu Zissulescu  <claziss@gmail.com>
 720
 721         * arc-dis.c (print_insn_arc): Detect and emit a warning when a
 722         faulty double register pair is detected.
 723
 724 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 725
 726         * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
 727
 728 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-dis.c (OP_R, Rm): Delete.
 731         (MOD_0F24, MOD_0F26): Rename to ...
 732         (X86_64_0F24, X86_64_0F26): ... respectively.
 733         (dis386): Update 'L' and 'Z' comments.
 734         (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
 735         table references.
 736         (mod_table): Move opcode 0F24 and 0F26 entries ...
 737         (x86_64_table): ... here.
 738         (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
 739         'Z' case block.
 740
 741 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 742
 743         * i386-dis.c (Rd, Rdq, MaskR): Delete.
 744         (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
 745         MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
 746         MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
 747         MOD_EVEX_0F387C): New enumerators.
 748         (reg_table): Use Edq for rdssp.
 749         (prefix_table): Use Edq for incssp.
 750         (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
 751         kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
 752         ktest*, and kshift*. Use Edq / MaskE for kmov*.
 753         * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
 754         * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
 755         0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
 756         * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
 757         0F3828_P_1 and 0F3838_P_1.
 758         * i386-dis-evex-w.h: Reference mod_table[] for opcodes
 759         0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
 760
 761 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
 764         PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
 765         PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
 766         PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
 767         PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
 768         PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
 769         (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
 770         VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
 771         VEX_LEN_0F38F3_R_3_P_0): Rename to ...
 772         (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
 773         VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
 774         (reg_table, prefix_table, three_byte_table, vex_table,
 775         vex_len_table, mod_table, rm_table): Replace / remove respective
 776         entries.
 777         (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
 778         of PREFIX_DATA in used_prefixes.
 779
 780 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 781
 782         * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
 783         MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
 784         MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
 785         MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
 786         (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
 787         MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
 788         (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
 789         VEX_W_0F3A33_L_0): Delete.
 790         (dis386): Adjust "BW" description.
 791         (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
 792         0F3A31, 0F3A32, and 0F3A33.
 793         (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 794         entries.
 795         (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 796         entries.
 797
 798 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 799
 800         * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
 801         PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
 802         PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
 803         PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
 804         PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
 805         PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
 806         PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
 807         PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
 808         PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
 809         PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
 810         PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
 811         PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
 812         PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
 813         PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
 814         PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
 815         PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
 816         PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
 817         PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
 818         PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
 819         PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
 820         PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
 821         PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
 822         PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
 823         PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
 824         PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
 825         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 826         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 827         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
 828         PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
 829         PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 830         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 831         PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
 832         PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
 833         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 834         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 835         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 836         PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
 837         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 838         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 839         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
 840         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 841         PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
 842         PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
 843         PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
 844         PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
 845         PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
 846         PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
 847         PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
 848         PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
 849         PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
 850         PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
 851         PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
 852         PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
 853         PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
 854         PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
 855         PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
 856         PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
 857         PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 858         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 859         PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
 860         PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
 861         PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
 862         PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
 863         PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
 864         PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
 865         PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
 866         PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
 867         PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
 868         PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
 869         PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
 870         PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
 871         PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
 872         PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
 873         PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
 874         PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
 875         PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
 876         PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
 877         PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
 878         PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
 879         PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
 880         PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
 881         PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
 882         PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
 883         PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
 884         PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
 885         PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
 886         PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
 887         PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
 888         PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
 889         PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
 890         PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
 891         PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
 892         PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
 893         PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
 894         PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
 895         PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
 896         PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
 897         PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
 898         PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
 899         PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
 900         PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
 901         PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
 902         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
 903         PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
 904         PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
 905         PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 906         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 907         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 908         PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
 909         PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
 910         PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 911         PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
 912         PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
 913         PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
 914         PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
 915         PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
 916         PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 917         PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
 918         PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
 919         PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
 920         PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
 921         PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
 922         PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
 923         PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
 924         PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
 925         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
 926         PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
 927         PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
 928         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
 929         PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
 930         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 931         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
 932         PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
 933         PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
 934         PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
 935         PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
 936         PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
 937         PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
 938         PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
 939         PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
 940         PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
 941         PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
 942         PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
 943         PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
 944         PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
 945         PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
 946         PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
 947         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
 948         PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
 949         PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
 950         PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
 951         PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
 952         PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
 953         PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
 954         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 955         PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 956         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
 957         (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
 958         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 959         MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
 960         MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
 961         MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
 962         MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
 963         MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 964         MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 965         MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 966         MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 967         MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
 968         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
 969         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
 970         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
 971         MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
 972         VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
 973         VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
 974         VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
 975         VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
 976         VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
 977         VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
 978         VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
 979         VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
 980         VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
 981         VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
 982         VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
 983         VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
 984         VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
 985         EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
 986         EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
 987         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
 988         EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
 989         EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
 990         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
 991         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
 992         EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
 993         EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
 994         EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
 995         EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
 996         EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
 997         EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
 998         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
 999         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1000         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
1001         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1002         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1003         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1004         EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
1005         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
1006         EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
1007         EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
1008         EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
1009         EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
1010         EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
1011         EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
1012         VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
1013         VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
1014         VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
1015         VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
1016         VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
1017         VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
1018         VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
1019         VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
1020         VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
1021         VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
1022         VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
1023         VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
1024         VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
1025         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
1026         VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
1027         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
1028         VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
1029         VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
1030         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
1031         EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
1032         EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
1033         EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
1034         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
1035         EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
1036         EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
1037         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
1038         EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
1039         EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
1040         EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
1041         EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
1042         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
1043         EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
1044         EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
1045         EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
1046         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
1047         EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
1048         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
1049         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
1050         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
1051         EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1052         EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
1053         EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1054         EVEX_W_0F3A72_P_2): Rename to ...
1055         (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1056         MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1057         MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1058         MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1059         MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1060         MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1061         MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1062         MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1063         MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1064         MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1065         MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1066         VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1067         VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1068         VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1069         VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1070         VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1071         VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1072         VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1073         VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1074         VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1075         EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1076         EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1077         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1078         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1079         EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1080         EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1081         EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1082         EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1083         EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1084         EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1085         EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1086         EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1087         EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1088         EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1089         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1090         EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1091         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1092         EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1093         EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1094         EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1095         EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1096         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1097         EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1098         EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1099         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1100         VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1101         VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1102         VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1103         VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1104         VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1105         VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1106         VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1107         VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1108         VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1109         VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1110         VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1111         VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1112         VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1113         EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1114         EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1115         EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1116         EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1117         EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1118         EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1119         EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1120         EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1121         EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1122         EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1123         EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1124         EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1125         EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1126         EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1127         respectively.
1128         (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1129         vex_w_table, mod_table): Replace / remove respective entries.
1130         (print_insn): Move up dp->prefix_requirement handling. Handle
1131         PREFIX_DATA.
1132         * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1133         i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1134         Replace / remove respective entries.
1135
1136 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1137
1138         * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1139         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1140         (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1141         vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1142         Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1143         the latter two.
1144         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1145         0F2C, 0F2D, 0F2E, and 0F2F.
1146         * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1147         0F2F table entries.
1148
1149 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1150
1151         * i386-dis.c (OP_VexR, VexScalarR): New.
1152         (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1153         XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1154         need_vex_reg): Delete.
1155         (prefix_table): Replace VexScalar by VexScalarR and
1156         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1157         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1158         (vex_len_table): Replace EXqVexScalarS by EXqS.
1159         (get_valid_dis386): Don't set need_vex_reg.
1160         (print_insn): Don't initialize need_vex_reg.
1161         (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1162         q_scalar_swap_mode cases.
1163         (OP_EX): Don't check for d_scalar_swap_mode and
1164         q_scalar_swap_mode.
1165         (OP_VEX): Done check need_vex_reg.
1166         * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1167         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1168         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1169
1170 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1171
1172         * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1173         (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1174         VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1175         VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1176         (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1177         VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1178         VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1179         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1180         (vex_table): Replace Vex128 by Vex.
1181         (vex_len_table): Likewise. Adjust referenced enum names.
1182         (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1183         referenced enum names.
1184         (OP_VEX): Drop vex128_mode and vex256_mode cases.
1185         * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1186
1187 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1188
1189         * i386-dis.c (dis386): "LW" description now applies to "DQ".
1190         (putop): Handle "DQ". Don't handle "LW" anymore.
1191         (prefix_table, mod_table): Replace %LW by %DQ.
1192         * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1193
1194 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1195
1196         * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1197         dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1198         d_scalar_swap_mode case handling. Move shift adjsutment into
1199         the case its applicable to.
1200
1201 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1204         (EXbScalar, EXwScalar): Fold to ...
1205         (EXbwUnit): ... this.
1206         (b_scalar_mode, w_scalar_mode): Fold to ...
1207         (bw_unit_mode): ... this.
1208         (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1209         w_scalar_mode handling by bw_unit_mode one.
1210         * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1211         ...
1212         * i386-dis-evex-prefix.h: ... here.
1213
1214 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1215
1216         * i386-dis.c (PCMPESTR_Fixup): Delete.
1217         (dis386): Adjust "LQ" description.
1218         (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1219         cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1220         PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1221         vpcmpestrm, and vpcmpestri.
1222         (putop): Honor "cond" when handling LQ.
1223         * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1224         vcvtsi2ss and vcvtusi2ss.
1225         * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1226         vcvtsi2sd and vcvtusi2sd.
1227
1228 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1229
1230         * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1231         (simd_cmp_op): Add const.
1232         (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1233         (CMP_Fixup): Handle VEX case.
1234         (prefix_table): Replace VCMP by CMP.
1235         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1236
1237 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1238
1239         * i386-dis.c (MOVBE_Fixup): Delete.
1240         (Mv): Define.
1241         (prefix_table): Use Mv for movbe entries.
1242
1243 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1244
1245         * i386-dis.c (CRC32_Fixup): Delete.
1246         (prefix_table): Use Eb/Ev for crc32 entries.
1247
1248 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1249
1250         * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1251         Conditionalize invocations of "USED_REX (0)".
1252
1253 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1256         CH, DH, BH, AX, DX): Delete.
1257         (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1258         eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1259         dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1260
1261 2020-07-10  Lili Cui  <lili.cui@intel.com>
1262
1263         * i386-dis.c (TMM): New.
1264         (EXtmm): Likewise.
1265         (VexTmm): Likewise.
1266         (MVexSIBMEM): Likewise.
1267         (tmm_mode): Likewise.
1268         (vex_sibmem_mode): Likewise.
1269         (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1270         (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1271         (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1272         (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1273         (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1274         (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1275         (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1276         (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1277         (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1278         (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1279         (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1280         (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1281         (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1282         (PREFIX_VEX_0F3849_X86_64): Likewise.
1283         (PREFIX_VEX_0F384B_X86_64): Likewise.
1284         (PREFIX_VEX_0F385C_X86_64): Likewise.
1285         (PREFIX_VEX_0F385E_X86_64): Likewise.
1286         (X86_64_VEX_0F3849): Likewise.
1287         (X86_64_VEX_0F384B): Likewise.
1288         (X86_64_VEX_0F385C): Likewise.
1289         (X86_64_VEX_0F385E): Likewise.
1290         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1291         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1292         (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1293         (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1294         (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1295         (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1296         (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1297         (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1298         (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1299         (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1300         (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1301         (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1302         (VEX_W_0F3849_X86_64_P_0): Likewise.
1303         (VEX_W_0F3849_X86_64_P_2): Likewise.
1304         (VEX_W_0F3849_X86_64_P_3): Likewise.
1305         (VEX_W_0F384B_X86_64_P_1): Likewise.
1306         (VEX_W_0F384B_X86_64_P_2): Likewise.
1307         (VEX_W_0F384B_X86_64_P_3): Likewise.
1308         (VEX_W_0F385C_X86_64_P_1): Likewise.
1309         (VEX_W_0F385E_X86_64_P_0): Likewise.
1310         (VEX_W_0F385E_X86_64_P_1): Likewise.
1311         (VEX_W_0F385E_X86_64_P_2): Likewise.
1312         (VEX_W_0F385E_X86_64_P_3): Likewise.
1313         (names_tmm): Likewise.
1314         (att_names_tmm): Likewise.
1315         (intel_operand_size): Handle void_mode.
1316         (OP_XMM): Handle tmm_mode.
1317         (OP_EX): Likewise.
1318         (OP_VEX): Likewise.
1319         * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1320         CpuAMX_BF16 and CpuAMX_TILE.
1321         (operand_type_shorthands): Add RegTMM.
1322         (operand_type_init): Likewise.
1323         (operand_types): Add Tmmword.
1324         (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1325         (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1326         * i386-opc.h (CpuAMX_INT8): New.
1327         (CpuAMX_BF16): Likewise.
1328         (CpuAMX_TILE): Likewise.
1329         (SIBMEM): Likewise.
1330         (Tmmword): Likewise.
1331         (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1332         (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1333         (i386_operand_type): Add tmmword.
1334         * i386-opc.tbl: Add AMX instructions.
1335         * i386-reg.tbl: Add AMX registers.
1336         * i386-init.h: Regenerated.
1337         * i386-tbl.h: Likewise.
1338
1339 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1340
1341         * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1342         (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1343         Rename to ...
1344         (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1345         REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1346         respectively.
1347         (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1348         VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1349         VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1350         VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1351         VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1352         VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1353         VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1354         VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1355         VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1356         VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1357         VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1358         VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1359         VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1360         VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1361         VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1362         VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1363         VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1364         VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1365         VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1366         VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1367         VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1368         VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1369         VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1370         VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1371         VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1372         VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1373         VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1374         VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1375         VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1376         VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1377         VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1378         VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1379         VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1380         VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1381         VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1382         VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1383         (reg_table): Re-order XOP entries. Adjust their operands.
1384         (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1385         08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1386         08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1387         09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1388         09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1389         09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1390         entries by references ...
1391         (vex_len_table): ... to resepctive new entries here. For several
1392         new and existing entries reference ...
1393         (vex_w_table): ... new entries here.
1394         (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1395
1396 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1397
1398         * i386-dis.c (XMVexScalarI4): Define.
1399         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1400         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1401         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1402         (vex_len_table): Move scalar FMA4 entries ...
1403         (prefix_table): ... here.
1404         (OP_REG_VexI4): Handle scalar_mode.
1405         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1406         * i386-tbl.h: Re-generate.
1407
1408 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1409
1410         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1411         Vex_2src_2): Delete.
1412         (OP_VexW, VexW): New.
1413         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1414         for shifts and rotates by register.
1415
1416 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1417
1418         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1419         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1420         OP_EX_VexReg): Delete.
1421         (OP_VexI4, VexI4): New.
1422         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1423         (prefix_table): ... here.
1424         (print_insn): Drop setting of vex_w_done.
1425
1426 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1427
1428         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1429         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1430         (xop_table): Replace operands of 4-operand insns.
1431         (OP_REG_VexI4): Move VEX.W based operand swaping here.
1432
1433 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
1434
1435         * arc-opc.c (insert_rbd): New function.
1436         (RBD): Define.
1437         (RBDdup): Likewise.
1438         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1439         instructions.
1440
1441 2020-07-07  Jan Beulich  <jbeulich@suse.com>
1442
1443         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1444         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1445         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1446         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1447         Delete.
1448         (putop): Handle "BW".
1449         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1450         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1451         and 0F3A3F ...
1452         * i386-dis-evex-prefix.h: ... here.
1453
1454 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1455
1456         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1457         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1458         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1459         VEX_W_0FXOP_09_83): New enumerators.
1460         (xop_table): Reference the above.
1461         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1462         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1463         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1464         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1465
1466 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1467
1468         * i386-dis.c (EVEX_W_0F3838_P_1,
1469         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1470         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1471         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1472         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1473         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1474         (putop): Centralize management of last[]. Delete SAVE_LAST.
1475         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1476         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1477         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1478         * i386-dis-evex-prefix.h: here.
1479
1480 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1481
1482         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1483         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1484         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1485         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1486         enumerators.
1487         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1488         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1489         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1490         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1491         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1492         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1493         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1494         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1495         these, respectively.
1496         * i386-dis-evex-len.h: Adjust comments.
1497         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1498         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1499         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1500         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1501         MOD_EVEX_0F385B_P_2_W_1 table entries.
1502         * i386-dis-evex-w.h: Reference mod_table[] for
1503         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1504         EVEX_W_0F385B_P_2.
1505
1506 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1507
1508         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1509         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1510         EXymm.
1511         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1512         Likewise. Mark 256-bit entries invalid.
1513
1514 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1515
1516         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1517         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1518         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1519         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1520         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1521         PREFIX_EVEX_0F382B): Delete.
1522         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1523         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1524         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1525         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1526         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1527         to ...
1528         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1529         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1530         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1531         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1532         respectively.
1533         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1534         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1535         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1536         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1537         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1538         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1539         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1540         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1541         PREFIX_EVEX_0F382B): Remove table entries.
1542         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1543         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1544         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1545
1546 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1547
1548         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1549         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1550         enumerators.
1551         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1552         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1553         EVEX_LEN_0F3A01_P_2_W_1 table entries.
1554         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1555         entries.
1556
1557 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1558
1559         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1560         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1561         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1562         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1563         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1564         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1565         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1566         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1567         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1568         entries.
1569
1570 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1571
1572         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1573         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1574         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1575         respectively.
1576         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1577         entries.
1578         * i386-dis-evex.h (evex_table): Reference VEX table entry for
1579         opcode 0F3A1D.
1580         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1581         entry.
1582         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1583
1584 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1585
1586         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1587         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1588         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1589         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1590         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1591         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1592         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1593         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1594         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1595         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1596         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1597         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1598         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1599         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1600         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1601         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1602         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1603         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1604         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1605         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1606         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1607         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1608         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1609         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1610         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1611         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1612         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1613         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1614         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1615         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1616         (prefix_table): Add EXxEVexR to FMA table entries.
1617         (OP_Rounding): Move abort() invocation.
1618         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1619         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1620         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1621         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1622         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1623         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1624         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1625         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1626         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1627         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1628         0F3ACE, 0F3ACF.
1629         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1630         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1631         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1632         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1633         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1634         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1635         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1636         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1637         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1638         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1639         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1640         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1641         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1642         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1643         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1644         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1645         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1646         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1647         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1648         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1649         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1650         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1651         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1652         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1653         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1654         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1655         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1656         Delete table entries.
1657         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1658         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1659         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1660         Likewise.
1661
1662 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1663
1664         * i386-dis.c (EXqScalarS): Delete.
1665         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1666         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1667
1668 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1669
1670         * i386-dis.c (safe-ctype.h): Include.
1671         (EXdScalar, EXqScalar): Delete.
1672         (d_scalar_mode, q_scalar_mode): Delete.
1673         (prefix_table, vex_len_table): Use EXxmm_md in place of
1674         EXdScalar and EXxmm_mq in place of EXqScalar.
1675         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1676         d_scalar_mode and q_scalar_mode.
1677         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1678         (vmovsd): Use EXxmm_mq.
1679
1680 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
1681
1682         PR 26204
1683         * arc-dis.c: Fix spelling mistake.
1684         * po/opcodes.pot: Regenerate.
1685
1686 2020-07-06  Nick Clifton  <nickc@redhat.com>
1687
1688         * po/pt_BR.po: Updated Brazilian Portugugese translation.
1689         * po/uk.po: Updated Ukranian translation.
1690
1691 2020-07-04  Nick Clifton  <nickc@redhat.com>
1692
1693         * configure: Regenerate.
1694         * po/opcodes.pot: Regenerate.
1695
1696 2020-07-04  Nick Clifton  <nickc@redhat.com>
1697
1698         Binutils 2.35 branch created.
1699
1700 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
1701
1702         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1703         * i386-opc.h (VexSwapSources): New.
1704         (i386_opcode_modifier): Add vexswapsources.
1705         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1706         with two source operands swapped.
1707         * i386-tbl.h: Regenerated.
1708
1709 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
1710
1711         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
1712         unprivileged CSR can also be initialized.
1713
1714 2020-06-29  Alan Modra  <amodra@gmail.com>
1715
1716         * arm-dis.c: Use C style comments.
1717         * cr16-opc.c: Likewise.
1718         * ft32-dis.c: Likewise.
1719         * moxie-opc.c: Likewise.
1720         * tic54x-dis.c: Likewise.
1721         * s12z-opc.c: Remove useless comment.
1722         * xgate-dis.c: Likewise.
1723
1724 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1725
1726         * i386-opc.tbl: Add a blank line.
1727
1728 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1729
1730         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1731         (VecSIB128): Renamed to ...
1732         (VECSIB128): This.
1733         (VecSIB256): Renamed to ...
1734         (VECSIB256): This.
1735         (VecSIB512): Renamed to ...
1736         (VECSIB512): This.
1737         (VecSIB): Renamed to ...
1738         (SIB): This.
1739         (i386_opcode_modifier): Replace vecsib with sib.
1740         * i386-opc.tbl (VecSIB128): New.
1741         (VecSIB256): Likewise.
1742         (VecSIB512): Likewise.
1743         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1744         and VecSIB512, respectively.
1745
1746 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1747
1748         * i386-dis.c: Adjust description of I macro.
1749         (x86_64_table): Drop use of I.
1750         (float_mem): Replace use of I.
1751         (putop): Remove handling of I. Adjust setting/clearing of "alt".
1752
1753 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1754
1755         * i386-dis.c: (print_insn): Avoid straight assignment to
1756         priv.orig_sizeflag when processing -M sub-options.
1757
1758 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1759
1760         * i386-dis.c: Adjust description of J macro.
1761         (dis386, x86_64_table, mod_table): Replace J.
1762         (putop): Remove handling of J.
1763
1764 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1765
1766         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1767
1768 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1769
1770         * i386-dis.c: Adjust description of "LQ" macro.
1771         (dis386_twobyte): Use LQ for sysret.
1772         (putop): Adjust handling of LQ.
1773
1774 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
1775
1776         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1777         * riscv-dis.c: Include elfxx-riscv.h.
1778
1779 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
1780
1781         * i386-dis.c (prefix_table): Revert the last vmgexit change.
1782
1783 2020-06-17  Lili Cui  <lili.cui@intel.com>
1784
1785         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1786
1787 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
1788
1789         PR gas/26115
1790         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1791         * i386-opc.tbl: Likewise.
1792         * i386-tbl.h: Regenerated.
1793
1794 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
1795
1796         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1797
1798 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
1799
1800         * aarch64-opc.c (SYSREG): New macro for describing system registers.
1801         (SR_CORE): Likewise.
1802         (SR_FEAT): Likewise.
1803         (SR_RNG): Likewise.
1804         (SR_V8_1): Likewise.
1805         (SR_V8_2): Likewise.
1806         (SR_V8_3): Likewise.
1807         (SR_V8_4): Likewise.
1808         (SR_PAN): Likewise.
1809         (SR_RAS): Likewise.
1810         (SR_SSBS): Likewise.
1811         (SR_SVE): Likewise.
1812         (SR_ID_PFR2): Likewise.
1813         (SR_PROFILE): Likewise.
1814         (SR_MEMTAG): Likewise.
1815         (SR_SCXTNUM): Likewise.
1816         (aarch64_sys_regs): Refactor to store feature information in the table.
1817         (aarch64_sys_reg_supported_p): Collapse logic for system registers
1818         that now describe their own features.
1819         (aarch64_pstatefield_supported_p): Likewise.
1820
1821 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
1822
1823         * i386-dis.c (prefix_table): Fix a typo in comments.
1824
1825 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1826
1827         * i386-dis.c (rex_ignored): Delete.
1828         (ckprefix): Drop rex_ignored initialization.
1829         (get_valid_dis386): Drop setting of rex_ignored.
1830         (print_insn): Drop checking of rex_ignored. Don't record data
1831         size prefix as used with VEX-and-alike encodings.
1832
1833 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1834
1835         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1836         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1837         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1838         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1839         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1840         VEX_0F12, and VEX_0F16.
1841         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1842         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1843         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1844         from movlps and movhlps. New MOD_0F12_PREFIX_2,
1845         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1846         MOD_VEX_0F16_PREFIX_2 entries.
1847
1848 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1849
1850         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1851         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1852         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1853         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1854         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1855         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1856         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1857         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1858         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1859         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1860         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1861         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1862         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1863         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1864         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1865         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1866         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1867         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1868         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1869         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1870         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1871         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1872         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1873         EVEX_W_0FC6_P_2): Delete.
1874         (print_insn): Add EVEX.W vs embedded prefix consistency check
1875         to prefix validation.
1876         * i386-dis-evex.h (evex_table): Don't further descend for
1877         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1878         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1879         and 0F2B.
1880         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1881         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1882         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1883         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1884         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1885         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1886         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1887         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1888         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1889         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1890         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1891         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1892         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1893         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1894         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1895         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1896         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1897         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1898         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1899         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1900         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1901         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1902         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1903         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1904         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1905         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1906         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1907
1908 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1909
1910         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1911         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1912         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1913         vmovmskpX.
1914         (print_insn): Drop pointless check against bad_opcode. Split
1915         prefix validation into legacy and VEX-and-alike parts.
1916         (putop): Re-work 'X' macro handling.
1917
1918 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1919
1920         * i386-dis.c (MOD_0F51): Rename to ...
1921         (MOD_0F50): ... this.
1922
1923 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
1924
1925         * arm-dis.c (arm_opcodes): Add dfb.
1926         (thumb32_opcodes): Add dfb.
1927
1928 2020-06-08  Jan Beulich  <jbeulich@suse.com>
1929
1930         * i386-opc.h (reg_entry): Const-qualify reg_name field.
1931
1932 2020-06-06  Alan Modra  <amodra@gmail.com>
1933
1934         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1935
1936 2020-06-05  Alan Modra  <amodra@gmail.com>
1937
1938         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
1939         size is large enough.
1940
1941 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
1942
1943         * disassemble.c (disassemble_init_for_target): Set endian_code for
1944         bpf targets.
1945         * bpf-desc.c: Regenerate.
1946         * bpf-opc.c: Likewise.
1947         * bpf-dis.c: Likewise.
1948
1949 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
1950
1951         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1952         (cgen_put_insn_value): Likewise.
1953         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1954         * cgen-dis.in (print_insn): Likewise.
1955         * cgen-ibld.in (insert_1): Likewise.
1956         (insert_1): Likewise.
1957         (insert_insn_normal): Likewise.
1958         (extract_1): Likewise.
1959         * bpf-dis.c: Regenerate.
1960         * bpf-ibld.c: Likewise.
1961         * bpf-ibld.c: Likewise.
1962         * cgen-dis.in: Likewise.
1963         * cgen-ibld.in: Likewise.
1964         * cgen-opc.c: Likewise.
1965         * epiphany-dis.c: Likewise.
1966         * epiphany-ibld.c: Likewise.
1967         * fr30-dis.c: Likewise.
1968         * fr30-ibld.c: Likewise.
1969         * frv-dis.c: Likewise.
1970         * frv-ibld.c: Likewise.
1971         * ip2k-dis.c: Likewise.
1972         * ip2k-ibld.c: Likewise.
1973         * iq2000-dis.c: Likewise.
1974         * iq2000-ibld.c: Likewise.
1975         * lm32-dis.c: Likewise.
1976         * lm32-ibld.c: Likewise.
1977         * m32c-dis.c: Likewise.
1978         * m32c-ibld.c: Likewise.
1979         * m32r-dis.c: Likewise.
1980         * m32r-ibld.c: Likewise.
1981         * mep-dis.c: Likewise.
1982         * mep-ibld.c: Likewise.
1983         * mt-dis.c: Likewise.
1984         * mt-ibld.c: Likewise.
1985         * or1k-dis.c: Likewise.
1986         * or1k-ibld.c: Likewise.
1987         * xc16x-dis.c: Likewise.
1988         * xc16x-ibld.c: Likewise.
1989         * xstormy16-dis.c: Likewise.
1990         * xstormy16-ibld.c: Likewise.
1991
1992 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
1993
1994         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1995         (print_insn_): Handle instruction endian.
1996         * bpf-dis.c: Regenerate.
1997         * bpf-desc.c: Regenerate.
1998         * epiphany-dis.c: Likewise.
1999         * epiphany-desc.c: Likewise.
2000         * fr30-dis.c: Likewise.
2001         * fr30-desc.c: Likewise.
2002         * frv-dis.c: Likewise.
2003         * frv-desc.c: Likewise.
2004         * ip2k-dis.c: Likewise.
2005         * ip2k-desc.c: Likewise.
2006         * iq2000-dis.c: Likewise.
2007         * iq2000-desc.c: Likewise.
2008         * lm32-dis.c: Likewise.
2009         * lm32-desc.c: Likewise.
2010         * m32c-dis.c: Likewise.
2011         * m32c-desc.c: Likewise.
2012         * m32r-dis.c: Likewise.
2013         * m32r-desc.c: Likewise.
2014         * mep-dis.c: Likewise.
2015         * mep-desc.c: Likewise.
2016         * mt-dis.c: Likewise.
2017         * mt-desc.c: Likewise.
2018         * or1k-dis.c: Likewise.
2019         * or1k-desc.c: Likewise.
2020         * xc16x-dis.c: Likewise.
2021         * xc16x-desc.c: Likewise.
2022         * xstormy16-dis.c: Likewise.
2023         * xstormy16-desc.c: Likewise.
2024
2025 2020-06-03  Nick Clifton  <nickc@redhat.com>
2026
2027         * po/sr.po: Updated Serbian translation.
2028
2029 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
2030
2031         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
2032         (riscv_get_priv_spec_class): Likewise.
2033
2034 2020-06-01  Alan Modra  <amodra@gmail.com>
2035
2036         * bpf-desc.c: Regenerate.
2037
2038 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
2039             David Faust <david.faust@oracle.com>
2040
2041         * bpf-desc.c: Regenerate.
2042         * bpf-opc.h: Likewise.
2043         * bpf-opc.c: Likewise.
2044         * bpf-dis.c: Likewise.
2045
2046 2020-05-28  Alan Modra  <amodra@gmail.com>
2047
2048         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
2049         values.
2050
2051 2020-05-28  Alan Modra  <amodra@gmail.com>
2052
2053         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2054         immediates.
2055         (print_insn_ns32k): Revert last change.
2056
2057 2020-05-28  Nick Clifton  <nickc@redhat.com>
2058
2059         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2060         static.
2061
2062 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
2063
2064         Fix extraction of signed constants in nios2 disassembler (again).
2065
2066         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2067         extractions of signed fields.
2068
2069 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
2070
2071         * s390-opc.txt: Relocate vector load/store instructions with
2072         additional alignment parameter and change architecture level
2073         constraint from z14 to z13.
2074
2075 2020-05-21  Alan Modra  <amodra@gmail.com>
2076
2077         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2078         * sparc-dis.c: Likewise.
2079         * tic4x-dis.c: Likewise.
2080         * xtensa-dis.c: Likewise.
2081         * bpf-desc.c: Regenerate.
2082         * epiphany-desc.c: Regenerate.
2083         * fr30-desc.c: Regenerate.
2084         * frv-desc.c: Regenerate.
2085         * ip2k-desc.c: Regenerate.
2086         * iq2000-desc.c: Regenerate.
2087         * lm32-desc.c: Regenerate.
2088         * m32c-desc.c: Regenerate.
2089         * m32r-desc.c: Regenerate.
2090         * mep-asm.c: Regenerate.
2091         * mep-desc.c: Regenerate.
2092         * mt-desc.c: Regenerate.
2093         * or1k-desc.c: Regenerate.
2094         * xc16x-desc.c: Regenerate.
2095         * xstormy16-desc.c: Regenerate.
2096
2097 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
2098
2099         * riscv-opc.c (riscv_ext_version_table): The table used to store
2100         all information about the supported spec and the corresponding ISA
2101         versions.  Currently, only Zicsr is supported to verify the
2102         correctness of Z sub extension settings.  Others will be supported
2103         in the future patches.
2104         (struct isa_spec_t, isa_specs): List for all supported ISA spec
2105         classes and the corresponding strings.
2106         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
2107         spec class by giving a ISA spec string.
2108         * riscv-opc.c (struct priv_spec_t): New structure.
2109         (struct priv_spec_t priv_specs): List for all supported privilege spec
2110         classes and the corresponding strings.
2111         (riscv_get_priv_spec_class): New function.  Get the corresponding
2112         privilege spec class by giving a spec string.
2113         (riscv_get_priv_spec_name): New function.  Get the corresponding
2114         privilege spec string by giving a CSR version class.
2115         * riscv-dis.c: Updated since DECLARE_CSR is changed.
2116         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2117         according to the chosen version.  Build a hash table riscv_csr_hash to
2118         store the valid CSR for the chosen pirv verison.  Dump the direct
2119         CSR address rather than it's name if it is invalid.
2120         (parse_riscv_dis_option_without_args): New function.  Parse the options
2121         without arguments.
2122         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2123         parse the options without arguments first, and then handle the options
2124         with arguments.  Add the new option -Mpriv-spec, which has argument.
2125         * riscv-dis.c (print_riscv_disassembler_options): Add description
2126         about the new OBJDUMP option.
2127
2128 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
2129
2130         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2131         WC values on POWER10 sync, dcbf  and wait instructions.
2132         (insert_pl, extract_pl): New functions.
2133         (L2OPT, LS, WC): Use insert_ls and extract_ls.
2134         (LS3): New , 3-bit L for sync.
2135         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2136         (SC2, PL): New, 2-bit SC and PL for sync and wait.
2137         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2138         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2139         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2140         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2141         <wait>: Enable PL operand on POWER10.
2142         <dcbf>: Enable L3OPT operand on POWER10.
2143         <sync>: Enable SC2 operand on POWER10.
2144
2145 2020-05-19  Stafford Horne  <shorne@gmail.com>
2146
2147         PR 25184
2148         * or1k-asm.c: Regenerate.
2149         * or1k-desc.c: Regenerate.
2150         * or1k-desc.h: Regenerate.
2151         * or1k-dis.c: Regenerate.
2152         * or1k-ibld.c: Regenerate.
2153         * or1k-opc.c: Regenerate.
2154         * or1k-opc.h: Regenerate.
2155         * or1k-opinst.c: Regenerate.
2156
2157 2020-05-11  Alan Modra  <amodra@gmail.com>
2158
2159         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2160         xsmaxcqp, xsmincqp.
2161
2162 2020-05-11  Alan Modra  <amodra@gmail.com>
2163
2164         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2165         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2166
2167 2020-05-11  Alan Modra  <amodra@gmail.com>
2168
2169         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2170
2171 2020-05-11  Alan Modra  <amodra@gmail.com>
2172
2173         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2174         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2175
2176 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2177
2178         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2179         mnemonics.
2180
2181 2020-05-11  Alan Modra  <amodra@gmail.com>
2182
2183         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2184         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2185         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2186         (prefix_opcodes): Add xxeval.
2187
2188 2020-05-11  Alan Modra  <amodra@gmail.com>
2189
2190         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2191         xxgenpcvwm, xxgenpcvdm.
2192
2193 2020-05-11  Alan Modra  <amodra@gmail.com>
2194
2195         * ppc-opc.c (MP, VXVAM_MASK): Define.
2196         (VXVAPS_MASK): Use VXVA_MASK.
2197         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2198         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2199         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2200         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2201
2202 2020-05-11  Alan Modra  <amodra@gmail.com>
2203             Peter Bergner  <bergner@linux.ibm.com>
2204
2205         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2206         New functions.
2207         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2208         YMSK2, XA6a, XA6ap, XB6a entries.
2209         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2210         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2211         (PPCVSX4): Define.
2212         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2213         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2214         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2215         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2216         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2217         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2218         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2219         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2220         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2221         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2222         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2223         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2224         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2225         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2226
2227 2020-05-11  Alan Modra  <amodra@gmail.com>
2228
2229         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2230         (insert_xts, extract_xts): New functions.
2231         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2232         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2233         (VXRC_MASK, VXSH_MASK): Define.
2234         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2235         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2236         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2237         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2238         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2239         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2240         xxblendvh, xxblendvw, xxblendvd, xxpermx.
2241
2242 2020-05-11  Alan Modra  <amodra@gmail.com>
2243
2244         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2245         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2246         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2247         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2248         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2249
2250 2020-05-11  Alan Modra  <amodra@gmail.com>
2251
2252         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2253         (XTP, DQXP, DQXP_MASK): Define.
2254         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2255         (prefix_opcodes): Add plxvp and pstxvp.
2256
2257 2020-05-11  Alan Modra  <amodra@gmail.com>
2258
2259         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2260         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2261         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2262
2263 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2264
2265         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2266
2267 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2268
2269         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2270         (L1OPT): Define.
2271         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2272
2273 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2274
2275         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2276
2277 2020-05-11  Alan Modra  <amodra@gmail.com>
2278
2279         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2280
2281 2020-05-11  Alan Modra  <amodra@gmail.com>
2282
2283         * ppc-dis.c (ppc_opts): Add "power10" entry.
2284         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2285         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
2286
2287 2020-05-11  Nick Clifton  <nickc@redhat.com>
2288
2289         * po/fr.po: Updated French translation.
2290
2291 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
2292
2293         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2294         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2295         (operand_general_constraint_met_p): validate
2296         AARCH64_OPND_UNDEFINED.
2297         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2298         for FLD_imm16_2.
2299         * aarch64-asm-2.c: Regenerated.
2300         * aarch64-dis-2.c: Regenerated.
2301         * aarch64-opc-2.c: Regenerated.
2302
2303 2020-04-29  Nick Clifton  <nickc@redhat.com>
2304
2305         PR 22699
2306         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2307         and SETRC insns.
2308
2309 2020-04-29  Nick Clifton  <nickc@redhat.com>
2310
2311         * po/sv.po: Updated Swedish translation.
2312
2313 2020-04-29  Nick Clifton  <nickc@redhat.com>
2314
2315         PR 22699
2316         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
2317         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2318         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2319         IMM0_8U case.
2320
2321 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
2322
2323         PR 25848
2324         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2325         cmpi only on m68020up and cpu32.
2326
2327 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2328
2329         * aarch64-asm.c (aarch64_ins_none): New.
2330         * aarch64-asm.h (ins_none): New declaration.
2331         * aarch64-dis.c (aarch64_ext_none): New.
2332         * aarch64-dis.h (ext_none): New declaration.
2333         * aarch64-opc.c (aarch64_print_operand): Update case for
2334         AARCH64_OPND_BARRIER_PSB.
2335         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2336         (AARCH64_OPERANDS): Update inserter/extracter for
2337         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2338         * aarch64-asm-2.c: Regenerated.
2339         * aarch64-dis-2.c: Regenerated.
2340         * aarch64-opc-2.c: Regenerated.
2341
2342 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2343
2344         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2345         (aarch64_feature_ras, RAS): Likewise.
2346         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2347         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2348         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2349         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2350         * aarch64-asm-2.c: Regenerated.
2351         * aarch64-dis-2.c: Regenerated.
2352         * aarch64-opc-2.c: Regenerated.
2353
2354 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
2355
2356         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2357         (print_insn_neon): Support disassembly of conditional
2358         instructions.
2359
2360 2020-02-16  David Faust  <david.faust@oracle.com>
2361
2362         * bpf-desc.c: Regenerate.
2363         * bpf-desc.h: Likewise.
2364         * bpf-opc.c: Regenerate.
2365         * bpf-opc.h: Likewise.
2366
2367 2020-04-07  Lili Cui  <lili.cui@intel.com>
2368
2369         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2370         (prefix_table): New instructions (see prefixes above).
2371         (rm_table): Likewise
2372         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2373         CPU_ANY_TSXLDTRK_FLAGS.
2374         (cpu_flags): Add CpuTSXLDTRK.
2375         * i386-opc.h (enum): Add CpuTSXLDTRK.
2376         (i386_cpu_flags): Add cputsxldtrk.
2377         * i386-opc.tbl: Add XSUSPLDTRK insns.
2378         * i386-init.h: Regenerate.
2379         * i386-tbl.h: Likewise.
2380
2381 2020-04-02  Lili Cui  <lili.cui@intel.com>
2382
2383         * i386-dis.c (prefix_table): New instructions serialize.
2384         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2385         CPU_ANY_SERIALIZE_FLAGS.
2386         (cpu_flags): Add CpuSERIALIZE.
2387         * i386-opc.h (enum): Add CpuSERIALIZE.
2388         (i386_cpu_flags): Add cpuserialize.
2389         * i386-opc.tbl: Add SERIALIZE insns.
2390         * i386-init.h: Regenerate.
2391         * i386-tbl.h: Likewise.
2392
2393 2020-03-26  Alan Modra  <amodra@gmail.com>
2394
2395         * disassemble.h (opcodes_assert): Declare.
2396         (OPCODES_ASSERT): Define.
2397         * disassemble.c: Don't include assert.h.  Include opintl.h.
2398         (opcodes_assert): New function.
2399         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2400         (bfd_h8_disassemble): Reduce size of data array.  Correctly
2401         calculate maxlen.  Omit insn decoding when insn length exceeds
2402         maxlen.  Exit from nibble loop when looking for E, before
2403         accessing next data byte.  Move processing of E outside loop.
2404         Replace tests of maxlen in loop with assertions.
2405
2406 2020-03-26  Alan Modra  <amodra@gmail.com>
2407
2408         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
2409
2410 2020-03-25  Alan Modra  <amodra@gmail.com>
2411
2412         * z80-dis.c (suffix): Init mybuf.
2413
2414 2020-03-22  Alan Modra  <amodra@gmail.com>
2415
2416         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2417         successflly read from section.
2418
2419 2020-03-22  Alan Modra  <amodra@gmail.com>
2420
2421         * arc-dis.c (find_format): Use ISO C string concatenation rather
2422         than line continuation within a string.  Don't access needs_limm
2423         before testing opcode != NULL.
2424
2425 2020-03-22  Alan Modra  <amodra@gmail.com>
2426
2427         * ns32k-dis.c (print_insn_arg): Update comment.
2428         (print_insn_ns32k): Reduce size of index_offset array, and
2429         initialize, passing -1 to print_insn_arg for args that are not
2430         an index.  Don't exit arg loop early.  Abort on bad arg number.
2431
2432 2020-03-22  Alan Modra  <amodra@gmail.com>
2433
2434         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2435         * s12z-opc.c: Formatting.
2436         (operands_f): Return an int.
2437         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2438         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2439         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2440         (exg_sex_discrim): Likewise.
2441         (create_immediate_operand, create_bitfield_operand),
2442         (create_register_operand_with_size, create_register_all_operand),
2443         (create_register_all16_operand, create_simple_memory_operand),
2444         (create_memory_operand, create_memory_auto_operand): Don't
2445         segfault on malloc failure.
2446         (z_ext24_decode): Return an int status, negative on fail, zero
2447         on success.
2448         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2449         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2450         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2451         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2452         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2453         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2454         (loop_primitive_decode, shift_decode, psh_pul_decode),
2455         (bit_field_decode): Similarly.
2456         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
2457         to return value, update callers.
2458         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2459         Don't segfault on NULL operand.
2460         (decode_operation): Return OP_INVALID on first fail.
2461         (decode_s12z): Check all reads, returning -1 on fail.
2462
2463 2020-03-20  Alan Modra  <amodra@gmail.com>
2464
2465         * metag-dis.c (print_insn_metag): Don't ignore status from
2466         read_memory_func.
2467
2468 2020-03-20  Alan Modra  <amodra@gmail.com>
2469
2470         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2471         Initialize parts of buffer not written when handling a possible
2472         2-byte insn at end of section.  Don't attempt decoding of such
2473         an insn by the 4-byte machinery.
2474
2475 2020-03-20  Alan Modra  <amodra@gmail.com>
2476
2477         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2478         partially filled buffer.  Prevent lookup of 4-byte insns when
2479         only VLE 2-byte insns are possible due to section size.  Print
2480         ".word" rather than ".long" for 2-byte leftovers.
2481
2482 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
2483
2484         PR 25641
2485         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2486
2487 2020-03-13  Jan Beulich  <jbeulich@suse.com>
2488
2489         * i386-dis.c (X86_64_0D): Rename to ...
2490         (X86_64_0E): ... this.
2491
2492 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
2493
2494         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2495         * Makefile.in: Regenerated.
2496
2497 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2498
2499         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2500         3-operand pseudos.
2501         * i386-tbl.h: Re-generate.
2502
2503 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2504
2505         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2506         vprot*, vpsha*, and vpshl*.
2507         * i386-tbl.h: Re-generate.
2508
2509 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2510
2511         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2512         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2513         * i386-tbl.h: Re-generate.
2514
2515 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2516
2517         * i386-gen.c (set_bitfield): Ignore zero-length field names.
2518         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2519         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2520         * i386-tbl.h: Re-generate.
2521
2522 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2523
2524         * i386-gen.c (struct template_arg, struct template_instance,
2525         struct template_param, struct template, templates,
2526         parse_template, expand_templates): New.
2527         (process_i386_opcodes): Various local variables moved to
2528         expand_templates. Call parse_template and expand_templates.
2529         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2530         * i386-tbl.h: Re-generate.
2531
2532 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2533
2534         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2535         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2536         register and memory source templates. Replace VexW= by VexW*
2537         where applicable.
2538         * i386-tbl.h: Re-generate.
2539
2540 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2541
2542         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2543         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2544         * i386-tbl.h: Re-generate.
2545
2546 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2547
2548         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2549         * i386-tbl.h: Re-generate.
2550
2551 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2552
2553         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2554         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2555         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2556         VexW0 on SSE2AVX variants.
2557         (vmovq): Drop NoRex64 from XMM/XMM variants.
2558         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2559         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2560         applicable use VexW0.
2561         * i386-tbl.h: Re-generate.
2562
2563 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2564
2565         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2566         * i386-opc.h (Rex64): Delete.
2567         (struct i386_opcode_modifier): Remove rex64 field.
2568         * i386-opc.tbl (crc32): Drop Rex64.
2569         Replace Rex64 with Size64 everywhere else.
2570         * i386-tbl.h: Re-generate.
2571
2572 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2573
2574         * i386-dis.c (OP_E_memory): Exclude recording of used address
2575         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2576         addressed memory operands for MPX insns.
2577
2578 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2579
2580         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2581         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2582         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2583         (ptwrite): Split into non-64-bit and 64-bit forms.
2584         * i386-tbl.h: Re-generate.
2585
2586 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2587
2588         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2589         template.
2590         * i386-tbl.h: Re-generate.
2591
2592 2020-03-04  Jan Beulich  <jbeulich@suse.com>
2593
2594         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2595         (prefix_table): Move vmmcall here. Add vmgexit.
2596         (rm_table): Replace vmmcall entry by prefix_table[] escape.
2597         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2598         (cpu_flags): Add CpuSEV_ES entry.
2599         * i386-opc.h (CpuSEV_ES): New.
2600         (union i386_cpu_flags): Add cpusev_es field.
2601         * i386-opc.tbl (vmgexit): New.
2602         * i386-init.h, i386-tbl.h: Re-generate.
2603
2604 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2605
2606         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2607         with MnemonicSize.
2608         * i386-opc.h (IGNORESIZE): New.
2609         (DEFAULTSIZE): Likewise.
2610         (IgnoreSize): Removed.
2611         (DefaultSize): Likewise.
2612         (MnemonicSize): New.
2613         (i386_opcode_modifier): Replace ignoresize/defaultsize with
2614         mnemonicsize.
2615         * i386-opc.tbl (IgnoreSize): New.
2616         (DefaultSize): Likewise.
2617         * i386-tbl.h: Regenerated.
2618
2619 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2620
2621         PR 25627
2622         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2623         instructions.
2624
2625 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2626
2627         PR gas/25622
2628         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2629         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2630         * i386-tbl.h: Regenerated.
2631
2632 2020-02-26  Alan Modra  <amodra@gmail.com>
2633
2634         * aarch64-asm.c: Indent labels correctly.
2635         * aarch64-dis.c: Likewise.
2636         * aarch64-gen.c: Likewise.
2637         * aarch64-opc.c: Likewise.
2638         * alpha-dis.c: Likewise.
2639         * i386-dis.c: Likewise.
2640         * nds32-asm.c: Likewise.
2641         * nfp-dis.c: Likewise.
2642         * visium-dis.c: Likewise.
2643
2644 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
2645
2646         * arc-regs.h (int_vector_base): Make it available for all ARC
2647         CPUs.
2648
2649 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
2650
2651         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2652         changed.
2653
2654 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
2655
2656         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2657         c.mv/c.li if rs1 is zero.
2658
2659 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
2660
2661         * i386-gen.c (cpu_flag_init): Replace CpuABM with
2662         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
2663         CPU_POPCNT_FLAGS.
2664         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
2665         * i386-opc.h (CpuABM): Removed.
2666         (CpuPOPCNT): New.
2667         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
2668         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2669         popcnt.  Remove CpuABM from lzcnt.
2670         * i386-init.h: Regenerated.
2671         * i386-tbl.h: Likewise.
2672
2673 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2674
2675         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2676         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2677         VexW1 instead of open-coding them.
2678         * i386-tbl.h: Re-generate.
2679
2680 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2681
2682         * i386-opc.tbl (AddrPrefixOpReg): Define.
2683         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2684         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2685         templates. Drop NoRex64.
2686         * i386-tbl.h: Re-generate.
2687
2688 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2689
2690         PR gas/6518
2691         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2692         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2693         into Intel syntax instance (with Unpsecified) and AT&T one
2694         (without).
2695         (vcvtneps2bf16): Likewise, along with folding the two so far
2696         separate ones.
2697         * i386-tbl.h: Re-generate.
2698
2699 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2700
2701         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2702         CPU_ANY_SSE4A_FLAGS.
2703
2704 2020-02-17  Alan Modra  <amodra@gmail.com>
2705
2706         * i386-gen.c (cpu_flag_init): Correct last change.
2707
2708 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2709
2710         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
2711         CPU_ANY_SSE4_FLAGS.
2712
2713 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
2714
2715         * i386-opc.tbl (movsx): Remove Intel syntax comments.
2716         (movzx): Likewise.
2717
2718 2020-02-14  Jan Beulich  <jbeulich@suse.com>
2719
2720         PR gas/25438
2721         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2722         destination for Cpu64-only variant.
2723         (movzx): Fold patterns.
2724         * i386-tbl.h: Re-generate.
2725
2726 2020-02-13  Jan Beulich  <jbeulich@suse.com>
2727
2728         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2729         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2730         CPU_ANY_SSE4_FLAGS entry.
2731         * i386-init.h: Re-generate.
2732
2733 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2734
2735         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2736         with Unspecified, making the present one AT&T syntax only.
2737         * i386-tbl.h: Re-generate.
2738
2739 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2740
2741         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2742         * i386-tbl.h: Re-generate.
2743
2744 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2745
2746         PR gas/24546
2747         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2748         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2749         Amd64 and Intel64 templates.
2750         (call, jmp): Likewise for far indirect variants. Dro
2751         Unspecified.
2752         * i386-tbl.h: Re-generate.
2753
2754 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2755
2756         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2757         * i386-opc.h (ShortForm): Delete.
2758         (struct i386_opcode_modifier): Remove shortform field.
2759         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2760         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2761         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2762         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2763         Drop ShortForm.
2764         * i386-tbl.h: Re-generate.
2765
2766 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2767
2768         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2769         fucompi): Drop ShortForm from operand-less templates.
2770         * i386-tbl.h: Re-generate.
2771
2772 2020-02-11  Alan Modra  <amodra@gmail.com>
2773
2774         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2775         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2776         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2777         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2778         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2779
2780 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
2781
2782         * arm-dis.c (print_insn_cde): Define 'V' parse character.
2783         (cde_opcodes): Add VCX* instructions.
2784
2785 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
2786             Matthew Malcomson  <matthew.malcomson@arm.com>
2787
2788         * arm-dis.c (struct cdeopcode32): New.
2789         (CDE_OPCODE): New macro.
2790         (cde_opcodes): New disassembly table.
2791         (regnames): New option to table.
2792         (cde_coprocs): New global variable.
2793         (print_insn_cde): New
2794         (print_insn_thumb32): Use print_insn_cde.
2795         (parse_arm_disassembler_options): Parse coprocN args.
2796
2797 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
2798
2799         PR gas/25516
2800         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2801         with ISA64.
2802         * i386-opc.h (AMD64): Removed.
2803         (Intel64): Likewose.
2804         (AMD64): New.
2805         (INTEL64): Likewise.
2806         (INTEL64ONLY): Likewise.
2807         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2808         * i386-opc.tbl (Amd64): New.
2809         (Intel64): Likewise.
2810         (Intel64Only): Likewise.
2811         Replace AMD64 with Amd64.  Update sysenter/sysenter with
2812         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
2813         * i386-tbl.h: Regenerated.
2814
2815 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
2816
2817         PR 25469
2818         * z80-dis.c: Add support for GBZ80 opcodes.
2819
2820 2020-02-04  Alan Modra  <amodra@gmail.com>
2821
2822         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2823
2824 2020-02-03  Alan Modra  <amodra@gmail.com>
2825
2826         * m32c-ibld.c: Regenerate.
2827
2828 2020-02-01  Alan Modra  <amodra@gmail.com>
2829
2830         * frv-ibld.c: Regenerate.
2831
2832 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2833
2834         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2835         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2836         (OP_E_memory): Replace xmm_mdq_mode case label by
2837         vex_scalar_w_dq_mode one.
2838         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2839
2840 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2841
2842         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2843         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2844         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2845         (intel_operand_size): Drop vex_w_dq_mode case label.
2846
2847 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
2848
2849         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2850         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2851
2852 2020-01-30  Alan Modra  <amodra@gmail.com>
2853
2854         * m32c-ibld.c: Regenerate.
2855
2856 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
2857
2858         * bpf-opc.c: Regenerate.
2859
2860 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2861
2862         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2863         (dis386): Use them to replace C2/C3 table entries.
2864         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2865         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2866         ones. Use Size64 instead of DefaultSize on Intel64 ones.
2867         * i386-tbl.h: Re-generate.
2868
2869 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2870
2871         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2872         forms.
2873         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2874         DefaultSize.
2875         * i386-tbl.h: Re-generate.
2876
2877 2020-01-30  Alan Modra  <amodra@gmail.com>
2878
2879         * tic4x-dis.c (tic4x_dp): Make unsigned.
2880
2881 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
2882             Jan Beulich  <jbeulich@suse.com>
2883
2884         PR binutils/25445
2885         * i386-dis.c (MOVSXD_Fixup): New function.
2886         (movsxd_mode): New enum.
2887         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2888         (intel_operand_size): Handle movsxd_mode.
2889         (OP_E_register): Likewise.
2890         (OP_G): Likewise.
2891         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2892         register on movsxd.  Add movsxd with 16-bit destination register
2893         for AMD64 and Intel64 ISAs.
2894         * i386-tbl.h: Regenerated.
2895
2896 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
2897
2898         PR 25403
2899         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2900         * aarch64-asm-2.c: Regenerate
2901         * aarch64-dis-2.c: Likewise.
2902         * aarch64-opc-2.c: Likewise.
2903
2904 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2905
2906         * i386-opc.tbl (sysret): Drop DefaultSize.
2907         * i386-tbl.h: Re-generate.
2908
2909 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2910
2911         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2912         Dword.
2913         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2914         * i386-tbl.h: Re-generate.
2915
2916 2020-01-20  Nick Clifton  <nickc@redhat.com>
2917
2918         * po/de.po: Updated German translation.
2919         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2920         * po/uk.po: Updated Ukranian translation.
2921
2922 2020-01-20  Alan Modra  <amodra@gmail.com>
2923
2924         * hppa-dis.c (fput_const): Remove useless cast.
2925
2926 2020-01-20  Alan Modra  <amodra@gmail.com>
2927
2928         * arm-dis.c (print_insn_arm): Wrap 'T' value.
2929
2930 2020-01-18  Nick Clifton  <nickc@redhat.com>
2931
2932         * configure: Regenerate.
2933         * po/opcodes.pot: Regenerate.
2934
2935 2020-01-18  Nick Clifton  <nickc@redhat.com>
2936
2937         Binutils 2.34 branch created.
2938
2939 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
2940
2941         * opintl.h: Fix spelling error (seperate).
2942
2943 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
2944
2945         * i386-opc.tbl: Add {vex} pseudo prefix.
2946         * i386-tbl.h: Regenerated.
2947
2948 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
2949
2950         PR 25376
2951         * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2952         (neon_opcodes): Likewise.
2953         (select_arm_features): Make sure we enable MVE bits when selecting
2954         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
2955         any architecture.
2956
2957 2020-01-16  Jan Beulich  <jbeulich@suse.com>
2958
2959         * i386-opc.tbl: Drop stale comment from XOP section.
2960
2961 2020-01-16  Jan Beulich  <jbeulich@suse.com>
2962
2963         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2964         (extractps): Add VexWIG to SSE2AVX forms.
2965         * i386-tbl.h: Re-generate.
2966
2967 2020-01-16  Jan Beulich  <jbeulich@suse.com>
2968
2969         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2970         Size64 from and use VexW1 on SSE2AVX forms.
2971         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2972         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2973         * i386-tbl.h: Re-generate.
2974
2975 2020-01-15  Alan Modra  <amodra@gmail.com>
2976
2977         * tic4x-dis.c (tic4x_version): Make unsigned long.
2978         (optab, optab_special, registernames): New file scope vars.
2979         (tic4x_print_register): Set up registernames rather than
2980         malloc'd registertable.
2981         (tic4x_disassemble): Delete optable and optable_special.  Use
2982         optab and optab_special instead.  Throw away old optab,
2983         optab_special and registernames when info->mach changes.
2984
2985 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
2986
2987         PR 25377
2988         * z80-dis.c (suffix): Use .db instruction to generate double
2989         prefix.
2990
2991 2020-01-14  Alan Modra  <amodra@gmail.com>
2992
2993         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
2994         values to unsigned before shifting.
2995
2996 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
2997
2998         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2999         flow instructions.
3000         (print_insn_thumb16, print_insn_thumb32): Likewise.
3001         (print_insn): Initialize the insn info.
3002         * i386-dis.c (print_insn): Initialize the insn info fields, and
3003         detect jumps.
3004
3005 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3006
3007         * arc-opc.c (C_NE): Make it required.
3008
3009 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3010
3011         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
3012         reserved register name.
3013
3014 2020-01-13  Alan Modra  <amodra@gmail.com>
3015
3016         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
3017         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
3018
3019 2020-01-13  Alan Modra  <amodra@gmail.com>
3020
3021         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
3022         result of wasm_read_leb128 in a uint64_t and check that bits
3023         are not lost when copying to other locals.  Use uint32_t for
3024         most locals.  Use PRId64 when printing int64_t.
3025
3026 2020-01-13  Alan Modra  <amodra@gmail.com>
3027
3028         * score-dis.c: Formatting.
3029         * score7-dis.c: Formatting.
3030
3031 2020-01-13  Alan Modra  <amodra@gmail.com>
3032
3033         * score-dis.c (print_insn_score48): Use unsigned variables for
3034         unsigned values.  Don't left shift negative values.
3035         (print_insn_score32): Likewise.
3036         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
3037
3038 2020-01-13  Alan Modra  <amodra@gmail.com>
3039
3040         * tic4x-dis.c (tic4x_print_register): Remove dead code.
3041
3042 2020-01-13  Alan Modra  <amodra@gmail.com>
3043
3044         * fr30-ibld.c: Regenerate.
3045
3046 2020-01-13  Alan Modra  <amodra@gmail.com>
3047
3048         * xgate-dis.c (print_insn): Don't left shift signed value.
3049         (ripBits): Formatting, use 1u.
3050
3051 2020-01-10  Alan Modra  <amodra@gmail.com>
3052
3053         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3054         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
3055
3056 2020-01-10  Alan Modra  <amodra@gmail.com>
3057
3058         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3059         and XRREG value earlier to avoid a shift with negative exponent.
3060         * m10200-dis.c (disassemble): Similarly.
3061
3062 2020-01-09  Nick Clifton  <nickc@redhat.com>
3063
3064         PR 25224
3065         * z80-dis.c (ld_ii_ii): Use correct cast.
3066
3067 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
3068
3069         PR 25224
3070         * z80-dis.c (ld_ii_ii): Use character constant when checking
3071         opcode byte value.
3072
3073 2020-01-09  Jan Beulich  <jbeulich@suse.com>
3074
3075         * i386-dis.c (SEP_Fixup): New.
3076         (SEP): Define.
3077         (dis386_twobyte): Use it for sysenter/sysexit.
3078         (enum x86_64_isa): Change amd64 enumerator to value 1.
3079         (OP_J): Compare isa64 against intel64 instead of amd64.
3080         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3081         forms.
3082         * i386-tbl.h: Re-generate.
3083
3084 2020-01-08  Alan Modra  <amodra@gmail.com>
3085
3086         * z8k-dis.c: Include libiberty.h
3087         (instr_data_s): Make max_fetched unsigned.
3088         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3089         Don't exceed byte_info bounds.
3090         (output_instr): Make num_bytes unsigned.
3091         (unpack_instr): Likewise for nibl_count and loop.
3092         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3093         idx unsigned.
3094         * z8k-opc.h: Regenerate.
3095
3096 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
3097
3098         * arc-tbl.h (llock): Use 'LLOCK' as class.
3099         (llockd): Likewise.
3100         (scond): Use 'SCOND' as class.
3101         (scondd): Likewise.
3102         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3103         (scondd): Likewise.
3104
3105 2020-01-06  Alan Modra  <amodra@gmail.com>
3106
3107         * m32c-ibld.c: Regenerate.
3108
3109 2020-01-06  Alan Modra  <amodra@gmail.com>
3110
3111         PR 25344
3112         * z80-dis.c (suffix): Don't use a local struct buffer copy.
3113         Peek at next byte to prevent recursion on repeated prefix bytes.
3114         Ensure uninitialised "mybuf" is not accessed.
3115         (print_insn_z80): Don't zero n_fetch and n_used here,..
3116         (print_insn_z80_buf): ..do it here instead.
3117
3118 2020-01-04  Alan Modra  <amodra@gmail.com>
3119
3120         * m32r-ibld.c: Regenerate.
3121
3122 2020-01-04  Alan Modra  <amodra@gmail.com>
3123
3124         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3125
3126 2020-01-04  Alan Modra  <amodra@gmail.com>
3127
3128         * crx-dis.c (match_opcode): Avoid shift left of signed value.
3129
3130 2020-01-04  Alan Modra  <amodra@gmail.com>
3131
3132         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3133
3134 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3135
3136         * aarch64-tbl.h (aarch64_opcode_table): Use
3137         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3138
3139 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3140
3141         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3142         forms of SUDOT and USDOT.
3143
3144 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3145
3146         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3147         uzip{1,2}.
3148         * aarch64-dis-2.c: Re-generate.
3149
3150 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3151
3152         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3153         FMMLA encoding.
3154         * aarch64-dis-2.c: Re-generate.
3155
3156 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
3157
3158         * z80-dis.c: Add support for eZ80 and Z80 instructions.
3159
3160 2020-01-01  Alan Modra  <amodra@gmail.com>
3161
3162         Update year range in copyright notice of all files.
3163
3164 For older changes see ChangeLog-2019
3165 \f
3166 Copyright (C) 2020 Free Software Foundation, Inc.
3167
3168 Copying and distribution of this file, with or without modification,
3169 are permitted in any medium without royalty provided the copyright
3170 notice and this notice are preserved.
3171
3172 Local Variables:
3173 mode: change-log
3174 left-margin: 8
3175 fill-column: 74
3176 version-control: never
3177 End: