opcodes/ChangeLog

   1 2019-10-30  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
   4         of W.
   5         * i386-opc.h (W): Extend comment.
   6         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
   7         general purpose variants not allowing for byte operands.
   8         * i386-tbl.h: Re-generate.
   9
  10 2019-10-29  Nick Clifton  <nickc@redhat.com>
  11
  12         * tic30-dis.c (print_branch): Correct size of operand array.
  13
  14 2019-10-29  Nick Clifton  <nickc@redhat.com>
  15
  16         * d30v-dis.c (print_insn): Check that operand index is valid
  17         before attempting to access the operands array.
  18
  19 2019-10-29  Nick Clifton  <nickc@redhat.com>
  20
  21         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
  22         locating the bit to be tested.
  23
  24 2019-10-29  Nick Clifton  <nickc@redhat.com>
  25
  26         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
  27         values.
  28         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
  29         (print_insn_s12z):  Check for illegal size values.
  30
  31 2019-10-28  Nick Clifton  <nickc@redhat.com>
  32
  33         * csky-dis.c (csky_chars_to_number): Check for a negative
  34         count. Use an unsigned integer to construct the return value.
  35
  36 2019-10-28  Nick Clifton  <nickc@redhat.com>
  37
  38         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
  39         operand buffer.  Set value to 15 not 13.
  40         (get_register_operand): Use OPERAND_BUFFER_LEN.
  41         (get_indirect_operand): Likewise.
  42         (print_two_operand): Likewise.
  43         (print_three_operand): Likewise.
  44         (print_oar_insn): Likewise.
  45
  46 2019-10-28  Nick Clifton  <nickc@redhat.com>
  47
  48         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
  49         (bit_extract_simple): Likewise.
  50         (bit_copy): Likewise.
  51         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
  52         index_offset array are not accessed.
  53
  54 2019-10-28  Nick Clifton  <nickc@redhat.com>
  55
  56         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
  57         operand.
  58
  59 2019-10-25  Nick Clifton  <nickc@redhat.com>
  60
  61         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
  62         access to opcodes.op array element.
  63
  64 2019-10-23  Nick Clifton  <nickc@redhat.com>
  65
  66         * rx-dis.c (get_register_name): Fix spelling typo in error
  67         message.
  68         (get_condition_name, get_flag_name, get_double_register_name)
  69         (get_double_register_high_name, get_double_register_low_name)
  70         (get_double_control_register_name, get_double_condition_name)
  71         (get_opsize_name, get_size_name): Likewise.
  72
  73 2019-10-22  Nick Clifton  <nickc@redhat.com>
  74
  75         * rx-dis.c (get_size_name): New function.  Provides safe
  76         access to name array.
  77         (get_opsize_name): Likewise.
  78         (print_insn_rx): Use the accessor functions.
  79
  80 2019-10-16  Nick Clifton  <nickc@redhat.com>
  81
  82         * rx-dis.c (get_register_name): New function.  Provides safe
  83         access to name array.
  84         (get_condition_name, get_flag_name, get_double_register_name)
  85         (get_double_register_high_name, get_double_register_low_name)
  86         (get_double_control_register_name, get_double_condition_name):
  87         Likewise.
  88         (print_insn_rx): Use the accessor functions.
  89
  90 2019-10-09  Nick Clifton  <nickc@redhat.com>
  91
  92         PR 25041
  93         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
  94         instructions.
  95
  96 2019-10-07  Jan Beulich  <jbeulich@suse.com>
  97
  98         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
  99         (cmpsd): Likewise. Move EsSeg to other operand.
 100         * opcodes/i386-tbl.h: Re-generate.
 101
 102 2019-09-23  Alan Modra  <amodra@gmail.com>
 103
 104         * m68k-dis.c: Include cpu-m68k.h
 105
 106 2019-09-23  Alan Modra  <amodra@gmail.com>
 107
 108         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 109         "elf/mips.h" earlier.
 110
 111 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 112
 113         PR gas/25012
 114         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 115         with SReg operand.
 116         * i386-tbl.h: Re-generate.
 117
 118 2019-09-18  Alan Modra  <amodra@gmail.com>
 119
 120         * arc-ext.c: Update throughout for bfd section macro changes.
 121
 122 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 123
 124         * Makefile.in: Re-generate.
 125         * configure: Re-generate.
 126
 127 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 128
 129         * riscv-opc.c (riscv_opcodes): Change subset field
 130         to insn_class field for all instructions.
 131         (riscv_insn_types): Likewise.
 132
 133 2019-09-16  Phil Blundell  <pb@pbcl.net>
 134
 135         * configure: Regenerated.
 136
 137 2019-09-10  Miod Vallat  <miod@online.fr>
 138
 139         PR 24982
 140         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 141
 142 2019-09-09  Phil Blundell  <pb@pbcl.net>
 143
 144         binutils 2.33 branch created.
 145
 146 2019-09-03  Nick Clifton  <nickc@redhat.com>
 147
 148         PR 24961
 149         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 150         greater than zero before indexing via (bufcnt -1).
 151
 152 2019-09-03  Nick Clifton  <nickc@redhat.com>
 153
 154         PR 24958
 155         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 156         (MAX_SPEC_REG_NAME_LEN): Define.
 157         (struct mmix_dis_info): Use defined constants for array lengths.
 158         (get_reg_name): New function.
 159         (get_sprec_reg_name): New function.
 160         (print_insn_mmix): Use new functions.
 161
 162 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 163
 164         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 165         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 166         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 167
 168 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 169
 170         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 171         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 172         (aarch64_sys_reg_supported_p): Update checks for the above.
 173
 174 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 175
 176         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 177         cases MVE_SQRSHRL and MVE_UQRSHLL.
 178         (print_insn_mve): Add case for specifier 'k' to check
 179         specific bit of the instruction.
 180
 181 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 182
 183         PR 24854
 184         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 185         encountering an unknown machine type.
 186         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 187         cases return -1 rather than calling abort.
 188
 189 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 192         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 193         IgnoreSize.
 194         * i386-tbl.h: Re-generate.
 195
 196 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 197
 198         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 199         instructions.
 200
 201 2019-07-30  Mel Chen <mel.chen@sifive.com>
 202
 203         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 204         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 205
 206         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 207         fscsr.
 208
 209 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 210
 211         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 212         and MPY class instructions.
 213         (parse_option): Add nps400 option.
 214         (print_arc_disassembler_options): Add nps400 info.
 215
 216 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 217
 218         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 219         (bspop): Likewise.
 220         (modapp): Likewise.
 221         * arc-opc.c (RAD_CHK): Add.
 222         * arc-tbl.h: Regenerate.
 223
 224 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 225
 226         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 227         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 228
 229 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 230
 231         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 232         instructions as UNPREDICTABLE.
 233
 234 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 235
 236         * bpf-desc.c: Regenerated.
 237
 238 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-gen.c (static_assert): Define.
 241         (main): Use it.
 242         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 243         (Opcode_Modifier_Num): ... this.
 244         (Mem): Delete.
 245
 246 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-gen.c (operand_types): Move RegMem ...
 249         (opcode_modifiers): ... here.
 250         * i386-opc.h (RegMem): Move to opcode modifer enum.
 251         (union i386_operand_type): Move regmem field ...
 252         (struct i386_opcode_modifier): ... here.
 253         * i386-opc.tbl (RegMem): Define.
 254         (mov, movq): Move RegMem on segment, control, debug, and test
 255         register flavors.
 256         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 257         to non-SSE2AVX flavor.
 258         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 259         Move RegMem on register only flavors. Drop IgnoreSize from
 260         legacy encoding flavors.
 261         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 262         flavors.
 263         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 264         register only flavors.
 265         (vmovd): Move RegMem and drop IgnoreSize on register only
 266         flavor. Change opcode and operand order to store form.
 267         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 268
 269 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 272         entries.
 273         * i386-opc.h (SReg2, SReg3): Replace by ...
 274         (SReg): ... this.
 275         (union i386_operand_type): Replace sreg fields.
 276         * i386-opc.tbl (mov, ): Use SReg.
 277         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 278         register flavors.
 279         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 280         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 281
 282 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 283
 284         * bpf-desc.c: Regenerate.
 285         * bpf-opc.c: Likewise.
 286         * bpf-opc.h: Likewise.
 287
 288 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 289
 290         * bpf-desc.c: Regenerate.
 291         * bpf-opc.c: Likewise.
 292
 293 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 294
 295         * arm-dis.c (print_insn_coprocessor): Rename index to
 296         index_operand.
 297
 298 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 299
 300         * riscv-opc.c (riscv_insn_types): Add r4 type.
 301
 302         * riscv-opc.c (riscv_insn_types): Add b and j type.
 303
 304         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 305         format for sb type and correct s type.
 306
 307 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 308
 309         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 310         SVE FMOV alias of FCPY.
 311
 312 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 313
 314         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 315         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 316
 317 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 318
 319         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 320         registers in an instruction prefixed by MOVPRFX.
 321
 322 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 323
 324         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 325         sve_size_13 icode to account for variant behaviour of
 326         pmull{t,b}.
 327         * aarch64-dis-2.c: Regenerate.
 328         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 329         sve_size_13 icode to account for variant behaviour of
 330         pmull{t,b}.
 331         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 332         (OP_SVE_VVV_Q_D): Add new qualifier.
 333         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 334         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 335         AES and those not.
 336
 337 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 338
 339         * opcodes/i386-gen.c (operand_type_init): Remove
 340         OPERAND_TYPE_VEC_IMM4 entry.
 341         (operand_types): Remove Vec_Imm4.
 342         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 343         (union i386_operand_type): Remove vec_imm4.
 344         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 345         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 346
 347 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 350         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 351         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 352         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 353         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 354         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 355         * i386-tbl.h: Re-generate.
 356
 357 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 360         register operands.
 361         * i386-tbl.h: Re-generate.
 362
 363 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-opc.tbl (C): New.
 366         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 367         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 368         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 369         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 370         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 371         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 372         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 373         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 374         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 375         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 376         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 377         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 378         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 379         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 380         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 381         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 382         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 383         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 384         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 385         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 386         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 387         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 388         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 389         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 390         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 391         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 392         flavors.
 393         * i386-tbl.h: Re-generate.
 394
 395 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 398         register operands.
 399         * i386-tbl.h: Re-generate.
 400
 401 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 402
 403         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 404         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 405         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 406         * i386-tbl.h: Re-generate.
 407
 408 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 409
 410         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 411         Disp8MemShift from register only templates.
 412         * i386-tbl.h: Re-generate.
 413
 414 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 417         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 418         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 419         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 420         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 421         EVEX_W_0F11_P_3_M_1): Delete.
 422         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 423         EVEX_W_0F11_P_3): New.
 424         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 425         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 426         MOD_EVEX_0F11_PREFIX_3 table entries.
 427         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 428         PREFIX_EVEX_0F11 table entries.
 429         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 430         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 431         EVEX_W_0F11_P_3_M_{0,1} table entries.
 432
 433 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 434
 435         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 436         Delete.
 437
 438 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         PR binutils/24719
 441         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 442         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 443         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 444         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 445         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 446         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 447         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 448         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 449         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 450         PREFIX_EVEX_0F38C6_REG_6 entries.
 451         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 452         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 453         EVEX_W_0F38C7_R_6_P_2 entries.
 454         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 455         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 456         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 457         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 458         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 459         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 460         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 461
 462 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 463
 464         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 465         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 466         VEX_LEN_0F2D_P_3): Delete.
 467         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 468         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 469         (prefix_table): ... here.
 470
 471 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 472
 473         * i386-dis.c (Iq): Delete.
 474         (Id): New.
 475         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 476         TBM insns.
 477         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 478         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 479         (OP_E_memory): Also honor needindex when deciding whether an
 480         address size prefix needs printing.
 481         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 482
 483 2019-06-26  Jim Wilson  <jimw@sifive.com>
 484
 485         PR binutils/24739
 486         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 487         Set info->display_endian to info->endian_code.
 488
 489 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 492         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 493         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 494         OPERAND_TYPE_ACC64 entries.
 495         * i386-init.h: Re-generate.
 496
 497 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 498
 499         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 500         Delete.
 501         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 502         of dqa_mode.
 503         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 504         entries here.
 505         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 506         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 507
 508 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 509
 510         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 511         variables.
 512
 513 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 514
 515         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 516         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 517         movnti.
 518         * i386-opc.tbl (movnti): Add IgnoreSize.
 519         * i386-tbl.h: Re-generate.
 520
 521 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 524         * i386-tbl.h: Re-generate.
 525
 526 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 527
 528         * i386-dis-evex.h: Break into ...
 529         * i386-dis-evex-len.h: New file.
 530         * i386-dis-evex-mod.h: Likewise.
 531         * i386-dis-evex-prefix.h: Likewise.
 532         * i386-dis-evex-reg.h: Likewise.
 533         * i386-dis-evex-w.h: Likewise.
 534         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 535         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 536         i386-dis-evex-mod.h.
 537
 538 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 539
 540         PR binutils/24700
 541         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 542         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 543         EVEX_W_0F385B_P_2.
 544         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 545         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 546         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 547         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 548         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 549         EVEX_LEN_0F385B_P_2_W_1.
 550         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 551         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 552         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 553         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 554         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 555         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 556         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 557         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 558         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 559         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 560
 561 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         PR binutils/24691
 564         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 565         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 566         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 567         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 568         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 569         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 570         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 571         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 572         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 573         EVEX_LEN_0F3A43_P_2_W_1.
 574         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 575         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 576         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 577         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 578         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 579         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 580         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 581         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 582         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 583         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 584         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 585         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 586
 587 2019-06-14  Nick Clifton  <nickc@redhat.com>
 588
 589         * po/fr.po; Updated French translation.
 590
 591 2019-06-13  Stafford Horne  <shorne@gmail.com>
 592
 593         * or1k-asm.c: Regenerated.
 594         * or1k-desc.c: Regenerated.
 595         * or1k-desc.h: Regenerated.
 596         * or1k-dis.c: Regenerated.
 597         * or1k-ibld.c: Regenerated.
 598         * or1k-opc.c: Regenerated.
 599         * or1k-opc.h: Regenerated.
 600         * or1k-opinst.c: Regenerated.
 601
 602 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 603
 604         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 605
 606 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 607
 608         PR binutils/24633
 609         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 610         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 611         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 612         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 613         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 614         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 615         EVEX_LEN_0F3A1B_P_2_W_1.
 616         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 617         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 618         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 619         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 620         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 621         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 622         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 623         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 624
 625 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 626
 627         PR binutils/24626
 628         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 629         EVEX.vvvv when disassembling VEX and EVEX instructions.
 630         (OP_VEX): Set vex.register_specifier to 0 after readding
 631         vex.register_specifier.
 632         (OP_Vex_2src_1): Likewise.
 633         (OP_Vex_2src_2): Likewise.
 634         (OP_LWP_E): Likewise.
 635         (OP_EX_Vex): Don't check vex.register_specifier.
 636         (OP_XMM_Vex): Likewise.
 637
 638 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 639             Lili Cui  <lili.cui@intel.com>
 640
 641         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 642         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 643         instructions.
 644         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 645         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 646         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 647         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 648         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 649         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 650         * i386-init.h: Regenerated.
 651         * i386-tbl.h: Likewise.
 652
 653 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 654             Lili Cui  <lili.cui@intel.com>
 655
 656         * doc/c-i386.texi: Document enqcmd.
 657         * testsuite/gas/i386/enqcmd-intel.d: New file.
 658         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 659         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 660         * testsuite/gas/i386/enqcmd.d: Likewise.
 661         * testsuite/gas/i386/enqcmd.s: Likewise.
 662         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 663         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 664         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 665         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 666         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 667         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 668         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 669         and x86-64-enqcmd.
 670
 671 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 672
 673         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 674
 675 2019-06-03  Alan Modra  <amodra@gmail.com>
 676
 677         * ppc-dis.c (prefix_opcd_indices): Correct size.
 678
 679 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         PR gas/24625
 682         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 683         Disp8ShiftVL.
 684         * i386-tbl.h: Regenerated.
 685
 686 2019-05-24  Alan Modra  <amodra@gmail.com>
 687
 688         * po/POTFILES.in: Regenerate.
 689
 690 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 691             Alan Modra  <amodra@gmail.com>
 692
 693         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 694         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 695         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 696         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 697         XTOP>): Define and add entries.
 698         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 699         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 700         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 701         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 702
 703 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 704             Alan Modra  <amodra@gmail.com>
 705
 706         * ppc-dis.c (ppc_opts): Add "future" entry.
 707         (PREFIX_OPCD_SEGS): Define.
 708         (prefix_opcd_indices): New array.
 709         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 710         (lookup_prefix): New function.
 711         (print_insn_powerpc): Handle 64-bit prefix instructions.
 712         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 713         (PMRR, POWERXX): Define.
 714         (prefix_opcodes): New instruction table.
 715         (prefix_num_opcodes): New constant.
 716
 717 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 718
 719         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 720         * configure: Regenerated.
 721         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 722         and cpu/bpf.opc.
 723         (HFILES): Add bpf-desc.h and bpf-opc.h.
 724         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 725         bpf-ibld.c and bpf-opc.c.
 726         (BPF_DEPS): Define.
 727         * Makefile.in: Regenerated.
 728         * disassemble.c (ARCH_bpf): Define.
 729         (disassembler): Add case for bfd_arch_bpf.
 730         (disassemble_init_for_target): Likewise.
 731         (enum epbf_isa_attr): Define.
 732         * disassemble.h: extern print_insn_bpf.
 733         * bpf-asm.c: Generated.
 734         * bpf-opc.h: Likewise.
 735         * bpf-opc.c: Likewise.
 736         * bpf-ibld.c: Likewise.
 737         * bpf-dis.c: Likewise.
 738         * bpf-desc.h: Likewise.
 739         * bpf-desc.c: Likewise.
 740
 741 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 742
 743         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 744         and VMSR with the new operands.
 745
 746 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 747
 748         * arm-dis.c (enum mve_instructions): New enum
 749         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 750         and cneg.
 751         (mve_opcodes): New instructions as above.
 752         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 753         csneg and csel.
 754         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 755
 756 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 757
 758         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 759         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 760         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 761         uqshl, urshrl and urshr.
 762         (is_mve_okay_in_it): Add new instructions to TRUE list.
 763         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 764         (print_insn_mve): Updated to accept new %j,
 765         %<bitfield>m and %<bitfield>n patterns.
 766
 767 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 768
 769         * mips-opc.c (mips_builtin_opcodes): Change source register
 770         constraint for DAUI.
 771
 772 2019-05-20  Nick Clifton  <nickc@redhat.com>
 773
 774         * po/fr.po: Updated French translation.
 775
 776 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 777             Michael Collison <michael.collison@arm.com>
 778
 779         * arm-dis.c (thumb32_opcodes): Add new instructions.
 780         (enum mve_instructions): Likewise.
 781         (enum mve_undefined): Add new reasons.
 782         (is_mve_encoding_conflict): Handle new instructions.
 783         (is_mve_undefined): Likewise.
 784         (is_mve_unpredictable): Likewise.
 785         (print_mve_undefined): Likewise.
 786         (print_mve_size): Likewise.
 787
 788 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 789             Michael Collison <michael.collison@arm.com>
 790
 791         * arm-dis.c (thumb32_opcodes): Add new instructions.
 792         (enum mve_instructions): Likewise.
 793         (is_mve_encoding_conflict): Handle new instructions.
 794         (is_mve_undefined): Likewise.
 795         (is_mve_unpredictable): Likewise.
 796         (print_mve_size): Likewise.
 797
 798 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 799             Michael Collison <michael.collison@arm.com>
 800
 801         * arm-dis.c (thumb32_opcodes): Add new instructions.
 802         (enum mve_instructions): Likewise.
 803         (is_mve_encoding_conflict): Likewise.
 804         (is_mve_unpredictable): Likewise.
 805         (print_mve_size): Likewise.
 806
 807 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 808             Michael Collison <michael.collison@arm.com>
 809
 810         * arm-dis.c (thumb32_opcodes): Add new instructions.
 811         (enum mve_instructions): Likewise.
 812         (is_mve_encoding_conflict): Handle new instructions.
 813         (is_mve_undefined): Likewise.
 814         (is_mve_unpredictable): Likewise.
 815         (print_mve_size): Likewise.
 816
 817 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 818             Michael Collison <michael.collison@arm.com>
 819
 820         * arm-dis.c (thumb32_opcodes): Add new instructions.
 821         (enum mve_instructions): Likewise.
 822         (is_mve_encoding_conflict): Handle new instructions.
 823         (is_mve_undefined): Likewise.
 824         (is_mve_unpredictable): Likewise.
 825         (print_mve_size): Likewise.
 826         (print_insn_mve): Likewise.
 827
 828 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 829             Michael Collison <michael.collison@arm.com>
 830
 831         * arm-dis.c (thumb32_opcodes): Add new instructions.
 832         (print_insn_thumb32): Handle new instructions.
 833
 834 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 835             Michael Collison <michael.collison@arm.com>
 836
 837         * arm-dis.c (enum mve_instructions): Add new instructions.
 838         (enum mve_undefined): Add new reasons.
 839         (is_mve_encoding_conflict): Handle new instructions.
 840         (is_mve_undefined): Likewise.
 841         (is_mve_unpredictable): Likewise.
 842         (print_mve_undefined): Likewise.
 843         (print_mve_size): Likewise.
 844         (print_mve_shift_n): Likewise.
 845         (print_insn_mve): Likewise.
 846
 847 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 848             Michael Collison <michael.collison@arm.com>
 849
 850         * arm-dis.c (enum mve_instructions): Add new instructions.
 851         (is_mve_encoding_conflict): Handle new instructions.
 852         (is_mve_unpredictable): Likewise.
 853         (print_mve_rotate): Likewise.
 854         (print_mve_size): Likewise.
 855         (print_insn_mve): Likewise.
 856
 857 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 858             Michael Collison <michael.collison@arm.com>
 859
 860         * arm-dis.c (enum mve_instructions): Add new instructions.
 861         (is_mve_encoding_conflict): Handle new instructions.
 862         (is_mve_unpredictable): Likewise.
 863         (print_mve_size): Likewise.
 864         (print_insn_mve): Likewise.
 865
 866 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 867             Michael Collison <michael.collison@arm.com>
 868
 869         * arm-dis.c (enum mve_instructions): Add new instructions.
 870         (enum mve_undefined): Add new reasons.
 871         (is_mve_encoding_conflict): Handle new instructions.
 872         (is_mve_undefined): Likewise.
 873         (is_mve_unpredictable): Likewise.
 874         (print_mve_undefined): Likewise.
 875         (print_mve_size): Likewise.
 876         (print_insn_mve): Likewise.
 877
 878 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 879             Michael Collison <michael.collison@arm.com>
 880
 881         * arm-dis.c (enum mve_instructions): Add new instructions.
 882         (is_mve_encoding_conflict): Handle new instructions.
 883         (is_mve_undefined): Likewise.
 884         (is_mve_unpredictable): Likewise.
 885         (print_mve_size): Likewise.
 886         (print_insn_mve): Likewise.
 887
 888 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 889             Michael Collison <michael.collison@arm.com>
 890
 891         * arm-dis.c (enum mve_instructions): Add new instructions.
 892         (enum mve_unpredictable): Add new reasons.
 893         (enum mve_undefined): Likewise.
 894         (is_mve_okay_in_it): Handle new isntructions.
 895         (is_mve_encoding_conflict): Likewise.
 896         (is_mve_undefined): Likewise.
 897         (is_mve_unpredictable): Likewise.
 898         (print_mve_vmov_index): Likewise.
 899         (print_simd_imm8): Likewise.
 900         (print_mve_undefined): Likewise.
 901         (print_mve_unpredictable): Likewise.
 902         (print_mve_size): Likewise.
 903         (print_insn_mve): Likewise.
 904
 905 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 906             Michael Collison <michael.collison@arm.com>
 907
 908         * arm-dis.c (enum mve_instructions): Add new instructions.
 909         (enum mve_unpredictable): Add new reasons.
 910         (enum mve_undefined): Likewise.
 911         (is_mve_encoding_conflict): Handle new instructions.
 912         (is_mve_undefined): Likewise.
 913         (is_mve_unpredictable): Likewise.
 914         (print_mve_undefined): Likewise.
 915         (print_mve_unpredictable): Likewise.
 916         (print_mve_rounding_mode): Likewise.
 917         (print_mve_vcvt_size): Likewise.
 918         (print_mve_size): Likewise.
 919         (print_insn_mve): Likewise.
 920
 921 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 922             Michael Collison <michael.collison@arm.com>
 923
 924         * arm-dis.c (enum mve_instructions): Add new instructions.
 925         (enum mve_unpredictable): Add new reasons.
 926         (enum mve_undefined): Likewise.
 927         (is_mve_undefined): Handle new instructions.
 928         (is_mve_unpredictable): Likewise.
 929         (print_mve_undefined): Likewise.
 930         (print_mve_unpredictable): Likewise.
 931         (print_mve_size): Likewise.
 932         (print_insn_mve): Likewise.
 933
 934 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 935             Michael Collison <michael.collison@arm.com>
 936
 937         * arm-dis.c (enum mve_instructions): Add new instructions.
 938         (enum mve_undefined): Add new reasons.
 939         (insns): Add new instructions.
 940         (is_mve_encoding_conflict):
 941         (print_mve_vld_str_addr): New print function.
 942         (is_mve_undefined): Handle new instructions.
 943         (is_mve_unpredictable): Likewise.
 944         (print_mve_undefined): Likewise.
 945         (print_mve_size): Likewise.
 946         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 947         (print_insn_mve):  Handle new operands.
 948
 949 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 950             Michael Collison <michael.collison@arm.com>
 951
 952         * arm-dis.c (enum mve_instructions): Add new instructions.
 953         (enum mve_unpredictable): Add new reasons.
 954         (is_mve_encoding_conflict): Handle new instructions.
 955         (is_mve_unpredictable): Likewise.
 956         (mve_opcodes): Add new instructions.
 957         (print_mve_unpredictable): Handle new reasons.
 958         (print_mve_register_blocks): New print function.
 959         (print_mve_size): Handle new instructions.
 960         (print_insn_mve): Likewise.
 961
 962 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 963             Michael Collison <michael.collison@arm.com>
 964
 965         * arm-dis.c (enum mve_instructions): Add new instructions.
 966         (enum mve_unpredictable): Add new reasons.
 967         (enum mve_undefined): Likewise.
 968         (is_mve_encoding_conflict): Handle new instructions.
 969         (is_mve_undefined): Likewise.
 970         (is_mve_unpredictable): Likewise.
 971         (coprocessor_opcodes): Move NEON VDUP from here...
 972         (neon_opcodes): ... to here.
 973         (mve_opcodes): Add new instructions.
 974         (print_mve_undefined):  Handle new reasons.
 975         (print_mve_unpredictable): Likewise.
 976         (print_mve_size): Handle new instructions.
 977         (print_insn_neon): Handle vdup.
 978         (print_insn_mve): Handle new operands.
 979
 980 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 981             Michael Collison <michael.collison@arm.com>
 982
 983         * arm-dis.c (enum mve_instructions): Add new instructions.
 984         (enum mve_unpredictable): Add new values.
 985         (mve_opcodes): Add new instructions.
 986         (vec_condnames): New array with vector conditions.
 987         (mve_predicatenames): New array with predicate suffixes.
 988         (mve_vec_sizename): New array with vector sizes.
 989         (enum vpt_pred_state): New enum with vector predication states.
 990         (struct vpt_block): New struct type for vpt blocks.
 991         (vpt_block_state): Global struct to keep track of state.
 992         (mve_extract_pred_mask): New helper function.
 993         (num_instructions_vpt_block): Likewise.
 994         (mark_outside_vpt_block): Likewise.
 995         (mark_inside_vpt_block): Likewise.
 996         (invert_next_predicate_state): Likewise.
 997         (update_next_predicate_state): Likewise.
 998         (update_vpt_block_state): Likewise.
 999         (is_vpt_instruction): Likewise.
1000         (is_mve_encoding_conflict): Add entries for new instructions.
1001         (is_mve_unpredictable): Likewise.
1002         (print_mve_unpredictable): Handle new cases.
1003         (print_instruction_predicate): Likewise.
1004         (print_mve_size): New function.
1005         (print_vec_condition): New function.
1006         (print_insn_mve): Handle vpt blocks and new print operands.
1007
1008 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1009
1010         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1011         8, 14 and 15 for Armv8.1-M Mainline.
1012
1013 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1014             Michael Collison <michael.collison@arm.com>
1015
1016         * arm-dis.c (enum mve_instructions): New enum.
1017         (enum mve_unpredictable): Likewise.
1018         (enum mve_undefined): Likewise.
1019         (struct mopcode32): New struct.
1020         (is_mve_okay_in_it): New function.
1021         (is_mve_architecture): Likewise.
1022         (arm_decode_field): Likewise.
1023         (arm_decode_field_multiple): Likewise.
1024         (is_mve_encoding_conflict): Likewise.
1025         (is_mve_undefined): Likewise.
1026         (is_mve_unpredictable): Likewise.
1027         (print_mve_undefined): Likewise.
1028         (print_mve_unpredictable): Likewise.
1029         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1030         (print_insn_mve): New function.
1031         (print_insn_thumb32): Handle MVE architecture.
1032         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1033
1034 2019-05-10  Nick Clifton  <nickc@redhat.com>
1035
1036         PR 24538
1037         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1038         end of the table prematurely.
1039
1040 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1041
1042         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1043         macros for R6.
1044
1045 2019-05-11  Alan Modra  <amodra@gmail.com>
1046
1047         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1048         when -Mraw is in effect.
1049
1050 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1051
1052         * aarch64-dis-2.c: Regenerate.
1053         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1054         (OP_SVE_BBB): New variant set.
1055         (OP_SVE_DDDD): New variant set.
1056         (OP_SVE_HHH): New variant set.
1057         (OP_SVE_HHHU): New variant set.
1058         (OP_SVE_SSS): New variant set.
1059         (OP_SVE_SSSU): New variant set.
1060         (OP_SVE_SHH): New variant set.
1061         (OP_SVE_SBBU): New variant set.
1062         (OP_SVE_DSS): New variant set.
1063         (OP_SVE_DHHU): New variant set.
1064         (OP_SVE_VMV_HSD_BHS): New variant set.
1065         (OP_SVE_VVU_HSD_BHS): New variant set.
1066         (OP_SVE_VVVU_SD_BH): New variant set.
1067         (OP_SVE_VVVU_BHSD): New variant set.
1068         (OP_SVE_VVV_QHD_DBS): New variant set.
1069         (OP_SVE_VVV_HSD_BHS): New variant set.
1070         (OP_SVE_VVV_HSD_BHS2): New variant set.
1071         (OP_SVE_VVV_BHS_HSD): New variant set.
1072         (OP_SVE_VV_BHS_HSD): New variant set.
1073         (OP_SVE_VVV_SD): New variant set.
1074         (OP_SVE_VVU_BHS_HSD): New variant set.
1075         (OP_SVE_VZVV_SD): New variant set.
1076         (OP_SVE_VZVV_BH): New variant set.
1077         (OP_SVE_VZV_SD): New variant set.
1078         (aarch64_opcode_table): Add sve2 instructions.
1079
1080 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1081
1082         * aarch64-asm-2.c: Regenerated.
1083         * aarch64-dis-2.c: Regenerated.
1084         * aarch64-opc-2.c: Regenerated.
1085         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1086         for SVE_SHLIMM_UNPRED_22.
1087         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1088         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1089         operand.
1090
1091 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1092
1093         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1094         sve_size_tsz_bhs iclass encode.
1095         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1096         sve_size_tsz_bhs iclass decode.
1097
1098 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1099
1100         * aarch64-asm-2.c: Regenerated.
1101         * aarch64-dis-2.c: Regenerated.
1102         * aarch64-opc-2.c: Regenerated.
1103         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1104         for SVE_Zm4_11_INDEX.
1105         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1106         (fields): Handle SVE_i2h field.
1107         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1108         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1109
1110 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1111
1112         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1113         sve_shift_tsz_bhsd iclass encode.
1114         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1115         sve_shift_tsz_bhsd iclass decode.
1116
1117 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1118
1119         * aarch64-asm-2.c: Regenerated.
1120         * aarch64-dis-2.c: Regenerated.
1121         * aarch64-opc-2.c: Regenerated.
1122         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1123         (aarch64_encode_variant_using_iclass): Handle
1124         sve_shift_tsz_hsd iclass encode.
1125         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1126         sve_shift_tsz_hsd iclass decode.
1127         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1128         for SVE_SHRIMM_UNPRED_22.
1129         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1130         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1131         operand.
1132
1133 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1134
1135         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1136         sve_size_013 iclass encode.
1137         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1138         sve_size_013 iclass decode.
1139
1140 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1141
1142         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1143         sve_size_bh iclass encode.
1144         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1145         sve_size_bh iclass decode.
1146
1147 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1148
1149         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1150         sve_size_sd2 iclass encode.
1151         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1152         sve_size_sd2 iclass decode.
1153         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1154         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1155
1156 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1157
1158         * aarch64-asm-2.c: Regenerated.
1159         * aarch64-dis-2.c: Regenerated.
1160         * aarch64-opc-2.c: Regenerated.
1161         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1162         for SVE_ADDR_ZX.
1163         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1164         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1165
1166 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1167
1168         * aarch64-asm-2.c: Regenerated.
1169         * aarch64-dis-2.c: Regenerated.
1170         * aarch64-opc-2.c: Regenerated.
1171         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1172         for SVE_Zm3_11_INDEX.
1173         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1174         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1175         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1176         fields.
1177         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1178
1179 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1180
1181         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1182         sve_size_hsd2 iclass encode.
1183         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1184         sve_size_hsd2 iclass decode.
1185         * aarch64-opc.c (fields): Handle SVE_size field.
1186         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1187
1188 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1189
1190         * aarch64-asm-2.c: Regenerated.
1191         * aarch64-dis-2.c: Regenerated.
1192         * aarch64-opc-2.c: Regenerated.
1193         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1194         for SVE_IMM_ROT3.
1195         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1196         (fields): Handle SVE_rot3 field.
1197         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1198         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1199
1200 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1201
1202         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1203         instructions.
1204
1205 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1206
1207         * aarch64-tbl.h
1208         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1209         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1210         aarch64_feature_sve2bitperm): New feature sets.
1211         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1212         for feature set addresses.
1213         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1214         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1215
1216 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1217             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1218
1219         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1220         argument and set ASE_EVA_R6 appropriately.
1221         (set_default_mips_dis_options): Pass ISA to above.
1222         (parse_mips_dis_option): Likewise.
1223         * mips-opc.c (EVAR6): New macro.
1224         (mips_builtin_opcodes): Add llwpe, scwpe.
1225
1226 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1227
1228         * aarch64-asm-2.c: Regenerated.
1229         * aarch64-dis-2.c: Regenerated.
1230         * aarch64-opc-2.c: Regenerated.
1231         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1232         AARCH64_OPND_TME_UIMM16.
1233         (aarch64_print_operand): Likewise.
1234         * aarch64-tbl.h (QL_IMM_NIL): New.
1235         (TME): New.
1236         (_TME_INSN): New.
1237         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1238
1239 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1240
1241         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1242
1243 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1244             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1245
1246         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1247
1248 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1249
1250         * s12z-opc.h: Add extern "C" bracketing to help
1251         users who wish to use this interface in c++ code.
1252
1253 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1254
1255         * s12z-opc.c (bm_decode): Handle bit map operations with the
1256         "reserved0" mode.
1257
1258 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1259
1260         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1261         specifier.  Add entries for VLDR and VSTR of system registers.
1262         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1263         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1264         of %J and %K format specifier.
1265
1266 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1267
1268         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1269         Add new entries for VSCCLRM instruction.
1270         (print_insn_coprocessor): Handle new %C format control code.
1271
1272 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1273
1274         * arm-dis.c (enum isa): New enum.
1275         (struct sopcode32): New structure.
1276         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1277         set isa field of all current entries to ANY.
1278         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1279         Only match an entry if its isa field allows the current mode.
1280
1281 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1282
1283         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1284         CLRM.
1285         (print_insn_thumb32): Add logic to print %n CLRM register list.
1286
1287 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1288
1289         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1290         and %Q patterns.
1291
1292 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1293
1294         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1295         (print_insn_thumb32): Edit the switch case for %Z.
1296
1297 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1298
1299         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1300
1301 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1302
1303         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1304
1305 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1306
1307         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1308
1309 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1310
1311         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1312         Arm register with r13 and r15 unpredictable.
1313         (thumb32_opcodes): New instructions for bfx and bflx.
1314
1315 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1316
1317         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1318
1319 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1320
1321         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1322
1323 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1324
1325         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1326
1327 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1328
1329         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1330
1331 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1332
1333         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1334         "optr". ("operator" is a reserved word in c++).
1335
1336 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1337
1338         * aarch64-opc.c (aarch64_print_operand): Add case for
1339         AARCH64_OPND_Rt_SP.
1340         (verify_constraints): Likewise.
1341         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1342         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1343         to accept Rt|SP as first operand.
1344         (AARCH64_OPERANDS): Add new Rt_SP.
1345         * aarch64-asm-2.c: Regenerated.
1346         * aarch64-dis-2.c: Regenerated.
1347         * aarch64-opc-2.c: Regenerated.
1348
1349 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1350
1351         * aarch64-asm-2.c: Regenerated.
1352         * aarch64-dis-2.c: Likewise.
1353         * aarch64-opc-2.c: Likewise.
1354         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1355
1356 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1357
1358         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1359
1360 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1361
1362         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1363         * i386-init.h: Regenerated.
1364
1365 2019-04-07  Alan Modra  <amodra@gmail.com>
1366
1367         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1368         op_separator to control printing of spaces, comma and parens
1369         rather than need_comma, need_paren and spaces vars.
1370
1371 2019-04-07  Alan Modra  <amodra@gmail.com>
1372
1373         PR 24421
1374         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1375         (print_insn_neon, print_insn_arm): Likewise.
1376
1377 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1378
1379         * i386-dis-evex.h (evex_table): Updated to support BF16
1380         instructions.
1381         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1382         and EVEX_W_0F3872_P_3.
1383         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1384         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1385         * i386-opc.h (enum): Add CpuAVX512_BF16.
1386         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1387         * i386-opc.tbl: Add AVX512 BF16 instructions.
1388         * i386-init.h: Regenerated.
1389         * i386-tbl.h: Likewise.
1390
1391 2019-04-05  Alan Modra  <amodra@gmail.com>
1392
1393         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1394         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1395         to favour printing of "-" branch hint when using the "y" bit.
1396         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1397
1398 2019-04-05  Alan Modra  <amodra@gmail.com>
1399
1400         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1401         opcode until first operand is output.
1402
1403 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1404
1405         PR gas/24349
1406         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1407         (valid_bo_post_v2): Add support for 'at' branch hints.
1408         (insert_bo): Only error on branch on ctr.
1409         (get_bo_hint_mask): New function.
1410         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1411         for inserting 'at' branch hints.
1412         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1413         for extracting 'at' branch hints.
1414         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1415         (BOE): Delete operand.
1416         (BOM, BOP): New operands.
1417         (RM): Update value.
1418         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1419         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1420         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1421         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1422         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1423         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1424         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1425         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1426         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1427         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1428         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1429         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1430         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1431         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1432         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1433         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1434         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1435         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1436         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1437         bttarl+>: New extended mnemonics.
1438
1439 2019-03-28  Alan Modra  <amodra@gmail.com>
1440
1441         PR 24390
1442         * ppc-opc.c (BTF): Define.
1443         (powerpc_opcodes): Use for mtfsb*.
1444         * ppc-dis.c (print_insn_powerpc): Print fields with both
1445         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1446
1447 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1448
1449         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1450         (mapping_symbol_for_insn): Implement new algorithm.
1451         (print_insn): Remove duplicate code.
1452
1453 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1454
1455         * aarch64-dis.c (print_insn_aarch64):
1456         Implement override.
1457
1458 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1459
1460         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1461         order.
1462
1463 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1464
1465         * aarch64-dis.c (last_stop_offset): New.
1466         (print_insn_aarch64): Use stop_offset.
1467
1468 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1469
1470         PR gas/24359
1471         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1472         CPU_ANY_AVX2_FLAGS.
1473         * i386-init.h: Regenerated.
1474
1475 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1476
1477         PR gas/24348
1478         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1479         vmovdqu16, vmovdqu32 and vmovdqu64.
1480         * i386-tbl.h: Regenerated.
1481
1482 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1483
1484         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1485         from vstrszb, vstrszh, and vstrszf.
1486
1487 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1488
1489         * s390-opc.txt: Add instruction descriptions.
1490
1491 2019-02-08  Jim Wilson  <jimw@sifive.com>
1492
1493         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1494         <bne>: Likewise.
1495
1496 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1497
1498         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1499
1500 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1501
1502         PR binutils/23212
1503         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1504         * aarch64-opc.c (verify_elem_sd): New.
1505         (fields): Add FLD_sz entr.
1506         * aarch64-tbl.h (_SIMD_INSN): New.
1507         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1508         fmulx scalar and vector by element isns.
1509
1510 2019-02-07  Nick Clifton  <nickc@redhat.com>
1511
1512         * po/sv.po: Updated Swedish translation.
1513
1514 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1515
1516         * s390-mkopc.c (main): Accept arch13 as cpu string.
1517         * s390-opc.c: Add new instruction formats and instruction opcode
1518         masks.
1519         * s390-opc.txt: Add new arch13 instructions.
1520
1521 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1522
1523         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1524         (aarch64_opcode): Change encoding for stg, stzg
1525         st2g and st2zg.
1526         * aarch64-asm-2.c: Regenerated.
1527         * aarch64-dis-2.c: Regenerated.
1528         * aarch64-opc-2.c: Regenerated.
1529
1530 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1531
1532         * aarch64-asm-2.c: Regenerated.
1533         * aarch64-dis-2.c: Likewise.
1534         * aarch64-opc-2.c: Likewise.
1535         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1536
1537 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1538             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1539
1540         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1541         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1542         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1543         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1544         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1545         case for ldstgv_indexed.
1546         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1547         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1548         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1549         * aarch64-asm-2.c: Regenerated.
1550         * aarch64-dis-2.c: Regenerated.
1551         * aarch64-opc-2.c: Regenerated.
1552
1553 2019-01-23  Nick Clifton  <nickc@redhat.com>
1554
1555         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1556
1557 2019-01-21  Nick Clifton  <nickc@redhat.com>
1558
1559         * po/de.po: Updated German translation.
1560         * po/uk.po: Updated Ukranian translation.
1561
1562 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1563         * mips-dis.c (mips_arch_choices): Fix typo in
1564         gs464, gs464e and gs264e descriptors.
1565
1566 2019-01-19  Nick Clifton  <nickc@redhat.com>
1567
1568         * configure: Regenerate.
1569         * po/opcodes.pot: Regenerate.
1570
1571 2018-06-24  Nick Clifton  <nickc@redhat.com>
1572
1573         2.32 branch created.
1574
1575 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1576
1577         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1578         if it is null.
1579         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1580         zero.
1581
1582 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1583
1584         * configure: Regenerate.
1585
1586 2019-01-07  Alan Modra  <amodra@gmail.com>
1587
1588         * configure: Regenerate.
1589         * po/POTFILES.in: Regenerate.
1590
1591 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1592
1593         * s12z-opc.c: New file.
1594         * s12z-opc.h: New file.
1595         * s12z-dis.c: Removed all code not directly related to display
1596         of instructions.  Used the interface provided by the new files
1597         instead.
1598         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1599         * Makefile.in: Regenerate.
1600         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1601         * configure: Regenerate.
1602
1603 2019-01-01  Alan Modra  <amodra@gmail.com>
1604
1605         Update year range in copyright notice of all files.
1606
1607 For older changes see ChangeLog-2018
1608 \f
1609 Copyright (C) 2019 Free Software Foundation, Inc.
1610
1611 Copying and distribution of this file, with or without modification,
1612 are permitted in any medium without royalty provided the copyright
1613 notice and this notice are preserved.
1614
1615 Local Variables:
1616 mode: change-log
1617 left-margin: 8
1618 fill-column: 74
1619 version-control: never
1620 End: