1 2020-09-21 Alan Modra <amodra@gmail.com>
3 * rx-dis.c (flag_names): Add missing comma.
4 (register_names, flag_names, double_register_names),
5 (double_register_high_names, double_register_low_names),
6 (double_control_register_names, double_condition_names): Remove
9 2020-09-18 David Faust <david.faust@oracle.com>
11 * bpf-desc.c: Regenerate.
12 * bpf-desc.h: Likewise.
13 * bpf-opc.c: Likewise.
14 * bpf-opc.h: Likewise.
16 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
18 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
21 2020-09-16 Alan Modra <amodra@gmail.com>
23 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
25 2020-09-10 Nick Clifton <nickc@redhat.com>
27 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
28 for hidden, local, no-type symbols.
29 (disassemble_init_powerpc): Point the symbol_is_valid field in the
30 info structure at the new function.
32 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
34 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
35 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
38 2020-09-10 Nick Clifton <nickc@redhat.com>
40 * csky-dis.c (csky_output_operand): Coerce the immediate values to
43 2020-09-10 Alan Modra <amodra@gmail.com>
45 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
47 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
49 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
52 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
54 * csky-dis.c (csky_output_operand): Add handlers for
55 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
56 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
57 to support FPUV3 instructions.
58 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
59 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
60 OPRND_TYPE_DFLOAT_FMOVI.
61 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
62 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
63 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
64 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
65 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
66 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
67 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
68 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
69 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
70 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
71 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
72 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
73 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
74 (csky_v2_opcodes): Add FPUV3 instructions.
76 2020-09-08 Alex Coplan <alex.coplan@arm.com>
78 * aarch64-dis.c (print_operands): Pass CPU features to
79 aarch64_print_operand().
80 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
81 preferred disassembly of system registers.
82 (SR_RNG): Refactor to use new SR_FEAT2 macro.
89 (SR_EXPAND_EL12): New.
90 (aarch64_sys_regs): Specify which registers are only on
91 A-profile, add R-profile system registers.
95 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
98 2020-09-08 Alex Coplan <alex.coplan@arm.com>
100 * aarch64-tbl.h (aarch64_feature_v8_r): New.
103 (aarch64_opcode_table): Add dfb.
104 * aarch64-opc-2.c: Regenerate.
105 * aarch64-asm-2.c: Regenerate.
106 * aarch64-dis-2.c: Regenerate.
108 2020-09-08 Alex Coplan <alex.coplan@arm.com>
110 * aarch64-dis.c (arch_variant): New.
111 (determine_disassembling_preference): Disassemble according to
113 (select_aarch64_variant): New.
114 (print_insn_aarch64): Set feature set.
116 2020-09-02 Alan Modra <amodra@gmail.com>
118 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
119 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
120 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
121 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
122 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
123 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
124 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
125 for value parameter and update code to suit.
126 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
127 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
129 2020-09-02 Alan Modra <amodra@gmail.com>
131 * i386-dis.c (OP_E_memory): Don't cast to signed type when
133 (get32, get32s): Use unsigned types in shift expressions.
135 2020-09-02 Alan Modra <amodra@gmail.com>
137 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
139 2020-09-02 Alan Modra <amodra@gmail.com>
141 * crx-dis.c: Whitespace.
142 (print_arg): Use unsigned type for longdisp and mask variables,
143 and for left shift constant.
145 2020-09-02 Alan Modra <amodra@gmail.com>
147 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
148 * bpf-ibld.c: Regenerate.
149 * epiphany-ibld.c: Regenerate.
150 * fr30-ibld.c: Regenerate.
151 * frv-ibld.c: Regenerate.
152 * ip2k-ibld.c: Regenerate.
153 * iq2000-ibld.c: Regenerate.
154 * lm32-ibld.c: Regenerate.
155 * m32c-ibld.c: Regenerate.
156 * m32r-ibld.c: Regenerate.
157 * mep-ibld.c: Regenerate.
158 * mt-ibld.c: Regenerate.
159 * or1k-ibld.c: Regenerate.
160 * xc16x-ibld.c: Regenerate.
161 * xstormy16-ibld.c: Regenerate.
163 2020-09-02 Alan Modra <amodra@gmail.com>
165 * bfin-dis.c (MASKBITS): Use SIGNBIT.
167 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
169 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
170 to CSKYV2_ISA_3E3R3 instruction set.
172 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
174 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
176 2020-09-01 Alan Modra <amodra@gmail.com>
178 * mep-ibld.c: Regenerate.
180 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
182 * csky-dis.c (csky_output_operand): Assign dis_info.value for
185 2020-08-30 Alan Modra <amodra@gmail.com>
187 * cr16-dis.c: Formatting.
188 (parameter): Delete struct typedef. Use dwordU instead
190 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
192 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
194 2020-08-29 Alan Modra <amodra@gmail.com>
197 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
198 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
200 2020-08-28 Alan Modra <amodra@gmail.com>
204 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
205 (extract_normal): Likewise.
206 (insert_normal): Likewise, and move past zero length test.
207 (put_insn_int_value): Handle mask for zero length, use 1UL.
208 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
209 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
210 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
211 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
213 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
215 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
216 (csky_dis_info): Add member isa.
217 (csky_find_inst_info): Skip instructions that do not belong to
219 (csky_get_disassembler): Get infomation from attribute section.
220 (print_insn_csky): Set defualt ISA flag.
221 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
222 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
223 isa_flag32'type to unsigned 64 bits.
225 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
227 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
229 2020-08-26 David Faust <david.faust@oracle.com>
231 * bpf-desc.c: Regenerate.
232 * bpf-desc.h: Likewise.
233 * bpf-opc.c: Likewise.
234 * bpf-opc.h: Likewise.
235 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
236 ISA when appropriate.
238 2020-08-25 Alan Modra <amodra@gmail.com>
241 * vax-dis.c (parse_disassembler_options): Always add at least one
242 to entry_addr_total_slots.
244 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
246 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
247 in other CPUs to speed up disassembling.
248 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
249 Change plsli.u16 to plsli.16, change sync's operand format.
251 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
253 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
255 2020-08-21 Nick Clifton <nickc@redhat.com>
257 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
260 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
262 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
264 2020-08-19 Alan Modra <amodra@gmail.com>
266 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
269 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
271 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
272 <xvcvbf16spn>: ...to this.
274 2020-08-12 Alex Coplan <alex.coplan@arm.com>
276 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
278 2020-08-12 Nick Clifton <nickc@redhat.com>
280 * po/sr.po: Updated Serbian translation.
282 2020-08-11 Alan Modra <amodra@gmail.com>
284 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
286 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
288 * aarch64-opc.c (aarch64_print_operand):
289 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
290 (aarch64_sys_reg_supported_p): Function removed.
291 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
292 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
295 2020-08-10 Alan Modra <amodra@gmail.com>
297 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
300 2020-08-10 Alan Modra <amodra@gmail.com>
302 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
303 Enable icbt for power5, miso for power8.
305 2020-08-10 Alan Modra <amodra@gmail.com>
307 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
308 mtvsrd, and similarly for mfvsrd.
310 2020-08-04 Christian Groessler <chris@groessler.org>
311 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
313 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
314 opcodes (special "out" to absolute address).
315 * z8k-opc.h: Regenerate.
317 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
320 * i386-opc.h (Prefix_Disp8): New.
321 (Prefix_Disp16): Likewise.
322 (Prefix_Disp32): Likewise.
323 (Prefix_Load): Likewise.
324 (Prefix_Store): Likewise.
325 (Prefix_VEX): Likewise.
326 (Prefix_VEX3): Likewise.
327 (Prefix_EVEX): Likewise.
328 (Prefix_REX): Likewise.
329 (Prefix_NoOptimize): Likewise.
330 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
331 * i386-tbl.h: Regenerated.
333 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
335 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
336 default case with abort() instead of printing an error message and
337 continuing, to avoid a maybe-uninitialized warning.
339 2020-07-24 Nick Clifton <nickc@redhat.com>
341 * po/de.po: Updated German translation.
343 2020-07-21 Jan Beulich <jbeulich@suse.com>
345 * i386-dis.c (OP_E_memory): Revert previous change.
347 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
350 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
351 without base nor index registers.
353 2020-07-15 Jan Beulich <jbeulich@suse.com>
355 * i386-dis.c (putop): Move 'V' and 'W' handling.
357 2020-07-15 Jan Beulich <jbeulich@suse.com>
359 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
360 construct for push/pop of register.
361 (putop): Honor cond when handling 'P'. Drop handling of plain
364 2020-07-15 Jan Beulich <jbeulich@suse.com>
366 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
367 description. Drop '&' description. Use P for push of immediate,
368 pushf/popf, enter, and leave. Use %LP for lret/retf.
369 (dis386_twobyte): Use P for push/pop of fs/gs.
370 (reg_table): Use P for push/pop. Use @ for near call/jmp.
371 (x86_64_table): Use P for far call/jmp.
372 (putop): Drop handling of 'U' and '&'. Move and adjust handling
373 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
375 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
376 and dqw_mode (unconditional).
378 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
381 * i386-dis.c (OP_E_memory): Without base nor index registers,
382 32-bit displacement to 64 bits.
384 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
386 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
387 faulty double register pair is detected.
389 2020-07-14 Jan Beulich <jbeulich@suse.com>
391 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
393 2020-07-14 Jan Beulich <jbeulich@suse.com>
395 * i386-dis.c (OP_R, Rm): Delete.
396 (MOD_0F24, MOD_0F26): Rename to ...
397 (X86_64_0F24, X86_64_0F26): ... respectively.
398 (dis386): Update 'L' and 'Z' comments.
399 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
401 (mod_table): Move opcode 0F24 and 0F26 entries ...
402 (x86_64_table): ... here.
403 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
406 2020-07-14 Jan Beulich <jbeulich@suse.com>
408 * i386-dis.c (Rd, Rdq, MaskR): Delete.
409 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
410 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
411 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
412 MOD_EVEX_0F387C): New enumerators.
413 (reg_table): Use Edq for rdssp.
414 (prefix_table): Use Edq for incssp.
415 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
416 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
417 ktest*, and kshift*. Use Edq / MaskE for kmov*.
418 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
419 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
420 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
421 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
422 0F3828_P_1 and 0F3838_P_1.
423 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
424 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
426 2020-07-14 Jan Beulich <jbeulich@suse.com>
428 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
429 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
430 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
431 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
432 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
433 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
434 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
435 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
436 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
437 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
438 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
439 (reg_table, prefix_table, three_byte_table, vex_table,
440 vex_len_table, mod_table, rm_table): Replace / remove respective
442 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
443 of PREFIX_DATA in used_prefixes.
445 2020-07-14 Jan Beulich <jbeulich@suse.com>
447 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
448 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
449 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
450 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
451 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
452 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
453 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
454 VEX_W_0F3A33_L_0): Delete.
455 (dis386): Adjust "BW" description.
456 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
457 0F3A31, 0F3A32, and 0F3A33.
458 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
460 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
463 2020-07-14 Jan Beulich <jbeulich@suse.com>
465 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
466 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
467 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
468 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
469 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
470 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
471 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
472 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
473 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
474 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
475 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
476 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
477 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
478 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
479 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
480 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
481 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
482 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
483 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
484 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
485 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
486 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
487 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
488 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
489 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
490 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
491 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
492 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
493 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
494 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
495 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
496 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
497 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
498 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
499 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
500 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
501 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
502 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
503 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
504 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
505 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
506 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
507 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
508 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
509 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
510 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
511 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
512 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
513 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
514 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
515 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
516 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
517 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
518 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
519 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
520 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
521 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
522 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
523 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
524 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
525 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
526 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
527 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
528 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
529 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
530 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
531 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
532 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
533 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
534 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
535 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
536 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
537 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
538 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
539 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
540 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
541 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
542 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
543 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
544 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
545 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
546 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
547 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
548 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
549 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
550 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
551 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
552 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
553 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
554 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
555 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
556 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
557 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
558 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
559 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
560 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
561 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
562 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
563 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
564 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
565 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
566 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
567 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
568 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
569 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
570 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
571 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
572 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
573 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
574 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
575 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
576 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
577 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
578 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
579 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
580 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
581 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
582 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
583 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
584 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
585 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
586 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
587 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
588 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
589 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
590 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
591 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
592 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
593 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
594 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
595 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
596 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
597 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
598 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
599 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
600 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
601 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
602 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
603 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
604 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
605 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
606 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
607 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
608 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
609 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
610 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
611 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
612 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
613 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
614 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
615 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
616 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
617 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
618 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
619 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
620 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
621 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
622 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
623 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
624 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
625 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
626 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
627 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
628 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
629 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
630 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
631 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
632 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
633 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
634 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
635 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
636 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
637 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
638 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
639 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
640 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
641 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
642 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
643 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
644 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
645 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
646 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
647 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
648 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
649 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
650 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
651 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
652 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
653 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
654 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
655 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
656 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
657 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
658 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
659 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
660 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
661 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
662 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
663 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
664 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
665 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
666 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
667 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
668 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
669 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
670 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
671 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
672 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
673 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
674 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
675 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
676 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
677 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
678 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
679 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
680 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
681 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
682 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
683 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
684 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
685 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
686 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
687 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
688 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
689 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
690 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
691 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
692 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
693 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
694 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
695 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
696 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
697 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
698 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
699 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
700 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
701 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
702 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
703 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
704 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
705 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
706 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
707 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
708 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
709 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
710 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
711 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
712 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
713 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
714 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
715 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
716 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
717 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
718 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
719 EVEX_W_0F3A72_P_2): Rename to ...
720 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
721 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
722 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
723 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
724 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
725 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
726 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
727 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
728 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
729 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
730 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
731 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
732 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
733 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
734 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
735 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
736 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
737 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
738 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
739 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
740 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
741 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
742 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
743 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
744 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
745 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
746 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
747 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
748 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
749 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
750 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
751 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
752 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
753 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
754 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
755 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
756 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
757 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
758 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
759 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
760 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
761 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
762 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
763 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
764 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
765 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
766 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
767 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
768 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
769 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
770 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
771 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
772 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
773 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
774 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
775 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
776 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
777 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
778 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
779 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
780 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
781 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
782 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
783 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
784 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
785 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
786 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
787 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
788 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
789 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
790 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
791 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
793 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
794 vex_w_table, mod_table): Replace / remove respective entries.
795 (print_insn): Move up dp->prefix_requirement handling. Handle
797 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
798 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
799 Replace / remove respective entries.
801 2020-07-14 Jan Beulich <jbeulich@suse.com>
803 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
804 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
805 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
806 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
807 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
809 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
810 0F2C, 0F2D, 0F2E, and 0F2F.
811 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
814 2020-07-14 Jan Beulich <jbeulich@suse.com>
816 * i386-dis.c (OP_VexR, VexScalarR): New.
817 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
818 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
819 need_vex_reg): Delete.
820 (prefix_table): Replace VexScalar by VexScalarR and
821 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
822 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
823 (vex_len_table): Replace EXqVexScalarS by EXqS.
824 (get_valid_dis386): Don't set need_vex_reg.
825 (print_insn): Don't initialize need_vex_reg.
826 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
827 q_scalar_swap_mode cases.
828 (OP_EX): Don't check for d_scalar_swap_mode and
830 (OP_VEX): Done check need_vex_reg.
831 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
832 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
833 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
835 2020-07-14 Jan Beulich <jbeulich@suse.com>
837 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
838 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
839 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
840 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
841 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
842 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
843 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
844 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
845 (vex_table): Replace Vex128 by Vex.
846 (vex_len_table): Likewise. Adjust referenced enum names.
847 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
848 referenced enum names.
849 (OP_VEX): Drop vex128_mode and vex256_mode cases.
850 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
852 2020-07-14 Jan Beulich <jbeulich@suse.com>
854 * i386-dis.c (dis386): "LW" description now applies to "DQ".
855 (putop): Handle "DQ". Don't handle "LW" anymore.
856 (prefix_table, mod_table): Replace %LW by %DQ.
857 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
859 2020-07-14 Jan Beulich <jbeulich@suse.com>
861 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
862 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
863 d_scalar_swap_mode case handling. Move shift adjsutment into
864 the case its applicable to.
866 2020-07-14 Jan Beulich <jbeulich@suse.com>
868 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
869 (EXbScalar, EXwScalar): Fold to ...
870 (EXbwUnit): ... this.
871 (b_scalar_mode, w_scalar_mode): Fold to ...
872 (bw_unit_mode): ... this.
873 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
874 w_scalar_mode handling by bw_unit_mode one.
875 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
877 * i386-dis-evex-prefix.h: ... here.
879 2020-07-14 Jan Beulich <jbeulich@suse.com>
881 * i386-dis.c (PCMPESTR_Fixup): Delete.
882 (dis386): Adjust "LQ" description.
883 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
884 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
885 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
886 vpcmpestrm, and vpcmpestri.
887 (putop): Honor "cond" when handling LQ.
888 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
889 vcvtsi2ss and vcvtusi2ss.
890 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
891 vcvtsi2sd and vcvtusi2sd.
893 2020-07-14 Jan Beulich <jbeulich@suse.com>
895 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
896 (simd_cmp_op): Add const.
897 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
898 (CMP_Fixup): Handle VEX case.
899 (prefix_table): Replace VCMP by CMP.
900 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
902 2020-07-14 Jan Beulich <jbeulich@suse.com>
904 * i386-dis.c (MOVBE_Fixup): Delete.
906 (prefix_table): Use Mv for movbe entries.
908 2020-07-14 Jan Beulich <jbeulich@suse.com>
910 * i386-dis.c (CRC32_Fixup): Delete.
911 (prefix_table): Use Eb/Ev for crc32 entries.
913 2020-07-14 Jan Beulich <jbeulich@suse.com>
915 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
916 Conditionalize invocations of "USED_REX (0)".
918 2020-07-14 Jan Beulich <jbeulich@suse.com>
920 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
921 CH, DH, BH, AX, DX): Delete.
922 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
923 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
924 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
926 2020-07-10 Lili Cui <lili.cui@intel.com>
928 * i386-dis.c (TMM): New.
931 (MVexSIBMEM): Likewise.
932 (tmm_mode): Likewise.
933 (vex_sibmem_mode): Likewise.
934 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
935 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
936 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
937 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
938 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
939 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
940 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
941 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
942 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
943 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
944 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
945 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
946 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
947 (PREFIX_VEX_0F3849_X86_64): Likewise.
948 (PREFIX_VEX_0F384B_X86_64): Likewise.
949 (PREFIX_VEX_0F385C_X86_64): Likewise.
950 (PREFIX_VEX_0F385E_X86_64): Likewise.
951 (X86_64_VEX_0F3849): Likewise.
952 (X86_64_VEX_0F384B): Likewise.
953 (X86_64_VEX_0F385C): Likewise.
954 (X86_64_VEX_0F385E): Likewise.
955 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
956 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
957 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
958 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
959 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
960 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
961 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
962 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
963 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
964 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
965 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
966 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
967 (VEX_W_0F3849_X86_64_P_0): Likewise.
968 (VEX_W_0F3849_X86_64_P_2): Likewise.
969 (VEX_W_0F3849_X86_64_P_3): Likewise.
970 (VEX_W_0F384B_X86_64_P_1): Likewise.
971 (VEX_W_0F384B_X86_64_P_2): Likewise.
972 (VEX_W_0F384B_X86_64_P_3): Likewise.
973 (VEX_W_0F385C_X86_64_P_1): Likewise.
974 (VEX_W_0F385E_X86_64_P_0): Likewise.
975 (VEX_W_0F385E_X86_64_P_1): Likewise.
976 (VEX_W_0F385E_X86_64_P_2): Likewise.
977 (VEX_W_0F385E_X86_64_P_3): Likewise.
978 (names_tmm): Likewise.
979 (att_names_tmm): Likewise.
980 (intel_operand_size): Handle void_mode.
981 (OP_XMM): Handle tmm_mode.
984 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
985 CpuAMX_BF16 and CpuAMX_TILE.
986 (operand_type_shorthands): Add RegTMM.
987 (operand_type_init): Likewise.
988 (operand_types): Add Tmmword.
989 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
990 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
991 * i386-opc.h (CpuAMX_INT8): New.
992 (CpuAMX_BF16): Likewise.
993 (CpuAMX_TILE): Likewise.
996 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
997 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
998 (i386_operand_type): Add tmmword.
999 * i386-opc.tbl: Add AMX instructions.
1000 * i386-reg.tbl: Add AMX registers.
1001 * i386-init.h: Regenerated.
1002 * i386-tbl.h: Likewise.
1004 2020-07-08 Jan Beulich <jbeulich@suse.com>
1006 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1007 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1009 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1010 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1012 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1013 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1014 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1015 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1016 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1017 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1018 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1019 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1020 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1021 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1022 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1023 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1024 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1025 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1026 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1027 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1028 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1029 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1030 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1031 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1032 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1033 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1034 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1035 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1036 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1037 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1038 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1039 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1040 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1041 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1042 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1043 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1044 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1045 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1046 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1047 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1048 (reg_table): Re-order XOP entries. Adjust their operands.
1049 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1050 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1051 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1052 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1053 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1054 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1055 entries by references ...
1056 (vex_len_table): ... to resepctive new entries here. For several
1057 new and existing entries reference ...
1058 (vex_w_table): ... new entries here.
1059 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1061 2020-07-08 Jan Beulich <jbeulich@suse.com>
1063 * i386-dis.c (XMVexScalarI4): Define.
1064 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1065 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1066 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1067 (vex_len_table): Move scalar FMA4 entries ...
1068 (prefix_table): ... here.
1069 (OP_REG_VexI4): Handle scalar_mode.
1070 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1071 * i386-tbl.h: Re-generate.
1073 2020-07-08 Jan Beulich <jbeulich@suse.com>
1075 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1076 Vex_2src_2): Delete.
1077 (OP_VexW, VexW): New.
1078 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1079 for shifts and rotates by register.
1081 2020-07-08 Jan Beulich <jbeulich@suse.com>
1083 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1084 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1085 OP_EX_VexReg): Delete.
1086 (OP_VexI4, VexI4): New.
1087 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1088 (prefix_table): ... here.
1089 (print_insn): Drop setting of vex_w_done.
1091 2020-07-08 Jan Beulich <jbeulich@suse.com>
1093 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1094 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1095 (xop_table): Replace operands of 4-operand insns.
1096 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1098 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1100 * arc-opc.c (insert_rbd): New function.
1103 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1106 2020-07-07 Jan Beulich <jbeulich@suse.com>
1108 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1109 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1110 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1111 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1113 (putop): Handle "BW".
1114 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1115 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1117 * i386-dis-evex-prefix.h: ... here.
1119 2020-07-06 Jan Beulich <jbeulich@suse.com>
1121 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1122 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1123 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1124 VEX_W_0FXOP_09_83): New enumerators.
1125 (xop_table): Reference the above.
1126 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1127 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1128 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1129 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1131 2020-07-06 Jan Beulich <jbeulich@suse.com>
1133 * i386-dis.c (EVEX_W_0F3838_P_1,
1134 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1135 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1136 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1137 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1138 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1139 (putop): Centralize management of last[]. Delete SAVE_LAST.
1140 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1141 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1142 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1143 * i386-dis-evex-prefix.h: here.
1145 2020-07-06 Jan Beulich <jbeulich@suse.com>
1147 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1148 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1149 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1150 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1152 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1153 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1154 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1155 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1156 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1157 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1158 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1159 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1160 these, respectively.
1161 * i386-dis-evex-len.h: Adjust comments.
1162 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1163 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1164 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1165 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1166 MOD_EVEX_0F385B_P_2_W_1 table entries.
1167 * i386-dis-evex-w.h: Reference mod_table[] for
1168 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1171 2020-07-06 Jan Beulich <jbeulich@suse.com>
1173 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1174 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1176 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1177 Likewise. Mark 256-bit entries invalid.
1179 2020-07-06 Jan Beulich <jbeulich@suse.com>
1181 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1182 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1183 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1184 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1185 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1186 PREFIX_EVEX_0F382B): Delete.
1187 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1188 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1189 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1190 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1191 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1193 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1194 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1195 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1196 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1198 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1199 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1200 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1201 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1202 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1203 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1204 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1205 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1206 PREFIX_EVEX_0F382B): Remove table entries.
1207 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1208 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1209 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1211 2020-07-06 Jan Beulich <jbeulich@suse.com>
1213 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1214 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1216 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1217 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1218 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1219 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1222 2020-07-06 Jan Beulich <jbeulich@suse.com>
1224 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1225 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1226 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1227 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1228 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1229 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1230 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1231 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1232 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1235 2020-07-06 Jan Beulich <jbeulich@suse.com>
1237 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1238 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1239 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1241 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1243 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1245 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1247 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1249 2020-07-06 Jan Beulich <jbeulich@suse.com>
1251 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1252 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1253 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1254 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1255 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1256 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1257 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1258 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1259 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1260 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1261 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1262 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1263 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1264 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1265 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1266 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1267 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1268 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1269 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1270 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1271 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1272 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1273 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1274 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1275 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1276 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1277 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1278 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1279 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1280 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1281 (prefix_table): Add EXxEVexR to FMA table entries.
1282 (OP_Rounding): Move abort() invocation.
1283 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1284 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1285 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1286 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1287 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1288 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1289 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1290 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1291 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1292 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1294 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1295 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1296 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1297 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1298 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1299 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1300 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1301 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1302 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1303 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1304 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1305 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1306 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1307 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1308 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1309 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1310 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1311 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1312 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1313 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1314 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1315 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1316 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1317 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1318 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1319 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1320 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1321 Delete table entries.
1322 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1323 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1324 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1327 2020-07-06 Jan Beulich <jbeulich@suse.com>
1329 * i386-dis.c (EXqScalarS): Delete.
1330 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1331 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1333 2020-07-06 Jan Beulich <jbeulich@suse.com>
1335 * i386-dis.c (safe-ctype.h): Include.
1336 (EXdScalar, EXqScalar): Delete.
1337 (d_scalar_mode, q_scalar_mode): Delete.
1338 (prefix_table, vex_len_table): Use EXxmm_md in place of
1339 EXdScalar and EXxmm_mq in place of EXqScalar.
1340 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1341 d_scalar_mode and q_scalar_mode.
1342 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1343 (vmovsd): Use EXxmm_mq.
1345 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1348 * arc-dis.c: Fix spelling mistake.
1349 * po/opcodes.pot: Regenerate.
1351 2020-07-06 Nick Clifton <nickc@redhat.com>
1353 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1354 * po/uk.po: Updated Ukranian translation.
1356 2020-07-04 Nick Clifton <nickc@redhat.com>
1358 * configure: Regenerate.
1359 * po/opcodes.pot: Regenerate.
1361 2020-07-04 Nick Clifton <nickc@redhat.com>
1363 Binutils 2.35 branch created.
1365 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1367 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1368 * i386-opc.h (VexSwapSources): New.
1369 (i386_opcode_modifier): Add vexswapsources.
1370 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1371 with two source operands swapped.
1372 * i386-tbl.h: Regenerated.
1374 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1376 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1377 unprivileged CSR can also be initialized.
1379 2020-06-29 Alan Modra <amodra@gmail.com>
1381 * arm-dis.c: Use C style comments.
1382 * cr16-opc.c: Likewise.
1383 * ft32-dis.c: Likewise.
1384 * moxie-opc.c: Likewise.
1385 * tic54x-dis.c: Likewise.
1386 * s12z-opc.c: Remove useless comment.
1387 * xgate-dis.c: Likewise.
1389 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1391 * i386-opc.tbl: Add a blank line.
1393 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1395 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1396 (VecSIB128): Renamed to ...
1398 (VecSIB256): Renamed to ...
1400 (VecSIB512): Renamed to ...
1402 (VecSIB): Renamed to ...
1404 (i386_opcode_modifier): Replace vecsib with sib.
1405 * i386-opc.tbl (VecSIB128): New.
1406 (VecSIB256): Likewise.
1407 (VecSIB512): Likewise.
1408 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1409 and VecSIB512, respectively.
1411 2020-06-26 Jan Beulich <jbeulich@suse.com>
1413 * i386-dis.c: Adjust description of I macro.
1414 (x86_64_table): Drop use of I.
1415 (float_mem): Replace use of I.
1416 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1418 2020-06-26 Jan Beulich <jbeulich@suse.com>
1420 * i386-dis.c: (print_insn): Avoid straight assignment to
1421 priv.orig_sizeflag when processing -M sub-options.
1423 2020-06-25 Jan Beulich <jbeulich@suse.com>
1425 * i386-dis.c: Adjust description of J macro.
1426 (dis386, x86_64_table, mod_table): Replace J.
1427 (putop): Remove handling of J.
1429 2020-06-25 Jan Beulich <jbeulich@suse.com>
1431 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1433 2020-06-25 Jan Beulich <jbeulich@suse.com>
1435 * i386-dis.c: Adjust description of "LQ" macro.
1436 (dis386_twobyte): Use LQ for sysret.
1437 (putop): Adjust handling of LQ.
1439 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1441 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1442 * riscv-dis.c: Include elfxx-riscv.h.
1444 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1446 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1448 2020-06-17 Lili Cui <lili.cui@intel.com>
1450 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1452 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1455 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1456 * i386-opc.tbl: Likewise.
1457 * i386-tbl.h: Regenerated.
1459 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1461 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1463 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1465 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1466 (SR_CORE): Likewise.
1467 (SR_FEAT): Likewise.
1469 (SR_V8_1): Likewise.
1470 (SR_V8_2): Likewise.
1471 (SR_V8_3): Likewise.
1472 (SR_V8_4): Likewise.
1475 (SR_SSBS): Likewise.
1477 (SR_ID_PFR2): Likewise.
1478 (SR_PROFILE): Likewise.
1479 (SR_MEMTAG): Likewise.
1480 (SR_SCXTNUM): Likewise.
1481 (aarch64_sys_regs): Refactor to store feature information in the table.
1482 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1483 that now describe their own features.
1484 (aarch64_pstatefield_supported_p): Likewise.
1486 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1488 * i386-dis.c (prefix_table): Fix a typo in comments.
1490 2020-06-09 Jan Beulich <jbeulich@suse.com>
1492 * i386-dis.c (rex_ignored): Delete.
1493 (ckprefix): Drop rex_ignored initialization.
1494 (get_valid_dis386): Drop setting of rex_ignored.
1495 (print_insn): Drop checking of rex_ignored. Don't record data
1496 size prefix as used with VEX-and-alike encodings.
1498 2020-06-09 Jan Beulich <jbeulich@suse.com>
1500 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1501 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1502 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1503 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1504 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1505 VEX_0F12, and VEX_0F16.
1506 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1507 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1508 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1509 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1510 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1511 MOD_VEX_0F16_PREFIX_2 entries.
1513 2020-06-09 Jan Beulich <jbeulich@suse.com>
1515 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1516 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1517 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1518 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1519 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1520 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1521 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1522 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1523 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1524 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1525 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1526 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1527 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1528 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1529 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1530 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1531 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1532 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1533 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1534 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1535 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1536 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1537 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1538 EVEX_W_0FC6_P_2): Delete.
1539 (print_insn): Add EVEX.W vs embedded prefix consistency check
1540 to prefix validation.
1541 * i386-dis-evex.h (evex_table): Don't further descend for
1542 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1543 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1545 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1546 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1547 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1548 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1549 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1550 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1551 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1552 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1553 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1554 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1555 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1556 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1557 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1558 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1559 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1560 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1561 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1562 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1563 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1564 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1565 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1566 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1567 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1568 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1569 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1570 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1571 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1573 2020-06-09 Jan Beulich <jbeulich@suse.com>
1575 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1576 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1577 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1579 (print_insn): Drop pointless check against bad_opcode. Split
1580 prefix validation into legacy and VEX-and-alike parts.
1581 (putop): Re-work 'X' macro handling.
1583 2020-06-09 Jan Beulich <jbeulich@suse.com>
1585 * i386-dis.c (MOD_0F51): Rename to ...
1586 (MOD_0F50): ... this.
1588 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1590 * arm-dis.c (arm_opcodes): Add dfb.
1591 (thumb32_opcodes): Add dfb.
1593 2020-06-08 Jan Beulich <jbeulich@suse.com>
1595 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1597 2020-06-06 Alan Modra <amodra@gmail.com>
1599 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1601 2020-06-05 Alan Modra <amodra@gmail.com>
1603 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1604 size is large enough.
1606 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1608 * disassemble.c (disassemble_init_for_target): Set endian_code for
1610 * bpf-desc.c: Regenerate.
1611 * bpf-opc.c: Likewise.
1612 * bpf-dis.c: Likewise.
1614 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1616 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1617 (cgen_put_insn_value): Likewise.
1618 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1619 * cgen-dis.in (print_insn): Likewise.
1620 * cgen-ibld.in (insert_1): Likewise.
1621 (insert_1): Likewise.
1622 (insert_insn_normal): Likewise.
1623 (extract_1): Likewise.
1624 * bpf-dis.c: Regenerate.
1625 * bpf-ibld.c: Likewise.
1626 * bpf-ibld.c: Likewise.
1627 * cgen-dis.in: Likewise.
1628 * cgen-ibld.in: Likewise.
1629 * cgen-opc.c: Likewise.
1630 * epiphany-dis.c: Likewise.
1631 * epiphany-ibld.c: Likewise.
1632 * fr30-dis.c: Likewise.
1633 * fr30-ibld.c: Likewise.
1634 * frv-dis.c: Likewise.
1635 * frv-ibld.c: Likewise.
1636 * ip2k-dis.c: Likewise.
1637 * ip2k-ibld.c: Likewise.
1638 * iq2000-dis.c: Likewise.
1639 * iq2000-ibld.c: Likewise.
1640 * lm32-dis.c: Likewise.
1641 * lm32-ibld.c: Likewise.
1642 * m32c-dis.c: Likewise.
1643 * m32c-ibld.c: Likewise.
1644 * m32r-dis.c: Likewise.
1645 * m32r-ibld.c: Likewise.
1646 * mep-dis.c: Likewise.
1647 * mep-ibld.c: Likewise.
1648 * mt-dis.c: Likewise.
1649 * mt-ibld.c: Likewise.
1650 * or1k-dis.c: Likewise.
1651 * or1k-ibld.c: Likewise.
1652 * xc16x-dis.c: Likewise.
1653 * xc16x-ibld.c: Likewise.
1654 * xstormy16-dis.c: Likewise.
1655 * xstormy16-ibld.c: Likewise.
1657 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1659 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1660 (print_insn_): Handle instruction endian.
1661 * bpf-dis.c: Regenerate.
1662 * bpf-desc.c: Regenerate.
1663 * epiphany-dis.c: Likewise.
1664 * epiphany-desc.c: Likewise.
1665 * fr30-dis.c: Likewise.
1666 * fr30-desc.c: Likewise.
1667 * frv-dis.c: Likewise.
1668 * frv-desc.c: Likewise.
1669 * ip2k-dis.c: Likewise.
1670 * ip2k-desc.c: Likewise.
1671 * iq2000-dis.c: Likewise.
1672 * iq2000-desc.c: Likewise.
1673 * lm32-dis.c: Likewise.
1674 * lm32-desc.c: Likewise.
1675 * m32c-dis.c: Likewise.
1676 * m32c-desc.c: Likewise.
1677 * m32r-dis.c: Likewise.
1678 * m32r-desc.c: Likewise.
1679 * mep-dis.c: Likewise.
1680 * mep-desc.c: Likewise.
1681 * mt-dis.c: Likewise.
1682 * mt-desc.c: Likewise.
1683 * or1k-dis.c: Likewise.
1684 * or1k-desc.c: Likewise.
1685 * xc16x-dis.c: Likewise.
1686 * xc16x-desc.c: Likewise.
1687 * xstormy16-dis.c: Likewise.
1688 * xstormy16-desc.c: Likewise.
1690 2020-06-03 Nick Clifton <nickc@redhat.com>
1692 * po/sr.po: Updated Serbian translation.
1694 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1696 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1697 (riscv_get_priv_spec_class): Likewise.
1699 2020-06-01 Alan Modra <amodra@gmail.com>
1701 * bpf-desc.c: Regenerate.
1703 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1704 David Faust <david.faust@oracle.com>
1706 * bpf-desc.c: Regenerate.
1707 * bpf-opc.h: Likewise.
1708 * bpf-opc.c: Likewise.
1709 * bpf-dis.c: Likewise.
1711 2020-05-28 Alan Modra <amodra@gmail.com>
1713 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1716 2020-05-28 Alan Modra <amodra@gmail.com>
1718 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1720 (print_insn_ns32k): Revert last change.
1722 2020-05-28 Nick Clifton <nickc@redhat.com>
1724 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1727 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1729 Fix extraction of signed constants in nios2 disassembler (again).
1731 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1732 extractions of signed fields.
1734 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1736 * s390-opc.txt: Relocate vector load/store instructions with
1737 additional alignment parameter and change architecture level
1738 constraint from z14 to z13.
1740 2020-05-21 Alan Modra <amodra@gmail.com>
1742 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1743 * sparc-dis.c: Likewise.
1744 * tic4x-dis.c: Likewise.
1745 * xtensa-dis.c: Likewise.
1746 * bpf-desc.c: Regenerate.
1747 * epiphany-desc.c: Regenerate.
1748 * fr30-desc.c: Regenerate.
1749 * frv-desc.c: Regenerate.
1750 * ip2k-desc.c: Regenerate.
1751 * iq2000-desc.c: Regenerate.
1752 * lm32-desc.c: Regenerate.
1753 * m32c-desc.c: Regenerate.
1754 * m32r-desc.c: Regenerate.
1755 * mep-asm.c: Regenerate.
1756 * mep-desc.c: Regenerate.
1757 * mt-desc.c: Regenerate.
1758 * or1k-desc.c: Regenerate.
1759 * xc16x-desc.c: Regenerate.
1760 * xstormy16-desc.c: Regenerate.
1762 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1764 * riscv-opc.c (riscv_ext_version_table): The table used to store
1765 all information about the supported spec and the corresponding ISA
1766 versions. Currently, only Zicsr is supported to verify the
1767 correctness of Z sub extension settings. Others will be supported
1768 in the future patches.
1769 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1770 classes and the corresponding strings.
1771 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1772 spec class by giving a ISA spec string.
1773 * riscv-opc.c (struct priv_spec_t): New structure.
1774 (struct priv_spec_t priv_specs): List for all supported privilege spec
1775 classes and the corresponding strings.
1776 (riscv_get_priv_spec_class): New function. Get the corresponding
1777 privilege spec class by giving a spec string.
1778 (riscv_get_priv_spec_name): New function. Get the corresponding
1779 privilege spec string by giving a CSR version class.
1780 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1781 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1782 according to the chosen version. Build a hash table riscv_csr_hash to
1783 store the valid CSR for the chosen pirv verison. Dump the direct
1784 CSR address rather than it's name if it is invalid.
1785 (parse_riscv_dis_option_without_args): New function. Parse the options
1787 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1788 parse the options without arguments first, and then handle the options
1789 with arguments. Add the new option -Mpriv-spec, which has argument.
1790 * riscv-dis.c (print_riscv_disassembler_options): Add description
1791 about the new OBJDUMP option.
1793 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1795 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1796 WC values on POWER10 sync, dcbf and wait instructions.
1797 (insert_pl, extract_pl): New functions.
1798 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1799 (LS3): New , 3-bit L for sync.
1800 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1801 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1802 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1803 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1804 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1805 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1806 <wait>: Enable PL operand on POWER10.
1807 <dcbf>: Enable L3OPT operand on POWER10.
1808 <sync>: Enable SC2 operand on POWER10.
1810 2020-05-19 Stafford Horne <shorne@gmail.com>
1813 * or1k-asm.c: Regenerate.
1814 * or1k-desc.c: Regenerate.
1815 * or1k-desc.h: Regenerate.
1816 * or1k-dis.c: Regenerate.
1817 * or1k-ibld.c: Regenerate.
1818 * or1k-opc.c: Regenerate.
1819 * or1k-opc.h: Regenerate.
1820 * or1k-opinst.c: Regenerate.
1822 2020-05-11 Alan Modra <amodra@gmail.com>
1824 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1827 2020-05-11 Alan Modra <amodra@gmail.com>
1829 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1830 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1832 2020-05-11 Alan Modra <amodra@gmail.com>
1834 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1836 2020-05-11 Alan Modra <amodra@gmail.com>
1838 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1839 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1841 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1843 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1846 2020-05-11 Alan Modra <amodra@gmail.com>
1848 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1849 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1850 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1851 (prefix_opcodes): Add xxeval.
1853 2020-05-11 Alan Modra <amodra@gmail.com>
1855 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1856 xxgenpcvwm, xxgenpcvdm.
1858 2020-05-11 Alan Modra <amodra@gmail.com>
1860 * ppc-opc.c (MP, VXVAM_MASK): Define.
1861 (VXVAPS_MASK): Use VXVA_MASK.
1862 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1863 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1864 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1865 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1867 2020-05-11 Alan Modra <amodra@gmail.com>
1868 Peter Bergner <bergner@linux.ibm.com>
1870 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1872 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1873 YMSK2, XA6a, XA6ap, XB6a entries.
1874 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1875 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1877 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1878 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1879 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1880 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1881 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1882 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1883 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1884 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1885 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1886 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1887 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1888 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1889 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1890 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1892 2020-05-11 Alan Modra <amodra@gmail.com>
1894 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1895 (insert_xts, extract_xts): New functions.
1896 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1897 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1898 (VXRC_MASK, VXSH_MASK): Define.
1899 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1900 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1901 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1902 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1903 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1904 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1905 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1907 2020-05-11 Alan Modra <amodra@gmail.com>
1909 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1910 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1911 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1912 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1913 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1915 2020-05-11 Alan Modra <amodra@gmail.com>
1917 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1918 (XTP, DQXP, DQXP_MASK): Define.
1919 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1920 (prefix_opcodes): Add plxvp and pstxvp.
1922 2020-05-11 Alan Modra <amodra@gmail.com>
1924 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1925 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1926 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1928 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1930 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1932 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1934 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1936 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1938 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1940 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1942 2020-05-11 Alan Modra <amodra@gmail.com>
1944 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1946 2020-05-11 Alan Modra <amodra@gmail.com>
1948 * ppc-dis.c (ppc_opts): Add "power10" entry.
1949 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1950 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1952 2020-05-11 Nick Clifton <nickc@redhat.com>
1954 * po/fr.po: Updated French translation.
1956 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1958 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1959 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1960 (operand_general_constraint_met_p): validate
1961 AARCH64_OPND_UNDEFINED.
1962 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1964 * aarch64-asm-2.c: Regenerated.
1965 * aarch64-dis-2.c: Regenerated.
1966 * aarch64-opc-2.c: Regenerated.
1968 2020-04-29 Nick Clifton <nickc@redhat.com>
1971 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1974 2020-04-29 Nick Clifton <nickc@redhat.com>
1976 * po/sv.po: Updated Swedish translation.
1978 2020-04-29 Nick Clifton <nickc@redhat.com>
1981 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1982 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1983 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1986 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1989 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1990 cmpi only on m68020up and cpu32.
1992 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1994 * aarch64-asm.c (aarch64_ins_none): New.
1995 * aarch64-asm.h (ins_none): New declaration.
1996 * aarch64-dis.c (aarch64_ext_none): New.
1997 * aarch64-dis.h (ext_none): New declaration.
1998 * aarch64-opc.c (aarch64_print_operand): Update case for
1999 AARCH64_OPND_BARRIER_PSB.
2000 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2001 (AARCH64_OPERANDS): Update inserter/extracter for
2002 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2003 * aarch64-asm-2.c: Regenerated.
2004 * aarch64-dis-2.c: Regenerated.
2005 * aarch64-opc-2.c: Regenerated.
2007 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2009 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2010 (aarch64_feature_ras, RAS): Likewise.
2011 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2012 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2013 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2014 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2015 * aarch64-asm-2.c: Regenerated.
2016 * aarch64-dis-2.c: Regenerated.
2017 * aarch64-opc-2.c: Regenerated.
2019 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2021 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2022 (print_insn_neon): Support disassembly of conditional
2025 2020-02-16 David Faust <david.faust@oracle.com>
2027 * bpf-desc.c: Regenerate.
2028 * bpf-desc.h: Likewise.
2029 * bpf-opc.c: Regenerate.
2030 * bpf-opc.h: Likewise.
2032 2020-04-07 Lili Cui <lili.cui@intel.com>
2034 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2035 (prefix_table): New instructions (see prefixes above).
2036 (rm_table): Likewise
2037 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2038 CPU_ANY_TSXLDTRK_FLAGS.
2039 (cpu_flags): Add CpuTSXLDTRK.
2040 * i386-opc.h (enum): Add CpuTSXLDTRK.
2041 (i386_cpu_flags): Add cputsxldtrk.
2042 * i386-opc.tbl: Add XSUSPLDTRK insns.
2043 * i386-init.h: Regenerate.
2044 * i386-tbl.h: Likewise.
2046 2020-04-02 Lili Cui <lili.cui@intel.com>
2048 * i386-dis.c (prefix_table): New instructions serialize.
2049 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2050 CPU_ANY_SERIALIZE_FLAGS.
2051 (cpu_flags): Add CpuSERIALIZE.
2052 * i386-opc.h (enum): Add CpuSERIALIZE.
2053 (i386_cpu_flags): Add cpuserialize.
2054 * i386-opc.tbl: Add SERIALIZE insns.
2055 * i386-init.h: Regenerate.
2056 * i386-tbl.h: Likewise.
2058 2020-03-26 Alan Modra <amodra@gmail.com>
2060 * disassemble.h (opcodes_assert): Declare.
2061 (OPCODES_ASSERT): Define.
2062 * disassemble.c: Don't include assert.h. Include opintl.h.
2063 (opcodes_assert): New function.
2064 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2065 (bfd_h8_disassemble): Reduce size of data array. Correctly
2066 calculate maxlen. Omit insn decoding when insn length exceeds
2067 maxlen. Exit from nibble loop when looking for E, before
2068 accessing next data byte. Move processing of E outside loop.
2069 Replace tests of maxlen in loop with assertions.
2071 2020-03-26 Alan Modra <amodra@gmail.com>
2073 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2075 2020-03-25 Alan Modra <amodra@gmail.com>
2077 * z80-dis.c (suffix): Init mybuf.
2079 2020-03-22 Alan Modra <amodra@gmail.com>
2081 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2082 successflly read from section.
2084 2020-03-22 Alan Modra <amodra@gmail.com>
2086 * arc-dis.c (find_format): Use ISO C string concatenation rather
2087 than line continuation within a string. Don't access needs_limm
2088 before testing opcode != NULL.
2090 2020-03-22 Alan Modra <amodra@gmail.com>
2092 * ns32k-dis.c (print_insn_arg): Update comment.
2093 (print_insn_ns32k): Reduce size of index_offset array, and
2094 initialize, passing -1 to print_insn_arg for args that are not
2095 an index. Don't exit arg loop early. Abort on bad arg number.
2097 2020-03-22 Alan Modra <amodra@gmail.com>
2099 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2100 * s12z-opc.c: Formatting.
2101 (operands_f): Return an int.
2102 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2103 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2104 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2105 (exg_sex_discrim): Likewise.
2106 (create_immediate_operand, create_bitfield_operand),
2107 (create_register_operand_with_size, create_register_all_operand),
2108 (create_register_all16_operand, create_simple_memory_operand),
2109 (create_memory_operand, create_memory_auto_operand): Don't
2110 segfault on malloc failure.
2111 (z_ext24_decode): Return an int status, negative on fail, zero
2113 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2114 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2115 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2116 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2117 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2118 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2119 (loop_primitive_decode, shift_decode, psh_pul_decode),
2120 (bit_field_decode): Similarly.
2121 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2122 to return value, update callers.
2123 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2124 Don't segfault on NULL operand.
2125 (decode_operation): Return OP_INVALID on first fail.
2126 (decode_s12z): Check all reads, returning -1 on fail.
2128 2020-03-20 Alan Modra <amodra@gmail.com>
2130 * metag-dis.c (print_insn_metag): Don't ignore status from
2133 2020-03-20 Alan Modra <amodra@gmail.com>
2135 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2136 Initialize parts of buffer not written when handling a possible
2137 2-byte insn at end of section. Don't attempt decoding of such
2138 an insn by the 4-byte machinery.
2140 2020-03-20 Alan Modra <amodra@gmail.com>
2142 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2143 partially filled buffer. Prevent lookup of 4-byte insns when
2144 only VLE 2-byte insns are possible due to section size. Print
2145 ".word" rather than ".long" for 2-byte leftovers.
2147 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2150 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2152 2020-03-13 Jan Beulich <jbeulich@suse.com>
2154 * i386-dis.c (X86_64_0D): Rename to ...
2155 (X86_64_0E): ... this.
2157 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2159 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2160 * Makefile.in: Regenerated.
2162 2020-03-09 Jan Beulich <jbeulich@suse.com>
2164 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2166 * i386-tbl.h: Re-generate.
2168 2020-03-09 Jan Beulich <jbeulich@suse.com>
2170 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2171 vprot*, vpsha*, and vpshl*.
2172 * i386-tbl.h: Re-generate.
2174 2020-03-09 Jan Beulich <jbeulich@suse.com>
2176 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2177 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2178 * i386-tbl.h: Re-generate.
2180 2020-03-09 Jan Beulich <jbeulich@suse.com>
2182 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2183 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2184 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2185 * i386-tbl.h: Re-generate.
2187 2020-03-09 Jan Beulich <jbeulich@suse.com>
2189 * i386-gen.c (struct template_arg, struct template_instance,
2190 struct template_param, struct template, templates,
2191 parse_template, expand_templates): New.
2192 (process_i386_opcodes): Various local variables moved to
2193 expand_templates. Call parse_template and expand_templates.
2194 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2195 * i386-tbl.h: Re-generate.
2197 2020-03-06 Jan Beulich <jbeulich@suse.com>
2199 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2200 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2201 register and memory source templates. Replace VexW= by VexW*
2203 * i386-tbl.h: Re-generate.
2205 2020-03-06 Jan Beulich <jbeulich@suse.com>
2207 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2208 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2209 * i386-tbl.h: Re-generate.
2211 2020-03-06 Jan Beulich <jbeulich@suse.com>
2213 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2214 * i386-tbl.h: Re-generate.
2216 2020-03-06 Jan Beulich <jbeulich@suse.com>
2218 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2219 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2220 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2221 VexW0 on SSE2AVX variants.
2222 (vmovq): Drop NoRex64 from XMM/XMM variants.
2223 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2224 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2225 applicable use VexW0.
2226 * i386-tbl.h: Re-generate.
2228 2020-03-06 Jan Beulich <jbeulich@suse.com>
2230 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2231 * i386-opc.h (Rex64): Delete.
2232 (struct i386_opcode_modifier): Remove rex64 field.
2233 * i386-opc.tbl (crc32): Drop Rex64.
2234 Replace Rex64 with Size64 everywhere else.
2235 * i386-tbl.h: Re-generate.
2237 2020-03-06 Jan Beulich <jbeulich@suse.com>
2239 * i386-dis.c (OP_E_memory): Exclude recording of used address
2240 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2241 addressed memory operands for MPX insns.
2243 2020-03-06 Jan Beulich <jbeulich@suse.com>
2245 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2246 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2247 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2248 (ptwrite): Split into non-64-bit and 64-bit forms.
2249 * i386-tbl.h: Re-generate.
2251 2020-03-06 Jan Beulich <jbeulich@suse.com>
2253 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2255 * i386-tbl.h: Re-generate.
2257 2020-03-04 Jan Beulich <jbeulich@suse.com>
2259 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2260 (prefix_table): Move vmmcall here. Add vmgexit.
2261 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2262 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2263 (cpu_flags): Add CpuSEV_ES entry.
2264 * i386-opc.h (CpuSEV_ES): New.
2265 (union i386_cpu_flags): Add cpusev_es field.
2266 * i386-opc.tbl (vmgexit): New.
2267 * i386-init.h, i386-tbl.h: Re-generate.
2269 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2271 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2273 * i386-opc.h (IGNORESIZE): New.
2274 (DEFAULTSIZE): Likewise.
2275 (IgnoreSize): Removed.
2276 (DefaultSize): Likewise.
2277 (MnemonicSize): New.
2278 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2280 * i386-opc.tbl (IgnoreSize): New.
2281 (DefaultSize): Likewise.
2282 * i386-tbl.h: Regenerated.
2284 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2287 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2290 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2293 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2294 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2295 * i386-tbl.h: Regenerated.
2297 2020-02-26 Alan Modra <amodra@gmail.com>
2299 * aarch64-asm.c: Indent labels correctly.
2300 * aarch64-dis.c: Likewise.
2301 * aarch64-gen.c: Likewise.
2302 * aarch64-opc.c: Likewise.
2303 * alpha-dis.c: Likewise.
2304 * i386-dis.c: Likewise.
2305 * nds32-asm.c: Likewise.
2306 * nfp-dis.c: Likewise.
2307 * visium-dis.c: Likewise.
2309 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2311 * arc-regs.h (int_vector_base): Make it available for all ARC
2314 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2316 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2319 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2321 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2322 c.mv/c.li if rs1 is zero.
2324 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2326 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2327 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2329 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2330 * i386-opc.h (CpuABM): Removed.
2332 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2333 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2334 popcnt. Remove CpuABM from lzcnt.
2335 * i386-init.h: Regenerated.
2336 * i386-tbl.h: Likewise.
2338 2020-02-17 Jan Beulich <jbeulich@suse.com>
2340 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2341 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2342 VexW1 instead of open-coding them.
2343 * i386-tbl.h: Re-generate.
2345 2020-02-17 Jan Beulich <jbeulich@suse.com>
2347 * i386-opc.tbl (AddrPrefixOpReg): Define.
2348 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2349 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2350 templates. Drop NoRex64.
2351 * i386-tbl.h: Re-generate.
2353 2020-02-17 Jan Beulich <jbeulich@suse.com>
2356 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2357 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2358 into Intel syntax instance (with Unpsecified) and AT&T one
2360 (vcvtneps2bf16): Likewise, along with folding the two so far
2362 * i386-tbl.h: Re-generate.
2364 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2366 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2367 CPU_ANY_SSE4A_FLAGS.
2369 2020-02-17 Alan Modra <amodra@gmail.com>
2371 * i386-gen.c (cpu_flag_init): Correct last change.
2373 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2375 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2378 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2380 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2383 2020-02-14 Jan Beulich <jbeulich@suse.com>
2386 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2387 destination for Cpu64-only variant.
2388 (movzx): Fold patterns.
2389 * i386-tbl.h: Re-generate.
2391 2020-02-13 Jan Beulich <jbeulich@suse.com>
2393 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2394 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2395 CPU_ANY_SSE4_FLAGS entry.
2396 * i386-init.h: Re-generate.
2398 2020-02-12 Jan Beulich <jbeulich@suse.com>
2400 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2401 with Unspecified, making the present one AT&T syntax only.
2402 * i386-tbl.h: Re-generate.
2404 2020-02-12 Jan Beulich <jbeulich@suse.com>
2406 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2407 * i386-tbl.h: Re-generate.
2409 2020-02-12 Jan Beulich <jbeulich@suse.com>
2412 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2413 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2414 Amd64 and Intel64 templates.
2415 (call, jmp): Likewise for far indirect variants. Dro
2417 * i386-tbl.h: Re-generate.
2419 2020-02-11 Jan Beulich <jbeulich@suse.com>
2421 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2422 * i386-opc.h (ShortForm): Delete.
2423 (struct i386_opcode_modifier): Remove shortform field.
2424 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2425 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2426 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2427 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2429 * i386-tbl.h: Re-generate.
2431 2020-02-11 Jan Beulich <jbeulich@suse.com>
2433 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2434 fucompi): Drop ShortForm from operand-less templates.
2435 * i386-tbl.h: Re-generate.
2437 2020-02-11 Alan Modra <amodra@gmail.com>
2439 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2440 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2441 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2442 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2443 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2445 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2447 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2448 (cde_opcodes): Add VCX* instructions.
2450 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2451 Matthew Malcomson <matthew.malcomson@arm.com>
2453 * arm-dis.c (struct cdeopcode32): New.
2454 (CDE_OPCODE): New macro.
2455 (cde_opcodes): New disassembly table.
2456 (regnames): New option to table.
2457 (cde_coprocs): New global variable.
2458 (print_insn_cde): New
2459 (print_insn_thumb32): Use print_insn_cde.
2460 (parse_arm_disassembler_options): Parse coprocN args.
2462 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2465 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2467 * i386-opc.h (AMD64): Removed.
2468 (Intel64): Likewose.
2470 (INTEL64): Likewise.
2471 (INTEL64ONLY): Likewise.
2472 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2473 * i386-opc.tbl (Amd64): New.
2474 (Intel64): Likewise.
2475 (Intel64Only): Likewise.
2476 Replace AMD64 with Amd64. Update sysenter/sysenter with
2477 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2478 * i386-tbl.h: Regenerated.
2480 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2483 * z80-dis.c: Add support for GBZ80 opcodes.
2485 2020-02-04 Alan Modra <amodra@gmail.com>
2487 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2489 2020-02-03 Alan Modra <amodra@gmail.com>
2491 * m32c-ibld.c: Regenerate.
2493 2020-02-01 Alan Modra <amodra@gmail.com>
2495 * frv-ibld.c: Regenerate.
2497 2020-01-31 Jan Beulich <jbeulich@suse.com>
2499 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2500 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2501 (OP_E_memory): Replace xmm_mdq_mode case label by
2502 vex_scalar_w_dq_mode one.
2503 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2505 2020-01-31 Jan Beulich <jbeulich@suse.com>
2507 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2508 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2509 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2510 (intel_operand_size): Drop vex_w_dq_mode case label.
2512 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2514 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2515 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2517 2020-01-30 Alan Modra <amodra@gmail.com>
2519 * m32c-ibld.c: Regenerate.
2521 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2523 * bpf-opc.c: Regenerate.
2525 2020-01-30 Jan Beulich <jbeulich@suse.com>
2527 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2528 (dis386): Use them to replace C2/C3 table entries.
2529 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2530 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2531 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2532 * i386-tbl.h: Re-generate.
2534 2020-01-30 Jan Beulich <jbeulich@suse.com>
2536 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2538 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2540 * i386-tbl.h: Re-generate.
2542 2020-01-30 Alan Modra <amodra@gmail.com>
2544 * tic4x-dis.c (tic4x_dp): Make unsigned.
2546 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2547 Jan Beulich <jbeulich@suse.com>
2550 * i386-dis.c (MOVSXD_Fixup): New function.
2551 (movsxd_mode): New enum.
2552 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2553 (intel_operand_size): Handle movsxd_mode.
2554 (OP_E_register): Likewise.
2556 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2557 register on movsxd. Add movsxd with 16-bit destination register
2558 for AMD64 and Intel64 ISAs.
2559 * i386-tbl.h: Regenerated.
2561 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2564 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2565 * aarch64-asm-2.c: Regenerate
2566 * aarch64-dis-2.c: Likewise.
2567 * aarch64-opc-2.c: Likewise.
2569 2020-01-21 Jan Beulich <jbeulich@suse.com>
2571 * i386-opc.tbl (sysret): Drop DefaultSize.
2572 * i386-tbl.h: Re-generate.
2574 2020-01-21 Jan Beulich <jbeulich@suse.com>
2576 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2578 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2579 * i386-tbl.h: Re-generate.
2581 2020-01-20 Nick Clifton <nickc@redhat.com>
2583 * po/de.po: Updated German translation.
2584 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2585 * po/uk.po: Updated Ukranian translation.
2587 2020-01-20 Alan Modra <amodra@gmail.com>
2589 * hppa-dis.c (fput_const): Remove useless cast.
2591 2020-01-20 Alan Modra <amodra@gmail.com>
2593 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2595 2020-01-18 Nick Clifton <nickc@redhat.com>
2597 * configure: Regenerate.
2598 * po/opcodes.pot: Regenerate.
2600 2020-01-18 Nick Clifton <nickc@redhat.com>
2602 Binutils 2.34 branch created.
2604 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2606 * opintl.h: Fix spelling error (seperate).
2608 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2610 * i386-opc.tbl: Add {vex} pseudo prefix.
2611 * i386-tbl.h: Regenerated.
2613 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2616 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2617 (neon_opcodes): Likewise.
2618 (select_arm_features): Make sure we enable MVE bits when selecting
2619 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2622 2020-01-16 Jan Beulich <jbeulich@suse.com>
2624 * i386-opc.tbl: Drop stale comment from XOP section.
2626 2020-01-16 Jan Beulich <jbeulich@suse.com>
2628 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2629 (extractps): Add VexWIG to SSE2AVX forms.
2630 * i386-tbl.h: Re-generate.
2632 2020-01-16 Jan Beulich <jbeulich@suse.com>
2634 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2635 Size64 from and use VexW1 on SSE2AVX forms.
2636 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2637 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2638 * i386-tbl.h: Re-generate.
2640 2020-01-15 Alan Modra <amodra@gmail.com>
2642 * tic4x-dis.c (tic4x_version): Make unsigned long.
2643 (optab, optab_special, registernames): New file scope vars.
2644 (tic4x_print_register): Set up registernames rather than
2645 malloc'd registertable.
2646 (tic4x_disassemble): Delete optable and optable_special. Use
2647 optab and optab_special instead. Throw away old optab,
2648 optab_special and registernames when info->mach changes.
2650 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2653 * z80-dis.c (suffix): Use .db instruction to generate double
2656 2020-01-14 Alan Modra <amodra@gmail.com>
2658 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2659 values to unsigned before shifting.
2661 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2663 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2665 (print_insn_thumb16, print_insn_thumb32): Likewise.
2666 (print_insn): Initialize the insn info.
2667 * i386-dis.c (print_insn): Initialize the insn info fields, and
2670 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2672 * arc-opc.c (C_NE): Make it required.
2674 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2676 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2677 reserved register name.
2679 2020-01-13 Alan Modra <amodra@gmail.com>
2681 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2682 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2684 2020-01-13 Alan Modra <amodra@gmail.com>
2686 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2687 result of wasm_read_leb128 in a uint64_t and check that bits
2688 are not lost when copying to other locals. Use uint32_t for
2689 most locals. Use PRId64 when printing int64_t.
2691 2020-01-13 Alan Modra <amodra@gmail.com>
2693 * score-dis.c: Formatting.
2694 * score7-dis.c: Formatting.
2696 2020-01-13 Alan Modra <amodra@gmail.com>
2698 * score-dis.c (print_insn_score48): Use unsigned variables for
2699 unsigned values. Don't left shift negative values.
2700 (print_insn_score32): Likewise.
2701 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2703 2020-01-13 Alan Modra <amodra@gmail.com>
2705 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2707 2020-01-13 Alan Modra <amodra@gmail.com>
2709 * fr30-ibld.c: Regenerate.
2711 2020-01-13 Alan Modra <amodra@gmail.com>
2713 * xgate-dis.c (print_insn): Don't left shift signed value.
2714 (ripBits): Formatting, use 1u.
2716 2020-01-10 Alan Modra <amodra@gmail.com>
2718 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2719 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2721 2020-01-10 Alan Modra <amodra@gmail.com>
2723 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2724 and XRREG value earlier to avoid a shift with negative exponent.
2725 * m10200-dis.c (disassemble): Similarly.
2727 2020-01-09 Nick Clifton <nickc@redhat.com>
2730 * z80-dis.c (ld_ii_ii): Use correct cast.
2732 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2735 * z80-dis.c (ld_ii_ii): Use character constant when checking
2738 2020-01-09 Jan Beulich <jbeulich@suse.com>
2740 * i386-dis.c (SEP_Fixup): New.
2742 (dis386_twobyte): Use it for sysenter/sysexit.
2743 (enum x86_64_isa): Change amd64 enumerator to value 1.
2744 (OP_J): Compare isa64 against intel64 instead of amd64.
2745 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2747 * i386-tbl.h: Re-generate.
2749 2020-01-08 Alan Modra <amodra@gmail.com>
2751 * z8k-dis.c: Include libiberty.h
2752 (instr_data_s): Make max_fetched unsigned.
2753 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2754 Don't exceed byte_info bounds.
2755 (output_instr): Make num_bytes unsigned.
2756 (unpack_instr): Likewise for nibl_count and loop.
2757 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2759 * z8k-opc.h: Regenerate.
2761 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2763 * arc-tbl.h (llock): Use 'LLOCK' as class.
2765 (scond): Use 'SCOND' as class.
2767 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2770 2020-01-06 Alan Modra <amodra@gmail.com>
2772 * m32c-ibld.c: Regenerate.
2774 2020-01-06 Alan Modra <amodra@gmail.com>
2777 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2778 Peek at next byte to prevent recursion on repeated prefix bytes.
2779 Ensure uninitialised "mybuf" is not accessed.
2780 (print_insn_z80): Don't zero n_fetch and n_used here,..
2781 (print_insn_z80_buf): ..do it here instead.
2783 2020-01-04 Alan Modra <amodra@gmail.com>
2785 * m32r-ibld.c: Regenerate.
2787 2020-01-04 Alan Modra <amodra@gmail.com>
2789 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2791 2020-01-04 Alan Modra <amodra@gmail.com>
2793 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2795 2020-01-04 Alan Modra <amodra@gmail.com>
2797 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2799 2020-01-03 Jan Beulich <jbeulich@suse.com>
2801 * aarch64-tbl.h (aarch64_opcode_table): Use
2802 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2804 2020-01-03 Jan Beulich <jbeulich@suse.com>
2806 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2807 forms of SUDOT and USDOT.
2809 2020-01-03 Jan Beulich <jbeulich@suse.com>
2811 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2813 * opcodes/aarch64-dis-2.c: Re-generate.
2815 2020-01-03 Jan Beulich <jbeulich@suse.com>
2817 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2819 * opcodes/aarch64-dis-2.c: Re-generate.
2821 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2823 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2825 2020-01-01 Alan Modra <amodra@gmail.com>
2827 Update year range in copyright notice of all files.
2829 For older changes see ChangeLog-2019
2831 Copyright (C) 2020 Free Software Foundation, Inc.
2833 Copying and distribution of this file, with or without modification,
2834 are permitted in any medium without royalty provided the copyright
2835 notice and this notice are preserved.
2841 version-control: never
projects / deliverable / binutils-gdb.git / blob