opcodes/ChangeLog

   1 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (prefix_table): Fix a typo in comments.
   4
   5 2020-06-09  Jan Beulich  <jbeulich@suse.com>
   6
   7         * i386-dis.c (rex_ignored): Delete.
   8         (ckprefix): Drop rex_ignored initialization.
   9         (get_valid_dis386): Drop setting of rex_ignored.
  10         (print_insn): Drop checking of rex_ignored. Don't record data
  11         size prefix as used with VEX-and-alike encodings.
  12
  13 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
  16         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
  17         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
  18         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
  19         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
  20         VEX_0F12, and VEX_0F16.
  21         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
  22         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
  23         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
  24         from movlps and movhlps. New MOD_0F12_PREFIX_2,
  25         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
  26         MOD_VEX_0F16_PREFIX_2 entries.
  27
  28 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
  31         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
  32         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  33         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
  34         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
  35         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
  36         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
  37         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
  38         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
  39         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
  40         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
  41         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
  42         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
  43         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
  44         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
  45         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
  46         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
  47         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
  48         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
  49         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
  50         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
  51         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
  52         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
  53         EVEX_W_0FC6_P_2): Delete.
  54         (print_insn): Add EVEX.W vs embedded prefix consistency check
  55         to prefix validation.
  56         * i386-dis-evex.h (evex_table): Don't further descend for
  57         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
  58         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
  59         and 0F2B.
  60         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
  61         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
  62         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
  63         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
  64         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
  65         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  66         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
  67         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
  68         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
  69         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
  70         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
  71         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
  72         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
  73         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
  74         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
  75         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
  76         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
  77         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
  78         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
  79         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
  80         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
  81         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
  82         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
  83         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
  84         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
  85         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
  86         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
  87
  88 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  89
  90         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
  91         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
  92         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
  93         vmovmskpX.
  94         (print_insn): Drop pointless check against bad_opcode. Split
  95         prefix validation into legacy and VEX-and-alike parts.
  96         (putop): Re-work 'X' macro handling.
  97
  98 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  99
 100         * i386-dis.c (MOD_0F51): Rename to ...
 101         (MOD_0F50): ... this.
 102
 103 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 104
 105         * arm-dis.c (arm_opcodes): Add dfb.
 106         (thumb32_opcodes): Add dfb.
 107
 108 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 111
 112 2020-06-06  Alan Modra  <amodra@gmail.com>
 113
 114         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 115
 116 2020-06-05  Alan Modra  <amodra@gmail.com>
 117
 118         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 119         size is large enough.
 120
 121 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 122
 123         * disassemble.c (disassemble_init_for_target): Set endian_code for
 124         bpf targets.
 125         * bpf-desc.c: Regenerate.
 126         * bpf-opc.c: Likewise.
 127         * bpf-dis.c: Likewise.
 128
 129 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 130
 131         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 132         (cgen_put_insn_value): Likewise.
 133         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 134         * cgen-dis.in (print_insn): Likewise.
 135         * cgen-ibld.in (insert_1): Likewise.
 136         (insert_1): Likewise.
 137         (insert_insn_normal): Likewise.
 138         (extract_1): Likewise.
 139         * bpf-dis.c: Regenerate.
 140         * bpf-ibld.c: Likewise.
 141         * bpf-ibld.c: Likewise.
 142         * cgen-dis.in: Likewise.
 143         * cgen-ibld.in: Likewise.
 144         * cgen-opc.c: Likewise.
 145         * epiphany-dis.c: Likewise.
 146         * epiphany-ibld.c: Likewise.
 147         * fr30-dis.c: Likewise.
 148         * fr30-ibld.c: Likewise.
 149         * frv-dis.c: Likewise.
 150         * frv-ibld.c: Likewise.
 151         * ip2k-dis.c: Likewise.
 152         * ip2k-ibld.c: Likewise.
 153         * iq2000-dis.c: Likewise.
 154         * iq2000-ibld.c: Likewise.
 155         * lm32-dis.c: Likewise.
 156         * lm32-ibld.c: Likewise.
 157         * m32c-dis.c: Likewise.
 158         * m32c-ibld.c: Likewise.
 159         * m32r-dis.c: Likewise.
 160         * m32r-ibld.c: Likewise.
 161         * mep-dis.c: Likewise.
 162         * mep-ibld.c: Likewise.
 163         * mt-dis.c: Likewise.
 164         * mt-ibld.c: Likewise.
 165         * or1k-dis.c: Likewise.
 166         * or1k-ibld.c: Likewise.
 167         * xc16x-dis.c: Likewise.
 168         * xc16x-ibld.c: Likewise.
 169         * xstormy16-dis.c: Likewise.
 170         * xstormy16-ibld.c: Likewise.
 171
 172 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 173
 174         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 175         (print_insn_): Handle instruction endian.
 176         * bpf-dis.c: Regenerate.
 177         * bpf-desc.c: Regenerate.
 178         * epiphany-dis.c: Likewise.
 179         * epiphany-desc.c: Likewise.
 180         * fr30-dis.c: Likewise.
 181         * fr30-desc.c: Likewise.
 182         * frv-dis.c: Likewise.
 183         * frv-desc.c: Likewise.
 184         * ip2k-dis.c: Likewise.
 185         * ip2k-desc.c: Likewise.
 186         * iq2000-dis.c: Likewise.
 187         * iq2000-desc.c: Likewise.
 188         * lm32-dis.c: Likewise.
 189         * lm32-desc.c: Likewise.
 190         * m32c-dis.c: Likewise.
 191         * m32c-desc.c: Likewise.
 192         * m32r-dis.c: Likewise.
 193         * m32r-desc.c: Likewise.
 194         * mep-dis.c: Likewise.
 195         * mep-desc.c: Likewise.
 196         * mt-dis.c: Likewise.
 197         * mt-desc.c: Likewise.
 198         * or1k-dis.c: Likewise.
 199         * or1k-desc.c: Likewise.
 200         * xc16x-dis.c: Likewise.
 201         * xc16x-desc.c: Likewise.
 202         * xstormy16-dis.c: Likewise.
 203         * xstormy16-desc.c: Likewise.
 204
 205 2020-06-03  Nick Clifton  <nickc@redhat.com>
 206
 207         * po/sr.po: Updated Serbian translation.
 208
 209 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 210
 211         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 212         (riscv_get_priv_spec_class): Likewise.
 213
 214 2020-06-01  Alan Modra  <amodra@gmail.com>
 215
 216         * bpf-desc.c: Regenerate.
 217
 218 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 219             David Faust <david.faust@oracle.com>
 220
 221         * bpf-desc.c: Regenerate.
 222         * bpf-opc.h: Likewise.
 223         * bpf-opc.c: Likewise.
 224         * bpf-dis.c: Likewise.
 225
 226 2020-05-28  Alan Modra  <amodra@gmail.com>
 227
 228         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 229         values.
 230
 231 2020-05-28  Alan Modra  <amodra@gmail.com>
 232
 233         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 234         immediates.
 235         (print_insn_ns32k): Revert last change.
 236
 237 2020-05-28  Nick Clifton  <nickc@redhat.com>
 238
 239         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 240         static.
 241
 242 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 243
 244         Fix extraction of signed constants in nios2 disassembler (again).
 245
 246         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 247         extractions of signed fields.
 248
 249 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 250
 251         * s390-opc.txt: Relocate vector load/store instructions with
 252         additional alignment parameter and change architecture level
 253         constraint from z14 to z13.
 254
 255 2020-05-21  Alan Modra  <amodra@gmail.com>
 256
 257         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 258         * sparc-dis.c: Likewise.
 259         * tic4x-dis.c: Likewise.
 260         * xtensa-dis.c: Likewise.
 261         * bpf-desc.c: Regenerate.
 262         * epiphany-desc.c: Regenerate.
 263         * fr30-desc.c: Regenerate.
 264         * frv-desc.c: Regenerate.
 265         * ip2k-desc.c: Regenerate.
 266         * iq2000-desc.c: Regenerate.
 267         * lm32-desc.c: Regenerate.
 268         * m32c-desc.c: Regenerate.
 269         * m32r-desc.c: Regenerate.
 270         * mep-asm.c: Regenerate.
 271         * mep-desc.c: Regenerate.
 272         * mt-desc.c: Regenerate.
 273         * or1k-desc.c: Regenerate.
 274         * xc16x-desc.c: Regenerate.
 275         * xstormy16-desc.c: Regenerate.
 276
 277 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 278
 279         * riscv-opc.c (riscv_ext_version_table): The table used to store
 280         all information about the supported spec and the corresponding ISA
 281         versions.  Currently, only Zicsr is supported to verify the
 282         correctness of Z sub extension settings.  Others will be supported
 283         in the future patches.
 284         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 285         classes and the corresponding strings.
 286         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 287         spec class by giving a ISA spec string.
 288         * riscv-opc.c (struct priv_spec_t): New structure.
 289         (struct priv_spec_t priv_specs): List for all supported privilege spec
 290         classes and the corresponding strings.
 291         (riscv_get_priv_spec_class): New function.  Get the corresponding
 292         privilege spec class by giving a spec string.
 293         (riscv_get_priv_spec_name): New function.  Get the corresponding
 294         privilege spec string by giving a CSR version class.
 295         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 296         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 297         according to the chosen version.  Build a hash table riscv_csr_hash to
 298         store the valid CSR for the chosen pirv verison.  Dump the direct
 299         CSR address rather than it's name if it is invalid.
 300         (parse_riscv_dis_option_without_args): New function.  Parse the options
 301         without arguments.
 302         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 303         parse the options without arguments first, and then handle the options
 304         with arguments.  Add the new option -Mpriv-spec, which has argument.
 305         * riscv-dis.c (print_riscv_disassembler_options): Add description
 306         about the new OBJDUMP option.
 307
 308 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 309
 310         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 311         WC values on POWER10 sync, dcbf  and wait instructions.
 312         (insert_pl, extract_pl): New functions.
 313         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 314         (LS3): New , 3-bit L for sync.
 315         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 316         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 317         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 318         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 319         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 320         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 321         <wait>: Enable PL operand on POWER10.
 322         <dcbf>: Enable L3OPT operand on POWER10.
 323         <sync>: Enable SC2 operand on POWER10.
 324
 325 2020-05-19  Stafford Horne  <shorne@gmail.com>
 326
 327         PR 25184
 328         * or1k-asm.c: Regenerate.
 329         * or1k-desc.c: Regenerate.
 330         * or1k-desc.h: Regenerate.
 331         * or1k-dis.c: Regenerate.
 332         * or1k-ibld.c: Regenerate.
 333         * or1k-opc.c: Regenerate.
 334         * or1k-opc.h: Regenerate.
 335         * or1k-opinst.c: Regenerate.
 336
 337 2020-05-11  Alan Modra  <amodra@gmail.com>
 338
 339         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 340         xsmaxcqp, xsmincqp.
 341
 342 2020-05-11  Alan Modra  <amodra@gmail.com>
 343
 344         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 345         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 346
 347 2020-05-11  Alan Modra  <amodra@gmail.com>
 348
 349         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 350
 351 2020-05-11  Alan Modra  <amodra@gmail.com>
 352
 353         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 354         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 355
 356 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 357
 358         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 359         mnemonics.
 360
 361 2020-05-11  Alan Modra  <amodra@gmail.com>
 362
 363         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 364         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 365         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 366         (prefix_opcodes): Add xxeval.
 367
 368 2020-05-11  Alan Modra  <amodra@gmail.com>
 369
 370         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 371         xxgenpcvwm, xxgenpcvdm.
 372
 373 2020-05-11  Alan Modra  <amodra@gmail.com>
 374
 375         * ppc-opc.c (MP, VXVAM_MASK): Define.
 376         (VXVAPS_MASK): Use VXVA_MASK.
 377         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 378         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 379         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 380         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 381
 382 2020-05-11  Alan Modra  <amodra@gmail.com>
 383             Peter Bergner  <bergner@linux.ibm.com>
 384
 385         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 386         New functions.
 387         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 388         YMSK2, XA6a, XA6ap, XB6a entries.
 389         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 390         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 391         (PPCVSX4): Define.
 392         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 393         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 394         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 395         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 396         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 397         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 398         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 399         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 400         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 401         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 402         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 403         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 404         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 405         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 406
 407 2020-05-11  Alan Modra  <amodra@gmail.com>
 408
 409         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 410         (insert_xts, extract_xts): New functions.
 411         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 412         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 413         (VXRC_MASK, VXSH_MASK): Define.
 414         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 415         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 416         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 417         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 418         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 419         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 420         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 421
 422 2020-05-11  Alan Modra  <amodra@gmail.com>
 423
 424         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 425         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 426         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 427         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 428         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 429
 430 2020-05-11  Alan Modra  <amodra@gmail.com>
 431
 432         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 433         (XTP, DQXP, DQXP_MASK): Define.
 434         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 435         (prefix_opcodes): Add plxvp and pstxvp.
 436
 437 2020-05-11  Alan Modra  <amodra@gmail.com>
 438
 439         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 440         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 441         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 442
 443 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 444
 445         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 446
 447 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 448
 449         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 450         (L1OPT): Define.
 451         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 452
 453 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 454
 455         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 456
 457 2020-05-11  Alan Modra  <amodra@gmail.com>
 458
 459         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 460
 461 2020-05-11  Alan Modra  <amodra@gmail.com>
 462
 463         * ppc-dis.c (ppc_opts): Add "power10" entry.
 464         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 465         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 466
 467 2020-05-11  Nick Clifton  <nickc@redhat.com>
 468
 469         * po/fr.po: Updated French translation.
 470
 471 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 472
 473         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 474         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 475         (operand_general_constraint_met_p): validate
 476         AARCH64_OPND_UNDEFINED.
 477         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 478         for FLD_imm16_2.
 479         * aarch64-asm-2.c: Regenerated.
 480         * aarch64-dis-2.c: Regenerated.
 481         * aarch64-opc-2.c: Regenerated.
 482
 483 2020-04-29  Nick Clifton  <nickc@redhat.com>
 484
 485         PR 22699
 486         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 487         and SETRC insns.
 488
 489 2020-04-29  Nick Clifton  <nickc@redhat.com>
 490
 491         * po/sv.po: Updated Swedish translation.
 492
 493 2020-04-29  Nick Clifton  <nickc@redhat.com>
 494
 495         PR 22699
 496         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 497         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 498         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 499         IMM0_8U case.
 500
 501 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 502
 503         PR 25848
 504         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 505         cmpi only on m68020up and cpu32.
 506
 507 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 508
 509         * aarch64-asm.c (aarch64_ins_none): New.
 510         * aarch64-asm.h (ins_none): New declaration.
 511         * aarch64-dis.c (aarch64_ext_none): New.
 512         * aarch64-dis.h (ext_none): New declaration.
 513         * aarch64-opc.c (aarch64_print_operand): Update case for
 514         AARCH64_OPND_BARRIER_PSB.
 515         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 516         (AARCH64_OPERANDS): Update inserter/extracter for
 517         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 518         * aarch64-asm-2.c: Regenerated.
 519         * aarch64-dis-2.c: Regenerated.
 520         * aarch64-opc-2.c: Regenerated.
 521
 522 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 523
 524         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 525         (aarch64_feature_ras, RAS): Likewise.
 526         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 527         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 528         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 529         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 530         * aarch64-asm-2.c: Regenerated.
 531         * aarch64-dis-2.c: Regenerated.
 532         * aarch64-opc-2.c: Regenerated.
 533
 534 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 535
 536         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 537         (print_insn_neon): Support disassembly of conditional
 538         instructions.
 539
 540 2020-02-16  David Faust  <david.faust@oracle.com>
 541
 542         * bpf-desc.c: Regenerate.
 543         * bpf-desc.h: Likewise.
 544         * bpf-opc.c: Regenerate.
 545         * bpf-opc.h: Likewise.
 546
 547 2020-04-07  Lili Cui  <lili.cui@intel.com>
 548
 549         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 550         (prefix_table): New instructions (see prefixes above).
 551         (rm_table): Likewise
 552         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 553         CPU_ANY_TSXLDTRK_FLAGS.
 554         (cpu_flags): Add CpuTSXLDTRK.
 555         * i386-opc.h (enum): Add CpuTSXLDTRK.
 556         (i386_cpu_flags): Add cputsxldtrk.
 557         * i386-opc.tbl: Add XSUSPLDTRK insns.
 558         * i386-init.h: Regenerate.
 559         * i386-tbl.h: Likewise.
 560
 561 2020-04-02  Lili Cui  <lili.cui@intel.com>
 562
 563         * i386-dis.c (prefix_table): New instructions serialize.
 564         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 565         CPU_ANY_SERIALIZE_FLAGS.
 566         (cpu_flags): Add CpuSERIALIZE.
 567         * i386-opc.h (enum): Add CpuSERIALIZE.
 568         (i386_cpu_flags): Add cpuserialize.
 569         * i386-opc.tbl: Add SERIALIZE insns.
 570         * i386-init.h: Regenerate.
 571         * i386-tbl.h: Likewise.
 572
 573 2020-03-26  Alan Modra  <amodra@gmail.com>
 574
 575         * disassemble.h (opcodes_assert): Declare.
 576         (OPCODES_ASSERT): Define.
 577         * disassemble.c: Don't include assert.h.  Include opintl.h.
 578         (opcodes_assert): New function.
 579         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 580         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 581         calculate maxlen.  Omit insn decoding when insn length exceeds
 582         maxlen.  Exit from nibble loop when looking for E, before
 583         accessing next data byte.  Move processing of E outside loop.
 584         Replace tests of maxlen in loop with assertions.
 585
 586 2020-03-26  Alan Modra  <amodra@gmail.com>
 587
 588         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 589
 590 2020-03-25  Alan Modra  <amodra@gmail.com>
 591
 592         * z80-dis.c (suffix): Init mybuf.
 593
 594 2020-03-22  Alan Modra  <amodra@gmail.com>
 595
 596         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 597         successflly read from section.
 598
 599 2020-03-22  Alan Modra  <amodra@gmail.com>
 600
 601         * arc-dis.c (find_format): Use ISO C string concatenation rather
 602         than line continuation within a string.  Don't access needs_limm
 603         before testing opcode != NULL.
 604
 605 2020-03-22  Alan Modra  <amodra@gmail.com>
 606
 607         * ns32k-dis.c (print_insn_arg): Update comment.
 608         (print_insn_ns32k): Reduce size of index_offset array, and
 609         initialize, passing -1 to print_insn_arg for args that are not
 610         an index.  Don't exit arg loop early.  Abort on bad arg number.
 611
 612 2020-03-22  Alan Modra  <amodra@gmail.com>
 613
 614         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 615         * s12z-opc.c: Formatting.
 616         (operands_f): Return an int.
 617         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 618         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 619         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 620         (exg_sex_discrim): Likewise.
 621         (create_immediate_operand, create_bitfield_operand),
 622         (create_register_operand_with_size, create_register_all_operand),
 623         (create_register_all16_operand, create_simple_memory_operand),
 624         (create_memory_operand, create_memory_auto_operand): Don't
 625         segfault on malloc failure.
 626         (z_ext24_decode): Return an int status, negative on fail, zero
 627         on success.
 628         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 629         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 630         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 631         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 632         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 633         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 634         (loop_primitive_decode, shift_decode, psh_pul_decode),
 635         (bit_field_decode): Similarly.
 636         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 637         to return value, update callers.
 638         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 639         Don't segfault on NULL operand.
 640         (decode_operation): Return OP_INVALID on first fail.
 641         (decode_s12z): Check all reads, returning -1 on fail.
 642
 643 2020-03-20  Alan Modra  <amodra@gmail.com>
 644
 645         * metag-dis.c (print_insn_metag): Don't ignore status from
 646         read_memory_func.
 647
 648 2020-03-20  Alan Modra  <amodra@gmail.com>
 649
 650         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 651         Initialize parts of buffer not written when handling a possible
 652         2-byte insn at end of section.  Don't attempt decoding of such
 653         an insn by the 4-byte machinery.
 654
 655 2020-03-20  Alan Modra  <amodra@gmail.com>
 656
 657         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 658         partially filled buffer.  Prevent lookup of 4-byte insns when
 659         only VLE 2-byte insns are possible due to section size.  Print
 660         ".word" rather than ".long" for 2-byte leftovers.
 661
 662 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 663
 664         PR 25641
 665         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 666
 667 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 668
 669         * i386-dis.c (X86_64_0D): Rename to ...
 670         (X86_64_0E): ... this.
 671
 672 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 673
 674         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 675         * Makefile.in: Regenerated.
 676
 677 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 678
 679         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 680         3-operand pseudos.
 681         * i386-tbl.h: Re-generate.
 682
 683 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 684
 685         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 686         vprot*, vpsha*, and vpshl*.
 687         * i386-tbl.h: Re-generate.
 688
 689 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 692         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 693         * i386-tbl.h: Re-generate.
 694
 695 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 696
 697         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 698         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 699         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 700         * i386-tbl.h: Re-generate.
 701
 702 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 703
 704         * i386-gen.c (struct template_arg, struct template_instance,
 705         struct template_param, struct template, templates,
 706         parse_template, expand_templates): New.
 707         (process_i386_opcodes): Various local variables moved to
 708         expand_templates. Call parse_template and expand_templates.
 709         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 710         * i386-tbl.h: Re-generate.
 711
 712 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 715         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 716         register and memory source templates. Replace VexW= by VexW*
 717         where applicable.
 718         * i386-tbl.h: Re-generate.
 719
 720 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 721
 722         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 723         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 724         * i386-tbl.h: Re-generate.
 725
 726 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 729         * i386-tbl.h: Re-generate.
 730
 731 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 732
 733         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 734         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 735         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 736         VexW0 on SSE2AVX variants.
 737         (vmovq): Drop NoRex64 from XMM/XMM variants.
 738         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 739         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 740         applicable use VexW0.
 741         * i386-tbl.h: Re-generate.
 742
 743 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 744
 745         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 746         * i386-opc.h (Rex64): Delete.
 747         (struct i386_opcode_modifier): Remove rex64 field.
 748         * i386-opc.tbl (crc32): Drop Rex64.
 749         Replace Rex64 with Size64 everywhere else.
 750         * i386-tbl.h: Re-generate.
 751
 752 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 753
 754         * i386-dis.c (OP_E_memory): Exclude recording of used address
 755         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 756         addressed memory operands for MPX insns.
 757
 758 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 761         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 762         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 763         (ptwrite): Split into non-64-bit and 64-bit forms.
 764         * i386-tbl.h: Re-generate.
 765
 766 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 767
 768         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 769         template.
 770         * i386-tbl.h: Re-generate.
 771
 772 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 773
 774         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 775         (prefix_table): Move vmmcall here. Add vmgexit.
 776         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 777         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 778         (cpu_flags): Add CpuSEV_ES entry.
 779         * i386-opc.h (CpuSEV_ES): New.
 780         (union i386_cpu_flags): Add cpusev_es field.
 781         * i386-opc.tbl (vmgexit): New.
 782         * i386-init.h, i386-tbl.h: Re-generate.
 783
 784 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 785
 786         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 787         with MnemonicSize.
 788         * i386-opc.h (IGNORESIZE): New.
 789         (DEFAULTSIZE): Likewise.
 790         (IgnoreSize): Removed.
 791         (DefaultSize): Likewise.
 792         (MnemonicSize): New.
 793         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 794         mnemonicsize.
 795         * i386-opc.tbl (IgnoreSize): New.
 796         (DefaultSize): Likewise.
 797         * i386-tbl.h: Regenerated.
 798
 799 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 800
 801         PR 25627
 802         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 803         instructions.
 804
 805 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 806
 807         PR gas/25622
 808         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 809         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 810         * i386-tbl.h: Regenerated.
 811
 812 2020-02-26  Alan Modra  <amodra@gmail.com>
 813
 814         * aarch64-asm.c: Indent labels correctly.
 815         * aarch64-dis.c: Likewise.
 816         * aarch64-gen.c: Likewise.
 817         * aarch64-opc.c: Likewise.
 818         * alpha-dis.c: Likewise.
 819         * i386-dis.c: Likewise.
 820         * nds32-asm.c: Likewise.
 821         * nfp-dis.c: Likewise.
 822         * visium-dis.c: Likewise.
 823
 824 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 825
 826         * arc-regs.h (int_vector_base): Make it available for all ARC
 827         CPUs.
 828
 829 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 830
 831         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 832         changed.
 833
 834 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 835
 836         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 837         c.mv/c.li if rs1 is zero.
 838
 839 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 840
 841         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 842         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 843         CPU_POPCNT_FLAGS.
 844         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 845         * i386-opc.h (CpuABM): Removed.
 846         (CpuPOPCNT): New.
 847         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 848         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 849         popcnt.  Remove CpuABM from lzcnt.
 850         * i386-init.h: Regenerated.
 851         * i386-tbl.h: Likewise.
 852
 853 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 854
 855         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 856         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 857         VexW1 instead of open-coding them.
 858         * i386-tbl.h: Re-generate.
 859
 860 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 861
 862         * i386-opc.tbl (AddrPrefixOpReg): Define.
 863         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 864         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 865         templates. Drop NoRex64.
 866         * i386-tbl.h: Re-generate.
 867
 868 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 869
 870         PR gas/6518
 871         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 872         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 873         into Intel syntax instance (with Unpsecified) and AT&T one
 874         (without).
 875         (vcvtneps2bf16): Likewise, along with folding the two so far
 876         separate ones.
 877         * i386-tbl.h: Re-generate.
 878
 879 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 880
 881         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 882         CPU_ANY_SSE4A_FLAGS.
 883
 884 2020-02-17  Alan Modra  <amodra@gmail.com>
 885
 886         * i386-gen.c (cpu_flag_init): Correct last change.
 887
 888 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 889
 890         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 891         CPU_ANY_SSE4_FLAGS.
 892
 893 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 894
 895         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 896         (movzx): Likewise.
 897
 898 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 899
 900         PR gas/25438
 901         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 902         destination for Cpu64-only variant.
 903         (movzx): Fold patterns.
 904         * i386-tbl.h: Re-generate.
 905
 906 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 907
 908         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 909         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 910         CPU_ANY_SSE4_FLAGS entry.
 911         * i386-init.h: Re-generate.
 912
 913 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 914
 915         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 916         with Unspecified, making the present one AT&T syntax only.
 917         * i386-tbl.h: Re-generate.
 918
 919 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 920
 921         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 922         * i386-tbl.h: Re-generate.
 923
 924 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 925
 926         PR gas/24546
 927         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 928         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 929         Amd64 and Intel64 templates.
 930         (call, jmp): Likewise for far indirect variants. Dro
 931         Unspecified.
 932         * i386-tbl.h: Re-generate.
 933
 934 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 937         * i386-opc.h (ShortForm): Delete.
 938         (struct i386_opcode_modifier): Remove shortform field.
 939         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 940         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 941         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 942         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 943         Drop ShortForm.
 944         * i386-tbl.h: Re-generate.
 945
 946 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 949         fucompi): Drop ShortForm from operand-less templates.
 950         * i386-tbl.h: Re-generate.
 951
 952 2020-02-11  Alan Modra  <amodra@gmail.com>
 953
 954         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 955         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 956         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 957         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 958         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 959
 960 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 961
 962         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 963         (cde_opcodes): Add VCX* instructions.
 964
 965 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 966             Matthew Malcomson  <matthew.malcomson@arm.com>
 967
 968         * arm-dis.c (struct cdeopcode32): New.
 969         (CDE_OPCODE): New macro.
 970         (cde_opcodes): New disassembly table.
 971         (regnames): New option to table.
 972         (cde_coprocs): New global variable.
 973         (print_insn_cde): New
 974         (print_insn_thumb32): Use print_insn_cde.
 975         (parse_arm_disassembler_options): Parse coprocN args.
 976
 977 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 978
 979         PR gas/25516
 980         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 981         with ISA64.
 982         * i386-opc.h (AMD64): Removed.
 983         (Intel64): Likewose.
 984         (AMD64): New.
 985         (INTEL64): Likewise.
 986         (INTEL64ONLY): Likewise.
 987         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 988         * i386-opc.tbl (Amd64): New.
 989         (Intel64): Likewise.
 990         (Intel64Only): Likewise.
 991         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 992         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 993         * i386-tbl.h: Regenerated.
 994
 995 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 996
 997         PR 25469
 998         * z80-dis.c: Add support for GBZ80 opcodes.
 999
1000 2020-02-04  Alan Modra  <amodra@gmail.com>
1001
1002         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1003
1004 2020-02-03  Alan Modra  <amodra@gmail.com>
1005
1006         * m32c-ibld.c: Regenerate.
1007
1008 2020-02-01  Alan Modra  <amodra@gmail.com>
1009
1010         * frv-ibld.c: Regenerate.
1011
1012 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1013
1014         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1015         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1016         (OP_E_memory): Replace xmm_mdq_mode case label by
1017         vex_scalar_w_dq_mode one.
1018         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1019
1020 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1021
1022         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1023         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1024         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1025         (intel_operand_size): Drop vex_w_dq_mode case label.
1026
1027 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1028
1029         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1030         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1031
1032 2020-01-30  Alan Modra  <amodra@gmail.com>
1033
1034         * m32c-ibld.c: Regenerate.
1035
1036 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1037
1038         * bpf-opc.c: Regenerate.
1039
1040 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1041
1042         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1043         (dis386): Use them to replace C2/C3 table entries.
1044         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1045         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1046         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1047         * i386-tbl.h: Re-generate.
1048
1049 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1050
1051         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1052         forms.
1053         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1054         DefaultSize.
1055         * i386-tbl.h: Re-generate.
1056
1057 2020-01-30  Alan Modra  <amodra@gmail.com>
1058
1059         * tic4x-dis.c (tic4x_dp): Make unsigned.
1060
1061 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1062             Jan Beulich  <jbeulich@suse.com>
1063
1064         PR binutils/25445
1065         * i386-dis.c (MOVSXD_Fixup): New function.
1066         (movsxd_mode): New enum.
1067         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1068         (intel_operand_size): Handle movsxd_mode.
1069         (OP_E_register): Likewise.
1070         (OP_G): Likewise.
1071         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1072         register on movsxd.  Add movsxd with 16-bit destination register
1073         for AMD64 and Intel64 ISAs.
1074         * i386-tbl.h: Regenerated.
1075
1076 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1077
1078         PR 25403
1079         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1080         * aarch64-asm-2.c: Regenerate
1081         * aarch64-dis-2.c: Likewise.
1082         * aarch64-opc-2.c: Likewise.
1083
1084 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1085
1086         * i386-opc.tbl (sysret): Drop DefaultSize.
1087         * i386-tbl.h: Re-generate.
1088
1089 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1090
1091         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1092         Dword.
1093         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1094         * i386-tbl.h: Re-generate.
1095
1096 2020-01-20  Nick Clifton  <nickc@redhat.com>
1097
1098         * po/de.po: Updated German translation.
1099         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1100         * po/uk.po: Updated Ukranian translation.
1101
1102 2020-01-20  Alan Modra  <amodra@gmail.com>
1103
1104         * hppa-dis.c (fput_const): Remove useless cast.
1105
1106 2020-01-20  Alan Modra  <amodra@gmail.com>
1107
1108         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1109
1110 2020-01-18  Nick Clifton  <nickc@redhat.com>
1111
1112         * configure: Regenerate.
1113         * po/opcodes.pot: Regenerate.
1114
1115 2020-01-18  Nick Clifton  <nickc@redhat.com>
1116
1117         Binutils 2.34 branch created.
1118
1119 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1120
1121         * opintl.h: Fix spelling error (seperate).
1122
1123 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1124
1125         * i386-opc.tbl: Add {vex} pseudo prefix.
1126         * i386-tbl.h: Regenerated.
1127
1128 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1129
1130         PR 25376
1131         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1132         (neon_opcodes): Likewise.
1133         (select_arm_features): Make sure we enable MVE bits when selecting
1134         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1135         any architecture.
1136
1137 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-opc.tbl: Drop stale comment from XOP section.
1140
1141 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1142
1143         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1144         (extractps): Add VexWIG to SSE2AVX forms.
1145         * i386-tbl.h: Re-generate.
1146
1147 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1148
1149         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1150         Size64 from and use VexW1 on SSE2AVX forms.
1151         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1152         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1153         * i386-tbl.h: Re-generate.
1154
1155 2020-01-15  Alan Modra  <amodra@gmail.com>
1156
1157         * tic4x-dis.c (tic4x_version): Make unsigned long.
1158         (optab, optab_special, registernames): New file scope vars.
1159         (tic4x_print_register): Set up registernames rather than
1160         malloc'd registertable.
1161         (tic4x_disassemble): Delete optable and optable_special.  Use
1162         optab and optab_special instead.  Throw away old optab,
1163         optab_special and registernames when info->mach changes.
1164
1165 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1166
1167         PR 25377
1168         * z80-dis.c (suffix): Use .db instruction to generate double
1169         prefix.
1170
1171 2020-01-14  Alan Modra  <amodra@gmail.com>
1172
1173         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1174         values to unsigned before shifting.
1175
1176 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1177
1178         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1179         flow instructions.
1180         (print_insn_thumb16, print_insn_thumb32): Likewise.
1181         (print_insn): Initialize the insn info.
1182         * i386-dis.c (print_insn): Initialize the insn info fields, and
1183         detect jumps.
1184
1185 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1186
1187         * arc-opc.c (C_NE): Make it required.
1188
1189 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1190
1191         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1192         reserved register name.
1193
1194 2020-01-13  Alan Modra  <amodra@gmail.com>
1195
1196         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1197         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1198
1199 2020-01-13  Alan Modra  <amodra@gmail.com>
1200
1201         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1202         result of wasm_read_leb128 in a uint64_t and check that bits
1203         are not lost when copying to other locals.  Use uint32_t for
1204         most locals.  Use PRId64 when printing int64_t.
1205
1206 2020-01-13  Alan Modra  <amodra@gmail.com>
1207
1208         * score-dis.c: Formatting.
1209         * score7-dis.c: Formatting.
1210
1211 2020-01-13  Alan Modra  <amodra@gmail.com>
1212
1213         * score-dis.c (print_insn_score48): Use unsigned variables for
1214         unsigned values.  Don't left shift negative values.
1215         (print_insn_score32): Likewise.
1216         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1217
1218 2020-01-13  Alan Modra  <amodra@gmail.com>
1219
1220         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1221
1222 2020-01-13  Alan Modra  <amodra@gmail.com>
1223
1224         * fr30-ibld.c: Regenerate.
1225
1226 2020-01-13  Alan Modra  <amodra@gmail.com>
1227
1228         * xgate-dis.c (print_insn): Don't left shift signed value.
1229         (ripBits): Formatting, use 1u.
1230
1231 2020-01-10  Alan Modra  <amodra@gmail.com>
1232
1233         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1234         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1235
1236 2020-01-10  Alan Modra  <amodra@gmail.com>
1237
1238         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1239         and XRREG value earlier to avoid a shift with negative exponent.
1240         * m10200-dis.c (disassemble): Similarly.
1241
1242 2020-01-09  Nick Clifton  <nickc@redhat.com>
1243
1244         PR 25224
1245         * z80-dis.c (ld_ii_ii): Use correct cast.
1246
1247 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1248
1249         PR 25224
1250         * z80-dis.c (ld_ii_ii): Use character constant when checking
1251         opcode byte value.
1252
1253 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-dis.c (SEP_Fixup): New.
1256         (SEP): Define.
1257         (dis386_twobyte): Use it for sysenter/sysexit.
1258         (enum x86_64_isa): Change amd64 enumerator to value 1.
1259         (OP_J): Compare isa64 against intel64 instead of amd64.
1260         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1261         forms.
1262         * i386-tbl.h: Re-generate.
1263
1264 2020-01-08  Alan Modra  <amodra@gmail.com>
1265
1266         * z8k-dis.c: Include libiberty.h
1267         (instr_data_s): Make max_fetched unsigned.
1268         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1269         Don't exceed byte_info bounds.
1270         (output_instr): Make num_bytes unsigned.
1271         (unpack_instr): Likewise for nibl_count and loop.
1272         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1273         idx unsigned.
1274         * z8k-opc.h: Regenerate.
1275
1276 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1277
1278         * arc-tbl.h (llock): Use 'LLOCK' as class.
1279         (llockd): Likewise.
1280         (scond): Use 'SCOND' as class.
1281         (scondd): Likewise.
1282         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1283         (scondd): Likewise.
1284
1285 2020-01-06  Alan Modra  <amodra@gmail.com>
1286
1287         * m32c-ibld.c: Regenerate.
1288
1289 2020-01-06  Alan Modra  <amodra@gmail.com>
1290
1291         PR 25344
1292         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1293         Peek at next byte to prevent recursion on repeated prefix bytes.
1294         Ensure uninitialised "mybuf" is not accessed.
1295         (print_insn_z80): Don't zero n_fetch and n_used here,..
1296         (print_insn_z80_buf): ..do it here instead.
1297
1298 2020-01-04  Alan Modra  <amodra@gmail.com>
1299
1300         * m32r-ibld.c: Regenerate.
1301
1302 2020-01-04  Alan Modra  <amodra@gmail.com>
1303
1304         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1305
1306 2020-01-04  Alan Modra  <amodra@gmail.com>
1307
1308         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1309
1310 2020-01-04  Alan Modra  <amodra@gmail.com>
1311
1312         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1313
1314 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1315
1316         * aarch64-tbl.h (aarch64_opcode_table): Use
1317         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1318
1319 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1320
1321         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1322         forms of SUDOT and USDOT.
1323
1324 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1325
1326         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1327         uzip{1,2}.
1328         * opcodes/aarch64-dis-2.c: Re-generate.
1329
1330 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1331
1332         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1333         FMMLA encoding.
1334         * opcodes/aarch64-dis-2.c: Re-generate.
1335
1336 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1337
1338         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1339
1340 2020-01-01  Alan Modra  <amodra@gmail.com>
1341
1342         Update year range in copyright notice of all files.
1343
1344 For older changes see ChangeLog-2019
1345 \f
1346 Copyright (C) 2020 Free Software Foundation, Inc.
1347
1348 Copying and distribution of this file, with or without modification,
1349 are permitted in any medium without royalty provided the copyright
1350 notice and this notice are preserved.
1351
1352 Local Variables:
1353 mode: change-log
1354 left-margin: 8
1355 fill-column: 74
1356 version-control: never
1357 End: