1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
117 static void MOVSXD_Fixup (int, int);
119 static void OP_Mask (int, int);
122 /* Points to first byte not fetched. */
123 bfd_byte
*max_fetched
;
124 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
127 OPCODES_SIGJMP_BUF bailout
;
137 enum address_mode address_mode
;
139 /* Flags for the prefixes for the current instruction. See below. */
142 /* REX prefix the current instruction. See below. */
144 /* Bits of REX we've already used. */
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
155 rex_used |= (value) | REX_OPCODE; \
158 rex_used |= REX_OPCODE; \
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes
;
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
187 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
190 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
191 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
193 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
194 status
= (*info
->read_memory_func
) (start
,
196 addr
- priv
->max_fetched
,
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
206 if (priv
->max_fetched
== priv
->the_buffer
)
207 (*info
->memory_error_func
) (status
, start
, info
);
208 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
211 priv
->max_fetched
= addr
;
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
350 #define XMM { OP_XMM, xmm_mode }
351 #define TMM { OP_XMM, tmm_mode }
352 #define XMxmmq { OP_XMM, xmmq_mode }
353 #define EM { OP_EM, v_mode }
354 #define EMS { OP_EM, v_swap_mode }
355 #define EMd { OP_EM, d_mode }
356 #define EMx { OP_EM, x_mode }
357 #define EXbwUnit { OP_EX, bw_unit_mode }
358 #define EXw { OP_EX, w_mode }
359 #define EXd { OP_EX, d_mode }
360 #define EXdS { OP_EX, d_swap_mode }
361 #define EXq { OP_EX, q_mode }
362 #define EXqS { OP_EX, q_swap_mode }
363 #define EXx { OP_EX, x_mode }
364 #define EXxS { OP_EX, x_swap_mode }
365 #define EXxmm { OP_EX, xmm_mode }
366 #define EXymm { OP_EX, ymm_mode }
367 #define EXtmm { OP_EX, tmm_mode }
368 #define EXxmmq { OP_EX, xmmq_mode }
369 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
370 #define EXxmm_mb { OP_EX, xmm_mb_mode }
371 #define EXxmm_mw { OP_EX, xmm_mw_mode }
372 #define EXxmm_md { OP_EX, xmm_md_mode }
373 #define EXxmm_mq { OP_EX, xmm_mq_mode }
374 #define EXxmmdw { OP_EX, xmmdw_mode }
375 #define EXxmmqd { OP_EX, xmmqd_mode }
376 #define EXymmq { OP_EX, ymmq_mode }
377 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
378 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
379 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
380 #define MS { OP_MS, v_mode }
381 #define XS { OP_XS, v_mode }
382 #define EMCq { OP_EMC, q_mode }
383 #define MXC { OP_MXC, 0 }
384 #define OPSUF { OP_3DNowSuffix, 0 }
385 #define SEP { SEP_Fixup, 0 }
386 #define CMP { CMP_Fixup, 0 }
387 #define XMM0 { XMM_Fixup, 0 }
388 #define FXSAVE { FXSAVE_Fixup, 0 }
390 #define Vex { OP_VEX, vex_mode }
391 #define VexW { OP_VexW, vex_mode }
392 #define VexScalar { OP_VEX, vex_scalar_mode }
393 #define VexScalarR { OP_VexR, vex_scalar_mode }
394 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
395 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
396 #define VexGdq { OP_VEX, dq_mode }
397 #define VexTmm { OP_VEX, tmm_mode }
398 #define XMVexI4 { OP_REG_VexI4, x_mode }
399 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
400 #define VexI4 { OP_VexI4, 0 }
401 #define PCLMUL { PCLMUL_Fixup, 0 }
402 #define VPCMP { VPCMP_Fixup, 0 }
403 #define VPCOM { VPCOM_Fixup, 0 }
405 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
406 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
407 #define EXxEVexS { OP_Rounding, evex_sae_mode }
409 #define XMask { OP_Mask, mask_mode }
410 #define MaskG { OP_G, mask_mode }
411 #define MaskE { OP_E, mask_mode }
412 #define MaskBDE { OP_E, mask_bd_mode }
413 #define MaskVex { OP_VEX, mask_mode }
415 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
416 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
453 /* byte operand with operand swapped */
455 /* byte operand, sign extend like 'T' suffix */
457 /* operand size depends on prefixes */
459 /* operand size depends on prefixes with operand swapped */
461 /* operand size depends on address prefix */
465 /* double word operand */
467 /* double word operand with operand swapped */
469 /* quad word operand */
471 /* quad word operand with operand swapped */
473 /* ten-byte operand */
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
478 /* Similar to x_mode, but with different EVEX mem shifts. */
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
482 /* Similar to x_mode, but with disabled broadcast. */
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
487 /* 16-byte XMM operand */
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode
,
495 /* XMM register or byte memory operand */
497 /* XMM register or word memory operand */
499 /* XMM register or double word memory operand */
501 /* XMM register or quad word memory operand */
503 /* 16-byte XMM, word, double word or quad word operand. */
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
507 /* 32-byte YMM operand */
509 /* quad word, ymmword or zmmword memory operand. */
511 /* 32-byte YMM or 16-byte word operand */
515 /* d_mode in 32bit, q_mode in 64bit mode. */
517 /* pair of v_mode operands */
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
525 /* operand size depends on REX prefixes. */
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
532 /* bounds operand with operand swapped */
534 /* 4- or 6-byte pointer operand */
537 /* v_mode for indirect branch opcodes. */
539 /* v_mode for stack-related opcodes. */
541 /* non-quad operand size depends on prefixes */
543 /* 16-byte operand */
545 /* registers like dq_mode, memory like b_mode. */
547 /* registers like d_mode, memory like b_mode. */
549 /* registers like d_mode, memory like w_mode. */
551 /* registers like dq_mode, memory like d_mode. */
553 /* normal vex mode */
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode
,
558 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
559 vex_vsib_q_w_dq_mode
,
560 /* mandatory non-vector SIB. */
563 /* scalar, ignore vector length. */
565 /* like vex_mode, ignore vector length. */
567 /* Operand size depends on the VEX.W bit, ignore vector length. */
568 vex_scalar_w_dq_mode
,
570 /* Static rounding. */
572 /* Static rounding, 64-bit mode only. */
573 evex_rounding_64_mode
,
574 /* Supress all exceptions. */
577 /* Mask register operand. */
579 /* Mask register operand. */
647 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
649 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
650 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
651 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
652 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
653 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
654 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
655 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
656 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
657 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
658 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
659 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
660 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
661 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
662 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
663 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
664 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
691 REG_0F3A0F_PREFIX_1_MOD_3
,
704 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
709 REG_XOP_09_12_M_1_L_0
,
715 REG_EVEX_0F38C6_M_0_L_2
,
716 REG_EVEX_0F38C7_M_0_L_2
793 MOD_VEX_0F12_PREFIX_0
,
794 MOD_VEX_0F12_PREFIX_2
,
796 MOD_VEX_0F16_PREFIX_0
,
797 MOD_VEX_0F16_PREFIX_2
,
821 MOD_VEX_0FF0_PREFIX_3
,
828 MOD_VEX_0F3849_X86_64_P_0_W_0
,
829 MOD_VEX_0F3849_X86_64_P_2_W_0
,
830 MOD_VEX_0F3849_X86_64_P_3_W_0
,
831 MOD_VEX_0F384B_X86_64_P_1_W_0
,
832 MOD_VEX_0F384B_X86_64_P_2_W_0
,
833 MOD_VEX_0F384B_X86_64_P_3_W_0
,
835 MOD_VEX_0F385C_X86_64_P_1_W_0
,
836 MOD_VEX_0F385E_X86_64_P_0_W_0
,
837 MOD_VEX_0F385E_X86_64_P_1_W_0
,
838 MOD_VEX_0F385E_X86_64_P_2_W_0
,
839 MOD_VEX_0F385E_X86_64_P_3_W_0
,
849 MOD_EVEX_0F12_PREFIX_0
,
850 MOD_EVEX_0F12_PREFIX_2
,
852 MOD_EVEX_0F16_PREFIX_0
,
853 MOD_EVEX_0F16_PREFIX_2
,
859 MOD_EVEX_0F382A_P_1_W_1
,
861 MOD_EVEX_0F383A_P_1_W_0
,
881 RM_0F1E_P_1_MOD_3_REG_7
,
882 RM_0FAE_REG_6_MOD_3_P_0
,
884 RM_0F3A0F_P_1_MOD_3_REG_0
,
886 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
892 PREFIX_0F01_REG_1_RM_4
,
893 PREFIX_0F01_REG_1_RM_5
,
894 PREFIX_0F01_REG_1_RM_6
,
895 PREFIX_0F01_REG_1_RM_7
,
896 PREFIX_0F01_REG_3_RM_1
,
897 PREFIX_0F01_REG_5_MOD_0
,
898 PREFIX_0F01_REG_5_MOD_3_RM_0
,
899 PREFIX_0F01_REG_5_MOD_3_RM_1
,
900 PREFIX_0F01_REG_5_MOD_3_RM_2
,
901 PREFIX_0F01_REG_5_MOD_3_RM_4
,
902 PREFIX_0F01_REG_5_MOD_3_RM_5
,
903 PREFIX_0F01_REG_5_MOD_3_RM_6
,
904 PREFIX_0F01_REG_5_MOD_3_RM_7
,
905 PREFIX_0F01_REG_7_MOD_3_RM_2
,
906 PREFIX_0F01_REG_7_MOD_3_RM_6
,
907 PREFIX_0F01_REG_7_MOD_3_RM_7
,
945 PREFIX_0FAE_REG_0_MOD_3
,
946 PREFIX_0FAE_REG_1_MOD_3
,
947 PREFIX_0FAE_REG_2_MOD_3
,
948 PREFIX_0FAE_REG_3_MOD_3
,
949 PREFIX_0FAE_REG_4_MOD_0
,
950 PREFIX_0FAE_REG_4_MOD_3
,
951 PREFIX_0FAE_REG_5_MOD_3
,
952 PREFIX_0FAE_REG_6_MOD_0
,
953 PREFIX_0FAE_REG_6_MOD_3
,
954 PREFIX_0FAE_REG_7_MOD_0
,
959 PREFIX_0FC7_REG_6_MOD_0
,
960 PREFIX_0FC7_REG_6_MOD_3
,
961 PREFIX_0FC7_REG_7_MOD_3
,
989 PREFIX_VEX_0F41_L_1_M_1_W_0
,
990 PREFIX_VEX_0F41_L_1_M_1_W_1
,
991 PREFIX_VEX_0F42_L_1_M_1_W_0
,
992 PREFIX_VEX_0F42_L_1_M_1_W_1
,
993 PREFIX_VEX_0F44_L_0_M_1_W_0
,
994 PREFIX_VEX_0F44_L_0_M_1_W_1
,
995 PREFIX_VEX_0F45_L_1_M_1_W_0
,
996 PREFIX_VEX_0F45_L_1_M_1_W_1
,
997 PREFIX_VEX_0F46_L_1_M_1_W_0
,
998 PREFIX_VEX_0F46_L_1_M_1_W_1
,
999 PREFIX_VEX_0F47_L_1_M_1_W_0
,
1000 PREFIX_VEX_0F47_L_1_M_1_W_1
,
1001 PREFIX_VEX_0F4A_L_1_M_1_W_0
,
1002 PREFIX_VEX_0F4A_L_1_M_1_W_1
,
1003 PREFIX_VEX_0F4B_L_1_M_1_W_0
,
1004 PREFIX_VEX_0F4B_L_1_M_1_W_1
,
1022 PREFIX_VEX_0F90_L_0_W_0
,
1023 PREFIX_VEX_0F90_L_0_W_1
,
1024 PREFIX_VEX_0F91_L_0_M_0_W_0
,
1025 PREFIX_VEX_0F91_L_0_M_0_W_1
,
1026 PREFIX_VEX_0F92_L_0_M_1_W_0
,
1027 PREFIX_VEX_0F92_L_0_M_1_W_1
,
1028 PREFIX_VEX_0F93_L_0_M_1_W_0
,
1029 PREFIX_VEX_0F93_L_0_M_1_W_1
,
1030 PREFIX_VEX_0F98_L_0_M_1_W_0
,
1031 PREFIX_VEX_0F98_L_0_M_1_W_1
,
1032 PREFIX_VEX_0F99_L_0_M_1_W_0
,
1033 PREFIX_VEX_0F99_L_0_M_1_W_1
,
1038 PREFIX_VEX_0F3849_X86_64
,
1039 PREFIX_VEX_0F384B_X86_64
,
1040 PREFIX_VEX_0F385C_X86_64
,
1041 PREFIX_VEX_0F385E_X86_64
,
1042 PREFIX_VEX_0F38F5_L_0
,
1043 PREFIX_VEX_0F38F6_L_0
,
1044 PREFIX_VEX_0F38F7_L_0
,
1045 PREFIX_VEX_0F3AF0_L_0
,
1140 X86_64_0F01_REG_1_RM_5_PREFIX_2
,
1141 X86_64_0F01_REG_1_RM_6_PREFIX_2
,
1142 X86_64_0F01_REG_1_RM_7_PREFIX_2
,
1145 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
,
1146 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
,
1147 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
,
1148 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
,
1149 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
,
1150 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
,
1151 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
,
1154 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
,
1164 THREE_BYTE_0F38
= 0,
1191 VEX_LEN_0F12_P_0_M_0
= 0,
1192 VEX_LEN_0F12_P_0_M_1
,
1193 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1195 VEX_LEN_0F16_P_0_M_0
,
1196 VEX_LEN_0F16_P_0_M_1
,
1197 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1217 VEX_LEN_0FAE_R_2_M_0
,
1218 VEX_LEN_0FAE_R_3_M_0
,
1228 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1229 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1230 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1231 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1232 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1233 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1234 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1236 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1237 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1238 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1239 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1240 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1273 VEX_LEN_0FXOP_08_85
,
1274 VEX_LEN_0FXOP_08_86
,
1275 VEX_LEN_0FXOP_08_87
,
1276 VEX_LEN_0FXOP_08_8E
,
1277 VEX_LEN_0FXOP_08_8F
,
1278 VEX_LEN_0FXOP_08_95
,
1279 VEX_LEN_0FXOP_08_96
,
1280 VEX_LEN_0FXOP_08_97
,
1281 VEX_LEN_0FXOP_08_9E
,
1282 VEX_LEN_0FXOP_08_9F
,
1283 VEX_LEN_0FXOP_08_A3
,
1284 VEX_LEN_0FXOP_08_A6
,
1285 VEX_LEN_0FXOP_08_B6
,
1286 VEX_LEN_0FXOP_08_C0
,
1287 VEX_LEN_0FXOP_08_C1
,
1288 VEX_LEN_0FXOP_08_C2
,
1289 VEX_LEN_0FXOP_08_C3
,
1290 VEX_LEN_0FXOP_08_CC
,
1291 VEX_LEN_0FXOP_08_CD
,
1292 VEX_LEN_0FXOP_08_CE
,
1293 VEX_LEN_0FXOP_08_CF
,
1294 VEX_LEN_0FXOP_08_EC
,
1295 VEX_LEN_0FXOP_08_ED
,
1296 VEX_LEN_0FXOP_08_EE
,
1297 VEX_LEN_0FXOP_08_EF
,
1298 VEX_LEN_0FXOP_09_01
,
1299 VEX_LEN_0FXOP_09_02
,
1300 VEX_LEN_0FXOP_09_12_M_1
,
1301 VEX_LEN_0FXOP_09_82_W_0
,
1302 VEX_LEN_0FXOP_09_83_W_0
,
1303 VEX_LEN_0FXOP_09_90
,
1304 VEX_LEN_0FXOP_09_91
,
1305 VEX_LEN_0FXOP_09_92
,
1306 VEX_LEN_0FXOP_09_93
,
1307 VEX_LEN_0FXOP_09_94
,
1308 VEX_LEN_0FXOP_09_95
,
1309 VEX_LEN_0FXOP_09_96
,
1310 VEX_LEN_0FXOP_09_97
,
1311 VEX_LEN_0FXOP_09_98
,
1312 VEX_LEN_0FXOP_09_99
,
1313 VEX_LEN_0FXOP_09_9A
,
1314 VEX_LEN_0FXOP_09_9B
,
1315 VEX_LEN_0FXOP_09_C1
,
1316 VEX_LEN_0FXOP_09_C2
,
1317 VEX_LEN_0FXOP_09_C3
,
1318 VEX_LEN_0FXOP_09_C6
,
1319 VEX_LEN_0FXOP_09_C7
,
1320 VEX_LEN_0FXOP_09_CB
,
1321 VEX_LEN_0FXOP_09_D1
,
1322 VEX_LEN_0FXOP_09_D2
,
1323 VEX_LEN_0FXOP_09_D3
,
1324 VEX_LEN_0FXOP_09_D6
,
1325 VEX_LEN_0FXOP_09_D7
,
1326 VEX_LEN_0FXOP_09_DB
,
1327 VEX_LEN_0FXOP_09_E1
,
1328 VEX_LEN_0FXOP_09_E2
,
1329 VEX_LEN_0FXOP_09_E3
,
1330 VEX_LEN_0FXOP_0A_12
,
1335 EVEX_LEN_0F3816
= 0,
1337 EVEX_LEN_0F381A_M_0
,
1338 EVEX_LEN_0F381B_M_0
,
1340 EVEX_LEN_0F385A_M_0
,
1341 EVEX_LEN_0F385B_M_0
,
1342 EVEX_LEN_0F38C6_M_0
,
1343 EVEX_LEN_0F38C7_M_0
,
1360 VEX_W_0F41_L_1_M_1
= 0,
1382 VEX_W_0F381A_M_0_L_1
,
1389 VEX_W_0F3849_X86_64_P_0
,
1390 VEX_W_0F3849_X86_64_P_2
,
1391 VEX_W_0F3849_X86_64_P_3
,
1392 VEX_W_0F384B_X86_64_P_1
,
1393 VEX_W_0F384B_X86_64_P_2
,
1394 VEX_W_0F384B_X86_64_P_3
,
1401 VEX_W_0F385A_M_0_L_0
,
1402 VEX_W_0F385C_X86_64_P_1
,
1403 VEX_W_0F385E_X86_64_P_0
,
1404 VEX_W_0F385E_X86_64_P_1
,
1405 VEX_W_0F385E_X86_64_P_2
,
1406 VEX_W_0F385E_X86_64_P_3
,
1428 VEX_W_0FXOP_08_85_L_0
,
1429 VEX_W_0FXOP_08_86_L_0
,
1430 VEX_W_0FXOP_08_87_L_0
,
1431 VEX_W_0FXOP_08_8E_L_0
,
1432 VEX_W_0FXOP_08_8F_L_0
,
1433 VEX_W_0FXOP_08_95_L_0
,
1434 VEX_W_0FXOP_08_96_L_0
,
1435 VEX_W_0FXOP_08_97_L_0
,
1436 VEX_W_0FXOP_08_9E_L_0
,
1437 VEX_W_0FXOP_08_9F_L_0
,
1438 VEX_W_0FXOP_08_A6_L_0
,
1439 VEX_W_0FXOP_08_B6_L_0
,
1440 VEX_W_0FXOP_08_C0_L_0
,
1441 VEX_W_0FXOP_08_C1_L_0
,
1442 VEX_W_0FXOP_08_C2_L_0
,
1443 VEX_W_0FXOP_08_C3_L_0
,
1444 VEX_W_0FXOP_08_CC_L_0
,
1445 VEX_W_0FXOP_08_CD_L_0
,
1446 VEX_W_0FXOP_08_CE_L_0
,
1447 VEX_W_0FXOP_08_CF_L_0
,
1448 VEX_W_0FXOP_08_EC_L_0
,
1449 VEX_W_0FXOP_08_ED_L_0
,
1450 VEX_W_0FXOP_08_EE_L_0
,
1451 VEX_W_0FXOP_08_EF_L_0
,
1457 VEX_W_0FXOP_09_C1_L_0
,
1458 VEX_W_0FXOP_09_C2_L_0
,
1459 VEX_W_0FXOP_09_C3_L_0
,
1460 VEX_W_0FXOP_09_C6_L_0
,
1461 VEX_W_0FXOP_09_C7_L_0
,
1462 VEX_W_0FXOP_09_CB_L_0
,
1463 VEX_W_0FXOP_09_D1_L_0
,
1464 VEX_W_0FXOP_09_D2_L_0
,
1465 VEX_W_0FXOP_09_D3_L_0
,
1466 VEX_W_0FXOP_09_D6_L_0
,
1467 VEX_W_0FXOP_09_D7_L_0
,
1468 VEX_W_0FXOP_09_DB_L_0
,
1469 VEX_W_0FXOP_09_E1_L_0
,
1470 VEX_W_0FXOP_09_E2_L_0
,
1471 VEX_W_0FXOP_09_E3_L_0
,
1477 EVEX_W_0F12_P_0_M_1
,
1480 EVEX_W_0F16_P_0_M_1
,
1560 EVEX_W_0F381A_M_0_L_n
,
1561 EVEX_W_0F381B_M_0_L_2
,
1587 EVEX_W_0F385A_M_0_L_n
,
1588 EVEX_W_0F385B_M_0_L_2
,
1618 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1627 unsigned int prefix_requirement
;
1630 /* Upper case letters in the instruction names here are macros.
1631 'A' => print 'b' if no register operands or suffix_always is true
1632 'B' => print 'b' if suffix_always is true
1633 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1635 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1636 suffix_always is true
1637 'E' => print 'e' if 32-bit form of jcxz
1638 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1639 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1640 'H' => print ",pt" or ",pn" branch hint
1643 'K' => print 'd' or 'q' if rex prefix is present.
1645 'M' => print 'r' if intel_mnemonic is false.
1646 'N' => print 'n' if instruction has no wait "prefix"
1647 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1648 'P' => behave as 'T' except with register operand outside of suffix_always
1650 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1652 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1653 'S' => print 'w', 'l' or 'q' if suffix_always is true
1654 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1655 prefix or if suffix_always is true.
1658 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1659 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1661 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1662 '!' => change condition from true to false or from false to true.
1663 '%' => add 1 upper case letter to the macro.
1664 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1665 prefix or suffix_always is true (lcall/ljmp).
1666 '@' => in 64bit mode for Intel64 ISA or if instruction
1667 has no operand sizing prefix, print 'q' if suffix_always is true or
1668 nothing otherwise; behave as 'P' in all other cases
1670 2 upper case letter macros:
1671 "XY" => print 'x' or 'y' if suffix_always is true or no register
1672 operands and no broadcast.
1673 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1674 register operands and no broadcast.
1675 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1676 "XV" => print "{vex3}" pseudo prefix
1677 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1678 being false, or no operand at all in 64bit mode, or if suffix_always
1680 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1681 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1682 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1683 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1684 "BW" => print 'b' or 'w' depending on the VEX.W bit
1685 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1686 an operand size prefix, or suffix_always is true. print
1687 'q' if rex prefix is present.
1689 Many of the above letters print nothing in Intel mode. See "putop"
1692 Braces '{' and '}', and vertical bars '|', indicate alternative
1693 mnemonic strings for AT&T and Intel. */
1695 static const struct dis386 dis386
[] = {
1697 { "addB", { Ebh1
, Gb
}, 0 },
1698 { "addS", { Evh1
, Gv
}, 0 },
1699 { "addB", { Gb
, EbS
}, 0 },
1700 { "addS", { Gv
, EvS
}, 0 },
1701 { "addB", { AL
, Ib
}, 0 },
1702 { "addS", { eAX
, Iv
}, 0 },
1703 { X86_64_TABLE (X86_64_06
) },
1704 { X86_64_TABLE (X86_64_07
) },
1706 { "orB", { Ebh1
, Gb
}, 0 },
1707 { "orS", { Evh1
, Gv
}, 0 },
1708 { "orB", { Gb
, EbS
}, 0 },
1709 { "orS", { Gv
, EvS
}, 0 },
1710 { "orB", { AL
, Ib
}, 0 },
1711 { "orS", { eAX
, Iv
}, 0 },
1712 { X86_64_TABLE (X86_64_0E
) },
1713 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1715 { "adcB", { Ebh1
, Gb
}, 0 },
1716 { "adcS", { Evh1
, Gv
}, 0 },
1717 { "adcB", { Gb
, EbS
}, 0 },
1718 { "adcS", { Gv
, EvS
}, 0 },
1719 { "adcB", { AL
, Ib
}, 0 },
1720 { "adcS", { eAX
, Iv
}, 0 },
1721 { X86_64_TABLE (X86_64_16
) },
1722 { X86_64_TABLE (X86_64_17
) },
1724 { "sbbB", { Ebh1
, Gb
}, 0 },
1725 { "sbbS", { Evh1
, Gv
}, 0 },
1726 { "sbbB", { Gb
, EbS
}, 0 },
1727 { "sbbS", { Gv
, EvS
}, 0 },
1728 { "sbbB", { AL
, Ib
}, 0 },
1729 { "sbbS", { eAX
, Iv
}, 0 },
1730 { X86_64_TABLE (X86_64_1E
) },
1731 { X86_64_TABLE (X86_64_1F
) },
1733 { "andB", { Ebh1
, Gb
}, 0 },
1734 { "andS", { Evh1
, Gv
}, 0 },
1735 { "andB", { Gb
, EbS
}, 0 },
1736 { "andS", { Gv
, EvS
}, 0 },
1737 { "andB", { AL
, Ib
}, 0 },
1738 { "andS", { eAX
, Iv
}, 0 },
1739 { Bad_Opcode
}, /* SEG ES prefix */
1740 { X86_64_TABLE (X86_64_27
) },
1742 { "subB", { Ebh1
, Gb
}, 0 },
1743 { "subS", { Evh1
, Gv
}, 0 },
1744 { "subB", { Gb
, EbS
}, 0 },
1745 { "subS", { Gv
, EvS
}, 0 },
1746 { "subB", { AL
, Ib
}, 0 },
1747 { "subS", { eAX
, Iv
}, 0 },
1748 { Bad_Opcode
}, /* SEG CS prefix */
1749 { X86_64_TABLE (X86_64_2F
) },
1751 { "xorB", { Ebh1
, Gb
}, 0 },
1752 { "xorS", { Evh1
, Gv
}, 0 },
1753 { "xorB", { Gb
, EbS
}, 0 },
1754 { "xorS", { Gv
, EvS
}, 0 },
1755 { "xorB", { AL
, Ib
}, 0 },
1756 { "xorS", { eAX
, Iv
}, 0 },
1757 { Bad_Opcode
}, /* SEG SS prefix */
1758 { X86_64_TABLE (X86_64_37
) },
1760 { "cmpB", { Eb
, Gb
}, 0 },
1761 { "cmpS", { Ev
, Gv
}, 0 },
1762 { "cmpB", { Gb
, EbS
}, 0 },
1763 { "cmpS", { Gv
, EvS
}, 0 },
1764 { "cmpB", { AL
, Ib
}, 0 },
1765 { "cmpS", { eAX
, Iv
}, 0 },
1766 { Bad_Opcode
}, /* SEG DS prefix */
1767 { X86_64_TABLE (X86_64_3F
) },
1769 { "inc{S|}", { RMeAX
}, 0 },
1770 { "inc{S|}", { RMeCX
}, 0 },
1771 { "inc{S|}", { RMeDX
}, 0 },
1772 { "inc{S|}", { RMeBX
}, 0 },
1773 { "inc{S|}", { RMeSP
}, 0 },
1774 { "inc{S|}", { RMeBP
}, 0 },
1775 { "inc{S|}", { RMeSI
}, 0 },
1776 { "inc{S|}", { RMeDI
}, 0 },
1778 { "dec{S|}", { RMeAX
}, 0 },
1779 { "dec{S|}", { RMeCX
}, 0 },
1780 { "dec{S|}", { RMeDX
}, 0 },
1781 { "dec{S|}", { RMeBX
}, 0 },
1782 { "dec{S|}", { RMeSP
}, 0 },
1783 { "dec{S|}", { RMeBP
}, 0 },
1784 { "dec{S|}", { RMeSI
}, 0 },
1785 { "dec{S|}", { RMeDI
}, 0 },
1787 { "push{!P|}", { RMrAX
}, 0 },
1788 { "push{!P|}", { RMrCX
}, 0 },
1789 { "push{!P|}", { RMrDX
}, 0 },
1790 { "push{!P|}", { RMrBX
}, 0 },
1791 { "push{!P|}", { RMrSP
}, 0 },
1792 { "push{!P|}", { RMrBP
}, 0 },
1793 { "push{!P|}", { RMrSI
}, 0 },
1794 { "push{!P|}", { RMrDI
}, 0 },
1796 { "pop{!P|}", { RMrAX
}, 0 },
1797 { "pop{!P|}", { RMrCX
}, 0 },
1798 { "pop{!P|}", { RMrDX
}, 0 },
1799 { "pop{!P|}", { RMrBX
}, 0 },
1800 { "pop{!P|}", { RMrSP
}, 0 },
1801 { "pop{!P|}", { RMrBP
}, 0 },
1802 { "pop{!P|}", { RMrSI
}, 0 },
1803 { "pop{!P|}", { RMrDI
}, 0 },
1805 { X86_64_TABLE (X86_64_60
) },
1806 { X86_64_TABLE (X86_64_61
) },
1807 { X86_64_TABLE (X86_64_62
) },
1808 { X86_64_TABLE (X86_64_63
) },
1809 { Bad_Opcode
}, /* seg fs */
1810 { Bad_Opcode
}, /* seg gs */
1811 { Bad_Opcode
}, /* op size prefix */
1812 { Bad_Opcode
}, /* adr size prefix */
1814 { "pushP", { sIv
}, 0 },
1815 { "imulS", { Gv
, Ev
, Iv
}, 0 },
1816 { "pushP", { sIbT
}, 0 },
1817 { "imulS", { Gv
, Ev
, sIb
}, 0 },
1818 { "ins{b|}", { Ybr
, indirDX
}, 0 },
1819 { X86_64_TABLE (X86_64_6D
) },
1820 { "outs{b|}", { indirDXr
, Xb
}, 0 },
1821 { X86_64_TABLE (X86_64_6F
) },
1823 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
1824 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
1825 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
1826 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1827 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1828 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
1829 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1830 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
1832 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1833 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1834 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1835 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1836 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
1837 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1838 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
1839 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
1841 { REG_TABLE (REG_80
) },
1842 { REG_TABLE (REG_81
) },
1843 { X86_64_TABLE (X86_64_82
) },
1844 { REG_TABLE (REG_83
) },
1845 { "testB", { Eb
, Gb
}, 0 },
1846 { "testS", { Ev
, Gv
}, 0 },
1847 { "xchgB", { Ebh2
, Gb
}, 0 },
1848 { "xchgS", { Evh2
, Gv
}, 0 },
1850 { "movB", { Ebh3
, Gb
}, 0 },
1851 { "movS", { Evh3
, Gv
}, 0 },
1852 { "movB", { Gb
, EbS
}, 0 },
1853 { "movS", { Gv
, EvS
}, 0 },
1854 { "movD", { Sv
, Sw
}, 0 },
1855 { MOD_TABLE (MOD_8D
) },
1856 { "movD", { Sw
, Sv
}, 0 },
1857 { REG_TABLE (REG_8F
) },
1859 { PREFIX_TABLE (PREFIX_90
) },
1860 { "xchgS", { RMeCX
, eAX
}, 0 },
1861 { "xchgS", { RMeDX
, eAX
}, 0 },
1862 { "xchgS", { RMeBX
, eAX
}, 0 },
1863 { "xchgS", { RMeSP
, eAX
}, 0 },
1864 { "xchgS", { RMeBP
, eAX
}, 0 },
1865 { "xchgS", { RMeSI
, eAX
}, 0 },
1866 { "xchgS", { RMeDI
, eAX
}, 0 },
1868 { "cW{t|}R", { XX
}, 0 },
1869 { "cR{t|}O", { XX
}, 0 },
1870 { X86_64_TABLE (X86_64_9A
) },
1871 { Bad_Opcode
}, /* fwait */
1872 { "pushfP", { XX
}, 0 },
1873 { "popfP", { XX
}, 0 },
1874 { "sahf", { XX
}, 0 },
1875 { "lahf", { XX
}, 0 },
1877 { "mov%LB", { AL
, Ob
}, 0 },
1878 { "mov%LS", { eAX
, Ov
}, 0 },
1879 { "mov%LB", { Ob
, AL
}, 0 },
1880 { "mov%LS", { Ov
, eAX
}, 0 },
1881 { "movs{b|}", { Ybr
, Xb
}, 0 },
1882 { "movs{R|}", { Yvr
, Xv
}, 0 },
1883 { "cmps{b|}", { Xb
, Yb
}, 0 },
1884 { "cmps{R|}", { Xv
, Yv
}, 0 },
1886 { "testB", { AL
, Ib
}, 0 },
1887 { "testS", { eAX
, Iv
}, 0 },
1888 { "stosB", { Ybr
, AL
}, 0 },
1889 { "stosS", { Yvr
, eAX
}, 0 },
1890 { "lodsB", { ALr
, Xb
}, 0 },
1891 { "lodsS", { eAXr
, Xv
}, 0 },
1892 { "scasB", { AL
, Yb
}, 0 },
1893 { "scasS", { eAX
, Yv
}, 0 },
1895 { "movB", { RMAL
, Ib
}, 0 },
1896 { "movB", { RMCL
, Ib
}, 0 },
1897 { "movB", { RMDL
, Ib
}, 0 },
1898 { "movB", { RMBL
, Ib
}, 0 },
1899 { "movB", { RMAH
, Ib
}, 0 },
1900 { "movB", { RMCH
, Ib
}, 0 },
1901 { "movB", { RMDH
, Ib
}, 0 },
1902 { "movB", { RMBH
, Ib
}, 0 },
1904 { "mov%LV", { RMeAX
, Iv64
}, 0 },
1905 { "mov%LV", { RMeCX
, Iv64
}, 0 },
1906 { "mov%LV", { RMeDX
, Iv64
}, 0 },
1907 { "mov%LV", { RMeBX
, Iv64
}, 0 },
1908 { "mov%LV", { RMeSP
, Iv64
}, 0 },
1909 { "mov%LV", { RMeBP
, Iv64
}, 0 },
1910 { "mov%LV", { RMeSI
, Iv64
}, 0 },
1911 { "mov%LV", { RMeDI
, Iv64
}, 0 },
1913 { REG_TABLE (REG_C0
) },
1914 { REG_TABLE (REG_C1
) },
1915 { X86_64_TABLE (X86_64_C2
) },
1916 { X86_64_TABLE (X86_64_C3
) },
1917 { X86_64_TABLE (X86_64_C4
) },
1918 { X86_64_TABLE (X86_64_C5
) },
1919 { REG_TABLE (REG_C6
) },
1920 { REG_TABLE (REG_C7
) },
1922 { "enterP", { Iw
, Ib
}, 0 },
1923 { "leaveP", { XX
}, 0 },
1924 { "{l|}ret{|f}%LP", { Iw
}, 0 },
1925 { "{l|}ret{|f}%LP", { XX
}, 0 },
1926 { "int3", { XX
}, 0 },
1927 { "int", { Ib
}, 0 },
1928 { X86_64_TABLE (X86_64_CE
) },
1929 { "iret%LP", { XX
}, 0 },
1931 { REG_TABLE (REG_D0
) },
1932 { REG_TABLE (REG_D1
) },
1933 { REG_TABLE (REG_D2
) },
1934 { REG_TABLE (REG_D3
) },
1935 { X86_64_TABLE (X86_64_D4
) },
1936 { X86_64_TABLE (X86_64_D5
) },
1938 { "xlat", { DSBX
}, 0 },
1949 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1950 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1951 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1952 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1953 { "inB", { AL
, Ib
}, 0 },
1954 { "inG", { zAX
, Ib
}, 0 },
1955 { "outB", { Ib
, AL
}, 0 },
1956 { "outG", { Ib
, zAX
}, 0 },
1958 { X86_64_TABLE (X86_64_E8
) },
1959 { X86_64_TABLE (X86_64_E9
) },
1960 { X86_64_TABLE (X86_64_EA
) },
1961 { "jmp", { Jb
, BND
}, 0 },
1962 { "inB", { AL
, indirDX
}, 0 },
1963 { "inG", { zAX
, indirDX
}, 0 },
1964 { "outB", { indirDX
, AL
}, 0 },
1965 { "outG", { indirDX
, zAX
}, 0 },
1967 { Bad_Opcode
}, /* lock prefix */
1968 { "icebp", { XX
}, 0 },
1969 { Bad_Opcode
}, /* repne */
1970 { Bad_Opcode
}, /* repz */
1971 { "hlt", { XX
}, 0 },
1972 { "cmc", { XX
}, 0 },
1973 { REG_TABLE (REG_F6
) },
1974 { REG_TABLE (REG_F7
) },
1976 { "clc", { XX
}, 0 },
1977 { "stc", { XX
}, 0 },
1978 { "cli", { XX
}, 0 },
1979 { "sti", { XX
}, 0 },
1980 { "cld", { XX
}, 0 },
1981 { "std", { XX
}, 0 },
1982 { REG_TABLE (REG_FE
) },
1983 { REG_TABLE (REG_FF
) },
1986 static const struct dis386 dis386_twobyte
[] = {
1988 { REG_TABLE (REG_0F00
) },
1989 { REG_TABLE (REG_0F01
) },
1990 { "larS", { Gv
, Ew
}, 0 },
1991 { "lslS", { Gv
, Ew
}, 0 },
1993 { "syscall", { XX
}, 0 },
1994 { "clts", { XX
}, 0 },
1995 { "sysret%LQ", { XX
}, 0 },
1997 { "invd", { XX
}, 0 },
1998 { PREFIX_TABLE (PREFIX_0F09
) },
2000 { "ud2", { XX
}, 0 },
2002 { REG_TABLE (REG_0F0D
) },
2003 { "femms", { XX
}, 0 },
2004 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2006 { PREFIX_TABLE (PREFIX_0F10
) },
2007 { PREFIX_TABLE (PREFIX_0F11
) },
2008 { PREFIX_TABLE (PREFIX_0F12
) },
2009 { MOD_TABLE (MOD_0F13
) },
2010 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2011 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2012 { PREFIX_TABLE (PREFIX_0F16
) },
2013 { MOD_TABLE (MOD_0F17
) },
2015 { REG_TABLE (REG_0F18
) },
2016 { "nopQ", { Ev
}, 0 },
2017 { PREFIX_TABLE (PREFIX_0F1A
) },
2018 { PREFIX_TABLE (PREFIX_0F1B
) },
2019 { PREFIX_TABLE (PREFIX_0F1C
) },
2020 { "nopQ", { Ev
}, 0 },
2021 { PREFIX_TABLE (PREFIX_0F1E
) },
2022 { "nopQ", { Ev
}, 0 },
2024 { "movZ", { Em
, Cm
}, 0 },
2025 { "movZ", { Em
, Dm
}, 0 },
2026 { "movZ", { Cm
, Em
}, 0 },
2027 { "movZ", { Dm
, Em
}, 0 },
2028 { X86_64_TABLE (X86_64_0F24
) },
2030 { X86_64_TABLE (X86_64_0F26
) },
2033 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2034 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2035 { PREFIX_TABLE (PREFIX_0F2A
) },
2036 { PREFIX_TABLE (PREFIX_0F2B
) },
2037 { PREFIX_TABLE (PREFIX_0F2C
) },
2038 { PREFIX_TABLE (PREFIX_0F2D
) },
2039 { PREFIX_TABLE (PREFIX_0F2E
) },
2040 { PREFIX_TABLE (PREFIX_0F2F
) },
2042 { "wrmsr", { XX
}, 0 },
2043 { "rdtsc", { XX
}, 0 },
2044 { "rdmsr", { XX
}, 0 },
2045 { "rdpmc", { XX
}, 0 },
2046 { "sysenter", { SEP
}, 0 },
2047 { "sysexit%LQ", { SEP
}, 0 },
2049 { "getsec", { XX
}, 0 },
2051 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2053 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2060 { "cmovoS", { Gv
, Ev
}, 0 },
2061 { "cmovnoS", { Gv
, Ev
}, 0 },
2062 { "cmovbS", { Gv
, Ev
}, 0 },
2063 { "cmovaeS", { Gv
, Ev
}, 0 },
2064 { "cmoveS", { Gv
, Ev
}, 0 },
2065 { "cmovneS", { Gv
, Ev
}, 0 },
2066 { "cmovbeS", { Gv
, Ev
}, 0 },
2067 { "cmovaS", { Gv
, Ev
}, 0 },
2069 { "cmovsS", { Gv
, Ev
}, 0 },
2070 { "cmovnsS", { Gv
, Ev
}, 0 },
2071 { "cmovpS", { Gv
, Ev
}, 0 },
2072 { "cmovnpS", { Gv
, Ev
}, 0 },
2073 { "cmovlS", { Gv
, Ev
}, 0 },
2074 { "cmovgeS", { Gv
, Ev
}, 0 },
2075 { "cmovleS", { Gv
, Ev
}, 0 },
2076 { "cmovgS", { Gv
, Ev
}, 0 },
2078 { MOD_TABLE (MOD_0F50
) },
2079 { PREFIX_TABLE (PREFIX_0F51
) },
2080 { PREFIX_TABLE (PREFIX_0F52
) },
2081 { PREFIX_TABLE (PREFIX_0F53
) },
2082 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2083 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2084 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2085 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2087 { PREFIX_TABLE (PREFIX_0F58
) },
2088 { PREFIX_TABLE (PREFIX_0F59
) },
2089 { PREFIX_TABLE (PREFIX_0F5A
) },
2090 { PREFIX_TABLE (PREFIX_0F5B
) },
2091 { PREFIX_TABLE (PREFIX_0F5C
) },
2092 { PREFIX_TABLE (PREFIX_0F5D
) },
2093 { PREFIX_TABLE (PREFIX_0F5E
) },
2094 { PREFIX_TABLE (PREFIX_0F5F
) },
2096 { PREFIX_TABLE (PREFIX_0F60
) },
2097 { PREFIX_TABLE (PREFIX_0F61
) },
2098 { PREFIX_TABLE (PREFIX_0F62
) },
2099 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2100 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2101 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2102 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2103 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2105 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2106 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2107 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2108 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2109 { "punpcklqdq", { XM
, EXx
}, PREFIX_DATA
},
2110 { "punpckhqdq", { XM
, EXx
}, PREFIX_DATA
},
2111 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2112 { PREFIX_TABLE (PREFIX_0F6F
) },
2114 { PREFIX_TABLE (PREFIX_0F70
) },
2115 { MOD_TABLE (MOD_0F71
) },
2116 { MOD_TABLE (MOD_0F72
) },
2117 { MOD_TABLE (MOD_0F73
) },
2118 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2119 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2120 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2121 { "emms", { XX
}, PREFIX_OPCODE
},
2123 { PREFIX_TABLE (PREFIX_0F78
) },
2124 { PREFIX_TABLE (PREFIX_0F79
) },
2127 { PREFIX_TABLE (PREFIX_0F7C
) },
2128 { PREFIX_TABLE (PREFIX_0F7D
) },
2129 { PREFIX_TABLE (PREFIX_0F7E
) },
2130 { PREFIX_TABLE (PREFIX_0F7F
) },
2132 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2133 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2134 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2135 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2136 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2137 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2138 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2139 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2141 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2142 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2143 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2144 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2145 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2146 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2147 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2148 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2150 { "seto", { Eb
}, 0 },
2151 { "setno", { Eb
}, 0 },
2152 { "setb", { Eb
}, 0 },
2153 { "setae", { Eb
}, 0 },
2154 { "sete", { Eb
}, 0 },
2155 { "setne", { Eb
}, 0 },
2156 { "setbe", { Eb
}, 0 },
2157 { "seta", { Eb
}, 0 },
2159 { "sets", { Eb
}, 0 },
2160 { "setns", { Eb
}, 0 },
2161 { "setp", { Eb
}, 0 },
2162 { "setnp", { Eb
}, 0 },
2163 { "setl", { Eb
}, 0 },
2164 { "setge", { Eb
}, 0 },
2165 { "setle", { Eb
}, 0 },
2166 { "setg", { Eb
}, 0 },
2168 { "pushP", { fs
}, 0 },
2169 { "popP", { fs
}, 0 },
2170 { "cpuid", { XX
}, 0 },
2171 { "btS", { Ev
, Gv
}, 0 },
2172 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2173 { "shldS", { Ev
, Gv
, CL
}, 0 },
2174 { REG_TABLE (REG_0FA6
) },
2175 { REG_TABLE (REG_0FA7
) },
2177 { "pushP", { gs
}, 0 },
2178 { "popP", { gs
}, 0 },
2179 { "rsm", { XX
}, 0 },
2180 { "btsS", { Evh1
, Gv
}, 0 },
2181 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2182 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2183 { REG_TABLE (REG_0FAE
) },
2184 { "imulS", { Gv
, Ev
}, 0 },
2186 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2187 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2188 { MOD_TABLE (MOD_0FB2
) },
2189 { "btrS", { Evh1
, Gv
}, 0 },
2190 { MOD_TABLE (MOD_0FB4
) },
2191 { MOD_TABLE (MOD_0FB5
) },
2192 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2193 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2195 { PREFIX_TABLE (PREFIX_0FB8
) },
2196 { "ud1S", { Gv
, Ev
}, 0 },
2197 { REG_TABLE (REG_0FBA
) },
2198 { "btcS", { Evh1
, Gv
}, 0 },
2199 { PREFIX_TABLE (PREFIX_0FBC
) },
2200 { PREFIX_TABLE (PREFIX_0FBD
) },
2201 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2202 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2204 { "xaddB", { Ebh1
, Gb
}, 0 },
2205 { "xaddS", { Evh1
, Gv
}, 0 },
2206 { PREFIX_TABLE (PREFIX_0FC2
) },
2207 { MOD_TABLE (MOD_0FC3
) },
2208 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2209 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2210 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2211 { REG_TABLE (REG_0FC7
) },
2213 { "bswap", { RMeAX
}, 0 },
2214 { "bswap", { RMeCX
}, 0 },
2215 { "bswap", { RMeDX
}, 0 },
2216 { "bswap", { RMeBX
}, 0 },
2217 { "bswap", { RMeSP
}, 0 },
2218 { "bswap", { RMeBP
}, 0 },
2219 { "bswap", { RMeSI
}, 0 },
2220 { "bswap", { RMeDI
}, 0 },
2222 { PREFIX_TABLE (PREFIX_0FD0
) },
2223 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2224 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2225 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2226 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2227 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2228 { PREFIX_TABLE (PREFIX_0FD6
) },
2229 { MOD_TABLE (MOD_0FD7
) },
2231 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2232 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2233 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2234 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2235 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2236 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2237 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2238 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2240 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2241 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2242 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2243 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2244 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2245 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2246 { PREFIX_TABLE (PREFIX_0FE6
) },
2247 { PREFIX_TABLE (PREFIX_0FE7
) },
2249 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2250 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2251 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2252 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2253 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2254 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2255 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2256 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2258 { PREFIX_TABLE (PREFIX_0FF0
) },
2259 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2260 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2261 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2262 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2263 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2264 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2265 { PREFIX_TABLE (PREFIX_0FF7
) },
2267 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2268 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2269 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2270 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2271 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2272 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2273 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2274 { "ud0S", { Gv
, Ev
}, 0 },
2277 static const unsigned char onebyte_has_modrm
[256] = {
2278 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2279 /* ------------------------------- */
2280 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2281 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2282 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2283 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2284 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2285 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2286 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2287 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2288 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2289 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2290 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2291 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2292 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2293 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2294 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2295 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2296 /* ------------------------------- */
2297 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2300 static const unsigned char twobyte_has_modrm
[256] = {
2301 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2302 /* ------------------------------- */
2303 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2304 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2305 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2306 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2307 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2308 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2309 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2310 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2311 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2312 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2313 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2314 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2315 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2316 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2317 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2318 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2319 /* ------------------------------- */
2320 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2323 static char obuf
[100];
2325 static char *mnemonicendp
;
2326 static char scratchbuf
[100];
2327 static unsigned char *start_codep
;
2328 static unsigned char *insn_codep
;
2329 static unsigned char *codep
;
2330 static unsigned char *end_codep
;
2331 static int last_lock_prefix
;
2332 static int last_repz_prefix
;
2333 static int last_repnz_prefix
;
2334 static int last_data_prefix
;
2335 static int last_addr_prefix
;
2336 static int last_rex_prefix
;
2337 static int last_seg_prefix
;
2338 static int fwait_prefix
;
2339 /* The active segment register prefix. */
2340 static int active_seg_prefix
;
2341 #define MAX_CODE_LENGTH 15
2342 /* We can up to 14 prefixes since the maximum instruction length is
2344 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2345 static disassemble_info
*the_info
;
2353 static unsigned char need_modrm
;
2363 int register_specifier
;
2370 int mask_register_specifier
;
2376 static unsigned char need_vex
;
2384 /* If we are accessing mod/rm/reg without need_modrm set, then the
2385 values are stale. Hitting this abort likely indicates that you
2386 need to update onebyte_has_modrm or twobyte_has_modrm. */
2387 #define MODRM_CHECK if (!need_modrm) abort ()
2389 static const char **names64
;
2390 static const char **names32
;
2391 static const char **names16
;
2392 static const char **names8
;
2393 static const char **names8rex
;
2394 static const char **names_seg
;
2395 static const char *index64
;
2396 static const char *index32
;
2397 static const char **index16
;
2398 static const char **names_bnd
;
2400 static const char *intel_names64
[] = {
2401 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2402 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2404 static const char *intel_names32
[] = {
2405 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2406 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2408 static const char *intel_names16
[] = {
2409 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2410 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2412 static const char *intel_names8
[] = {
2413 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2415 static const char *intel_names8rex
[] = {
2416 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2417 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2419 static const char *intel_names_seg
[] = {
2420 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2422 static const char *intel_index64
= "riz";
2423 static const char *intel_index32
= "eiz";
2424 static const char *intel_index16
[] = {
2425 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2428 static const char *att_names64
[] = {
2429 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2430 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2432 static const char *att_names32
[] = {
2433 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2434 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2436 static const char *att_names16
[] = {
2437 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2438 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2440 static const char *att_names8
[] = {
2441 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2443 static const char *att_names8rex
[] = {
2444 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2445 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2447 static const char *att_names_seg
[] = {
2448 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2450 static const char *att_index64
= "%riz";
2451 static const char *att_index32
= "%eiz";
2452 static const char *att_index16
[] = {
2453 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2456 static const char **names_mm
;
2457 static const char *intel_names_mm
[] = {
2458 "mm0", "mm1", "mm2", "mm3",
2459 "mm4", "mm5", "mm6", "mm7"
2461 static const char *att_names_mm
[] = {
2462 "%mm0", "%mm1", "%mm2", "%mm3",
2463 "%mm4", "%mm5", "%mm6", "%mm7"
2466 static const char *intel_names_bnd
[] = {
2467 "bnd0", "bnd1", "bnd2", "bnd3"
2470 static const char *att_names_bnd
[] = {
2471 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2474 static const char **names_xmm
;
2475 static const char *intel_names_xmm
[] = {
2476 "xmm0", "xmm1", "xmm2", "xmm3",
2477 "xmm4", "xmm5", "xmm6", "xmm7",
2478 "xmm8", "xmm9", "xmm10", "xmm11",
2479 "xmm12", "xmm13", "xmm14", "xmm15",
2480 "xmm16", "xmm17", "xmm18", "xmm19",
2481 "xmm20", "xmm21", "xmm22", "xmm23",
2482 "xmm24", "xmm25", "xmm26", "xmm27",
2483 "xmm28", "xmm29", "xmm30", "xmm31"
2485 static const char *att_names_xmm
[] = {
2486 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2487 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2488 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2489 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2490 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2491 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2492 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2493 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2496 static const char **names_ymm
;
2497 static const char *intel_names_ymm
[] = {
2498 "ymm0", "ymm1", "ymm2", "ymm3",
2499 "ymm4", "ymm5", "ymm6", "ymm7",
2500 "ymm8", "ymm9", "ymm10", "ymm11",
2501 "ymm12", "ymm13", "ymm14", "ymm15",
2502 "ymm16", "ymm17", "ymm18", "ymm19",
2503 "ymm20", "ymm21", "ymm22", "ymm23",
2504 "ymm24", "ymm25", "ymm26", "ymm27",
2505 "ymm28", "ymm29", "ymm30", "ymm31"
2507 static const char *att_names_ymm
[] = {
2508 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2509 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2510 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2511 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2512 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2513 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2514 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2515 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2518 static const char **names_zmm
;
2519 static const char *intel_names_zmm
[] = {
2520 "zmm0", "zmm1", "zmm2", "zmm3",
2521 "zmm4", "zmm5", "zmm6", "zmm7",
2522 "zmm8", "zmm9", "zmm10", "zmm11",
2523 "zmm12", "zmm13", "zmm14", "zmm15",
2524 "zmm16", "zmm17", "zmm18", "zmm19",
2525 "zmm20", "zmm21", "zmm22", "zmm23",
2526 "zmm24", "zmm25", "zmm26", "zmm27",
2527 "zmm28", "zmm29", "zmm30", "zmm31"
2529 static const char *att_names_zmm
[] = {
2530 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2531 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2532 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2533 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2534 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2535 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2536 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2537 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2540 static const char **names_tmm
;
2541 static const char *intel_names_tmm
[] = {
2542 "tmm0", "tmm1", "tmm2", "tmm3",
2543 "tmm4", "tmm5", "tmm6", "tmm7"
2545 static const char *att_names_tmm
[] = {
2546 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2547 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2550 static const char **names_mask
;
2551 static const char *intel_names_mask
[] = {
2552 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2554 static const char *att_names_mask
[] = {
2555 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2558 static const char *names_rounding
[] =
2566 static const struct dis386 reg_table
[][8] = {
2569 { "addA", { Ebh1
, Ib
}, 0 },
2570 { "orA", { Ebh1
, Ib
}, 0 },
2571 { "adcA", { Ebh1
, Ib
}, 0 },
2572 { "sbbA", { Ebh1
, Ib
}, 0 },
2573 { "andA", { Ebh1
, Ib
}, 0 },
2574 { "subA", { Ebh1
, Ib
}, 0 },
2575 { "xorA", { Ebh1
, Ib
}, 0 },
2576 { "cmpA", { Eb
, Ib
}, 0 },
2580 { "addQ", { Evh1
, Iv
}, 0 },
2581 { "orQ", { Evh1
, Iv
}, 0 },
2582 { "adcQ", { Evh1
, Iv
}, 0 },
2583 { "sbbQ", { Evh1
, Iv
}, 0 },
2584 { "andQ", { Evh1
, Iv
}, 0 },
2585 { "subQ", { Evh1
, Iv
}, 0 },
2586 { "xorQ", { Evh1
, Iv
}, 0 },
2587 { "cmpQ", { Ev
, Iv
}, 0 },
2591 { "addQ", { Evh1
, sIb
}, 0 },
2592 { "orQ", { Evh1
, sIb
}, 0 },
2593 { "adcQ", { Evh1
, sIb
}, 0 },
2594 { "sbbQ", { Evh1
, sIb
}, 0 },
2595 { "andQ", { Evh1
, sIb
}, 0 },
2596 { "subQ", { Evh1
, sIb
}, 0 },
2597 { "xorQ", { Evh1
, sIb
}, 0 },
2598 { "cmpQ", { Ev
, sIb
}, 0 },
2602 { "pop{P|}", { stackEv
}, 0 },
2603 { XOP_8F_TABLE (XOP_09
) },
2607 { XOP_8F_TABLE (XOP_09
) },
2611 { "rolA", { Eb
, Ib
}, 0 },
2612 { "rorA", { Eb
, Ib
}, 0 },
2613 { "rclA", { Eb
, Ib
}, 0 },
2614 { "rcrA", { Eb
, Ib
}, 0 },
2615 { "shlA", { Eb
, Ib
}, 0 },
2616 { "shrA", { Eb
, Ib
}, 0 },
2617 { "shlA", { Eb
, Ib
}, 0 },
2618 { "sarA", { Eb
, Ib
}, 0 },
2622 { "rolQ", { Ev
, Ib
}, 0 },
2623 { "rorQ", { Ev
, Ib
}, 0 },
2624 { "rclQ", { Ev
, Ib
}, 0 },
2625 { "rcrQ", { Ev
, Ib
}, 0 },
2626 { "shlQ", { Ev
, Ib
}, 0 },
2627 { "shrQ", { Ev
, Ib
}, 0 },
2628 { "shlQ", { Ev
, Ib
}, 0 },
2629 { "sarQ", { Ev
, Ib
}, 0 },
2633 { "movA", { Ebh3
, Ib
}, 0 },
2640 { MOD_TABLE (MOD_C6_REG_7
) },
2644 { "movQ", { Evh3
, Iv
}, 0 },
2651 { MOD_TABLE (MOD_C7_REG_7
) },
2655 { "rolA", { Eb
, I1
}, 0 },
2656 { "rorA", { Eb
, I1
}, 0 },
2657 { "rclA", { Eb
, I1
}, 0 },
2658 { "rcrA", { Eb
, I1
}, 0 },
2659 { "shlA", { Eb
, I1
}, 0 },
2660 { "shrA", { Eb
, I1
}, 0 },
2661 { "shlA", { Eb
, I1
}, 0 },
2662 { "sarA", { Eb
, I1
}, 0 },
2666 { "rolQ", { Ev
, I1
}, 0 },
2667 { "rorQ", { Ev
, I1
}, 0 },
2668 { "rclQ", { Ev
, I1
}, 0 },
2669 { "rcrQ", { Ev
, I1
}, 0 },
2670 { "shlQ", { Ev
, I1
}, 0 },
2671 { "shrQ", { Ev
, I1
}, 0 },
2672 { "shlQ", { Ev
, I1
}, 0 },
2673 { "sarQ", { Ev
, I1
}, 0 },
2677 { "rolA", { Eb
, CL
}, 0 },
2678 { "rorA", { Eb
, CL
}, 0 },
2679 { "rclA", { Eb
, CL
}, 0 },
2680 { "rcrA", { Eb
, CL
}, 0 },
2681 { "shlA", { Eb
, CL
}, 0 },
2682 { "shrA", { Eb
, CL
}, 0 },
2683 { "shlA", { Eb
, CL
}, 0 },
2684 { "sarA", { Eb
, CL
}, 0 },
2688 { "rolQ", { Ev
, CL
}, 0 },
2689 { "rorQ", { Ev
, CL
}, 0 },
2690 { "rclQ", { Ev
, CL
}, 0 },
2691 { "rcrQ", { Ev
, CL
}, 0 },
2692 { "shlQ", { Ev
, CL
}, 0 },
2693 { "shrQ", { Ev
, CL
}, 0 },
2694 { "shlQ", { Ev
, CL
}, 0 },
2695 { "sarQ", { Ev
, CL
}, 0 },
2699 { "testA", { Eb
, Ib
}, 0 },
2700 { "testA", { Eb
, Ib
}, 0 },
2701 { "notA", { Ebh1
}, 0 },
2702 { "negA", { Ebh1
}, 0 },
2703 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
2704 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
2705 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
2706 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
2710 { "testQ", { Ev
, Iv
}, 0 },
2711 { "testQ", { Ev
, Iv
}, 0 },
2712 { "notQ", { Evh1
}, 0 },
2713 { "negQ", { Evh1
}, 0 },
2714 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
2715 { "imulQ", { Ev
}, 0 },
2716 { "divQ", { Ev
}, 0 },
2717 { "idivQ", { Ev
}, 0 },
2721 { "incA", { Ebh1
}, 0 },
2722 { "decA", { Ebh1
}, 0 },
2726 { "incQ", { Evh1
}, 0 },
2727 { "decQ", { Evh1
}, 0 },
2728 { "call{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2729 { MOD_TABLE (MOD_FF_REG_3
) },
2730 { "jmp{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2731 { MOD_TABLE (MOD_FF_REG_5
) },
2732 { "push{P|}", { stackEv
}, 0 },
2737 { "sldtD", { Sv
}, 0 },
2738 { "strD", { Sv
}, 0 },
2739 { "lldt", { Ew
}, 0 },
2740 { "ltr", { Ew
}, 0 },
2741 { "verr", { Ew
}, 0 },
2742 { "verw", { Ew
}, 0 },
2748 { MOD_TABLE (MOD_0F01_REG_0
) },
2749 { MOD_TABLE (MOD_0F01_REG_1
) },
2750 { MOD_TABLE (MOD_0F01_REG_2
) },
2751 { MOD_TABLE (MOD_0F01_REG_3
) },
2752 { "smswD", { Sv
}, 0 },
2753 { MOD_TABLE (MOD_0F01_REG_5
) },
2754 { "lmsw", { Ew
}, 0 },
2755 { MOD_TABLE (MOD_0F01_REG_7
) },
2759 { "prefetch", { Mb
}, 0 },
2760 { "prefetchw", { Mb
}, 0 },
2761 { "prefetchwt1", { Mb
}, 0 },
2762 { "prefetch", { Mb
}, 0 },
2763 { "prefetch", { Mb
}, 0 },
2764 { "prefetch", { Mb
}, 0 },
2765 { "prefetch", { Mb
}, 0 },
2766 { "prefetch", { Mb
}, 0 },
2770 { MOD_TABLE (MOD_0F18_REG_0
) },
2771 { MOD_TABLE (MOD_0F18_REG_1
) },
2772 { MOD_TABLE (MOD_0F18_REG_2
) },
2773 { MOD_TABLE (MOD_0F18_REG_3
) },
2774 { "nopQ", { Ev
}, 0 },
2775 { "nopQ", { Ev
}, 0 },
2776 { "nopQ", { Ev
}, 0 },
2777 { "nopQ", { Ev
}, 0 },
2779 /* REG_0F1C_P_0_MOD_0 */
2781 { "cldemote", { Mb
}, 0 },
2782 { "nopQ", { Ev
}, 0 },
2783 { "nopQ", { Ev
}, 0 },
2784 { "nopQ", { Ev
}, 0 },
2785 { "nopQ", { Ev
}, 0 },
2786 { "nopQ", { Ev
}, 0 },
2787 { "nopQ", { Ev
}, 0 },
2788 { "nopQ", { Ev
}, 0 },
2790 /* REG_0F1E_P_1_MOD_3 */
2792 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2793 { "rdsspK", { Edq
}, 0 },
2794 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2795 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2796 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2797 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2798 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2799 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
2801 /* REG_0F38D8_PREFIX_1 */
2803 { "aesencwide128kl", { M
}, 0 },
2804 { "aesdecwide128kl", { M
}, 0 },
2805 { "aesencwide256kl", { M
}, 0 },
2806 { "aesdecwide256kl", { M
}, 0 },
2808 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2810 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0
) },
2812 /* REG_0F71_MOD_0 */
2816 { "psrlw", { MS
, Ib
}, PREFIX_OPCODE
},
2818 { "psraw", { MS
, Ib
}, PREFIX_OPCODE
},
2820 { "psllw", { MS
, Ib
}, PREFIX_OPCODE
},
2822 /* REG_0F72_MOD_0 */
2826 { "psrld", { MS
, Ib
}, PREFIX_OPCODE
},
2828 { "psrad", { MS
, Ib
}, PREFIX_OPCODE
},
2830 { "pslld", { MS
, Ib
}, PREFIX_OPCODE
},
2832 /* REG_0F73_MOD_0 */
2836 { "psrlq", { MS
, Ib
}, PREFIX_OPCODE
},
2837 { "psrldq", { XS
, Ib
}, PREFIX_DATA
},
2840 { "psllq", { MS
, Ib
}, PREFIX_OPCODE
},
2841 { "pslldq", { XS
, Ib
}, PREFIX_DATA
},
2845 { "montmul", { { OP_0f07
, 0 } }, 0 },
2846 { "xsha1", { { OP_0f07
, 0 } }, 0 },
2847 { "xsha256", { { OP_0f07
, 0 } }, 0 },
2851 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
2852 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
2853 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
2854 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
2855 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
2856 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
2860 { MOD_TABLE (MOD_0FAE_REG_0
) },
2861 { MOD_TABLE (MOD_0FAE_REG_1
) },
2862 { MOD_TABLE (MOD_0FAE_REG_2
) },
2863 { MOD_TABLE (MOD_0FAE_REG_3
) },
2864 { MOD_TABLE (MOD_0FAE_REG_4
) },
2865 { MOD_TABLE (MOD_0FAE_REG_5
) },
2866 { MOD_TABLE (MOD_0FAE_REG_6
) },
2867 { MOD_TABLE (MOD_0FAE_REG_7
) },
2875 { "btQ", { Ev
, Ib
}, 0 },
2876 { "btsQ", { Evh1
, Ib
}, 0 },
2877 { "btrQ", { Evh1
, Ib
}, 0 },
2878 { "btcQ", { Evh1
, Ib
}, 0 },
2883 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
2885 { MOD_TABLE (MOD_0FC7_REG_3
) },
2886 { MOD_TABLE (MOD_0FC7_REG_4
) },
2887 { MOD_TABLE (MOD_0FC7_REG_5
) },
2888 { MOD_TABLE (MOD_0FC7_REG_6
) },
2889 { MOD_TABLE (MOD_0FC7_REG_7
) },
2891 /* REG_VEX_0F71_M_0 */
2895 { "vpsrlw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2897 { "vpsraw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2899 { "vpsllw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2901 /* REG_VEX_0F72_M_0 */
2905 { "vpsrld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2907 { "vpsrad", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2909 { "vpslld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2911 /* REG_VEX_0F73_M_0 */
2915 { "vpsrlq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2916 { "vpsrldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2919 { "vpsllq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2920 { "vpslldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2926 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
2927 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
2929 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2931 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
2933 /* REG_VEX_0F38F3_L_0 */
2936 { "blsrS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2937 { "blsmskS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2938 { "blsiS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2940 /* REG_XOP_09_01_L_0 */
2943 { "blcfill", { VexGdq
, Edq
}, 0 },
2944 { "blsfill", { VexGdq
, Edq
}, 0 },
2945 { "blcs", { VexGdq
, Edq
}, 0 },
2946 { "tzmsk", { VexGdq
, Edq
}, 0 },
2947 { "blcic", { VexGdq
, Edq
}, 0 },
2948 { "blsic", { VexGdq
, Edq
}, 0 },
2949 { "t1mskc", { VexGdq
, Edq
}, 0 },
2951 /* REG_XOP_09_02_L_0 */
2954 { "blcmsk", { VexGdq
, Edq
}, 0 },
2959 { "blci", { VexGdq
, Edq
}, 0 },
2961 /* REG_XOP_09_12_M_1_L_0 */
2963 { "llwpcb", { Edq
}, 0 },
2964 { "slwpcb", { Edq
}, 0 },
2966 /* REG_XOP_0A_12_L_0 */
2968 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
2969 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
2972 #include "i386-dis-evex-reg.h"
2975 static const struct dis386 prefix_table
[][4] = {
2978 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
2979 { "pause", { XX
}, 0 },
2980 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
2981 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
2984 /* PREFIX_0F01_REG_1_RM_4 */
2988 { "tdcall", { Skip_MODRM
}, 0 },
2992 /* PREFIX_0F01_REG_1_RM_5 */
2996 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2
) },
3000 /* PREFIX_0F01_REG_1_RM_6 */
3004 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2
) },
3008 /* PREFIX_0F01_REG_1_RM_7 */
3010 { "encls", { Skip_MODRM
}, 0 },
3012 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2
) },
3016 /* PREFIX_0F01_REG_3_RM_1 */
3018 { "vmmcall", { Skip_MODRM
}, 0 },
3019 { "vmgexit", { Skip_MODRM
}, 0 },
3021 { "vmgexit", { Skip_MODRM
}, 0 },
3024 /* PREFIX_0F01_REG_5_MOD_0 */
3027 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3030 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3032 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3033 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3035 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3038 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3043 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3046 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3049 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3052 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3055 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
) },
3058 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3061 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
) },
3064 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3066 { "rdpkru", { Skip_MODRM
}, 0 },
3067 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
) },
3070 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3072 { "wrpkru", { Skip_MODRM
}, 0 },
3073 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
) },
3076 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3078 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3079 { "mcommit", { Skip_MODRM
}, 0 },
3082 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3084 { "invlpgb", { Skip_MODRM
}, 0 },
3085 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
) },
3087 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
) },
3090 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3092 { "tlbsync", { Skip_MODRM
}, 0 },
3093 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
) },
3095 { "pvalidate", { Skip_MODRM
}, 0 },
3100 { "wbinvd", { XX
}, 0 },
3101 { "wbnoinvd", { XX
}, 0 },
3106 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3107 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3108 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3109 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3114 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3115 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3116 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3117 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3122 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3123 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3124 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3125 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3130 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3131 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3132 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3137 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3138 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3139 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3140 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3145 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3146 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3147 { "bndmov", { EbndS
, Gbnd
}, 0 },
3148 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3153 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3154 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3155 { "nopQ", { Ev
}, 0 },
3156 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3161 { "nopQ", { Ev
}, 0 },
3162 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3163 { "nopQ", { Ev
}, 0 },
3164 { NULL
, { XX
}, PREFIX_IGNORED
},
3169 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3170 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3171 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3172 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3177 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3178 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3179 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3180 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3185 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3186 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3187 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3188 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3193 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3194 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3195 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3196 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3201 { "ucomiss",{ XM
, EXd
}, 0 },
3203 { "ucomisd",{ XM
, EXq
}, 0 },
3208 { "comiss", { XM
, EXd
}, 0 },
3210 { "comisd", { XM
, EXq
}, 0 },
3215 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3216 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3217 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3218 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3223 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3224 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3229 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3230 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3235 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3236 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3237 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3238 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3243 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3244 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3245 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3246 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3251 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3252 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3253 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3254 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3259 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3260 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3261 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3266 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3267 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3268 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3269 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3274 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3275 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3276 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3277 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3282 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3283 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3284 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3285 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3290 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3291 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3292 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3293 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3298 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3300 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3305 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3307 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3312 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3314 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3319 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3320 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3321 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3326 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3327 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3328 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3329 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3334 {"vmread", { Em
, Gm
}, 0 },
3336 {"extrq", { XS
, Ib
, Ib
}, 0 },
3337 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3342 {"vmwrite", { Gm
, Em
}, 0 },
3344 {"extrq", { XM
, XS
}, 0 },
3345 {"insertq", { XM
, XS
}, 0 },
3352 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3353 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3360 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3361 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3366 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3367 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3368 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3373 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3374 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3375 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3378 /* PREFIX_0FAE_REG_0_MOD_3 */
3381 { "rdfsbase", { Ev
}, 0 },
3384 /* PREFIX_0FAE_REG_1_MOD_3 */
3387 { "rdgsbase", { Ev
}, 0 },
3390 /* PREFIX_0FAE_REG_2_MOD_3 */
3393 { "wrfsbase", { Ev
}, 0 },
3396 /* PREFIX_0FAE_REG_3_MOD_3 */
3399 { "wrgsbase", { Ev
}, 0 },
3402 /* PREFIX_0FAE_REG_4_MOD_0 */
3404 { "xsave", { FXSAVE
}, 0 },
3405 { "ptwrite{%LQ|}", { Edq
}, 0 },
3408 /* PREFIX_0FAE_REG_4_MOD_3 */
3411 { "ptwrite{%LQ|}", { Edq
}, 0 },
3414 /* PREFIX_0FAE_REG_5_MOD_3 */
3416 { "lfence", { Skip_MODRM
}, 0 },
3417 { "incsspK", { Edq
}, PREFIX_OPCODE
},
3420 /* PREFIX_0FAE_REG_6_MOD_0 */
3422 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3423 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3424 { "clwb", { Mb
}, PREFIX_OPCODE
},
3427 /* PREFIX_0FAE_REG_6_MOD_3 */
3429 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3430 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3431 { "tpause", { Edq
}, PREFIX_OPCODE
},
3432 { "umwait", { Edq
}, PREFIX_OPCODE
},
3435 /* PREFIX_0FAE_REG_7_MOD_0 */
3437 { "clflush", { Mb
}, 0 },
3439 { "clflushopt", { Mb
}, 0 },
3445 { "popcntS", { Gv
, Ev
}, 0 },
3450 { "bsfS", { Gv
, Ev
}, 0 },
3451 { "tzcntS", { Gv
, Ev
}, 0 },
3452 { "bsfS", { Gv
, Ev
}, 0 },
3457 { "bsrS", { Gv
, Ev
}, 0 },
3458 { "lzcntS", { Gv
, Ev
}, 0 },
3459 { "bsrS", { Gv
, Ev
}, 0 },
3464 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3465 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3466 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3467 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3470 /* PREFIX_0FC7_REG_6_MOD_0 */
3472 { "vmptrld",{ Mq
}, 0 },
3473 { "vmxon", { Mq
}, 0 },
3474 { "vmclear",{ Mq
}, 0 },
3477 /* PREFIX_0FC7_REG_6_MOD_3 */
3479 { "rdrand", { Ev
}, 0 },
3480 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1
) },
3481 { "rdrand", { Ev
}, 0 }
3484 /* PREFIX_0FC7_REG_7_MOD_3 */
3486 { "rdseed", { Ev
}, 0 },
3487 { "rdpid", { Em
}, 0 },
3488 { "rdseed", { Ev
}, 0 },
3495 { "addsubpd", { XM
, EXx
}, 0 },
3496 { "addsubps", { XM
, EXx
}, 0 },
3502 { "movq2dq",{ XM
, MS
}, 0 },
3503 { "movq", { EXqS
, XM
}, 0 },
3504 { "movdq2q",{ MX
, XS
}, 0 },
3510 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3511 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3512 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3517 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3519 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3527 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3532 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3534 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
3540 { REG_TABLE (REG_0F38D8_PREFIX_1
) },
3546 { MOD_TABLE (MOD_0F38DC_PREFIX_1
) },
3547 { "aesenc", { XM
, EXx
}, 0 },
3553 { MOD_TABLE (MOD_0F38DD_PREFIX_1
) },
3554 { "aesenclast", { XM
, EXx
}, 0 },
3560 { MOD_TABLE (MOD_0F38DE_PREFIX_1
) },
3561 { "aesdec", { XM
, EXx
}, 0 },
3567 { MOD_TABLE (MOD_0F38DF_PREFIX_1
) },
3568 { "aesdeclast", { XM
, EXx
}, 0 },
3573 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3575 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3576 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
3581 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3583 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3584 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
3589 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
3590 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3591 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3598 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
3599 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
3600 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
3605 { MOD_TABLE (MOD_0F38FA_PREFIX_1
) },
3611 { MOD_TABLE (MOD_0F38FB_PREFIX_1
) },
3617 { MOD_TABLE (MOD_0F3A0F_PREFIX_1
)},
3620 /* PREFIX_VEX_0F10 */
3622 { "vmovups", { XM
, EXx
}, 0 },
3623 { "vmovss", { XMScalar
, VexScalarR
, EXxmm_md
}, 0 },
3624 { "vmovupd", { XM
, EXx
}, 0 },
3625 { "vmovsd", { XMScalar
, VexScalarR
, EXxmm_mq
}, 0 },
3628 /* PREFIX_VEX_0F11 */
3630 { "vmovups", { EXxS
, XM
}, 0 },
3631 { "vmovss", { EXdS
, VexScalarR
, XMScalar
}, 0 },
3632 { "vmovupd", { EXxS
, XM
}, 0 },
3633 { "vmovsd", { EXqS
, VexScalarR
, XMScalar
}, 0 },
3636 /* PREFIX_VEX_0F12 */
3638 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3639 { "vmovsldup", { XM
, EXx
}, 0 },
3640 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
3641 { "vmovddup", { XM
, EXymmq
}, 0 },
3644 /* PREFIX_VEX_0F16 */
3646 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3647 { "vmovshdup", { XM
, EXx
}, 0 },
3648 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
3651 /* PREFIX_VEX_0F2A */
3654 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3656 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3659 /* PREFIX_VEX_0F2C */
3662 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
3664 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
3667 /* PREFIX_VEX_0F2D */
3670 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
3672 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
3675 /* PREFIX_VEX_0F2E */
3677 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3679 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3682 /* PREFIX_VEX_0F2F */
3684 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3686 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3689 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3691 { "kandw", { MaskG
, MaskVex
, MaskE
}, 0 },
3693 { "kandb", { MaskG
, MaskVex
, MaskE
}, 0 },
3696 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3698 { "kandq", { MaskG
, MaskVex
, MaskE
}, 0 },
3700 { "kandd", { MaskG
, MaskVex
, MaskE
}, 0 },
3703 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3705 { "kandnw", { MaskG
, MaskVex
, MaskE
}, 0 },
3707 { "kandnb", { MaskG
, MaskVex
, MaskE
}, 0 },
3710 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3712 { "kandnq", { MaskG
, MaskVex
, MaskE
}, 0 },
3714 { "kandnd", { MaskG
, MaskVex
, MaskE
}, 0 },
3717 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3719 { "knotw", { MaskG
, MaskE
}, 0 },
3721 { "knotb", { MaskG
, MaskE
}, 0 },
3724 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3726 { "knotq", { MaskG
, MaskE
}, 0 },
3728 { "knotd", { MaskG
, MaskE
}, 0 },
3731 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3733 { "korw", { MaskG
, MaskVex
, MaskE
}, 0 },
3735 { "korb", { MaskG
, MaskVex
, MaskE
}, 0 },
3738 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3740 { "korq", { MaskG
, MaskVex
, MaskE
}, 0 },
3742 { "kord", { MaskG
, MaskVex
, MaskE
}, 0 },
3745 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3747 { "kxnorw", { MaskG
, MaskVex
, MaskE
}, 0 },
3749 { "kxnorb", { MaskG
, MaskVex
, MaskE
}, 0 },
3752 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3754 { "kxnorq", { MaskG
, MaskVex
, MaskE
}, 0 },
3756 { "kxnord", { MaskG
, MaskVex
, MaskE
}, 0 },
3759 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3761 { "kxorw", { MaskG
, MaskVex
, MaskE
}, 0 },
3763 { "kxorb", { MaskG
, MaskVex
, MaskE
}, 0 },
3766 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3768 { "kxorq", { MaskG
, MaskVex
, MaskE
}, 0 },
3770 { "kxord", { MaskG
, MaskVex
, MaskE
}, 0 },
3773 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3775 { "kaddw", { MaskG
, MaskVex
, MaskE
}, 0 },
3777 { "kaddb", { MaskG
, MaskVex
, MaskE
}, 0 },
3780 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3782 { "kaddq", { MaskG
, MaskVex
, MaskE
}, 0 },
3784 { "kaddd", { MaskG
, MaskVex
, MaskE
}, 0 },
3787 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3789 { "kunpckwd", { MaskG
, MaskVex
, MaskE
}, 0 },
3791 { "kunpckbw", { MaskG
, MaskVex
, MaskE
}, 0 },
3794 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3796 { "kunpckdq", { MaskG
, MaskVex
, MaskE
}, 0 },
3799 /* PREFIX_VEX_0F51 */
3801 { "vsqrtps", { XM
, EXx
}, 0 },
3802 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3803 { "vsqrtpd", { XM
, EXx
}, 0 },
3804 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3807 /* PREFIX_VEX_0F52 */
3809 { "vrsqrtps", { XM
, EXx
}, 0 },
3810 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3813 /* PREFIX_VEX_0F53 */
3815 { "vrcpps", { XM
, EXx
}, 0 },
3816 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3819 /* PREFIX_VEX_0F58 */
3821 { "vaddps", { XM
, Vex
, EXx
}, 0 },
3822 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3823 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
3824 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3827 /* PREFIX_VEX_0F59 */
3829 { "vmulps", { XM
, Vex
, EXx
}, 0 },
3830 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3831 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
3832 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3835 /* PREFIX_VEX_0F5A */
3837 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
3838 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3839 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
3840 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3843 /* PREFIX_VEX_0F5B */
3845 { "vcvtdq2ps", { XM
, EXx
}, 0 },
3846 { "vcvttps2dq", { XM
, EXx
}, 0 },
3847 { "vcvtps2dq", { XM
, EXx
}, 0 },
3850 /* PREFIX_VEX_0F5C */
3852 { "vsubps", { XM
, Vex
, EXx
}, 0 },
3853 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3854 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
3855 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3858 /* PREFIX_VEX_0F5D */
3860 { "vminps", { XM
, Vex
, EXx
}, 0 },
3861 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3862 { "vminpd", { XM
, Vex
, EXx
}, 0 },
3863 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3866 /* PREFIX_VEX_0F5E */
3868 { "vdivps", { XM
, Vex
, EXx
}, 0 },
3869 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3870 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
3871 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3874 /* PREFIX_VEX_0F5F */
3876 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
3877 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3878 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
3879 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3882 /* PREFIX_VEX_0F6F */
3885 { "vmovdqu", { XM
, EXx
}, 0 },
3886 { "vmovdqa", { XM
, EXx
}, 0 },
3889 /* PREFIX_VEX_0F70 */
3892 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
3893 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
3894 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
3897 /* PREFIX_VEX_0F7C */
3901 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
3902 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
3905 /* PREFIX_VEX_0F7D */
3909 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
3910 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
3913 /* PREFIX_VEX_0F7E */
3916 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3917 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3920 /* PREFIX_VEX_0F7F */
3923 { "vmovdqu", { EXxS
, XM
}, 0 },
3924 { "vmovdqa", { EXxS
, XM
}, 0 },
3927 /* PREFIX_VEX_0F90_L_0_W_0 */
3929 { "kmovw", { MaskG
, MaskE
}, 0 },
3931 { "kmovb", { MaskG
, MaskBDE
}, 0 },
3934 /* PREFIX_VEX_0F90_L_0_W_1 */
3936 { "kmovq", { MaskG
, MaskE
}, 0 },
3938 { "kmovd", { MaskG
, MaskBDE
}, 0 },
3941 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3943 { "kmovw", { Ew
, MaskG
}, 0 },
3945 { "kmovb", { Eb
, MaskG
}, 0 },
3948 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3950 { "kmovq", { Eq
, MaskG
}, 0 },
3952 { "kmovd", { Ed
, MaskG
}, 0 },
3955 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3957 { "kmovw", { MaskG
, Edq
}, 0 },
3959 { "kmovb", { MaskG
, Edq
}, 0 },
3960 { "kmovd", { MaskG
, Edq
}, 0 },
3963 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3968 { "kmovK", { MaskG
, Edq
}, 0 },
3971 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3973 { "kmovw", { Gdq
, MaskE
}, 0 },
3975 { "kmovb", { Gdq
, MaskE
}, 0 },
3976 { "kmovd", { Gdq
, MaskE
}, 0 },
3979 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3984 { "kmovK", { Gdq
, MaskE
}, 0 },
3987 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3989 { "kortestw", { MaskG
, MaskE
}, 0 },
3991 { "kortestb", { MaskG
, MaskE
}, 0 },
3994 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3996 { "kortestq", { MaskG
, MaskE
}, 0 },
3998 { "kortestd", { MaskG
, MaskE
}, 0 },
4001 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4003 { "ktestw", { MaskG
, MaskE
}, 0 },
4005 { "ktestb", { MaskG
, MaskE
}, 0 },
4008 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4010 { "ktestq", { MaskG
, MaskE
}, 0 },
4012 { "ktestd", { MaskG
, MaskE
}, 0 },
4015 /* PREFIX_VEX_0FC2 */
4017 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
4018 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, CMP
}, 0 },
4019 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
4020 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, CMP
}, 0 },
4023 /* PREFIX_VEX_0FD0 */
4027 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
4028 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
4031 /* PREFIX_VEX_0FE6 */
4034 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
4035 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
4036 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
4039 /* PREFIX_VEX_0FF0 */
4044 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4047 /* PREFIX_VEX_0F3849_X86_64 */
4049 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
4051 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
4052 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
4055 /* PREFIX_VEX_0F384B_X86_64 */
4058 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
4059 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
4060 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
4063 /* PREFIX_VEX_0F385C_X86_64 */
4066 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
4070 /* PREFIX_VEX_0F385E_X86_64 */
4072 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
4073 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
4074 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
4075 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
4078 /* PREFIX_VEX_0F38F5_L_0 */
4080 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
4081 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
4083 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
4086 /* PREFIX_VEX_0F38F6_L_0 */
4091 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
4094 /* PREFIX_VEX_0F38F7_L_0 */
4096 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
4097 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
4098 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
4099 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
4102 /* PREFIX_VEX_0F3AF0_L_0 */
4107 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
4110 #include "i386-dis-evex-prefix.h"
4113 static const struct dis386 x86_64_table
[][2] = {
4116 { "pushP", { es
}, 0 },
4121 { "popP", { es
}, 0 },
4126 { "pushP", { cs
}, 0 },
4131 { "pushP", { ss
}, 0 },
4136 { "popP", { ss
}, 0 },
4141 { "pushP", { ds
}, 0 },
4146 { "popP", { ds
}, 0 },
4151 { "daa", { XX
}, 0 },
4156 { "das", { XX
}, 0 },
4161 { "aaa", { XX
}, 0 },
4166 { "aas", { XX
}, 0 },
4171 { "pushaP", { XX
}, 0 },
4176 { "popaP", { XX
}, 0 },
4181 { MOD_TABLE (MOD_62_32BIT
) },
4182 { EVEX_TABLE (EVEX_0F
) },
4187 { "arpl", { Ew
, Gw
}, 0 },
4188 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
4193 { "ins{R|}", { Yzr
, indirDX
}, 0 },
4194 { "ins{G|}", { Yzr
, indirDX
}, 0 },
4199 { "outs{R|}", { indirDXr
, Xz
}, 0 },
4200 { "outs{G|}", { indirDXr
, Xz
}, 0 },
4205 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4206 { REG_TABLE (REG_80
) },
4211 { "{l|}call{P|}", { Ap
}, 0 },
4216 { "retP", { Iw
, BND
}, 0 },
4217 { "ret@", { Iw
, BND
}, 0 },
4222 { "retP", { BND
}, 0 },
4223 { "ret@", { BND
}, 0 },
4228 { MOD_TABLE (MOD_C4_32BIT
) },
4229 { VEX_C4_TABLE (VEX_0F
) },
4234 { MOD_TABLE (MOD_C5_32BIT
) },
4235 { VEX_C5_TABLE (VEX_0F
) },
4240 { "into", { XX
}, 0 },
4245 { "aam", { Ib
}, 0 },
4250 { "aad", { Ib
}, 0 },
4255 { "callP", { Jv
, BND
}, 0 },
4256 { "call@", { Jv
, BND
}, 0 }
4261 { "jmpP", { Jv
, BND
}, 0 },
4262 { "jmp@", { Jv
, BND
}, 0 }
4267 { "{l|}jmp{P|}", { Ap
}, 0 },
4270 /* X86_64_0F01_REG_0 */
4272 { "sgdt{Q|Q}", { M
}, 0 },
4273 { "sgdt", { M
}, 0 },
4276 /* X86_64_0F01_REG_1 */
4278 { "sidt{Q|Q}", { M
}, 0 },
4279 { "sidt", { M
}, 0 },
4282 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4285 { "seamret", { Skip_MODRM
}, 0 },
4288 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4291 { "seamops", { Skip_MODRM
}, 0 },
4294 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4297 { "seamcall", { Skip_MODRM
}, 0 },
4300 /* X86_64_0F01_REG_2 */
4302 { "lgdt{Q|Q}", { M
}, 0 },
4303 { "lgdt", { M
}, 0 },
4306 /* X86_64_0F01_REG_3 */
4308 { "lidt{Q|Q}", { M
}, 0 },
4309 { "lidt", { M
}, 0 },
4312 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4315 { "uiret", { Skip_MODRM
}, 0 },
4318 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4321 { "testui", { Skip_MODRM
}, 0 },
4324 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4327 { "clui", { Skip_MODRM
}, 0 },
4330 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4333 { "stui", { Skip_MODRM
}, 0 },
4336 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4339 { "rmpadjust", { Skip_MODRM
}, 0 },
4342 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4345 { "rmpupdate", { Skip_MODRM
}, 0 },
4348 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4351 { "psmash", { Skip_MODRM
}, 0 },
4356 { "movZ", { Em
, Td
}, 0 },
4361 { "movZ", { Td
, Em
}, 0 },
4364 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4367 { "senduipi", { Eq
}, 0 },
4370 /* X86_64_VEX_0F3849 */
4373 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
4376 /* X86_64_VEX_0F384B */
4379 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
4382 /* X86_64_VEX_0F385C */
4385 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
4388 /* X86_64_VEX_0F385E */
4391 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
4395 static const struct dis386 three_byte_table
[][256] = {
4397 /* THREE_BYTE_0F38 */
4400 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
4401 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
4402 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
4403 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
4404 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
4405 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
4406 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
4407 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
4409 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
4410 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
4411 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
4412 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
4418 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4422 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4423 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4425 { "ptest", { XM
, EXx
}, PREFIX_DATA
},
4431 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
4432 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
4433 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
4436 { "pmovsxbw", { XM
, EXq
}, PREFIX_DATA
},
4437 { "pmovsxbd", { XM
, EXd
}, PREFIX_DATA
},
4438 { "pmovsxbq", { XM
, EXw
}, PREFIX_DATA
},
4439 { "pmovsxwd", { XM
, EXq
}, PREFIX_DATA
},
4440 { "pmovsxwq", { XM
, EXd
}, PREFIX_DATA
},
4441 { "pmovsxdq", { XM
, EXq
}, PREFIX_DATA
},
4445 { "pmuldq", { XM
, EXx
}, PREFIX_DATA
},
4446 { "pcmpeqq", { XM
, EXx
}, PREFIX_DATA
},
4447 { MOD_TABLE (MOD_0F382A
) },
4448 { "packusdw", { XM
, EXx
}, PREFIX_DATA
},
4454 { "pmovzxbw", { XM
, EXq
}, PREFIX_DATA
},
4455 { "pmovzxbd", { XM
, EXd
}, PREFIX_DATA
},
4456 { "pmovzxbq", { XM
, EXw
}, PREFIX_DATA
},
4457 { "pmovzxwd", { XM
, EXq
}, PREFIX_DATA
},
4458 { "pmovzxwq", { XM
, EXd
}, PREFIX_DATA
},
4459 { "pmovzxdq", { XM
, EXq
}, PREFIX_DATA
},
4461 { "pcmpgtq", { XM
, EXx
}, PREFIX_DATA
},
4463 { "pminsb", { XM
, EXx
}, PREFIX_DATA
},
4464 { "pminsd", { XM
, EXx
}, PREFIX_DATA
},
4465 { "pminuw", { XM
, EXx
}, PREFIX_DATA
},
4466 { "pminud", { XM
, EXx
}, PREFIX_DATA
},
4467 { "pmaxsb", { XM
, EXx
}, PREFIX_DATA
},
4468 { "pmaxsd", { XM
, EXx
}, PREFIX_DATA
},
4469 { "pmaxuw", { XM
, EXx
}, PREFIX_DATA
},
4470 { "pmaxud", { XM
, EXx
}, PREFIX_DATA
},
4472 { "pmulld", { XM
, EXx
}, PREFIX_DATA
},
4473 { "phminposuw", { XM
, EXx
}, PREFIX_DATA
},
4544 { "invept", { Gm
, Mo
}, PREFIX_DATA
},
4545 { "invvpid", { Gm
, Mo
}, PREFIX_DATA
},
4546 { "invpcid", { Gm
, M
}, PREFIX_DATA
},
4625 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4626 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4627 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4628 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4629 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4630 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4632 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_DATA
},
4643 { PREFIX_TABLE (PREFIX_0F38D8
) },
4646 { "aesimc", { XM
, EXx
}, PREFIX_DATA
},
4647 { PREFIX_TABLE (PREFIX_0F38DC
) },
4648 { PREFIX_TABLE (PREFIX_0F38DD
) },
4649 { PREFIX_TABLE (PREFIX_0F38DE
) },
4650 { PREFIX_TABLE (PREFIX_0F38DF
) },
4670 { PREFIX_TABLE (PREFIX_0F38F0
) },
4671 { PREFIX_TABLE (PREFIX_0F38F1
) },
4675 { MOD_TABLE (MOD_0F38F5
) },
4676 { PREFIX_TABLE (PREFIX_0F38F6
) },
4679 { PREFIX_TABLE (PREFIX_0F38F8
) },
4680 { MOD_TABLE (MOD_0F38F9
) },
4681 { PREFIX_TABLE (PREFIX_0F38FA
) },
4682 { PREFIX_TABLE (PREFIX_0F38FB
) },
4688 /* THREE_BYTE_0F3A */
4700 { "roundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4701 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4702 { "roundss", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4703 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_DATA
},
4704 { "blendps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4705 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4706 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4707 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4713 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
4714 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
4715 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
4716 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
4727 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_DATA
},
4728 { "insertps", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4729 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_DATA
},
4763 { "dpps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4764 { "dppd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4765 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4767 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_DATA
},
4799 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4800 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4801 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4802 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4920 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4922 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4923 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4941 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4961 { PREFIX_TABLE (PREFIX_0F3A0F
) },
4981 static const struct dis386 xop_table
[][256] = {
5134 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
5135 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
5136 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
5144 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
5145 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
5152 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
5153 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
5154 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
5162 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
5163 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
5167 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
5168 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
5171 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
5189 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
5201 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
5202 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
5203 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
5204 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
5214 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
5215 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
5216 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
5217 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
5250 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
5251 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
5252 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
5253 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
5277 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
5278 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
5296 { MOD_TABLE (MOD_XOP_09_12
) },
5420 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
5421 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
5422 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
5423 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
5438 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
5439 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
5440 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
5441 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
5442 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
5443 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
5444 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
5445 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
5447 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
5448 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
5449 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
5450 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
5493 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
5494 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
5495 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
5498 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
5499 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
5504 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
5511 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
5512 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
5513 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
5516 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
5517 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
5522 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
5529 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
5530 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
5531 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
5585 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
5587 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
5857 static const struct dis386 vex_table
[][256] = {
5879 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
5880 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
5881 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
5882 { MOD_TABLE (MOD_VEX_0F13
) },
5883 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5884 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5885 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
5886 { MOD_TABLE (MOD_VEX_0F17
) },
5906 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
5907 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
5908 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
5909 { MOD_TABLE (MOD_VEX_0F2B
) },
5910 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
5911 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
5912 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
5913 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
5934 { VEX_LEN_TABLE (VEX_LEN_0F41
) },
5935 { VEX_LEN_TABLE (VEX_LEN_0F42
) },
5937 { VEX_LEN_TABLE (VEX_LEN_0F44
) },
5938 { VEX_LEN_TABLE (VEX_LEN_0F45
) },
5939 { VEX_LEN_TABLE (VEX_LEN_0F46
) },
5940 { VEX_LEN_TABLE (VEX_LEN_0F47
) },
5944 { VEX_LEN_TABLE (VEX_LEN_0F4A
) },
5945 { VEX_LEN_TABLE (VEX_LEN_0F4B
) },
5951 { MOD_TABLE (MOD_VEX_0F50
) },
5952 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
5953 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
5954 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
5955 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5956 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5957 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5958 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5960 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
5961 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
5962 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
5963 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
5964 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
5965 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
5966 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
5967 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
5969 { "vpunpcklbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5970 { "vpunpcklwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5971 { "vpunpckldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5972 { "vpacksswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5973 { "vpcmpgtb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5974 { "vpcmpgtw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5975 { "vpcmpgtd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5976 { "vpackuswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5978 { "vpunpckhbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5979 { "vpunpckhwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5980 { "vpunpckhdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5981 { "vpackssdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5982 { "vpunpcklqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5983 { "vpunpckhqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5984 { VEX_LEN_TABLE (VEX_LEN_0F6E
) },
5985 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
5987 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
5988 { MOD_TABLE (MOD_VEX_0F71
) },
5989 { MOD_TABLE (MOD_VEX_0F72
) },
5990 { MOD_TABLE (MOD_VEX_0F73
) },
5991 { "vpcmpeqb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5992 { "vpcmpeqw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5993 { "vpcmpeqd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5994 { VEX_LEN_TABLE (VEX_LEN_0F77
) },
6000 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
6001 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
6002 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
6003 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
6023 { VEX_LEN_TABLE (VEX_LEN_0F90
) },
6024 { VEX_LEN_TABLE (VEX_LEN_0F91
) },
6025 { VEX_LEN_TABLE (VEX_LEN_0F92
) },
6026 { VEX_LEN_TABLE (VEX_LEN_0F93
) },
6032 { VEX_LEN_TABLE (VEX_LEN_0F98
) },
6033 { VEX_LEN_TABLE (VEX_LEN_0F99
) },
6056 { REG_TABLE (REG_VEX_0FAE
) },
6079 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
6081 { VEX_LEN_TABLE (VEX_LEN_0FC4
) },
6082 { VEX_LEN_TABLE (VEX_LEN_0FC5
) },
6083 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
6095 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
6096 { "vpsrlw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6097 { "vpsrld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6098 { "vpsrlq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6099 { "vpaddq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6100 { "vpmullw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6101 { VEX_LEN_TABLE (VEX_LEN_0FD6
) },
6102 { MOD_TABLE (MOD_VEX_0FD7
) },
6104 { "vpsubusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6105 { "vpsubusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6106 { "vpminub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6107 { "vpand", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6108 { "vpaddusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6109 { "vpaddusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6110 { "vpmaxub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6111 { "vpandn", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6113 { "vpavgb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6114 { "vpsraw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6115 { "vpsrad", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6116 { "vpavgw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6117 { "vpmulhuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6118 { "vpmulhw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6119 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
6120 { MOD_TABLE (MOD_VEX_0FE7
) },
6122 { "vpsubsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6123 { "vpsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6124 { "vpminsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6125 { "vpor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6126 { "vpaddsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6127 { "vpaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6128 { "vpmaxsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6129 { "vpxor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6131 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
6132 { "vpsllw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6133 { "vpslld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6134 { "vpsllq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6135 { "vpmuludq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6136 { "vpmaddwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6137 { "vpsadbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6138 { VEX_LEN_TABLE (VEX_LEN_0FF7
) },
6140 { "vpsubb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6141 { "vpsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6142 { "vpsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6143 { "vpsubq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6144 { "vpaddb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6145 { "vpaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6146 { "vpaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6152 { "vpshufb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6153 { "vphaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6154 { "vphaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6155 { "vphaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6156 { "vpmaddubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6157 { "vphsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6158 { "vphsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6159 { "vphsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6161 { "vpsignb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6162 { "vpsignw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6163 { "vpsignd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6164 { "vpmulhrsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6165 { VEX_W_TABLE (VEX_W_0F380C
) },
6166 { VEX_W_TABLE (VEX_W_0F380D
) },
6167 { VEX_W_TABLE (VEX_W_0F380E
) },
6168 { VEX_W_TABLE (VEX_W_0F380F
) },
6173 { VEX_W_TABLE (VEX_W_0F3813
) },
6176 { VEX_LEN_TABLE (VEX_LEN_0F3816
) },
6177 { "vptest", { XM
, EXx
}, PREFIX_DATA
},
6179 { VEX_W_TABLE (VEX_W_0F3818
) },
6180 { VEX_LEN_TABLE (VEX_LEN_0F3819
) },
6181 { MOD_TABLE (MOD_VEX_0F381A
) },
6183 { "vpabsb", { XM
, EXx
}, PREFIX_DATA
},
6184 { "vpabsw", { XM
, EXx
}, PREFIX_DATA
},
6185 { "vpabsd", { XM
, EXx
}, PREFIX_DATA
},
6188 { "vpmovsxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6189 { "vpmovsxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6190 { "vpmovsxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6191 { "vpmovsxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6192 { "vpmovsxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6193 { "vpmovsxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6197 { "vpmuldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6198 { "vpcmpeqq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6199 { MOD_TABLE (MOD_VEX_0F382A
) },
6200 { "vpackusdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6201 { MOD_TABLE (MOD_VEX_0F382C
) },
6202 { MOD_TABLE (MOD_VEX_0F382D
) },
6203 { MOD_TABLE (MOD_VEX_0F382E
) },
6204 { MOD_TABLE (MOD_VEX_0F382F
) },
6206 { "vpmovzxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6207 { "vpmovzxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6208 { "vpmovzxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6209 { "vpmovzxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6210 { "vpmovzxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6211 { "vpmovzxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6212 { VEX_LEN_TABLE (VEX_LEN_0F3836
) },
6213 { "vpcmpgtq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6215 { "vpminsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6216 { "vpminsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6217 { "vpminuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6218 { "vpminud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6219 { "vpmaxsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6220 { "vpmaxsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6221 { "vpmaxuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6222 { "vpmaxud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6224 { "vpmulld", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6225 { VEX_LEN_TABLE (VEX_LEN_0F3841
) },
6229 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6230 { VEX_W_TABLE (VEX_W_0F3846
) },
6231 { "vpsllv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6234 { X86_64_TABLE (X86_64_VEX_0F3849
) },
6236 { X86_64_TABLE (X86_64_VEX_0F384B
) },
6242 { VEX_W_TABLE (VEX_W_0F3850
) },
6243 { VEX_W_TABLE (VEX_W_0F3851
) },
6244 { VEX_W_TABLE (VEX_W_0F3852
) },
6245 { VEX_W_TABLE (VEX_W_0F3853
) },
6251 { VEX_W_TABLE (VEX_W_0F3858
) },
6252 { VEX_W_TABLE (VEX_W_0F3859
) },
6253 { MOD_TABLE (MOD_VEX_0F385A
) },
6255 { X86_64_TABLE (X86_64_VEX_0F385C
) },
6257 { X86_64_TABLE (X86_64_VEX_0F385E
) },
6287 { VEX_W_TABLE (VEX_W_0F3878
) },
6288 { VEX_W_TABLE (VEX_W_0F3879
) },
6309 { MOD_TABLE (MOD_VEX_0F388C
) },
6311 { MOD_TABLE (MOD_VEX_0F388E
) },
6314 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, VexGatherD
}, PREFIX_DATA
},
6315 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6316 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, VexGatherD
}, PREFIX_DATA
},
6317 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6320 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6321 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6323 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6324 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6325 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6326 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6327 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6328 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6329 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6330 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6338 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6339 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6341 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6342 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6343 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6344 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6345 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6346 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6347 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6348 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6356 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6357 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6359 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6360 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6361 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6362 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6363 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6364 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6365 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6366 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6384 { VEX_W_TABLE (VEX_W_0F38CF
) },
6398 { VEX_LEN_TABLE (VEX_LEN_0F38DB
) },
6399 { "vaesenc", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6400 { "vaesenclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6401 { "vaesdec", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6402 { "vaesdeclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6424 { VEX_LEN_TABLE (VEX_LEN_0F38F2
) },
6425 { VEX_LEN_TABLE (VEX_LEN_0F38F3
) },
6427 { VEX_LEN_TABLE (VEX_LEN_0F38F5
) },
6428 { VEX_LEN_TABLE (VEX_LEN_0F38F6
) },
6429 { VEX_LEN_TABLE (VEX_LEN_0F38F7
) },
6443 { VEX_LEN_TABLE (VEX_LEN_0F3A00
) },
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A01
) },
6445 { VEX_W_TABLE (VEX_W_0F3A02
) },
6447 { VEX_W_TABLE (VEX_W_0F3A04
) },
6448 { VEX_W_TABLE (VEX_W_0F3A05
) },
6449 { VEX_LEN_TABLE (VEX_LEN_0F3A06
) },
6452 { "vroundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6453 { "vroundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6454 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, PREFIX_DATA
},
6455 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, PREFIX_DATA
},
6456 { "vblendps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6457 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6458 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6459 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A14
) },
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A15
) },
6467 { VEX_LEN_TABLE (VEX_LEN_0F3A16
) },
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A17
) },
6470 { VEX_LEN_TABLE (VEX_LEN_0F3A18
) },
6471 { VEX_LEN_TABLE (VEX_LEN_0F3A19
) },
6475 { VEX_W_TABLE (VEX_W_0F3A1D
) },
6479 { VEX_LEN_TABLE (VEX_LEN_0F3A20
) },
6480 { VEX_LEN_TABLE (VEX_LEN_0F3A21
) },
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A22
) },
6497 { VEX_LEN_TABLE (VEX_LEN_0F3A30
) },
6498 { VEX_LEN_TABLE (VEX_LEN_0F3A31
) },
6499 { VEX_LEN_TABLE (VEX_LEN_0F3A32
) },
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A33
) },
6506 { VEX_LEN_TABLE (VEX_LEN_0F3A38
) },
6507 { VEX_LEN_TABLE (VEX_LEN_0F3A39
) },
6515 { "vdpps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A41
) },
6517 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6519 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, PREFIX_DATA
},
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A46
) },
6524 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6525 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6526 { VEX_W_TABLE (VEX_W_0F3A4A
) },
6527 { VEX_W_TABLE (VEX_W_0F3A4B
) },
6528 { VEX_W_TABLE (VEX_W_0F3A4C
) },
6546 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6547 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6548 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6549 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6551 { VEX_LEN_TABLE (VEX_LEN_0F3A60
) },
6552 { VEX_LEN_TABLE (VEX_LEN_0F3A61
) },
6553 { VEX_LEN_TABLE (VEX_LEN_0F3A62
) },
6554 { VEX_LEN_TABLE (VEX_LEN_0F3A63
) },
6560 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6561 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6562 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6563 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6564 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6565 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6566 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6567 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6578 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6579 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6580 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6581 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6582 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6583 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6584 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6585 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6674 { VEX_W_TABLE (VEX_W_0F3ACE
) },
6675 { VEX_W_TABLE (VEX_W_0F3ACF
) },
6693 { VEX_LEN_TABLE (VEX_LEN_0F3ADF
) },
6713 { VEX_LEN_TABLE (VEX_LEN_0F3AF0
) },
6733 #include "i386-dis-evex.h"
6735 static const struct dis386 vex_len_table
[][2] = {
6736 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6738 { "vmovlpX", { XM
, Vex
, EXq
}, 0 },
6741 /* VEX_LEN_0F12_P_0_M_1 */
6743 { "vmovhlps", { XM
, Vex
, EXq
}, 0 },
6746 /* VEX_LEN_0F13_M_0 */
6748 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
6751 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6753 { "vmovhpX", { XM
, Vex
, EXq
}, 0 },
6756 /* VEX_LEN_0F16_P_0_M_1 */
6758 { "vmovlhps", { XM
, Vex
, EXq
}, 0 },
6761 /* VEX_LEN_0F17_M_0 */
6763 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
6769 { MOD_TABLE (MOD_VEX_0F41_L_1
) },
6775 { MOD_TABLE (MOD_VEX_0F42_L_1
) },
6780 { MOD_TABLE (MOD_VEX_0F44_L_0
) },
6786 { MOD_TABLE (MOD_VEX_0F45_L_1
) },
6792 { MOD_TABLE (MOD_VEX_0F46_L_1
) },
6798 { MOD_TABLE (MOD_VEX_0F47_L_1
) },
6804 { MOD_TABLE (MOD_VEX_0F4A_L_1
) },
6810 { MOD_TABLE (MOD_VEX_0F4B_L_1
) },
6815 { "vmovK", { XMScalar
, Edq
}, PREFIX_DATA
},
6820 { "vzeroupper", { XX
}, 0 },
6821 { "vzeroall", { XX
}, 0 },
6824 /* VEX_LEN_0F7E_P_1 */
6826 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
6829 /* VEX_LEN_0F7E_P_2 */
6831 { "vmovK", { Edq
, XMScalar
}, 0 },
6836 { VEX_W_TABLE (VEX_W_0F90_L_0
) },
6841 { MOD_TABLE (MOD_VEX_0F91_L_0
) },
6846 { MOD_TABLE (MOD_VEX_0F92_L_0
) },
6851 { MOD_TABLE (MOD_VEX_0F93_L_0
) },
6856 { MOD_TABLE (MOD_VEX_0F98_L_0
) },
6861 { MOD_TABLE (MOD_VEX_0F99_L_0
) },
6864 /* VEX_LEN_0FAE_R_2_M_0 */
6866 { "vldmxcsr", { Md
}, 0 },
6869 /* VEX_LEN_0FAE_R_3_M_0 */
6871 { "vstmxcsr", { Md
}, 0 },
6876 { "vpinsrw", { XM
, Vex
, Edqw
, Ib
}, PREFIX_DATA
},
6881 { "vpextrw", { Gdq
, XS
, Ib
}, PREFIX_DATA
},
6886 { "vmovq", { EXqS
, XMScalar
}, PREFIX_DATA
},
6891 { "vmaskmovdqu", { XM
, XS
}, PREFIX_DATA
},
6894 /* VEX_LEN_0F3816 */
6897 { VEX_W_TABLE (VEX_W_0F3816_L_1
) },
6900 /* VEX_LEN_0F3819 */
6903 { VEX_W_TABLE (VEX_W_0F3819_L_1
) },
6906 /* VEX_LEN_0F381A_M_0 */
6909 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1
) },
6912 /* VEX_LEN_0F3836 */
6915 { VEX_W_TABLE (VEX_W_0F3836
) },
6918 /* VEX_LEN_0F3841 */
6920 { "vphminposuw", { XM
, EXx
}, PREFIX_DATA
},
6923 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6925 { "ldtilecfg", { M
}, 0 },
6928 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6930 { "tilerelease", { Skip_MODRM
}, 0 },
6933 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6935 { "sttilecfg", { M
}, 0 },
6938 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6940 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
6943 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6945 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
6947 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6949 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
6952 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6954 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
6957 /* VEX_LEN_0F385A_M_0 */
6960 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0
) },
6963 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6965 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
6968 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6970 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
6973 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6975 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
6978 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6980 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
6983 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6985 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
6988 /* VEX_LEN_0F38DB */
6990 { "vaesimc", { XM
, EXx
}, PREFIX_DATA
},
6993 /* VEX_LEN_0F38F2 */
6995 { "andnS", { Gdq
, VexGdq
, Edq
}, PREFIX_OPCODE
},
6998 /* VEX_LEN_0F38F3 */
7000 { REG_TABLE(REG_VEX_0F38F3_L_0
) },
7003 /* VEX_LEN_0F38F5 */
7005 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0
) },
7008 /* VEX_LEN_0F38F6 */
7010 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0
) },
7013 /* VEX_LEN_0F38F7 */
7015 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0
) },
7018 /* VEX_LEN_0F3A00 */
7021 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
7024 /* VEX_LEN_0F3A01 */
7027 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
7030 /* VEX_LEN_0F3A06 */
7033 { VEX_W_TABLE (VEX_W_0F3A06_L_1
) },
7036 /* VEX_LEN_0F3A14 */
7038 { "vpextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
7041 /* VEX_LEN_0F3A15 */
7043 { "vpextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
7046 /* VEX_LEN_0F3A16 */
7048 { "vpextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
7051 /* VEX_LEN_0F3A17 */
7053 { "vextractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
7056 /* VEX_LEN_0F3A18 */
7059 { VEX_W_TABLE (VEX_W_0F3A18_L_1
) },
7062 /* VEX_LEN_0F3A19 */
7065 { VEX_W_TABLE (VEX_W_0F3A19_L_1
) },
7068 /* VEX_LEN_0F3A20 */
7070 { "vpinsrb", { XM
, Vex
, Edqb
, Ib
}, PREFIX_DATA
},
7073 /* VEX_LEN_0F3A21 */
7075 { "vinsertps", { XM
, Vex
, EXd
, Ib
}, PREFIX_DATA
},
7078 /* VEX_LEN_0F3A22 */
7080 { "vpinsrK", { XM
, Vex
, Edq
, Ib
}, PREFIX_DATA
},
7083 /* VEX_LEN_0F3A30 */
7085 { MOD_TABLE (MOD_VEX_0F3A30_L_0
) },
7088 /* VEX_LEN_0F3A31 */
7090 { MOD_TABLE (MOD_VEX_0F3A31_L_0
) },
7093 /* VEX_LEN_0F3A32 */
7095 { MOD_TABLE (MOD_VEX_0F3A32_L_0
) },
7098 /* VEX_LEN_0F3A33 */
7100 { MOD_TABLE (MOD_VEX_0F3A33_L_0
) },
7103 /* VEX_LEN_0F3A38 */
7106 { VEX_W_TABLE (VEX_W_0F3A38_L_1
) },
7109 /* VEX_LEN_0F3A39 */
7112 { VEX_W_TABLE (VEX_W_0F3A39_L_1
) },
7115 /* VEX_LEN_0F3A41 */
7117 { "vdppd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7120 /* VEX_LEN_0F3A46 */
7123 { VEX_W_TABLE (VEX_W_0F3A46_L_1
) },
7126 /* VEX_LEN_0F3A60 */
7128 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7131 /* VEX_LEN_0F3A61 */
7133 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7136 /* VEX_LEN_0F3A62 */
7138 { "vpcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7141 /* VEX_LEN_0F3A63 */
7143 { "vpcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7146 /* VEX_LEN_0F3ADF */
7148 { "vaeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7151 /* VEX_LEN_0F3AF0 */
7153 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0
) },
7156 /* VEX_LEN_0FXOP_08_85 */
7158 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
7161 /* VEX_LEN_0FXOP_08_86 */
7163 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
7166 /* VEX_LEN_0FXOP_08_87 */
7168 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
7171 /* VEX_LEN_0FXOP_08_8E */
7173 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
7176 /* VEX_LEN_0FXOP_08_8F */
7178 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
7181 /* VEX_LEN_0FXOP_08_95 */
7183 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
7186 /* VEX_LEN_0FXOP_08_96 */
7188 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
7191 /* VEX_LEN_0FXOP_08_97 */
7193 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
7196 /* VEX_LEN_0FXOP_08_9E */
7198 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
7201 /* VEX_LEN_0FXOP_08_9F */
7203 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
7206 /* VEX_LEN_0FXOP_08_A3 */
7208 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7211 /* VEX_LEN_0FXOP_08_A6 */
7213 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
7216 /* VEX_LEN_0FXOP_08_B6 */
7218 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
7221 /* VEX_LEN_0FXOP_08_C0 */
7223 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
7226 /* VEX_LEN_0FXOP_08_C1 */
7228 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
7231 /* VEX_LEN_0FXOP_08_C2 */
7233 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
7236 /* VEX_LEN_0FXOP_08_C3 */
7238 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
7241 /* VEX_LEN_0FXOP_08_CC */
7243 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
7246 /* VEX_LEN_0FXOP_08_CD */
7248 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
7251 /* VEX_LEN_0FXOP_08_CE */
7253 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
7256 /* VEX_LEN_0FXOP_08_CF */
7258 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
7261 /* VEX_LEN_0FXOP_08_EC */
7263 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
7266 /* VEX_LEN_0FXOP_08_ED */
7268 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
7271 /* VEX_LEN_0FXOP_08_EE */
7273 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
7276 /* VEX_LEN_0FXOP_08_EF */
7278 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
7281 /* VEX_LEN_0FXOP_09_01 */
7283 { REG_TABLE (REG_XOP_09_01_L_0
) },
7286 /* VEX_LEN_0FXOP_09_02 */
7288 { REG_TABLE (REG_XOP_09_02_L_0
) },
7291 /* VEX_LEN_0FXOP_09_12_M_1 */
7293 { REG_TABLE (REG_XOP_09_12_M_1_L_0
) },
7296 /* VEX_LEN_0FXOP_09_82_W_0 */
7298 { "vfrczss", { XM
, EXd
}, 0 },
7301 /* VEX_LEN_0FXOP_09_83_W_0 */
7303 { "vfrczsd", { XM
, EXq
}, 0 },
7306 /* VEX_LEN_0FXOP_09_90 */
7308 { "vprotb", { XM
, EXx
, VexW
}, 0 },
7311 /* VEX_LEN_0FXOP_09_91 */
7313 { "vprotw", { XM
, EXx
, VexW
}, 0 },
7316 /* VEX_LEN_0FXOP_09_92 */
7318 { "vprotd", { XM
, EXx
, VexW
}, 0 },
7321 /* VEX_LEN_0FXOP_09_93 */
7323 { "vprotq", { XM
, EXx
, VexW
}, 0 },
7326 /* VEX_LEN_0FXOP_09_94 */
7328 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
7331 /* VEX_LEN_0FXOP_09_95 */
7333 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
7336 /* VEX_LEN_0FXOP_09_96 */
7338 { "vpshld", { XM
, EXx
, VexW
}, 0 },
7341 /* VEX_LEN_0FXOP_09_97 */
7343 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
7346 /* VEX_LEN_0FXOP_09_98 */
7348 { "vpshab", { XM
, EXx
, VexW
}, 0 },
7351 /* VEX_LEN_0FXOP_09_99 */
7353 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
7356 /* VEX_LEN_0FXOP_09_9A */
7358 { "vpshad", { XM
, EXx
, VexW
}, 0 },
7361 /* VEX_LEN_0FXOP_09_9B */
7363 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
7366 /* VEX_LEN_0FXOP_09_C1 */
7368 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
7371 /* VEX_LEN_0FXOP_09_C2 */
7373 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
7376 /* VEX_LEN_0FXOP_09_C3 */
7378 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
7381 /* VEX_LEN_0FXOP_09_C6 */
7383 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
7386 /* VEX_LEN_0FXOP_09_C7 */
7388 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
7391 /* VEX_LEN_0FXOP_09_CB */
7393 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
7396 /* VEX_LEN_0FXOP_09_D1 */
7398 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
7401 /* VEX_LEN_0FXOP_09_D2 */
7403 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
7406 /* VEX_LEN_0FXOP_09_D3 */
7408 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
7411 /* VEX_LEN_0FXOP_09_D6 */
7413 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
7416 /* VEX_LEN_0FXOP_09_D7 */
7418 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
7421 /* VEX_LEN_0FXOP_09_DB */
7423 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
7426 /* VEX_LEN_0FXOP_09_E1 */
7428 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
7431 /* VEX_LEN_0FXOP_09_E2 */
7433 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
7436 /* VEX_LEN_0FXOP_09_E3 */
7438 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
7441 /* VEX_LEN_0FXOP_0A_12 */
7443 { REG_TABLE (REG_XOP_0A_12_L_0
) },
7447 #include "i386-dis-evex-len.h"
7449 static const struct dis386 vex_w_table
[][2] = {
7451 /* VEX_W_0F41_L_1_M_1 */
7452 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0
) },
7453 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1
) },
7456 /* VEX_W_0F42_L_1_M_1 */
7457 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0
) },
7458 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1
) },
7461 /* VEX_W_0F44_L_0_M_1 */
7462 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0
) },
7463 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1
) },
7466 /* VEX_W_0F45_L_1_M_1 */
7467 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0
) },
7468 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1
) },
7471 /* VEX_W_0F46_L_1_M_1 */
7472 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0
) },
7473 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1
) },
7476 /* VEX_W_0F47_L_1_M_1 */
7477 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0
) },
7478 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1
) },
7481 /* VEX_W_0F4A_L_1_M_1 */
7482 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0
) },
7483 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1
) },
7486 /* VEX_W_0F4B_L_1_M_1 */
7487 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0
) },
7488 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1
) },
7491 /* VEX_W_0F90_L_0 */
7492 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0
) },
7493 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1
) },
7496 /* VEX_W_0F91_L_0_M_0 */
7497 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0
) },
7498 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1
) },
7501 /* VEX_W_0F92_L_0_M_1 */
7502 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0
) },
7503 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1
) },
7506 /* VEX_W_0F93_L_0_M_1 */
7507 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0
) },
7508 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1
) },
7511 /* VEX_W_0F98_L_0_M_1 */
7512 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0
) },
7513 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1
) },
7516 /* VEX_W_0F99_L_0_M_1 */
7517 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0
) },
7518 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1
) },
7522 { "vpermilps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7526 { "vpermilpd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7530 { "vtestps", { XM
, EXx
}, PREFIX_DATA
},
7534 { "vtestpd", { XM
, EXx
}, PREFIX_DATA
},
7538 { "vcvtph2ps", { XM
, EXxmmq
}, PREFIX_DATA
},
7541 /* VEX_W_0F3816_L_1 */
7542 { "vpermps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7546 { "vbroadcastss", { XM
, EXxmm_md
}, PREFIX_DATA
},
7549 /* VEX_W_0F3819_L_1 */
7550 { "vbroadcastsd", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7553 /* VEX_W_0F381A_M_0_L_1 */
7554 { "vbroadcastf128", { XM
, Mxmm
}, PREFIX_DATA
},
7557 /* VEX_W_0F382C_M_0 */
7558 { "vmaskmovps", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7561 /* VEX_W_0F382D_M_0 */
7562 { "vmaskmovpd", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7565 /* VEX_W_0F382E_M_0 */
7566 { "vmaskmovps", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7569 /* VEX_W_0F382F_M_0 */
7570 { "vmaskmovpd", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7574 { "vpermd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7578 { "vpsravd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7581 /* VEX_W_0F3849_X86_64_P_0 */
7582 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
7585 /* VEX_W_0F3849_X86_64_P_2 */
7586 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
7589 /* VEX_W_0F3849_X86_64_P_3 */
7590 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
7593 /* VEX_W_0F384B_X86_64_P_1 */
7594 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
7597 /* VEX_W_0F384B_X86_64_P_2 */
7598 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
7601 /* VEX_W_0F384B_X86_64_P_3 */
7602 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
7606 { "%XV vpdpbusd", { XM
, Vex
, EXx
}, 0 },
7610 { "%XV vpdpbusds", { XM
, Vex
, EXx
}, 0 },
7614 { "%XV vpdpwssd", { XM
, Vex
, EXx
}, 0 },
7618 { "%XV vpdpwssds", { XM
, Vex
, EXx
}, 0 },
7622 { "vpbroadcastd", { XM
, EXxmm_md
}, PREFIX_DATA
},
7626 { "vpbroadcastq", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7629 /* VEX_W_0F385A_M_0_L_0 */
7630 { "vbroadcasti128", { XM
, Mxmm
}, PREFIX_DATA
},
7633 /* VEX_W_0F385C_X86_64_P_1 */
7634 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
7637 /* VEX_W_0F385E_X86_64_P_0 */
7638 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
7641 /* VEX_W_0F385E_X86_64_P_1 */
7642 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
7645 /* VEX_W_0F385E_X86_64_P_2 */
7646 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
7649 /* VEX_W_0F385E_X86_64_P_3 */
7650 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
7654 { "vpbroadcastb", { XM
, EXxmm_mb
}, PREFIX_DATA
},
7658 { "vpbroadcastw", { XM
, EXxmm_mw
}, PREFIX_DATA
},
7662 { "vgf2p8mulb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7665 /* VEX_W_0F3A00_L_1 */
7667 { "vpermq", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7670 /* VEX_W_0F3A01_L_1 */
7672 { "vpermpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7676 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7680 { "vpermilps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7684 { "vpermilpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7687 /* VEX_W_0F3A06_L_1 */
7688 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7691 /* VEX_W_0F3A18_L_1 */
7692 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7695 /* VEX_W_0F3A19_L_1 */
7696 { "vextractf128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7700 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, PREFIX_DATA
},
7703 /* VEX_W_0F3A38_L_1 */
7704 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7707 /* VEX_W_0F3A39_L_1 */
7708 { "vextracti128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7711 /* VEX_W_0F3A46_L_1 */
7712 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7716 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7720 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7724 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7729 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7734 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7736 /* VEX_W_0FXOP_08_85_L_0 */
7738 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7740 /* VEX_W_0FXOP_08_86_L_0 */
7742 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7744 /* VEX_W_0FXOP_08_87_L_0 */
7746 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7748 /* VEX_W_0FXOP_08_8E_L_0 */
7750 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7752 /* VEX_W_0FXOP_08_8F_L_0 */
7754 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7756 /* VEX_W_0FXOP_08_95_L_0 */
7758 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7760 /* VEX_W_0FXOP_08_96_L_0 */
7762 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7764 /* VEX_W_0FXOP_08_97_L_0 */
7766 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7768 /* VEX_W_0FXOP_08_9E_L_0 */
7770 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7772 /* VEX_W_0FXOP_08_9F_L_0 */
7774 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7776 /* VEX_W_0FXOP_08_A6_L_0 */
7778 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7780 /* VEX_W_0FXOP_08_B6_L_0 */
7782 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7784 /* VEX_W_0FXOP_08_C0_L_0 */
7786 { "vprotb", { XM
, EXx
, Ib
}, 0 },
7788 /* VEX_W_0FXOP_08_C1_L_0 */
7790 { "vprotw", { XM
, EXx
, Ib
}, 0 },
7792 /* VEX_W_0FXOP_08_C2_L_0 */
7794 { "vprotd", { XM
, EXx
, Ib
}, 0 },
7796 /* VEX_W_0FXOP_08_C3_L_0 */
7798 { "vprotq", { XM
, EXx
, Ib
}, 0 },
7800 /* VEX_W_0FXOP_08_CC_L_0 */
7802 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7804 /* VEX_W_0FXOP_08_CD_L_0 */
7806 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7808 /* VEX_W_0FXOP_08_CE_L_0 */
7810 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7812 /* VEX_W_0FXOP_08_CF_L_0 */
7814 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7816 /* VEX_W_0FXOP_08_EC_L_0 */
7818 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7820 /* VEX_W_0FXOP_08_ED_L_0 */
7822 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7824 /* VEX_W_0FXOP_08_EE_L_0 */
7826 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7828 /* VEX_W_0FXOP_08_EF_L_0 */
7830 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7832 /* VEX_W_0FXOP_09_80 */
7834 { "vfrczps", { XM
, EXx
}, 0 },
7836 /* VEX_W_0FXOP_09_81 */
7838 { "vfrczpd", { XM
, EXx
}, 0 },
7840 /* VEX_W_0FXOP_09_82 */
7842 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
7844 /* VEX_W_0FXOP_09_83 */
7846 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
7848 /* VEX_W_0FXOP_09_C1_L_0 */
7850 { "vphaddbw", { XM
, EXxmm
}, 0 },
7852 /* VEX_W_0FXOP_09_C2_L_0 */
7854 { "vphaddbd", { XM
, EXxmm
}, 0 },
7856 /* VEX_W_0FXOP_09_C3_L_0 */
7858 { "vphaddbq", { XM
, EXxmm
}, 0 },
7860 /* VEX_W_0FXOP_09_C6_L_0 */
7862 { "vphaddwd", { XM
, EXxmm
}, 0 },
7864 /* VEX_W_0FXOP_09_C7_L_0 */
7866 { "vphaddwq", { XM
, EXxmm
}, 0 },
7868 /* VEX_W_0FXOP_09_CB_L_0 */
7870 { "vphadddq", { XM
, EXxmm
}, 0 },
7872 /* VEX_W_0FXOP_09_D1_L_0 */
7874 { "vphaddubw", { XM
, EXxmm
}, 0 },
7876 /* VEX_W_0FXOP_09_D2_L_0 */
7878 { "vphaddubd", { XM
, EXxmm
}, 0 },
7880 /* VEX_W_0FXOP_09_D3_L_0 */
7882 { "vphaddubq", { XM
, EXxmm
}, 0 },
7884 /* VEX_W_0FXOP_09_D6_L_0 */
7886 { "vphadduwd", { XM
, EXxmm
}, 0 },
7888 /* VEX_W_0FXOP_09_D7_L_0 */
7890 { "vphadduwq", { XM
, EXxmm
}, 0 },
7892 /* VEX_W_0FXOP_09_DB_L_0 */
7894 { "vphaddudq", { XM
, EXxmm
}, 0 },
7896 /* VEX_W_0FXOP_09_E1_L_0 */
7898 { "vphsubbw", { XM
, EXxmm
}, 0 },
7900 /* VEX_W_0FXOP_09_E2_L_0 */
7902 { "vphsubwd", { XM
, EXxmm
}, 0 },
7904 /* VEX_W_0FXOP_09_E3_L_0 */
7906 { "vphsubdq", { XM
, EXxmm
}, 0 },
7909 #include "i386-dis-evex-w.h"
7912 static const struct dis386 mod_table
[][2] = {
7915 { "bound{S|}", { Gv
, Ma
}, 0 },
7916 { EVEX_TABLE (EVEX_0F
) },
7920 { "leaS", { Gv
, M
}, 0 },
7924 { "lesS", { Gv
, Mp
}, 0 },
7925 { VEX_C4_TABLE (VEX_0F
) },
7929 { "ldsS", { Gv
, Mp
}, 0 },
7930 { VEX_C5_TABLE (VEX_0F
) },
7935 { RM_TABLE (RM_C6_REG_7
) },
7940 { RM_TABLE (RM_C7_REG_7
) },
7944 { "{l|}call^", { indirEp
}, 0 },
7948 { "{l|}jmp^", { indirEp
}, 0 },
7951 /* MOD_0F01_REG_0 */
7952 { X86_64_TABLE (X86_64_0F01_REG_0
) },
7953 { RM_TABLE (RM_0F01_REG_0
) },
7956 /* MOD_0F01_REG_1 */
7957 { X86_64_TABLE (X86_64_0F01_REG_1
) },
7958 { RM_TABLE (RM_0F01_REG_1
) },
7961 /* MOD_0F01_REG_2 */
7962 { X86_64_TABLE (X86_64_0F01_REG_2
) },
7963 { RM_TABLE (RM_0F01_REG_2
) },
7966 /* MOD_0F01_REG_3 */
7967 { X86_64_TABLE (X86_64_0F01_REG_3
) },
7968 { RM_TABLE (RM_0F01_REG_3
) },
7971 /* MOD_0F01_REG_5 */
7972 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
7973 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
7976 /* MOD_0F01_REG_7 */
7977 { "invlpg", { Mb
}, 0 },
7978 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
7981 /* MOD_0F12_PREFIX_0 */
7982 { "movlpX", { XM
, EXq
}, 0 },
7983 { "movhlps", { XM
, EXq
}, 0 },
7986 /* MOD_0F12_PREFIX_2 */
7987 { "movlpX", { XM
, EXq
}, 0 },
7991 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
7994 /* MOD_0F16_PREFIX_0 */
7995 { "movhpX", { XM
, EXq
}, 0 },
7996 { "movlhps", { XM
, EXq
}, 0 },
7999 /* MOD_0F16_PREFIX_2 */
8000 { "movhpX", { XM
, EXq
}, 0 },
8004 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
8007 /* MOD_0F18_REG_0 */
8008 { "prefetchnta", { Mb
}, 0 },
8009 { "nopQ", { Ev
}, 0 },
8012 /* MOD_0F18_REG_1 */
8013 { "prefetcht0", { Mb
}, 0 },
8014 { "nopQ", { Ev
}, 0 },
8017 /* MOD_0F18_REG_2 */
8018 { "prefetcht1", { Mb
}, 0 },
8019 { "nopQ", { Ev
}, 0 },
8022 /* MOD_0F18_REG_3 */
8023 { "prefetcht2", { Mb
}, 0 },
8024 { "nopQ", { Ev
}, 0 },
8027 /* MOD_0F1A_PREFIX_0 */
8028 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
8029 { "nopQ", { Ev
}, 0 },
8032 /* MOD_0F1B_PREFIX_0 */
8033 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
8034 { "nopQ", { Ev
}, 0 },
8037 /* MOD_0F1B_PREFIX_1 */
8038 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
8039 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8042 /* MOD_0F1C_PREFIX_0 */
8043 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
8044 { "nopQ", { Ev
}, 0 },
8047 /* MOD_0F1E_PREFIX_1 */
8048 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8049 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
8052 /* MOD_0F2B_PREFIX_0 */
8053 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
8056 /* MOD_0F2B_PREFIX_1 */
8057 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
8060 /* MOD_0F2B_PREFIX_2 */
8061 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
8064 /* MOD_0F2B_PREFIX_3 */
8065 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
8070 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8075 { REG_TABLE (REG_0F71_MOD_0
) },
8080 { REG_TABLE (REG_0F72_MOD_0
) },
8085 { REG_TABLE (REG_0F73_MOD_0
) },
8088 /* MOD_0FAE_REG_0 */
8089 { "fxsave", { FXSAVE
}, 0 },
8090 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
8093 /* MOD_0FAE_REG_1 */
8094 { "fxrstor", { FXSAVE
}, 0 },
8095 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
8098 /* MOD_0FAE_REG_2 */
8099 { "ldmxcsr", { Md
}, 0 },
8100 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
8103 /* MOD_0FAE_REG_3 */
8104 { "stmxcsr", { Md
}, 0 },
8105 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
8108 /* MOD_0FAE_REG_4 */
8109 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
8110 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
8113 /* MOD_0FAE_REG_5 */
8114 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
8115 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
8118 /* MOD_0FAE_REG_6 */
8119 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
8120 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
8123 /* MOD_0FAE_REG_7 */
8124 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
8125 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
8129 { "lssS", { Gv
, Mp
}, 0 },
8133 { "lfsS", { Gv
, Mp
}, 0 },
8137 { "lgsS", { Gv
, Mp
}, 0 },
8141 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
8144 /* MOD_0FC7_REG_3 */
8145 { "xrstors", { FXSAVE
}, 0 },
8148 /* MOD_0FC7_REG_4 */
8149 { "xsavec", { FXSAVE
}, 0 },
8152 /* MOD_0FC7_REG_5 */
8153 { "xsaves", { FXSAVE
}, 0 },
8156 /* MOD_0FC7_REG_6 */
8157 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
8158 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
8161 /* MOD_0FC7_REG_7 */
8162 { "vmptrst", { Mq
}, 0 },
8163 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
8168 { "pmovmskb", { Gdq
, MS
}, 0 },
8171 /* MOD_0FE7_PREFIX_2 */
8172 { "movntdq", { Mx
, XM
}, 0 },
8175 /* MOD_0FF0_PREFIX_3 */
8176 { "lddqu", { XM
, M
}, 0 },
8180 { "movntdqa", { XM
, Mx
}, PREFIX_DATA
},
8183 /* MOD_0F38DC_PREFIX_1 */
8184 { "aesenc128kl", { XM
, M
}, 0 },
8185 { "loadiwkey", { XM
, EXx
}, 0 },
8188 /* MOD_0F38DD_PREFIX_1 */
8189 { "aesdec128kl", { XM
, M
}, 0 },
8192 /* MOD_0F38DE_PREFIX_1 */
8193 { "aesenc256kl", { XM
, M
}, 0 },
8196 /* MOD_0F38DF_PREFIX_1 */
8197 { "aesdec256kl", { XM
, M
}, 0 },
8201 { "wrussK", { M
, Gdq
}, PREFIX_DATA
},
8204 /* MOD_0F38F6_PREFIX_0 */
8205 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
8208 /* MOD_0F38F8_PREFIX_1 */
8209 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
8212 /* MOD_0F38F8_PREFIX_2 */
8213 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
8216 /* MOD_0F38F8_PREFIX_3 */
8217 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
8221 { "movdiri", { Edq
, Gdq
}, PREFIX_OPCODE
},
8224 /* MOD_0F38FA_PREFIX_1 */
8226 { "encodekey128", { Gd
, Ed
}, 0 },
8229 /* MOD_0F38FB_PREFIX_1 */
8231 { "encodekey256", { Gd
, Ed
}, 0 },
8234 /* MOD_0F3A0F_PREFIX_1 */
8236 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3
) },
8239 /* MOD_VEX_0F12_PREFIX_0 */
8240 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
8241 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
8244 /* MOD_VEX_0F12_PREFIX_2 */
8245 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
8249 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
8252 /* MOD_VEX_0F16_PREFIX_0 */
8253 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
8254 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
8257 /* MOD_VEX_0F16_PREFIX_2 */
8258 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
8262 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
8266 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
8269 /* MOD_VEX_0F41_L_1 */
8271 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1
) },
8274 /* MOD_VEX_0F42_L_1 */
8276 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1
) },
8279 /* MOD_VEX_0F44_L_0 */
8281 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1
) },
8284 /* MOD_VEX_0F45_L_1 */
8286 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1
) },
8289 /* MOD_VEX_0F46_L_1 */
8291 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1
) },
8294 /* MOD_VEX_0F47_L_1 */
8296 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1
) },
8299 /* MOD_VEX_0F4A_L_1 */
8301 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1
) },
8304 /* MOD_VEX_0F4B_L_1 */
8306 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1
) },
8311 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8316 { REG_TABLE (REG_VEX_0F71_M_0
) },
8321 { REG_TABLE (REG_VEX_0F72_M_0
) },
8326 { REG_TABLE (REG_VEX_0F73_M_0
) },
8329 /* MOD_VEX_0F91_L_0 */
8330 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0
) },
8333 /* MOD_VEX_0F92_L_0 */
8335 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1
) },
8338 /* MOD_VEX_0F93_L_0 */
8340 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1
) },
8343 /* MOD_VEX_0F98_L_0 */
8345 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1
) },
8348 /* MOD_VEX_0F99_L_0 */
8350 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1
) },
8353 /* MOD_VEX_0FAE_REG_2 */
8354 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
8357 /* MOD_VEX_0FAE_REG_3 */
8358 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
8363 { "vpmovmskb", { Gdq
, XS
}, PREFIX_DATA
},
8367 { "vmovntdq", { Mx
, XM
}, PREFIX_DATA
},
8370 /* MOD_VEX_0FF0_PREFIX_3 */
8371 { "vlddqu", { XM
, M
}, 0 },
8374 /* MOD_VEX_0F381A */
8375 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0
) },
8378 /* MOD_VEX_0F382A */
8379 { "vmovntdqa", { XM
, Mx
}, PREFIX_DATA
},
8382 /* MOD_VEX_0F382C */
8383 { VEX_W_TABLE (VEX_W_0F382C_M_0
) },
8386 /* MOD_VEX_0F382D */
8387 { VEX_W_TABLE (VEX_W_0F382D_M_0
) },
8390 /* MOD_VEX_0F382E */
8391 { VEX_W_TABLE (VEX_W_0F382E_M_0
) },
8394 /* MOD_VEX_0F382F */
8395 { VEX_W_TABLE (VEX_W_0F382F_M_0
) },
8398 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8399 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
8400 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
8403 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8404 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
8407 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8409 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
8412 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8413 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
8416 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8417 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
8420 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8421 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
8424 /* MOD_VEX_0F385A */
8425 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0
) },
8428 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8430 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
8433 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8435 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
8438 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8440 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
8443 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8445 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
8448 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8450 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
8453 /* MOD_VEX_0F388C */
8454 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, PREFIX_DATA
},
8457 /* MOD_VEX_0F388E */
8458 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, PREFIX_DATA
},
8461 /* MOD_VEX_0F3A30_L_0 */
8463 { "kshiftr%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8466 /* MOD_VEX_0F3A31_L_0 */
8468 { "kshiftr%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8471 /* MOD_VEX_0F3A32_L_0 */
8473 { "kshiftl%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8476 /* MOD_VEX_0F3A33_L_0 */
8478 { "kshiftl%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8483 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
8486 #include "i386-dis-evex-mod.h"
8489 static const struct dis386 rm_table
[][8] = {
8492 { "xabort", { Skip_MODRM
, Ib
}, 0 },
8496 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
8500 { "enclv", { Skip_MODRM
}, 0 },
8501 { "vmcall", { Skip_MODRM
}, 0 },
8502 { "vmlaunch", { Skip_MODRM
}, 0 },
8503 { "vmresume", { Skip_MODRM
}, 0 },
8504 { "vmxoff", { Skip_MODRM
}, 0 },
8505 { "pconfig", { Skip_MODRM
}, 0 },
8509 { "monitor", { { OP_Monitor
, 0 } }, 0 },
8510 { "mwait", { { OP_Mwait
, 0 } }, 0 },
8511 { "clac", { Skip_MODRM
}, 0 },
8512 { "stac", { Skip_MODRM
}, 0 },
8513 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4
) },
8514 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5
) },
8515 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6
) },
8516 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7
) },
8520 { "xgetbv", { Skip_MODRM
}, 0 },
8521 { "xsetbv", { Skip_MODRM
}, 0 },
8524 { "vmfunc", { Skip_MODRM
}, 0 },
8525 { "xend", { Skip_MODRM
}, 0 },
8526 { "xtest", { Skip_MODRM
}, 0 },
8527 { "enclu", { Skip_MODRM
}, 0 },
8531 { "vmrun", { Skip_MODRM
}, 0 },
8532 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
8533 { "vmload", { Skip_MODRM
}, 0 },
8534 { "vmsave", { Skip_MODRM
}, 0 },
8535 { "stgi", { Skip_MODRM
}, 0 },
8536 { "clgi", { Skip_MODRM
}, 0 },
8537 { "skinit", { Skip_MODRM
}, 0 },
8538 { "invlpga", { Skip_MODRM
}, 0 },
8541 /* RM_0F01_REG_5_MOD_3 */
8542 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
8543 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
8544 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
8546 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4
) },
8547 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5
) },
8548 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6
) },
8549 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7
) },
8552 /* RM_0F01_REG_7_MOD_3 */
8553 { "swapgs", { Skip_MODRM
}, 0 },
8554 { "rdtscp", { Skip_MODRM
}, 0 },
8555 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
8556 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, PREFIX_OPCODE
},
8557 { "clzero", { Skip_MODRM
}, 0 },
8558 { "rdpru", { Skip_MODRM
}, 0 },
8559 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6
) },
8560 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7
) },
8563 /* RM_0F1E_P_1_MOD_3_REG_7 */
8564 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8565 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8566 { "endbr64", { Skip_MODRM
}, 0 },
8567 { "endbr32", { Skip_MODRM
}, 0 },
8568 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8569 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8570 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8571 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8574 /* RM_0FAE_REG_6_MOD_3 */
8575 { "mfence", { Skip_MODRM
}, 0 },
8578 /* RM_0FAE_REG_7_MOD_3 */
8579 { "sfence", { Skip_MODRM
}, 0 },
8582 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8583 { "hreset", { Skip_MODRM
, Ib
}, 0 },
8586 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8587 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
8591 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8593 /* We use the high bit to indicate different name for the same
8595 #define REP_PREFIX (0xf3 | 0x100)
8596 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8597 #define XRELEASE_PREFIX (0xf3 | 0x400)
8598 #define BND_PREFIX (0xf2 | 0x400)
8599 #define NOTRACK_PREFIX (0x3e | 0x100)
8601 /* Remember if the current op is a jump instruction. */
8602 static bool op_is_jump
= false;
8607 int newrex
, i
, length
;
8612 last_lock_prefix
= -1;
8613 last_repz_prefix
= -1;
8614 last_repnz_prefix
= -1;
8615 last_data_prefix
= -1;
8616 last_addr_prefix
= -1;
8617 last_rex_prefix
= -1;
8618 last_seg_prefix
= -1;
8620 active_seg_prefix
= 0;
8621 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
8622 all_prefixes
[i
] = 0;
8625 /* The maximum instruction length is 15bytes. */
8626 while (length
< MAX_CODE_LENGTH
- 1)
8628 FETCH_DATA (the_info
, codep
+ 1);
8632 /* REX prefixes family. */
8649 if (address_mode
== mode_64bit
)
8653 last_rex_prefix
= i
;
8656 prefixes
|= PREFIX_REPZ
;
8657 last_repz_prefix
= i
;
8660 prefixes
|= PREFIX_REPNZ
;
8661 last_repnz_prefix
= i
;
8664 prefixes
|= PREFIX_LOCK
;
8665 last_lock_prefix
= i
;
8668 prefixes
|= PREFIX_CS
;
8669 last_seg_prefix
= i
;
8671 if (address_mode
!= mode_64bit
)
8672 active_seg_prefix
= PREFIX_CS
;
8676 prefixes
|= PREFIX_SS
;
8677 last_seg_prefix
= i
;
8679 if (address_mode
!= mode_64bit
)
8680 active_seg_prefix
= PREFIX_SS
;
8684 prefixes
|= PREFIX_DS
;
8685 last_seg_prefix
= i
;
8687 if (address_mode
!= mode_64bit
)
8688 active_seg_prefix
= PREFIX_DS
;
8692 prefixes
|= PREFIX_ES
;
8693 last_seg_prefix
= i
;
8695 if (address_mode
!= mode_64bit
)
8696 active_seg_prefix
= PREFIX_ES
;
8700 prefixes
|= PREFIX_FS
;
8701 last_seg_prefix
= i
;
8702 active_seg_prefix
= PREFIX_FS
;
8705 prefixes
|= PREFIX_GS
;
8706 last_seg_prefix
= i
;
8707 active_seg_prefix
= PREFIX_GS
;
8710 prefixes
|= PREFIX_DATA
;
8711 last_data_prefix
= i
;
8714 prefixes
|= PREFIX_ADDR
;
8715 last_addr_prefix
= i
;
8718 /* fwait is really an instruction. If there are prefixes
8719 before the fwait, they belong to the fwait, *not* to the
8720 following instruction. */
8722 if (prefixes
|| rex
)
8724 prefixes
|= PREFIX_FWAIT
;
8726 /* This ensures that the previous REX prefixes are noticed
8727 as unused prefixes, as in the return case below. */
8731 prefixes
= PREFIX_FWAIT
;
8736 /* Rex is ignored when followed by another prefix. */
8742 if (*codep
!= FWAIT_OPCODE
)
8743 all_prefixes
[i
++] = *codep
;
8751 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8755 prefix_name (int pref
, int sizeflag
)
8757 static const char *rexes
[16] =
8762 "rex.XB", /* 0x43 */
8764 "rex.RB", /* 0x45 */
8765 "rex.RX", /* 0x46 */
8766 "rex.RXB", /* 0x47 */
8768 "rex.WB", /* 0x49 */
8769 "rex.WX", /* 0x4a */
8770 "rex.WXB", /* 0x4b */
8771 "rex.WR", /* 0x4c */
8772 "rex.WRB", /* 0x4d */
8773 "rex.WRX", /* 0x4e */
8774 "rex.WRXB", /* 0x4f */
8779 /* REX prefixes family. */
8796 return rexes
[pref
- 0x40];
8816 return (sizeflag
& DFLAG
) ? "data16" : "data32";
8818 if (address_mode
== mode_64bit
)
8819 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
8821 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
8826 case XACQUIRE_PREFIX
:
8828 case XRELEASE_PREFIX
:
8832 case NOTRACK_PREFIX
:
8839 static char op_out
[MAX_OPERANDS
][100];
8840 static int op_ad
, op_index
[MAX_OPERANDS
];
8841 static int two_source_ops
;
8842 static bfd_vma op_address
[MAX_OPERANDS
];
8843 static bfd_vma op_riprel
[MAX_OPERANDS
];
8844 static bfd_vma start_pc
;
8847 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8848 * (see topic "Redundant prefixes" in the "Differences from 8086"
8849 * section of the "Virtual 8086 Mode" chapter.)
8850 * 'pc' should be the address of this instruction, it will
8851 * be used to print the target address if this is a relative jump or call
8852 * The function returns the length of this instruction in bytes.
8855 static char intel_syntax
;
8856 static char intel_mnemonic
= !SYSV386_COMPAT
;
8857 static char open_char
;
8858 static char close_char
;
8859 static char separator_char
;
8860 static char scale_char
;
8868 static enum x86_64_isa isa64
;
8870 /* Here for backwards compatibility. When gdb stops using
8871 print_insn_i386_att and print_insn_i386_intel these functions can
8872 disappear, and print_insn_i386 be merged into print_insn. */
8874 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
8878 return print_insn (pc
, info
);
8882 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
8886 return print_insn (pc
, info
);
8890 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
8894 return print_insn (pc
, info
);
8898 print_i386_disassembler_options (FILE *stream
)
8900 fprintf (stream
, _("\n\
8901 The following i386/x86-64 specific disassembler options are supported for use\n\
8902 with the -M switch (multiple options should be separated by commas):\n"));
8904 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
8905 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
8906 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
8907 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
8908 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
8909 fprintf (stream
, _(" att-mnemonic\n"
8910 " Display instruction in AT&T mnemonic\n"));
8911 fprintf (stream
, _(" intel-mnemonic\n"
8912 " Display instruction in Intel mnemonic\n"));
8913 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
8914 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
8915 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
8916 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
8917 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
8918 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8919 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
8920 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
8924 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
8926 /* Get a pointer to struct dis386 with a valid name. */
8928 static const struct dis386
*
8929 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
8931 int vindex
, vex_table_index
;
8933 if (dp
->name
!= NULL
)
8936 switch (dp
->op
[0].bytemode
)
8939 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
8943 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
8944 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
8948 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
8951 case USE_PREFIX_TABLE
:
8954 /* The prefix in VEX is implicit. */
8960 case REPE_PREFIX_OPCODE
:
8963 case DATA_PREFIX_OPCODE
:
8966 case REPNE_PREFIX_OPCODE
:
8976 int last_prefix
= -1;
8979 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8980 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8982 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
8984 if (last_repz_prefix
> last_repnz_prefix
)
8987 prefix
= PREFIX_REPZ
;
8988 last_prefix
= last_repz_prefix
;
8993 prefix
= PREFIX_REPNZ
;
8994 last_prefix
= last_repnz_prefix
;
8997 /* Check if prefix should be ignored. */
8998 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
8999 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
9001 && !prefix_table
[dp
->op
[1].bytemode
][vindex
].name
)
9005 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
9008 prefix
= PREFIX_DATA
;
9009 last_prefix
= last_data_prefix
;
9014 used_prefixes
|= prefix
;
9015 all_prefixes
[last_prefix
] = 0;
9018 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
9021 case USE_X86_64_TABLE
:
9022 vindex
= address_mode
== mode_64bit
? 1 : 0;
9023 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
9026 case USE_3BYTE_TABLE
:
9027 FETCH_DATA (info
, codep
+ 2);
9029 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
9031 modrm
.mod
= (*codep
>> 6) & 3;
9032 modrm
.reg
= (*codep
>> 3) & 7;
9033 modrm
.rm
= *codep
& 7;
9036 case USE_VEX_LEN_TABLE
:
9046 /* This allows re-using in particular table entries where only
9047 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
9060 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
9063 case USE_EVEX_LEN_TABLE
:
9083 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
9086 case USE_XOP_8F_TABLE
:
9087 FETCH_DATA (info
, codep
+ 3);
9088 rex
= ~(*codep
>> 5) & 0x7;
9090 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9091 switch ((*codep
& 0x1f))
9097 vex_table_index
= XOP_08
;
9100 vex_table_index
= XOP_09
;
9103 vex_table_index
= XOP_0A
;
9107 vex
.w
= *codep
& 0x80;
9108 if (vex
.w
&& address_mode
== mode_64bit
)
9111 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9112 if (address_mode
!= mode_64bit
)
9114 /* In 16/32-bit mode REX_B is silently ignored. */
9118 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9119 switch ((*codep
& 0x3))
9124 vex
.prefix
= DATA_PREFIX_OPCODE
;
9127 vex
.prefix
= REPE_PREFIX_OPCODE
;
9130 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9136 dp
= &xop_table
[vex_table_index
][vindex
];
9139 FETCH_DATA (info
, codep
+ 1);
9140 modrm
.mod
= (*codep
>> 6) & 3;
9141 modrm
.reg
= (*codep
>> 3) & 7;
9142 modrm
.rm
= *codep
& 7;
9144 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9145 having to decode the bits for every otherwise valid encoding. */
9150 case USE_VEX_C4_TABLE
:
9152 FETCH_DATA (info
, codep
+ 3);
9153 rex
= ~(*codep
>> 5) & 0x7;
9154 switch ((*codep
& 0x1f))
9160 vex_table_index
= VEX_0F
;
9163 vex_table_index
= VEX_0F38
;
9166 vex_table_index
= VEX_0F3A
;
9170 vex
.w
= *codep
& 0x80;
9171 if (address_mode
== mode_64bit
)
9178 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9179 is ignored, other REX bits are 0 and the highest bit in
9180 VEX.vvvv is also ignored (but we mustn't clear it here). */
9183 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9184 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9185 switch ((*codep
& 0x3))
9190 vex
.prefix
= DATA_PREFIX_OPCODE
;
9193 vex
.prefix
= REPE_PREFIX_OPCODE
;
9196 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9202 dp
= &vex_table
[vex_table_index
][vindex
];
9204 /* There is no MODRM byte for VEX0F 77. */
9205 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
9207 FETCH_DATA (info
, codep
+ 1);
9208 modrm
.mod
= (*codep
>> 6) & 3;
9209 modrm
.reg
= (*codep
>> 3) & 7;
9210 modrm
.rm
= *codep
& 7;
9214 case USE_VEX_C5_TABLE
:
9216 FETCH_DATA (info
, codep
+ 2);
9217 rex
= (*codep
& 0x80) ? 0 : REX_R
;
9219 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9221 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9222 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9223 switch ((*codep
& 0x3))
9228 vex
.prefix
= DATA_PREFIX_OPCODE
;
9231 vex
.prefix
= REPE_PREFIX_OPCODE
;
9234 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9240 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
9242 /* There is no MODRM byte for VEX 77. */
9245 FETCH_DATA (info
, codep
+ 1);
9246 modrm
.mod
= (*codep
>> 6) & 3;
9247 modrm
.reg
= (*codep
>> 3) & 7;
9248 modrm
.rm
= *codep
& 7;
9252 case USE_VEX_W_TABLE
:
9256 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
9259 case USE_EVEX_TABLE
:
9263 FETCH_DATA (info
, codep
+ 4);
9264 /* The first byte after 0x62. */
9265 rex
= ~(*codep
>> 5) & 0x7;
9266 vex
.r
= *codep
& 0x10;
9267 switch ((*codep
& 0xf))
9272 vex_table_index
= EVEX_0F
;
9275 vex_table_index
= EVEX_0F38
;
9278 vex_table_index
= EVEX_0F3A
;
9282 /* The second byte after 0x62. */
9284 vex
.w
= *codep
& 0x80;
9285 if (vex
.w
&& address_mode
== mode_64bit
)
9288 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9291 if (!(*codep
& 0x4))
9294 switch ((*codep
& 0x3))
9299 vex
.prefix
= DATA_PREFIX_OPCODE
;
9302 vex
.prefix
= REPE_PREFIX_OPCODE
;
9305 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9309 /* The third byte after 0x62. */
9312 /* Remember the static rounding bits. */
9313 vex
.ll
= (*codep
>> 5) & 3;
9314 vex
.b
= (*codep
& 0x10) != 0;
9316 vex
.v
= *codep
& 0x8;
9317 vex
.mask_register_specifier
= *codep
& 0x7;
9318 vex
.zeroing
= *codep
& 0x80;
9320 if (address_mode
!= mode_64bit
)
9322 /* In 16/32-bit mode silently ignore following bits. */
9331 dp
= &evex_table
[vex_table_index
][vindex
];
9333 FETCH_DATA (info
, codep
+ 1);
9334 modrm
.mod
= (*codep
>> 6) & 3;
9335 modrm
.reg
= (*codep
>> 3) & 7;
9336 modrm
.rm
= *codep
& 7;
9338 /* Set vector length. */
9339 if (modrm
.mod
== 3 && vex
.b
)
9368 if (dp
->name
!= NULL
)
9371 return get_valid_dis386 (dp
, info
);
9375 get_sib (disassemble_info
*info
, int sizeflag
)
9377 /* If modrm.mod == 3, operand must be register. */
9379 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
9383 FETCH_DATA (info
, codep
+ 2);
9384 sib
.index
= (codep
[1] >> 3) & 7;
9385 sib
.scale
= (codep
[1] >> 6) & 3;
9386 sib
.base
= codep
[1] & 7;
9391 print_insn (bfd_vma pc
, disassemble_info
*info
)
9393 const struct dis386
*dp
;
9395 char *op_txt
[MAX_OPERANDS
];
9397 int sizeflag
, orig_sizeflag
;
9399 struct dis_private priv
;
9402 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
9403 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
9404 address_mode
= mode_32bit
;
9405 else if (info
->mach
== bfd_mach_i386_i8086
)
9407 address_mode
= mode_16bit
;
9408 priv
.orig_sizeflag
= 0;
9411 address_mode
= mode_64bit
;
9413 if (intel_syntax
== (char) -1)
9414 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
9416 for (p
= info
->disassembler_options
; p
!= NULL
; )
9418 if (startswith (p
, "amd64"))
9420 else if (startswith (p
, "intel64"))
9422 else if (startswith (p
, "x86-64"))
9424 address_mode
= mode_64bit
;
9425 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9427 else if (startswith (p
, "i386"))
9429 address_mode
= mode_32bit
;
9430 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9432 else if (startswith (p
, "i8086"))
9434 address_mode
= mode_16bit
;
9435 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
9437 else if (startswith (p
, "intel"))
9440 if (startswith (p
+ 5, "-mnemonic"))
9443 else if (startswith (p
, "att"))
9446 if (startswith (p
+ 3, "-mnemonic"))
9449 else if (startswith (p
, "addr"))
9451 if (address_mode
== mode_64bit
)
9453 if (p
[4] == '3' && p
[5] == '2')
9454 priv
.orig_sizeflag
&= ~AFLAG
;
9455 else if (p
[4] == '6' && p
[5] == '4')
9456 priv
.orig_sizeflag
|= AFLAG
;
9460 if (p
[4] == '1' && p
[5] == '6')
9461 priv
.orig_sizeflag
&= ~AFLAG
;
9462 else if (p
[4] == '3' && p
[5] == '2')
9463 priv
.orig_sizeflag
|= AFLAG
;
9466 else if (startswith (p
, "data"))
9468 if (p
[4] == '1' && p
[5] == '6')
9469 priv
.orig_sizeflag
&= ~DFLAG
;
9470 else if (p
[4] == '3' && p
[5] == '2')
9471 priv
.orig_sizeflag
|= DFLAG
;
9473 else if (startswith (p
, "suffix"))
9474 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
9476 p
= strchr (p
, ',');
9481 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
9483 (*info
->fprintf_func
) (info
->stream
,
9484 _("64-bit address is disabled"));
9490 names64
= intel_names64
;
9491 names32
= intel_names32
;
9492 names16
= intel_names16
;
9493 names8
= intel_names8
;
9494 names8rex
= intel_names8rex
;
9495 names_seg
= intel_names_seg
;
9496 names_mm
= intel_names_mm
;
9497 names_bnd
= intel_names_bnd
;
9498 names_xmm
= intel_names_xmm
;
9499 names_ymm
= intel_names_ymm
;
9500 names_zmm
= intel_names_zmm
;
9501 names_tmm
= intel_names_tmm
;
9502 index64
= intel_index64
;
9503 index32
= intel_index32
;
9504 names_mask
= intel_names_mask
;
9505 index16
= intel_index16
;
9508 separator_char
= '+';
9513 names64
= att_names64
;
9514 names32
= att_names32
;
9515 names16
= att_names16
;
9516 names8
= att_names8
;
9517 names8rex
= att_names8rex
;
9518 names_seg
= att_names_seg
;
9519 names_mm
= att_names_mm
;
9520 names_bnd
= att_names_bnd
;
9521 names_xmm
= att_names_xmm
;
9522 names_ymm
= att_names_ymm
;
9523 names_zmm
= att_names_zmm
;
9524 names_tmm
= att_names_tmm
;
9525 index64
= att_index64
;
9526 index32
= att_index32
;
9527 names_mask
= att_names_mask
;
9528 index16
= att_index16
;
9531 separator_char
= ',';
9535 /* The output looks better if we put 7 bytes on a line, since that
9536 puts most long word instructions on a single line. Use 8 bytes
9538 if ((info
->mach
& bfd_mach_l1om
) != 0)
9539 info
->bytes_per_line
= 8;
9541 info
->bytes_per_line
= 7;
9543 info
->private_data
= &priv
;
9544 priv
.max_fetched
= priv
.the_buffer
;
9545 priv
.insn_start
= pc
;
9548 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9556 start_codep
= priv
.the_buffer
;
9557 codep
= priv
.the_buffer
;
9559 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
9563 /* Getting here means we tried for data but didn't get it. That
9564 means we have an incomplete instruction of some sort. Just
9565 print the first byte as a prefix or a .byte pseudo-op. */
9566 if (codep
> priv
.the_buffer
)
9568 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
9570 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
9573 /* Just print the first byte as a .byte instruction. */
9574 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
9575 (unsigned int) priv
.the_buffer
[0]);
9585 sizeflag
= priv
.orig_sizeflag
;
9587 if (!ckprefix () || rex_used
)
9589 /* Too many prefixes or unused REX prefixes. */
9591 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
9593 (*info
->fprintf_func
) (info
->stream
, "%s%s",
9595 prefix_name (all_prefixes
[i
], sizeflag
));
9601 FETCH_DATA (info
, codep
+ 1);
9602 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
9604 if (((prefixes
& PREFIX_FWAIT
)
9605 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
9607 /* Handle prefixes before fwait. */
9608 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
9610 (*info
->fprintf_func
) (info
->stream
, "%s ",
9611 prefix_name (all_prefixes
[i
], sizeflag
));
9612 (*info
->fprintf_func
) (info
->stream
, "fwait");
9618 unsigned char threebyte
;
9621 FETCH_DATA (info
, codep
+ 1);
9623 dp
= &dis386_twobyte
[threebyte
];
9624 need_modrm
= twobyte_has_modrm
[threebyte
];
9629 dp
= &dis386
[*codep
];
9630 need_modrm
= onebyte_has_modrm
[*codep
];
9634 /* Save sizeflag for printing the extra prefixes later before updating
9635 it for mnemonic and operand processing. The prefix names depend
9636 only on the address mode. */
9637 orig_sizeflag
= sizeflag
;
9638 if (prefixes
& PREFIX_ADDR
)
9640 if ((prefixes
& PREFIX_DATA
))
9646 FETCH_DATA (info
, codep
+ 1);
9647 modrm
.mod
= (*codep
>> 6) & 3;
9648 modrm
.reg
= (*codep
>> 3) & 7;
9649 modrm
.rm
= *codep
& 7;
9652 memset (&modrm
, 0, sizeof (modrm
));
9655 memset (&vex
, 0, sizeof (vex
));
9657 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
9659 get_sib (info
, sizeflag
);
9664 dp
= get_valid_dis386 (dp
, info
);
9665 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
9667 get_sib (info
, sizeflag
);
9668 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9671 op_ad
= MAX_OPERANDS
- 1 - i
;
9673 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
9674 /* For EVEX instruction after the last operand masking
9675 should be printed. */
9676 if (i
== 0 && vex
.evex
)
9678 /* Don't print {%k0}. */
9679 if (vex
.mask_register_specifier
)
9682 oappend (names_mask
[vex
.mask_register_specifier
]);
9688 /* S/G insns require a mask and don't allow
9690 if ((dp
->op
[0].bytemode
== vex_vsib_d_w_dq_mode
9691 || dp
->op
[0].bytemode
== vex_vsib_q_w_dq_mode
)
9692 && (vex
.mask_register_specifier
== 0 || vex
.zeroing
))
9699 /* Clear instruction information. */
9702 the_info
->insn_info_valid
= 0;
9703 the_info
->branch_delay_insns
= 0;
9704 the_info
->data_size
= 0;
9705 the_info
->insn_type
= dis_noninsn
;
9706 the_info
->target
= 0;
9707 the_info
->target2
= 0;
9710 /* Reset jump operation indicator. */
9714 int jump_detection
= 0;
9716 /* Extract flags. */
9717 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9719 if ((dp
->op
[i
].rtn
== OP_J
)
9720 || (dp
->op
[i
].rtn
== OP_indirE
))
9721 jump_detection
|= 1;
9722 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
9723 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
9724 jump_detection
|= 2;
9725 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
9726 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
9727 jump_detection
|= 4;
9730 /* Determine if this is a jump or branch. */
9731 if ((jump_detection
& 0x3) == 0x3)
9734 if (jump_detection
& 0x4)
9735 the_info
->insn_type
= dis_condbranch
;
9737 the_info
->insn_type
=
9738 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
9739 ? dis_jsr
: dis_branch
;
9743 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9744 are all 0s in inverted form. */
9745 if (need_vex
&& vex
.register_specifier
!= 0)
9747 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9748 return end_codep
- priv
.the_buffer
;
9751 /* If EVEX.z is set, there must be an actual mask register in use. */
9752 if (vex
.zeroing
&& vex
.mask_register_specifier
== 0)
9754 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9755 return end_codep
- priv
.the_buffer
;
9758 switch (dp
->prefix_requirement
)
9761 /* If only the data prefix is marked as mandatory, its absence renders
9762 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9763 if (need_vex
? !vex
.prefix
: !(prefixes
& PREFIX_DATA
))
9765 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9766 return end_codep
- priv
.the_buffer
;
9768 used_prefixes
|= PREFIX_DATA
;
9771 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9772 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9773 used by putop and MMX/SSE operand and may be overridden by the
9774 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9777 ? vex
.prefix
== REPE_PREFIX_OPCODE
9778 || vex
.prefix
== REPNE_PREFIX_OPCODE
9780 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9782 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
9784 ? vex
.prefix
== DATA_PREFIX_OPCODE
9786 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
9788 && (used_prefixes
& PREFIX_DATA
) == 0))
9789 || (vex
.evex
&& dp
->prefix_requirement
!= PREFIX_DATA
9790 && !vex
.w
!= !(used_prefixes
& PREFIX_DATA
)))
9792 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9793 return end_codep
- priv
.the_buffer
;
9797 case PREFIX_IGNORED
:
9798 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9799 origins in all_prefixes. */
9800 used_prefixes
&= ~PREFIX_OPCODE
;
9801 if (last_data_prefix
>= 0)
9802 all_prefixes
[last_data_prefix
] = 0x66;
9803 if (last_repz_prefix
>= 0)
9804 all_prefixes
[last_repz_prefix
] = 0xf3;
9805 if (last_repnz_prefix
>= 0)
9806 all_prefixes
[last_repnz_prefix
] = 0xf2;
9810 /* Check if the REX prefix is used. */
9811 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
9812 all_prefixes
[last_rex_prefix
] = 0;
9814 /* Check if the SEG prefix is used. */
9815 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
9816 | PREFIX_FS
| PREFIX_GS
)) != 0
9817 && (used_prefixes
& active_seg_prefix
) != 0)
9818 all_prefixes
[last_seg_prefix
] = 0;
9820 /* Check if the ADDR prefix is used. */
9821 if ((prefixes
& PREFIX_ADDR
) != 0
9822 && (used_prefixes
& PREFIX_ADDR
) != 0)
9823 all_prefixes
[last_addr_prefix
] = 0;
9825 /* Check if the DATA prefix is used. */
9826 if ((prefixes
& PREFIX_DATA
) != 0
9827 && (used_prefixes
& PREFIX_DATA
) != 0
9829 all_prefixes
[last_data_prefix
] = 0;
9831 /* Print the extra prefixes. */
9833 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
9834 if (all_prefixes
[i
])
9837 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
9840 prefix_length
+= strlen (name
) + 1;
9841 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
9844 /* Check maximum code length. */
9845 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
9847 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9848 return MAX_CODE_LENGTH
;
9851 obufp
= mnemonicendp
;
9852 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
9855 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
9857 /* The enter and bound instructions are printed with operands in the same
9858 order as the intel book; everything else is printed in reverse order. */
9859 if (intel_syntax
|| two_source_ops
)
9863 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9864 op_txt
[i
] = op_out
[i
];
9866 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
9867 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
9869 op_txt
[2] = op_out
[3];
9870 op_txt
[3] = op_out
[2];
9873 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
9875 op_ad
= op_index
[i
];
9876 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
9877 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
9878 riprel
= op_riprel
[i
];
9879 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
9880 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
9885 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9886 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
9890 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9894 (*info
->fprintf_func
) (info
->stream
, ",");
9895 if (op_index
[i
] != -1 && !op_riprel
[i
])
9897 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
9899 if (the_info
&& op_is_jump
)
9901 the_info
->insn_info_valid
= 1;
9902 the_info
->branch_delay_insns
= 0;
9903 the_info
->data_size
= 0;
9904 the_info
->target
= target
;
9905 the_info
->target2
= 0;
9907 (*info
->print_address_func
) (target
, info
);
9910 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
9914 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9915 if (op_index
[i
] != -1 && op_riprel
[i
])
9917 (*info
->fprintf_func
) (info
->stream
, " # ");
9918 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
9919 + op_address
[op_index
[i
]]), info
);
9922 return codep
- priv
.the_buffer
;
9925 static const char *float_mem
[] = {
10000 static const unsigned char float_mem_mode
[] = {
10075 #define ST { OP_ST, 0 }
10076 #define STi { OP_STi, 0 }
10078 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10079 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10080 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10081 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10082 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10083 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10084 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10085 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10086 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10088 static const struct dis386 float_reg
[][8] = {
10091 { "fadd", { ST
, STi
}, 0 },
10092 { "fmul", { ST
, STi
}, 0 },
10093 { "fcom", { STi
}, 0 },
10094 { "fcomp", { STi
}, 0 },
10095 { "fsub", { ST
, STi
}, 0 },
10096 { "fsubr", { ST
, STi
}, 0 },
10097 { "fdiv", { ST
, STi
}, 0 },
10098 { "fdivr", { ST
, STi
}, 0 },
10102 { "fld", { STi
}, 0 },
10103 { "fxch", { STi
}, 0 },
10113 { "fcmovb", { ST
, STi
}, 0 },
10114 { "fcmove", { ST
, STi
}, 0 },
10115 { "fcmovbe",{ ST
, STi
}, 0 },
10116 { "fcmovu", { ST
, STi
}, 0 },
10124 { "fcmovnb",{ ST
, STi
}, 0 },
10125 { "fcmovne",{ ST
, STi
}, 0 },
10126 { "fcmovnbe",{ ST
, STi
}, 0 },
10127 { "fcmovnu",{ ST
, STi
}, 0 },
10129 { "fucomi", { ST
, STi
}, 0 },
10130 { "fcomi", { ST
, STi
}, 0 },
10135 { "fadd", { STi
, ST
}, 0 },
10136 { "fmul", { STi
, ST
}, 0 },
10139 { "fsub{!M|r}", { STi
, ST
}, 0 },
10140 { "fsub{M|}", { STi
, ST
}, 0 },
10141 { "fdiv{!M|r}", { STi
, ST
}, 0 },
10142 { "fdiv{M|}", { STi
, ST
}, 0 },
10146 { "ffree", { STi
}, 0 },
10148 { "fst", { STi
}, 0 },
10149 { "fstp", { STi
}, 0 },
10150 { "fucom", { STi
}, 0 },
10151 { "fucomp", { STi
}, 0 },
10157 { "faddp", { STi
, ST
}, 0 },
10158 { "fmulp", { STi
, ST
}, 0 },
10161 { "fsub{!M|r}p", { STi
, ST
}, 0 },
10162 { "fsub{M|}p", { STi
, ST
}, 0 },
10163 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
10164 { "fdiv{M|}p", { STi
, ST
}, 0 },
10168 { "ffreep", { STi
}, 0 },
10173 { "fucomip", { ST
, STi
}, 0 },
10174 { "fcomip", { ST
, STi
}, 0 },
10179 static char *fgrps
[][8] = {
10182 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10187 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10192 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10197 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10202 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10207 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10212 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10217 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10218 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10223 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10228 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10233 swap_operand (void)
10235 mnemonicendp
[0] = '.';
10236 mnemonicendp
[1] = 's';
10241 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
10242 int sizeflag ATTRIBUTE_UNUSED
)
10244 /* Skip mod/rm byte. */
10250 dofloat (int sizeflag
)
10252 const struct dis386
*dp
;
10253 unsigned char floatop
;
10255 floatop
= codep
[-1];
10257 if (modrm
.mod
!= 3)
10259 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
10261 putop (float_mem
[fp_indx
], sizeflag
);
10264 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
10267 /* Skip mod/rm byte. */
10271 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
10272 if (dp
->name
== NULL
)
10274 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
10276 /* Instruction fnstsw is only one with strange arg. */
10277 if (floatop
== 0xdf && codep
[-1] == 0xe0)
10278 strcpy (op_out
[0], names16
[0]);
10282 putop (dp
->name
, sizeflag
);
10287 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
10292 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
10296 /* Like oappend (below), but S is a string starting with '%'.
10297 In Intel syntax, the '%' is elided. */
10299 oappend_maybe_intel (const char *s
)
10301 oappend (s
+ intel_syntax
);
10305 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10307 oappend_maybe_intel ("%st");
10311 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10313 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
10314 oappend_maybe_intel (scratchbuf
);
10317 /* Capital letters in template are macros. */
10319 putop (const char *in_template
, int sizeflag
)
10324 unsigned int l
= 0, len
= 0;
10327 for (p
= in_template
; *p
; p
++)
10331 if (l
>= sizeof (last
) || !ISUPPER (*p
))
10350 while (*++p
!= '|')
10351 if (*p
== '}' || *p
== '\0')
10357 while (*++p
!= '}')
10369 if ((need_modrm
&& modrm
.mod
!= 3)
10370 || (sizeflag
& SUFFIX_ALWAYS
))
10379 if (sizeflag
& SUFFIX_ALWAYS
)
10382 else if (l
== 1 && last
[0] == 'L')
10384 if (address_mode
== mode_64bit
10385 && !(prefixes
& PREFIX_ADDR
))
10398 if (intel_syntax
&& !alt
)
10400 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10402 if (sizeflag
& DFLAG
)
10403 *obufp
++ = intel_syntax
? 'd' : 'l';
10405 *obufp
++ = intel_syntax
? 'w' : 's';
10406 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10410 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
10413 if (modrm
.mod
== 3)
10419 if (sizeflag
& DFLAG
)
10420 *obufp
++ = intel_syntax
? 'd' : 'l';
10423 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10429 case 'E': /* For jcxz/jecxz */
10430 if (address_mode
== mode_64bit
)
10432 if (sizeflag
& AFLAG
)
10438 if (sizeflag
& AFLAG
)
10440 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10445 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
10447 if (sizeflag
& AFLAG
)
10448 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10450 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
10451 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10455 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
10457 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
10461 if (!(rex
& REX_W
))
10462 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10467 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
10468 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
10470 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
10474 /* Set active_seg_prefix even if not set in 64-bit mode
10475 because here it is a valid branch hint. */
10476 if (prefixes
& PREFIX_DS
)
10478 active_seg_prefix
= PREFIX_DS
;
10483 active_seg_prefix
= PREFIX_CS
;
10498 if (intel_mnemonic
!= cond
)
10502 if ((prefixes
& PREFIX_FWAIT
) == 0)
10505 used_prefixes
|= PREFIX_FWAIT
;
10511 else if (intel_syntax
&& (sizeflag
& DFLAG
))
10515 if (!(rex
& REX_W
))
10516 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10519 if (address_mode
== mode_64bit
10520 && (isa64
== intel64
|| (rex
& REX_W
)
10521 || !(prefixes
& PREFIX_DATA
)))
10523 if (sizeflag
& SUFFIX_ALWAYS
)
10527 /* Fall through. */
10531 if ((modrm
.mod
== 3 || !cond
)
10532 && !(sizeflag
& SUFFIX_ALWAYS
))
10534 /* Fall through. */
10536 if ((!(rex
& REX_W
) && (prefixes
& PREFIX_DATA
))
10537 || ((sizeflag
& SUFFIX_ALWAYS
)
10538 && address_mode
!= mode_64bit
))
10540 *obufp
++ = (sizeflag
& DFLAG
) ?
10541 intel_syntax
? 'd' : 'l' : 'w';
10542 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10544 else if (sizeflag
& SUFFIX_ALWAYS
)
10547 else if (l
== 1 && last
[0] == 'L')
10549 if ((prefixes
& PREFIX_DATA
)
10551 || (sizeflag
& SUFFIX_ALWAYS
))
10558 if (sizeflag
& DFLAG
)
10559 *obufp
++ = intel_syntax
? 'd' : 'l';
10562 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10572 if (intel_syntax
&& !alt
)
10575 if ((need_modrm
&& modrm
.mod
!= 3)
10576 || (sizeflag
& SUFFIX_ALWAYS
))
10582 if (sizeflag
& DFLAG
)
10583 *obufp
++ = intel_syntax
? 'd' : 'l';
10586 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10590 else if (l
== 1 && last
[0] == 'D')
10591 *obufp
++ = vex
.w
? 'q' : 'd';
10592 else if (l
== 1 && last
[0] == 'L')
10594 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
10595 : address_mode
!= mode_64bit
)
10602 else if((address_mode
== mode_64bit
&& cond
)
10603 || (sizeflag
& SUFFIX_ALWAYS
))
10604 *obufp
++ = intel_syntax
? 'd' : 'l';
10613 else if (sizeflag
& DFLAG
)
10622 if (intel_syntax
&& !p
[1]
10623 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
10625 if (!(rex
& REX_W
))
10626 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10634 if (sizeflag
& SUFFIX_ALWAYS
)
10640 if (sizeflag
& DFLAG
)
10644 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10648 else if (l
== 1 && last
[0] == 'L')
10650 if (address_mode
== mode_64bit
10651 && !(prefixes
& PREFIX_ADDR
))
10667 && (last
[0] == 'L' || last
[0] == 'X'))
10669 if (last
[0] == 'X')
10677 else if (rex
& REX_W
)
10690 /* operand size flag for cwtl, cbtw */
10699 else if (sizeflag
& DFLAG
)
10703 if (!(rex
& REX_W
))
10704 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10710 if (last
[0] == 'X')
10711 *obufp
++ = vex
.w
? 'd': 's';
10712 else if (last
[0] == 'B')
10713 *obufp
++ = vex
.w
? 'w': 'b';
10724 ? vex
.prefix
== DATA_PREFIX_OPCODE
10725 : prefixes
& PREFIX_DATA
)
10728 used_prefixes
|= PREFIX_DATA
;
10734 if (l
== 1 && last
[0] == 'X')
10739 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10741 switch (vex
.length
)
10761 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10763 if (!intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
10764 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10766 else if (l
== 1 && last
[0] == 'X')
10771 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10773 switch (vex
.length
)
10794 if (isa64
== intel64
&& (rex
& REX_W
))
10800 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10802 if (sizeflag
& DFLAG
)
10806 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10815 mnemonicendp
= obufp
;
10820 oappend (const char *s
)
10822 obufp
= stpcpy (obufp
, s
);
10828 /* Only print the active segment register. */
10829 if (!active_seg_prefix
)
10832 used_prefixes
|= active_seg_prefix
;
10833 switch (active_seg_prefix
)
10836 oappend_maybe_intel ("%cs:");
10839 oappend_maybe_intel ("%ds:");
10842 oappend_maybe_intel ("%ss:");
10845 oappend_maybe_intel ("%es:");
10848 oappend_maybe_intel ("%fs:");
10851 oappend_maybe_intel ("%gs:");
10859 OP_indirE (int bytemode
, int sizeflag
)
10863 OP_E (bytemode
, sizeflag
);
10867 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
10869 if (address_mode
== mode_64bit
)
10877 sprintf_vma (tmp
, disp
);
10878 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
10879 strcpy (buf
+ 2, tmp
+ i
);
10883 bfd_signed_vma v
= disp
;
10890 /* Check for possible overflow on 0x8000000000000000. */
10893 strcpy (buf
, "9223372036854775808");
10907 tmp
[28 - i
] = (v
% 10) + '0';
10911 strcpy (buf
, tmp
+ 29 - i
);
10917 sprintf (buf
, "0x%x", (unsigned int) disp
);
10919 sprintf (buf
, "%d", (int) disp
);
10923 /* Put DISP in BUF as signed hex number. */
10926 print_displacement (char *buf
, bfd_vma disp
)
10928 bfd_signed_vma val
= disp
;
10937 /* Check for possible overflow. */
10940 switch (address_mode
)
10943 strcpy (buf
+ j
, "0x8000000000000000");
10946 strcpy (buf
+ j
, "0x80000000");
10949 strcpy (buf
+ j
, "0x8000");
10959 sprintf_vma (tmp
, (bfd_vma
) val
);
10960 for (i
= 0; tmp
[i
] == '0'; i
++)
10962 if (tmp
[i
] == '\0')
10964 strcpy (buf
+ j
, tmp
+ i
);
10968 intel_operand_size (int bytemode
, int sizeflag
)
10971 && (bytemode
== x_mode
10972 || bytemode
== evex_half_bcst_xmmq_mode
))
10975 oappend ("QWORD PTR ");
10977 oappend ("DWORD PTR ");
10986 oappend ("BYTE PTR ");
10991 oappend ("WORD PTR ");
10994 if (address_mode
== mode_64bit
&& isa64
== intel64
)
10996 oappend ("QWORD PTR ");
10999 /* Fall through. */
11001 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11003 oappend ("QWORD PTR ");
11006 /* Fall through. */
11012 oappend ("QWORD PTR ");
11013 else if (bytemode
== dq_mode
)
11014 oappend ("DWORD PTR ");
11017 if (sizeflag
& DFLAG
)
11018 oappend ("DWORD PTR ");
11020 oappend ("WORD PTR ");
11021 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11025 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
11027 oappend ("WORD PTR ");
11028 if (!(rex
& REX_W
))
11029 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11032 if (sizeflag
& DFLAG
)
11033 oappend ("QWORD PTR ");
11035 oappend ("DWORD PTR ");
11036 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11039 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11040 oappend ("WORD PTR ");
11042 oappend ("DWORD PTR ");
11043 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11048 oappend ("DWORD PTR ");
11052 oappend ("QWORD PTR ");
11055 if (address_mode
== mode_64bit
)
11056 oappend ("QWORD PTR ");
11058 oappend ("DWORD PTR ");
11061 if (sizeflag
& DFLAG
)
11062 oappend ("FWORD PTR ");
11064 oappend ("DWORD PTR ");
11065 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11068 oappend ("TBYTE PTR ");
11072 case evex_x_gscat_mode
:
11073 case evex_x_nobcst_mode
:
11077 switch (vex
.length
)
11080 oappend ("XMMWORD PTR ");
11083 oappend ("YMMWORD PTR ");
11086 oappend ("ZMMWORD PTR ");
11093 oappend ("XMMWORD PTR ");
11096 oappend ("XMMWORD PTR ");
11099 oappend ("YMMWORD PTR ");
11102 case evex_half_bcst_xmmq_mode
:
11106 switch (vex
.length
)
11109 oappend ("QWORD PTR ");
11112 oappend ("XMMWORD PTR ");
11115 oappend ("YMMWORD PTR ");
11125 switch (vex
.length
)
11130 oappend ("BYTE PTR ");
11140 switch (vex
.length
)
11145 oappend ("WORD PTR ");
11155 switch (vex
.length
)
11160 oappend ("DWORD PTR ");
11170 switch (vex
.length
)
11175 oappend ("QWORD PTR ");
11185 switch (vex
.length
)
11188 oappend ("WORD PTR ");
11191 oappend ("DWORD PTR ");
11194 oappend ("QWORD PTR ");
11204 switch (vex
.length
)
11207 oappend ("DWORD PTR ");
11210 oappend ("QWORD PTR ");
11213 oappend ("XMMWORD PTR ");
11223 switch (vex
.length
)
11226 oappend ("QWORD PTR ");
11229 oappend ("YMMWORD PTR ");
11232 oappend ("ZMMWORD PTR ");
11242 switch (vex
.length
)
11246 oappend ("XMMWORD PTR ");
11253 oappend ("OWORD PTR ");
11255 case vex_scalar_w_dq_mode
:
11260 oappend ("QWORD PTR ");
11262 oappend ("DWORD PTR ");
11264 case vex_vsib_d_w_dq_mode
:
11265 case vex_vsib_q_w_dq_mode
:
11270 oappend ("QWORD PTR ");
11272 oappend ("DWORD PTR ");
11275 if (!need_vex
|| vex
.length
!= 128)
11278 oappend ("DWORD PTR ");
11280 oappend ("BYTE PTR ");
11286 oappend ("QWORD PTR ");
11288 oappend ("WORD PTR ");
11298 OP_E_register (int bytemode
, int sizeflag
)
11300 int reg
= modrm
.rm
;
11301 const char **names
;
11307 if ((sizeflag
& SUFFIX_ALWAYS
)
11308 && (bytemode
== b_swap_mode
11309 || bytemode
== bnd_swap_mode
11310 || bytemode
== v_swap_mode
))
11337 names
= address_mode
== mode_64bit
? names64
: names32
;
11340 case bnd_swap_mode
:
11349 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11354 /* Fall through. */
11356 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11362 /* Fall through. */
11372 else if (bytemode
!= v_mode
&& bytemode
!= v_swap_mode
)
11376 if (sizeflag
& DFLAG
)
11380 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11384 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11388 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11391 names
= (address_mode
== mode_64bit
11392 ? names64
: names32
);
11393 if (!(prefixes
& PREFIX_ADDR
))
11394 names
= (address_mode
== mode_16bit
11395 ? names16
: names
);
11398 /* Remove "addr16/addr32". */
11399 all_prefixes
[last_addr_prefix
] = 0;
11400 names
= (address_mode
!= mode_32bit
11401 ? names32
: names16
);
11402 used_prefixes
|= PREFIX_ADDR
;
11412 names
= names_mask
;
11417 oappend (INTERNAL_DISASSEMBLER_ERROR
);
11420 oappend (names
[reg
]);
11424 OP_E_memory (int bytemode
, int sizeflag
)
11427 int add
= (rex
& REX_B
) ? 8 : 0;
11433 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11435 && bytemode
!= x_mode
11436 && bytemode
!= evex_half_bcst_xmmq_mode
)
11454 if (address_mode
!= mode_64bit
)
11464 case vex_scalar_w_dq_mode
:
11465 case vex_vsib_d_w_dq_mode
:
11466 case vex_vsib_q_w_dq_mode
:
11467 case evex_x_gscat_mode
:
11468 shift
= vex
.w
? 3 : 2;
11471 case evex_half_bcst_xmmq_mode
:
11474 shift
= vex
.w
? 3 : 2;
11477 /* Fall through. */
11482 case evex_x_nobcst_mode
:
11484 switch (vex
.length
)
11498 /* Make necessary corrections to shift for modes that need it. */
11499 if (bytemode
== xmmq_mode
11500 || bytemode
== evex_half_bcst_xmmq_mode
11501 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
11503 else if (bytemode
== xmmqd_mode
)
11505 else if (bytemode
== xmmdw_mode
)
11520 shift
= vex
.w
? 1 : 0;
11531 intel_operand_size (bytemode
, sizeflag
);
11534 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11536 /* 32/64 bit address mode */
11546 int addr32flag
= !((sizeflag
& AFLAG
)
11547 || bytemode
== v_bnd_mode
11548 || bytemode
== v_bndmk_mode
11549 || bytemode
== bnd_mode
11550 || bytemode
== bnd_swap_mode
);
11551 bool check_gather
= false;
11552 const char **indexes64
= names64
;
11553 const char **indexes32
= names32
;
11563 vindex
= sib
.index
;
11569 case vex_vsib_d_w_dq_mode
:
11570 case vex_vsib_q_w_dq_mode
:
11577 check_gather
= obufp
== op_out
[1];
11581 switch (vex
.length
)
11584 indexes64
= indexes32
= names_xmm
;
11588 || bytemode
== vex_vsib_q_w_dq_mode
)
11589 indexes64
= indexes32
= names_ymm
;
11591 indexes64
= indexes32
= names_xmm
;
11595 || bytemode
== vex_vsib_q_w_dq_mode
)
11596 indexes64
= indexes32
= names_zmm
;
11598 indexes64
= indexes32
= names_ymm
;
11605 haveindex
= vindex
!= 4;
11614 /* Check for mandatory SIB. */
11615 if (bytemode
== vex_vsib_d_w_dq_mode
11616 || bytemode
== vex_vsib_q_w_dq_mode
11617 || bytemode
== vex_sibmem_mode
)
11623 rbase
= base
+ add
;
11631 if (address_mode
== mode_64bit
&& !havesib
)
11634 if (riprel
&& bytemode
== v_bndmk_mode
)
11642 FETCH_DATA (the_info
, codep
+ 1);
11644 if ((disp
& 0x80) != 0)
11646 if (vex
.evex
&& shift
> 0)
11659 && address_mode
!= mode_16bit
)
11661 if (address_mode
== mode_64bit
)
11665 /* Without base nor index registers, zero-extend the
11666 lower 32-bit displacement to 64 bits. */
11667 disp
= (unsigned int) disp
;
11674 /* In 32-bit mode, we need index register to tell [offset]
11675 from [eiz*1 + offset]. */
11680 havedisp
= (havebase
11682 || (havesib
&& (haveindex
|| scale
!= 0)));
11685 if (modrm
.mod
!= 0 || base
== 5)
11687 if (havedisp
|| riprel
)
11688 print_displacement (scratchbuf
, disp
);
11690 print_operand_value (scratchbuf
, 1, disp
);
11691 oappend (scratchbuf
);
11695 oappend (!addr32flag
? "(%rip)" : "(%eip)");
11699 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
11700 && (address_mode
!= mode_64bit
11701 || ((bytemode
!= v_bnd_mode
)
11702 && (bytemode
!= v_bndmk_mode
)
11703 && (bytemode
!= bnd_mode
)
11704 && (bytemode
!= bnd_swap_mode
))))
11705 used_prefixes
|= PREFIX_ADDR
;
11707 if (havedisp
|| (intel_syntax
&& riprel
))
11709 *obufp
++ = open_char
;
11710 if (intel_syntax
&& riprel
)
11713 oappend (!addr32flag
? "rip" : "eip");
11717 oappend (address_mode
== mode_64bit
&& !addr32flag
11718 ? names64
[rbase
] : names32
[rbase
]);
11721 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11722 print index to tell base + index from base. */
11726 || (havebase
&& base
!= ESP_REG_NUM
))
11728 if (!intel_syntax
|| havebase
)
11730 *obufp
++ = separator_char
;
11734 oappend (address_mode
== mode_64bit
&& !addr32flag
11735 ? indexes64
[vindex
] : indexes32
[vindex
]);
11737 oappend (address_mode
== mode_64bit
&& !addr32flag
11738 ? index64
: index32
);
11740 *obufp
++ = scale_char
;
11742 sprintf (scratchbuf
, "%d", 1 << scale
);
11743 oappend (scratchbuf
);
11747 && (disp
|| modrm
.mod
!= 0 || base
== 5))
11749 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
11754 else if (modrm
.mod
!= 1 && disp
!= -disp
)
11762 print_displacement (scratchbuf
, disp
);
11764 print_operand_value (scratchbuf
, 1, disp
);
11765 oappend (scratchbuf
);
11768 *obufp
++ = close_char
;
11773 /* Both XMM/YMM/ZMM registers must be distinct. */
11774 int modrm_reg
= modrm
.reg
;
11780 if (vindex
== modrm_reg
)
11781 oappend ("/(bad)");
11784 else if (intel_syntax
)
11786 if (modrm
.mod
!= 0 || base
== 5)
11788 if (!active_seg_prefix
)
11790 oappend (names_seg
[ds_reg
- es_reg
]);
11793 print_operand_value (scratchbuf
, 1, disp
);
11794 oappend (scratchbuf
);
11798 else if (bytemode
== v_bnd_mode
11799 || bytemode
== v_bndmk_mode
11800 || bytemode
== bnd_mode
11801 || bytemode
== bnd_swap_mode
11802 || bytemode
== vex_vsib_d_w_dq_mode
11803 || bytemode
== vex_vsib_q_w_dq_mode
)
11810 /* 16 bit address mode */
11811 used_prefixes
|= prefixes
& PREFIX_ADDR
;
11818 if ((disp
& 0x8000) != 0)
11823 FETCH_DATA (the_info
, codep
+ 1);
11825 if ((disp
& 0x80) != 0)
11827 if (vex
.evex
&& shift
> 0)
11832 if ((disp
& 0x8000) != 0)
11838 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
11840 print_displacement (scratchbuf
, disp
);
11841 oappend (scratchbuf
);
11844 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
11846 *obufp
++ = open_char
;
11848 oappend (index16
[modrm
.rm
]);
11850 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
11852 if ((bfd_signed_vma
) disp
>= 0)
11857 else if (modrm
.mod
!= 1)
11864 print_displacement (scratchbuf
, disp
);
11865 oappend (scratchbuf
);
11868 *obufp
++ = close_char
;
11871 else if (intel_syntax
)
11873 if (!active_seg_prefix
)
11875 oappend (names_seg
[ds_reg
- es_reg
]);
11878 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
11879 oappend (scratchbuf
);
11883 && (bytemode
== x_mode
11884 || bytemode
== evex_half_bcst_xmmq_mode
))
11887 || bytemode
== evex_half_bcst_xmmq_mode
)
11889 switch (vex
.length
)
11892 oappend ("{1to2}");
11895 oappend ("{1to4}");
11898 oappend ("{1to8}");
11906 switch (vex
.length
)
11909 oappend ("{1to4}");
11912 oappend ("{1to8}");
11915 oappend ("{1to16}");
11925 OP_E (int bytemode
, int sizeflag
)
11927 /* Skip mod/rm byte. */
11931 if (modrm
.mod
== 3)
11932 OP_E_register (bytemode
, sizeflag
);
11934 OP_E_memory (bytemode
, sizeflag
);
11938 OP_G (int bytemode
, int sizeflag
)
11941 const char **names
;
11951 oappend (names8rex
[modrm
.reg
+ add
]);
11953 oappend (names8
[modrm
.reg
+ add
]);
11956 oappend (names16
[modrm
.reg
+ add
]);
11961 oappend (names32
[modrm
.reg
+ add
]);
11964 oappend (names64
[modrm
.reg
+ add
]);
11967 if (modrm
.reg
> 0x3)
11972 oappend (names_bnd
[modrm
.reg
]);
11982 oappend (names64
[modrm
.reg
+ add
]);
11983 else if (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
)
11984 oappend (names32
[modrm
.reg
+ add
]);
11987 if (sizeflag
& DFLAG
)
11988 oappend (names32
[modrm
.reg
+ add
]);
11990 oappend (names16
[modrm
.reg
+ add
]);
11991 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11995 names
= (address_mode
== mode_64bit
11996 ? names64
: names32
);
11997 if (!(prefixes
& PREFIX_ADDR
))
11999 if (address_mode
== mode_16bit
)
12004 /* Remove "addr16/addr32". */
12005 all_prefixes
[last_addr_prefix
] = 0;
12006 names
= (address_mode
!= mode_32bit
12007 ? names32
: names16
);
12008 used_prefixes
|= PREFIX_ADDR
;
12010 oappend (names
[modrm
.reg
+ add
]);
12013 if (address_mode
== mode_64bit
)
12014 oappend (names64
[modrm
.reg
+ add
]);
12016 oappend (names32
[modrm
.reg
+ add
]);
12020 if ((modrm
.reg
+ add
) > 0x7)
12025 oappend (names_mask
[modrm
.reg
+ add
]);
12028 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12041 FETCH_DATA (the_info
, codep
+ 8);
12042 a
= *codep
++ & 0xff;
12043 a
|= (*codep
++ & 0xff) << 8;
12044 a
|= (*codep
++ & 0xff) << 16;
12045 a
|= (*codep
++ & 0xffu
) << 24;
12046 b
= *codep
++ & 0xff;
12047 b
|= (*codep
++ & 0xff) << 8;
12048 b
|= (*codep
++ & 0xff) << 16;
12049 b
|= (*codep
++ & 0xffu
) << 24;
12050 x
= a
+ ((bfd_vma
) b
<< 32);
12058 static bfd_signed_vma
12063 FETCH_DATA (the_info
, codep
+ 4);
12064 x
= *codep
++ & (bfd_vma
) 0xff;
12065 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12066 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12067 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12071 static bfd_signed_vma
12076 FETCH_DATA (the_info
, codep
+ 4);
12077 x
= *codep
++ & (bfd_vma
) 0xff;
12078 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12079 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12080 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12082 x
= (x
^ ((bfd_vma
) 1 << 31)) - ((bfd_vma
) 1 << 31);
12092 FETCH_DATA (the_info
, codep
+ 2);
12093 x
= *codep
++ & 0xff;
12094 x
|= (*codep
++ & 0xff) << 8;
12099 set_op (bfd_vma op
, int riprel
)
12101 op_index
[op_ad
] = op_ad
;
12102 if (address_mode
== mode_64bit
)
12104 op_address
[op_ad
] = op
;
12105 op_riprel
[op_ad
] = riprel
;
12109 /* Mask to get a 32-bit address. */
12110 op_address
[op_ad
] = op
& 0xffffffff;
12111 op_riprel
[op_ad
] = riprel
& 0xffffffff;
12116 OP_REG (int code
, int sizeflag
)
12123 case es_reg
: case ss_reg
: case cs_reg
:
12124 case ds_reg
: case fs_reg
: case gs_reg
:
12125 oappend (names_seg
[code
- es_reg
]);
12137 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
12138 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
12139 s
= names16
[code
- ax_reg
+ add
];
12141 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
12143 /* Fall through. */
12144 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
12146 s
= names8rex
[code
- al_reg
+ add
];
12148 s
= names8
[code
- al_reg
];
12150 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
12151 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
12152 if (address_mode
== mode_64bit
12153 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12155 s
= names64
[code
- rAX_reg
+ add
];
12158 code
+= eAX_reg
- rAX_reg
;
12159 /* Fall through. */
12160 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
12161 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
12164 s
= names64
[code
- eAX_reg
+ add
];
12167 if (sizeflag
& DFLAG
)
12168 s
= names32
[code
- eAX_reg
+ add
];
12170 s
= names16
[code
- eAX_reg
+ add
];
12171 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12175 s
= INTERNAL_DISASSEMBLER_ERROR
;
12182 OP_IMREG (int code
, int sizeflag
)
12194 case al_reg
: case cl_reg
:
12195 s
= names8
[code
- al_reg
];
12204 /* Fall through. */
12205 case z_mode_ax_reg
:
12206 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12210 if (!(rex
& REX_W
))
12211 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12214 s
= INTERNAL_DISASSEMBLER_ERROR
;
12221 OP_I (int bytemode
, int sizeflag
)
12224 bfd_signed_vma mask
= -1;
12229 FETCH_DATA (the_info
, codep
+ 1);
12239 if (sizeflag
& DFLAG
)
12249 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12265 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12270 scratchbuf
[0] = '$';
12271 print_operand_value (scratchbuf
+ 1, 1, op
);
12272 oappend_maybe_intel (scratchbuf
);
12273 scratchbuf
[0] = '\0';
12277 OP_I64 (int bytemode
, int sizeflag
)
12279 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
12281 OP_I (bytemode
, sizeflag
);
12287 scratchbuf
[0] = '$';
12288 print_operand_value (scratchbuf
+ 1, 1, get64 ());
12289 oappend_maybe_intel (scratchbuf
);
12290 scratchbuf
[0] = '\0';
12294 OP_sI (int bytemode
, int sizeflag
)
12302 FETCH_DATA (the_info
, codep
+ 1);
12304 if ((op
& 0x80) != 0)
12306 if (bytemode
== b_T_mode
)
12308 if (address_mode
!= mode_64bit
12309 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12311 /* The operand-size prefix is overridden by a REX prefix. */
12312 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12320 if (!(rex
& REX_W
))
12322 if (sizeflag
& DFLAG
)
12330 /* The operand-size prefix is overridden by a REX prefix. */
12331 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12337 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12341 scratchbuf
[0] = '$';
12342 print_operand_value (scratchbuf
+ 1, 1, op
);
12343 oappend_maybe_intel (scratchbuf
);
12347 OP_J (int bytemode
, int sizeflag
)
12351 bfd_vma segment
= 0;
12356 FETCH_DATA (the_info
, codep
+ 1);
12358 if ((disp
& 0x80) != 0)
12363 if ((sizeflag
& DFLAG
)
12364 || (address_mode
== mode_64bit
12365 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
12366 || (rex
& REX_W
))))
12371 if ((disp
& 0x8000) != 0)
12373 /* In 16bit mode, address is wrapped around at 64k within
12374 the same segment. Otherwise, a data16 prefix on a jump
12375 instruction means that the pc is masked to 16 bits after
12376 the displacement is added! */
12378 if ((prefixes
& PREFIX_DATA
) == 0)
12379 segment
= ((start_pc
+ (codep
- start_codep
))
12380 & ~((bfd_vma
) 0xffff));
12382 if (address_mode
!= mode_64bit
12383 || (isa64
!= intel64
&& !(rex
& REX_W
)))
12384 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12387 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12390 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
12392 print_operand_value (scratchbuf
, 1, disp
);
12393 oappend (scratchbuf
);
12397 OP_SEG (int bytemode
, int sizeflag
)
12399 if (bytemode
== w_mode
)
12400 oappend (names_seg
[modrm
.reg
]);
12402 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
12406 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
12410 if (sizeflag
& DFLAG
)
12420 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12422 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
12424 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
12425 oappend (scratchbuf
);
12429 OP_OFF (int bytemode
, int sizeflag
)
12433 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12434 intel_operand_size (bytemode
, sizeflag
);
12437 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12444 if (!active_seg_prefix
)
12446 oappend (names_seg
[ds_reg
- es_reg
]);
12450 print_operand_value (scratchbuf
, 1, off
);
12451 oappend (scratchbuf
);
12455 OP_OFF64 (int bytemode
, int sizeflag
)
12459 if (address_mode
!= mode_64bit
12460 || (prefixes
& PREFIX_ADDR
))
12462 OP_OFF (bytemode
, sizeflag
);
12466 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12467 intel_operand_size (bytemode
, sizeflag
);
12474 if (!active_seg_prefix
)
12476 oappend (names_seg
[ds_reg
- es_reg
]);
12480 print_operand_value (scratchbuf
, 1, off
);
12481 oappend (scratchbuf
);
12485 ptr_reg (int code
, int sizeflag
)
12489 *obufp
++ = open_char
;
12490 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12491 if (address_mode
== mode_64bit
)
12493 if (!(sizeflag
& AFLAG
))
12494 s
= names32
[code
- eAX_reg
];
12496 s
= names64
[code
- eAX_reg
];
12498 else if (sizeflag
& AFLAG
)
12499 s
= names32
[code
- eAX_reg
];
12501 s
= names16
[code
- eAX_reg
];
12503 *obufp
++ = close_char
;
12508 OP_ESreg (int code
, int sizeflag
)
12514 case 0x6d: /* insw/insl */
12515 intel_operand_size (z_mode
, sizeflag
);
12517 case 0xa5: /* movsw/movsl/movsq */
12518 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12519 case 0xab: /* stosw/stosl */
12520 case 0xaf: /* scasw/scasl */
12521 intel_operand_size (v_mode
, sizeflag
);
12524 intel_operand_size (b_mode
, sizeflag
);
12527 oappend_maybe_intel ("%es:");
12528 ptr_reg (code
, sizeflag
);
12532 OP_DSreg (int code
, int sizeflag
)
12538 case 0x6f: /* outsw/outsl */
12539 intel_operand_size (z_mode
, sizeflag
);
12541 case 0xa5: /* movsw/movsl/movsq */
12542 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12543 case 0xad: /* lodsw/lodsl/lodsq */
12544 intel_operand_size (v_mode
, sizeflag
);
12547 intel_operand_size (b_mode
, sizeflag
);
12550 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12551 default segment register DS is printed. */
12552 if (!active_seg_prefix
)
12553 active_seg_prefix
= PREFIX_DS
;
12555 ptr_reg (code
, sizeflag
);
12559 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12567 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
12569 all_prefixes
[last_lock_prefix
] = 0;
12570 used_prefixes
|= PREFIX_LOCK
;
12575 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
12576 oappend_maybe_intel (scratchbuf
);
12580 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12589 sprintf (scratchbuf
, "dr%d", modrm
.reg
+ add
);
12591 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
12592 oappend (scratchbuf
);
12596 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12598 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
12599 oappend_maybe_intel (scratchbuf
);
12603 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12605 int reg
= modrm
.reg
;
12606 const char **names
;
12608 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12609 if (prefixes
& PREFIX_DATA
)
12618 oappend (names
[reg
]);
12622 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
12624 int reg
= modrm
.reg
;
12625 const char **names
;
12636 if (bytemode
== xmmq_mode
12637 || bytemode
== evex_half_bcst_xmmq_mode
)
12639 switch (vex
.length
)
12652 else if (bytemode
== ymm_mode
)
12654 else if (bytemode
== tmm_mode
)
12665 && bytemode
!= xmm_mode
12666 && bytemode
!= scalar_mode
)
12668 switch (vex
.length
)
12675 || bytemode
!= vex_vsib_q_w_dq_mode
)
12682 || bytemode
!= vex_vsib_q_w_dq_mode
)
12693 oappend (names
[reg
]);
12697 OP_EM (int bytemode
, int sizeflag
)
12700 const char **names
;
12702 if (modrm
.mod
!= 3)
12705 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
12707 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12708 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12710 OP_E (bytemode
, sizeflag
);
12714 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
12717 /* Skip mod/rm byte. */
12720 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12722 if (prefixes
& PREFIX_DATA
)
12731 oappend (names
[reg
]);
12734 /* cvt* are the only instructions in sse2 which have
12735 both SSE and MMX operands and also have 0x66 prefix
12736 in their opcode. 0x66 was originally used to differentiate
12737 between SSE and MMX instruction(operands). So we have to handle the
12738 cvt* separately using OP_EMC and OP_MXC */
12740 OP_EMC (int bytemode
, int sizeflag
)
12742 if (modrm
.mod
!= 3)
12744 if (intel_syntax
&& bytemode
== v_mode
)
12746 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12747 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12749 OP_E (bytemode
, sizeflag
);
12753 /* Skip mod/rm byte. */
12756 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12757 oappend (names_mm
[modrm
.rm
]);
12761 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12763 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12764 oappend (names_mm
[modrm
.reg
]);
12768 OP_EX (int bytemode
, int sizeflag
)
12771 const char **names
;
12773 /* Skip mod/rm byte. */
12777 if (modrm
.mod
!= 3)
12779 OP_E_memory (bytemode
, sizeflag
);
12794 if ((sizeflag
& SUFFIX_ALWAYS
)
12795 && (bytemode
== x_swap_mode
12796 || bytemode
== d_swap_mode
12797 || bytemode
== q_swap_mode
))
12801 && bytemode
!= xmm_mode
12802 && bytemode
!= xmmdw_mode
12803 && bytemode
!= xmmqd_mode
12804 && bytemode
!= xmm_mb_mode
12805 && bytemode
!= xmm_mw_mode
12806 && bytemode
!= xmm_md_mode
12807 && bytemode
!= xmm_mq_mode
12808 && bytemode
!= xmmq_mode
12809 && bytemode
!= evex_half_bcst_xmmq_mode
12810 && bytemode
!= ymm_mode
12811 && bytemode
!= tmm_mode
12812 && bytemode
!= vex_scalar_w_dq_mode
)
12814 switch (vex
.length
)
12829 else if (bytemode
== xmmq_mode
12830 || bytemode
== evex_half_bcst_xmmq_mode
)
12832 switch (vex
.length
)
12845 else if (bytemode
== tmm_mode
)
12855 else if (bytemode
== ymm_mode
)
12859 oappend (names
[reg
]);
12863 OP_MS (int bytemode
, int sizeflag
)
12865 if (modrm
.mod
== 3)
12866 OP_EM (bytemode
, sizeflag
);
12872 OP_XS (int bytemode
, int sizeflag
)
12874 if (modrm
.mod
== 3)
12875 OP_EX (bytemode
, sizeflag
);
12881 OP_M (int bytemode
, int sizeflag
)
12883 if (modrm
.mod
== 3)
12884 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12887 OP_E (bytemode
, sizeflag
);
12891 OP_0f07 (int bytemode
, int sizeflag
)
12893 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
12896 OP_E (bytemode
, sizeflag
);
12899 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12900 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12903 NOP_Fixup1 (int bytemode
, int sizeflag
)
12905 if ((prefixes
& PREFIX_DATA
) != 0
12908 && address_mode
== mode_64bit
))
12909 OP_REG (bytemode
, sizeflag
);
12911 strcpy (obuf
, "nop");
12915 NOP_Fixup2 (int bytemode
, int sizeflag
)
12917 if ((prefixes
& PREFIX_DATA
) != 0
12920 && address_mode
== mode_64bit
))
12921 OP_IMREG (bytemode
, sizeflag
);
12924 static const char *const Suffix3DNow
[] = {
12925 /* 00 */ NULL
, NULL
, NULL
, NULL
,
12926 /* 04 */ NULL
, NULL
, NULL
, NULL
,
12927 /* 08 */ NULL
, NULL
, NULL
, NULL
,
12928 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
12929 /* 10 */ NULL
, NULL
, NULL
, NULL
,
12930 /* 14 */ NULL
, NULL
, NULL
, NULL
,
12931 /* 18 */ NULL
, NULL
, NULL
, NULL
,
12932 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
12933 /* 20 */ NULL
, NULL
, NULL
, NULL
,
12934 /* 24 */ NULL
, NULL
, NULL
, NULL
,
12935 /* 28 */ NULL
, NULL
, NULL
, NULL
,
12936 /* 2C */ NULL
, NULL
, NULL
, NULL
,
12937 /* 30 */ NULL
, NULL
, NULL
, NULL
,
12938 /* 34 */ NULL
, NULL
, NULL
, NULL
,
12939 /* 38 */ NULL
, NULL
, NULL
, NULL
,
12940 /* 3C */ NULL
, NULL
, NULL
, NULL
,
12941 /* 40 */ NULL
, NULL
, NULL
, NULL
,
12942 /* 44 */ NULL
, NULL
, NULL
, NULL
,
12943 /* 48 */ NULL
, NULL
, NULL
, NULL
,
12944 /* 4C */ NULL
, NULL
, NULL
, NULL
,
12945 /* 50 */ NULL
, NULL
, NULL
, NULL
,
12946 /* 54 */ NULL
, NULL
, NULL
, NULL
,
12947 /* 58 */ NULL
, NULL
, NULL
, NULL
,
12948 /* 5C */ NULL
, NULL
, NULL
, NULL
,
12949 /* 60 */ NULL
, NULL
, NULL
, NULL
,
12950 /* 64 */ NULL
, NULL
, NULL
, NULL
,
12951 /* 68 */ NULL
, NULL
, NULL
, NULL
,
12952 /* 6C */ NULL
, NULL
, NULL
, NULL
,
12953 /* 70 */ NULL
, NULL
, NULL
, NULL
,
12954 /* 74 */ NULL
, NULL
, NULL
, NULL
,
12955 /* 78 */ NULL
, NULL
, NULL
, NULL
,
12956 /* 7C */ NULL
, NULL
, NULL
, NULL
,
12957 /* 80 */ NULL
, NULL
, NULL
, NULL
,
12958 /* 84 */ NULL
, NULL
, NULL
, NULL
,
12959 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
12960 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
12961 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
12962 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
12963 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
12964 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
12965 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
12966 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
12967 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
12968 /* AC */ NULL
, NULL
, "pfacc", NULL
,
12969 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
12970 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
12971 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
12972 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
12973 /* C0 */ NULL
, NULL
, NULL
, NULL
,
12974 /* C4 */ NULL
, NULL
, NULL
, NULL
,
12975 /* C8 */ NULL
, NULL
, NULL
, NULL
,
12976 /* CC */ NULL
, NULL
, NULL
, NULL
,
12977 /* D0 */ NULL
, NULL
, NULL
, NULL
,
12978 /* D4 */ NULL
, NULL
, NULL
, NULL
,
12979 /* D8 */ NULL
, NULL
, NULL
, NULL
,
12980 /* DC */ NULL
, NULL
, NULL
, NULL
,
12981 /* E0 */ NULL
, NULL
, NULL
, NULL
,
12982 /* E4 */ NULL
, NULL
, NULL
, NULL
,
12983 /* E8 */ NULL
, NULL
, NULL
, NULL
,
12984 /* EC */ NULL
, NULL
, NULL
, NULL
,
12985 /* F0 */ NULL
, NULL
, NULL
, NULL
,
12986 /* F4 */ NULL
, NULL
, NULL
, NULL
,
12987 /* F8 */ NULL
, NULL
, NULL
, NULL
,
12988 /* FC */ NULL
, NULL
, NULL
, NULL
,
12992 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12994 const char *mnemonic
;
12996 FETCH_DATA (the_info
, codep
+ 1);
12997 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12998 place where an 8-bit immediate would normally go. ie. the last
12999 byte of the instruction. */
13000 obufp
= mnemonicendp
;
13001 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
13003 oappend (mnemonic
);
13006 /* Since a variable sized modrm/sib chunk is between the start
13007 of the opcode (0x0f0f) and the opcode suffix, we need to do
13008 all the modrm processing first, and don't know until now that
13009 we have a bad opcode. This necessitates some cleaning up. */
13010 op_out
[0][0] = '\0';
13011 op_out
[1][0] = '\0';
13014 mnemonicendp
= obufp
;
13017 static const struct op simd_cmp_op
[] =
13019 { STRING_COMMA_LEN ("eq") },
13020 { STRING_COMMA_LEN ("lt") },
13021 { STRING_COMMA_LEN ("le") },
13022 { STRING_COMMA_LEN ("unord") },
13023 { STRING_COMMA_LEN ("neq") },
13024 { STRING_COMMA_LEN ("nlt") },
13025 { STRING_COMMA_LEN ("nle") },
13026 { STRING_COMMA_LEN ("ord") }
13029 static const struct op vex_cmp_op
[] =
13031 { STRING_COMMA_LEN ("eq_uq") },
13032 { STRING_COMMA_LEN ("nge") },
13033 { STRING_COMMA_LEN ("ngt") },
13034 { STRING_COMMA_LEN ("false") },
13035 { STRING_COMMA_LEN ("neq_oq") },
13036 { STRING_COMMA_LEN ("ge") },
13037 { STRING_COMMA_LEN ("gt") },
13038 { STRING_COMMA_LEN ("true") },
13039 { STRING_COMMA_LEN ("eq_os") },
13040 { STRING_COMMA_LEN ("lt_oq") },
13041 { STRING_COMMA_LEN ("le_oq") },
13042 { STRING_COMMA_LEN ("unord_s") },
13043 { STRING_COMMA_LEN ("neq_us") },
13044 { STRING_COMMA_LEN ("nlt_uq") },
13045 { STRING_COMMA_LEN ("nle_uq") },
13046 { STRING_COMMA_LEN ("ord_s") },
13047 { STRING_COMMA_LEN ("eq_us") },
13048 { STRING_COMMA_LEN ("nge_uq") },
13049 { STRING_COMMA_LEN ("ngt_uq") },
13050 { STRING_COMMA_LEN ("false_os") },
13051 { STRING_COMMA_LEN ("neq_os") },
13052 { STRING_COMMA_LEN ("ge_oq") },
13053 { STRING_COMMA_LEN ("gt_oq") },
13054 { STRING_COMMA_LEN ("true_us") },
13058 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13060 unsigned int cmp_type
;
13062 FETCH_DATA (the_info
, codep
+ 1);
13063 cmp_type
= *codep
++ & 0xff;
13064 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
13067 char *p
= mnemonicendp
- 2;
13071 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13072 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13075 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
13078 char *p
= mnemonicendp
- 2;
13082 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
13083 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
13084 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
13088 /* We have a reserved extension byte. Output it directly. */
13089 scratchbuf
[0] = '$';
13090 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13091 oappend_maybe_intel (scratchbuf
);
13092 scratchbuf
[0] = '\0';
13097 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13099 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13102 strcpy (op_out
[0], names32
[0]);
13103 strcpy (op_out
[1], names32
[1]);
13104 if (bytemode
== eBX_reg
)
13105 strcpy (op_out
[2], names32
[3]);
13106 two_source_ops
= 1;
13108 /* Skip mod/rm byte. */
13114 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
13115 int sizeflag ATTRIBUTE_UNUSED
)
13117 /* monitor %{e,r,}ax,%ecx,%edx" */
13120 const char **names
= (address_mode
== mode_64bit
13121 ? names64
: names32
);
13123 if (prefixes
& PREFIX_ADDR
)
13125 /* Remove "addr16/addr32". */
13126 all_prefixes
[last_addr_prefix
] = 0;
13127 names
= (address_mode
!= mode_32bit
13128 ? names32
: names16
);
13129 used_prefixes
|= PREFIX_ADDR
;
13131 else if (address_mode
== mode_16bit
)
13133 strcpy (op_out
[0], names
[0]);
13134 strcpy (op_out
[1], names32
[1]);
13135 strcpy (op_out
[2], names32
[2]);
13136 two_source_ops
= 1;
13138 /* Skip mod/rm byte. */
13146 /* Throw away prefixes and 1st. opcode byte. */
13147 codep
= insn_codep
+ 1;
13152 REP_Fixup (int bytemode
, int sizeflag
)
13154 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13156 if (prefixes
& PREFIX_REPZ
)
13157 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
13164 OP_IMREG (bytemode
, sizeflag
);
13167 OP_ESreg (bytemode
, sizeflag
);
13170 OP_DSreg (bytemode
, sizeflag
);
13179 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13181 if ( isa64
!= amd64
)
13186 mnemonicendp
= obufp
;
13190 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13194 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13196 if (prefixes
& PREFIX_REPNZ
)
13197 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
13200 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13204 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13205 int sizeflag ATTRIBUTE_UNUSED
)
13208 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13209 we've seen a PREFIX_DS. */
13210 if ((prefixes
& PREFIX_DS
) != 0
13211 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
13213 /* NOTRACK prefix is only valid on indirect branch instructions.
13214 NB: DATA prefix is unsupported for Intel64. */
13215 active_seg_prefix
= 0;
13216 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
13220 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13221 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13225 HLE_Fixup1 (int bytemode
, int sizeflag
)
13228 && (prefixes
& PREFIX_LOCK
) != 0)
13230 if (prefixes
& PREFIX_REPZ
)
13231 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13232 if (prefixes
& PREFIX_REPNZ
)
13233 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13236 OP_E (bytemode
, sizeflag
);
13239 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13240 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13244 HLE_Fixup2 (int bytemode
, int sizeflag
)
13246 if (modrm
.mod
!= 3)
13248 if (prefixes
& PREFIX_REPZ
)
13249 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13250 if (prefixes
& PREFIX_REPNZ
)
13251 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13254 OP_E (bytemode
, sizeflag
);
13257 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13258 "xrelease" for memory operand. No check for LOCK prefix. */
13261 HLE_Fixup3 (int bytemode
, int sizeflag
)
13264 && last_repz_prefix
> last_repnz_prefix
13265 && (prefixes
& PREFIX_REPZ
) != 0)
13266 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13268 OP_E (bytemode
, sizeflag
);
13272 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
13277 /* Change cmpxchg8b to cmpxchg16b. */
13278 char *p
= mnemonicendp
- 2;
13279 mnemonicendp
= stpcpy (p
, "16b");
13282 else if ((prefixes
& PREFIX_LOCK
) != 0)
13284 if (prefixes
& PREFIX_REPZ
)
13285 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13286 if (prefixes
& PREFIX_REPNZ
)
13287 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13290 OP_M (bytemode
, sizeflag
);
13294 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
13296 const char **names
;
13300 switch (vex
.length
)
13314 oappend (names
[reg
]);
13318 FXSAVE_Fixup (int bytemode
, int sizeflag
)
13320 /* Add proper suffix to "fxsave" and "fxrstor". */
13324 char *p
= mnemonicendp
;
13330 OP_M (bytemode
, sizeflag
);
13333 /* Display the destination register operand for instructions with
13337 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13339 int reg
, modrm_reg
, sib_index
= -1;
13340 const char **names
;
13345 reg
= vex
.register_specifier
;
13346 vex
.register_specifier
= 0;
13347 if (address_mode
!= mode_64bit
)
13349 else if (vex
.evex
&& !vex
.v
)
13354 case vex_scalar_mode
:
13355 oappend (names_xmm
[reg
]);
13358 case vex_vsib_d_w_dq_mode
:
13359 case vex_vsib_q_w_dq_mode
:
13360 /* This must be the 3rd operand. */
13361 if (obufp
!= op_out
[2])
13363 if (vex
.length
== 128
13364 || (bytemode
!= vex_vsib_d_w_dq_mode
13366 oappend (names_xmm
[reg
]);
13368 oappend (names_ymm
[reg
]);
13370 /* All 3 XMM/YMM registers must be distinct. */
13371 modrm_reg
= modrm
.reg
;
13377 sib_index
= sib
.index
;
13382 if (reg
== modrm_reg
|| reg
== sib_index
)
13383 strcpy (obufp
, "/(bad)");
13384 if (modrm_reg
== sib_index
|| modrm_reg
== reg
)
13385 strcat (op_out
[0], "/(bad)");
13386 if (sib_index
== modrm_reg
|| sib_index
== reg
)
13387 strcat (op_out
[1], "/(bad)");
13392 /* All 3 TMM registers must be distinct. */
13397 /* This must be the 3rd operand. */
13398 if (obufp
!= op_out
[2])
13400 oappend (names_tmm
[reg
]);
13401 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
13402 strcpy (obufp
, "/(bad)");
13405 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
13408 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
13409 strcat (op_out
[0], "/(bad)");
13411 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
13412 strcat (op_out
[1], "/(bad)");
13418 switch (vex
.length
)
13439 names
= names_mask
;
13459 names
= names_mask
;
13462 /* See PR binutils/20893 for a reproducer. */
13474 oappend (names
[reg
]);
13478 OP_VexR (int bytemode
, int sizeflag
)
13480 if (modrm
.mod
== 3)
13481 OP_VEX (bytemode
, sizeflag
);
13485 OP_VexW (int bytemode
, int sizeflag
)
13487 OP_VEX (bytemode
, sizeflag
);
13491 /* Swap 2nd and 3rd operands. */
13492 strcpy (scratchbuf
, op_out
[2]);
13493 strcpy (op_out
[2], op_out
[1]);
13494 strcpy (op_out
[1], scratchbuf
);
13499 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13502 const char **names
= names_xmm
;
13504 FETCH_DATA (the_info
, codep
+ 1);
13507 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
13511 if (address_mode
!= mode_64bit
)
13514 if (bytemode
== x_mode
&& vex
.length
== 256)
13517 oappend (names
[reg
]);
13521 /* Swap 3rd and 4th operands. */
13522 strcpy (scratchbuf
, op_out
[3]);
13523 strcpy (op_out
[3], op_out
[2]);
13524 strcpy (op_out
[2], scratchbuf
);
13529 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
13530 int sizeflag ATTRIBUTE_UNUSED
)
13532 scratchbuf
[0] = '$';
13533 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
13534 oappend_maybe_intel (scratchbuf
);
13538 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13539 int sizeflag ATTRIBUTE_UNUSED
)
13541 unsigned int cmp_type
;
13546 FETCH_DATA (the_info
, codep
+ 1);
13547 cmp_type
= *codep
++ & 0xff;
13548 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13549 If it's the case, print suffix, otherwise - print the immediate. */
13550 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
13555 char *p
= mnemonicendp
- 2;
13557 /* vpcmp* can have both one- and two-lettered suffix. */
13571 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13572 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13576 /* We have a reserved extension byte. Output it directly. */
13577 scratchbuf
[0] = '$';
13578 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13579 oappend_maybe_intel (scratchbuf
);
13580 scratchbuf
[0] = '\0';
13584 static const struct op xop_cmp_op
[] =
13586 { STRING_COMMA_LEN ("lt") },
13587 { STRING_COMMA_LEN ("le") },
13588 { STRING_COMMA_LEN ("gt") },
13589 { STRING_COMMA_LEN ("ge") },
13590 { STRING_COMMA_LEN ("eq") },
13591 { STRING_COMMA_LEN ("neq") },
13592 { STRING_COMMA_LEN ("false") },
13593 { STRING_COMMA_LEN ("true") }
13597 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13598 int sizeflag ATTRIBUTE_UNUSED
)
13600 unsigned int cmp_type
;
13602 FETCH_DATA (the_info
, codep
+ 1);
13603 cmp_type
= *codep
++ & 0xff;
13604 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
13607 char *p
= mnemonicendp
- 2;
13609 /* vpcom* can have both one- and two-lettered suffix. */
13623 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
13624 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
13628 /* We have a reserved extension byte. Output it directly. */
13629 scratchbuf
[0] = '$';
13630 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13631 oappend_maybe_intel (scratchbuf
);
13632 scratchbuf
[0] = '\0';
13636 static const struct op pclmul_op
[] =
13638 { STRING_COMMA_LEN ("lql") },
13639 { STRING_COMMA_LEN ("hql") },
13640 { STRING_COMMA_LEN ("lqh") },
13641 { STRING_COMMA_LEN ("hqh") }
13645 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13646 int sizeflag ATTRIBUTE_UNUSED
)
13648 unsigned int pclmul_type
;
13650 FETCH_DATA (the_info
, codep
+ 1);
13651 pclmul_type
= *codep
++ & 0xff;
13652 switch (pclmul_type
)
13663 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
13666 char *p
= mnemonicendp
- 3;
13671 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
13672 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
13676 /* We have a reserved extension byte. Output it directly. */
13677 scratchbuf
[0] = '$';
13678 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
13679 oappend_maybe_intel (scratchbuf
);
13680 scratchbuf
[0] = '\0';
13685 MOVSXD_Fixup (int bytemode
, int sizeflag
)
13687 /* Add proper suffix to "movsxd". */
13688 char *p
= mnemonicendp
;
13713 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13720 OP_E (bytemode
, sizeflag
);
13724 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13727 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
13731 if ((rex
& REX_R
) != 0 || !vex
.r
)
13737 oappend (names_mask
[modrm
.reg
]);
13741 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13743 if (modrm
.mod
== 3 && vex
.b
)
13746 case evex_rounding_64_mode
:
13747 if (address_mode
!= mode_64bit
)
13752 /* Fall through. */
13753 case evex_rounding_mode
:
13754 oappend (names_rounding
[vex
.ll
]);
13756 case evex_sae_mode
: