2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
24 #include "disassemble.h"
25 #include "libiberty.h"
26 #include "opcode/riscv.h"
29 #include "elf/riscv.h"
30 #include "elfxx-riscv.h"
32 #include "bfd_stdint.h"
35 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
37 struct riscv_private_data
41 bfd_vma hi_addr
[OP_MASK_RD
+ 1];
44 static const char * const *riscv_gpr_names
;
45 static const char * const *riscv_fpr_names
;
48 static int no_aliases
; /* If set disassemble as most general inst. */
51 set_default_riscv_dis_options (void)
53 riscv_gpr_names
= riscv_gpr_names_abi
;
54 riscv_fpr_names
= riscv_fpr_names_abi
;
59 parse_riscv_dis_option_without_args (const char *option
)
61 if (strcmp (option
, "no-aliases") == 0)
63 else if (strcmp (option
, "numeric") == 0)
65 riscv_gpr_names
= riscv_gpr_names_numeric
;
66 riscv_fpr_names
= riscv_fpr_names_numeric
;
74 parse_riscv_dis_option (const char *option
)
78 if (parse_riscv_dis_option_without_args (option
))
81 equal
= strchr (option
, '=');
84 /* The option without '=' should be defined above. */
85 opcodes_error_handler (_("unrecognized disassembler option: %s"), option
);
89 || *(equal
+ 1) == '\0')
91 /* Invalid options with '=', no option name before '=',
92 and no value after '='. */
93 opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
100 if (strcmp (option
, "priv-spec") == 0)
102 if (!riscv_get_priv_spec_class (value
, &default_priv_spec
))
103 opcodes_error_handler (_("unknown privilege spec set by %s=%s"),
108 /* xgettext:c-format */
109 opcodes_error_handler (_("unrecognized disassembler option: %s"), option
);
114 parse_riscv_dis_options (const char *opts_in
)
116 char *opts
= xstrdup (opts_in
), *opt
= opts
, *opt_end
= opts
;
118 set_default_riscv_dis_options ();
120 for ( ; opt_end
!= NULL
; opt
= opt_end
+ 1)
122 if ((opt_end
= strchr (opt
, ',')) != NULL
)
124 parse_riscv_dis_option (opt
);
130 /* Print one argument from an array. */
133 arg_print (struct disassemble_info
*info
, unsigned long val
,
134 const char* const* array
, size_t size
)
136 const char *s
= val
>= size
|| array
[val
] == NULL
? "unknown" : array
[val
];
137 (*info
->fprintf_func
) (info
->stream
, "%s", s
);
141 maybe_print_address (struct riscv_private_data
*pd
, int base_reg
, int offset
)
143 if (pd
->hi_addr
[base_reg
] != (bfd_vma
)-1)
145 pd
->print_addr
= (base_reg
!= 0 ? pd
->hi_addr
[base_reg
] : 0) + offset
;
146 pd
->hi_addr
[base_reg
] = -1;
148 else if (base_reg
== X_GP
&& pd
->gp
!= (bfd_vma
)-1)
149 pd
->print_addr
= pd
->gp
+ offset
;
150 else if (base_reg
== X_TP
|| base_reg
== 0)
151 pd
->print_addr
= offset
;
154 /* Print insn arguments for 32/64-bit code. */
157 print_insn_args (const char *d
, insn_t l
, bfd_vma pc
, disassemble_info
*info
)
159 struct riscv_private_data
*pd
= info
->private_data
;
160 int rs1
= (l
>> OP_SH_RS1
) & OP_MASK_RS1
;
161 int rd
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
162 fprintf_ftype print
= info
->fprintf_func
;
165 print (info
->stream
, "\t");
167 for (; *d
!= '\0'; d
++)
174 case 's': /* RS1 x8-x15 */
175 case 'w': /* RS1 x8-x15 */
176 print (info
->stream
, "%s",
177 riscv_gpr_names
[EXTRACT_OPERAND (CRS1S
, l
) + 8]);
179 case 't': /* RS2 x8-x15 */
180 case 'x': /* RS2 x8-x15 */
181 print (info
->stream
, "%s",
182 riscv_gpr_names
[EXTRACT_OPERAND (CRS2S
, l
) + 8]);
184 case 'U': /* RS1, constrained to equal RD */
185 print (info
->stream
, "%s", riscv_gpr_names
[rd
]);
187 case 'c': /* RS1, constrained to equal sp */
188 print (info
->stream
, "%s", riscv_gpr_names
[X_SP
]);
191 print (info
->stream
, "%s",
192 riscv_gpr_names
[EXTRACT_OPERAND (CRS2
, l
)]);
195 print (info
->stream
, "%d", (int)EXTRACT_RVC_SIMM3 (l
));
199 print (info
->stream
, "%d", (int)EXTRACT_RVC_IMM (l
));
202 print (info
->stream
, "%d", (int)EXTRACT_RVC_LW_IMM (l
));
205 print (info
->stream
, "%d", (int)EXTRACT_RVC_LD_IMM (l
));
208 print (info
->stream
, "%d", (int)EXTRACT_RVC_LWSP_IMM (l
));
211 print (info
->stream
, "%d", (int)EXTRACT_RVC_LDSP_IMM (l
));
214 print (info
->stream
, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l
));
217 print (info
->stream
, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l
));
220 print (info
->stream
, "%d", (int)EXTRACT_RVC_SWSP_IMM (l
));
223 print (info
->stream
, "%d", (int)EXTRACT_RVC_SDSP_IMM (l
));
226 info
->target
= EXTRACT_RVC_B_IMM (l
) + pc
;
227 (*info
->print_address_func
) (info
->target
, info
);
230 info
->target
= EXTRACT_RVC_J_IMM (l
) + pc
;
231 (*info
->print_address_func
) (info
->target
, info
);
234 print (info
->stream
, "0x%x",
235 (int)(EXTRACT_RVC_IMM (l
) & (RISCV_BIGIMM_REACH
-1)));
238 print (info
->stream
, "0x%x", (int)EXTRACT_RVC_IMM (l
) & 0x3f);
241 print (info
->stream
, "0x%x", (int)EXTRACT_RVC_IMM (l
) & 0x1f);
243 case 'T': /* floating-point RS2 */
244 print (info
->stream
, "%s",
245 riscv_fpr_names
[EXTRACT_OPERAND (CRS2
, l
)]);
247 case 'D': /* floating-point RS2 x8-x15 */
248 print (info
->stream
, "%s",
249 riscv_fpr_names
[EXTRACT_OPERAND (CRS2S
, l
) + 8]);
259 print (info
->stream
, "%c", *d
);
263 /* Only print constant 0 if it is the last argument */
265 print (info
->stream
, "0");
270 if ((l
& MASK_JALR
) == MATCH_JALR
)
271 maybe_print_address (pd
, rs1
, 0);
272 print (info
->stream
, "%s", riscv_gpr_names
[rs1
]);
276 print (info
->stream
, "%s",
277 riscv_gpr_names
[EXTRACT_OPERAND (RS2
, l
)]);
281 print (info
->stream
, "0x%x",
282 (unsigned)EXTRACT_UTYPE_IMM (l
) >> RISCV_IMM_BITS
);
286 arg_print (info
, EXTRACT_OPERAND (RM
, l
),
287 riscv_rm
, ARRAY_SIZE (riscv_rm
));
291 arg_print (info
, EXTRACT_OPERAND (PRED
, l
),
292 riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
));
296 arg_print (info
, EXTRACT_OPERAND (SUCC
, l
),
297 riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
));
301 maybe_print_address (pd
, rs1
, EXTRACT_ITYPE_IMM (l
));
304 if (((l
& MASK_ADDI
) == MATCH_ADDI
&& rs1
!= 0)
305 || (l
& MASK_JALR
) == MATCH_JALR
)
306 maybe_print_address (pd
, rs1
, EXTRACT_ITYPE_IMM (l
));
307 print (info
->stream
, "%d", (int)EXTRACT_ITYPE_IMM (l
));
311 maybe_print_address (pd
, rs1
, EXTRACT_STYPE_IMM (l
));
312 print (info
->stream
, "%d", (int)EXTRACT_STYPE_IMM (l
));
316 info
->target
= EXTRACT_UJTYPE_IMM (l
) + pc
;
317 (*info
->print_address_func
) (info
->target
, info
);
321 info
->target
= EXTRACT_SBTYPE_IMM (l
) + pc
;
322 (*info
->print_address_func
) (info
->target
, info
);
326 if ((l
& MASK_AUIPC
) == MATCH_AUIPC
)
327 pd
->hi_addr
[rd
] = pc
+ EXTRACT_UTYPE_IMM (l
);
328 else if ((l
& MASK_LUI
) == MATCH_LUI
)
329 pd
->hi_addr
[rd
] = EXTRACT_UTYPE_IMM (l
);
330 else if ((l
& MASK_C_LUI
) == MATCH_C_LUI
)
331 pd
->hi_addr
[rd
] = EXTRACT_RVC_LUI_IMM (l
);
332 print (info
->stream
, "%s", riscv_gpr_names
[rd
]);
336 print (info
->stream
, "%s", riscv_gpr_names
[0]);
340 print (info
->stream
, "0x%x", (int)EXTRACT_OPERAND (SHAMT
, l
));
344 print (info
->stream
, "0x%x", (int)EXTRACT_OPERAND (SHAMTW
, l
));
349 print (info
->stream
, "%s", riscv_fpr_names
[rs1
]);
353 print (info
->stream
, "%s", riscv_fpr_names
[EXTRACT_OPERAND (RS2
, l
)]);
357 print (info
->stream
, "%s", riscv_fpr_names
[rd
]);
361 print (info
->stream
, "%s", riscv_fpr_names
[EXTRACT_OPERAND (RS3
, l
)]);
366 static const char *riscv_csr_hash
[4096]; /* Total 2^12 CSR. */
367 static bfd_boolean init_csr
= FALSE
;
368 unsigned int csr
= EXTRACT_OPERAND (CSR
, l
);
373 for (i
= 0; i
< 4096; i
++)
374 riscv_csr_hash
[i
] = NULL
;
376 /* Set to the newest privilege version. */
377 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
378 default_priv_spec
= PRIV_SPEC_CLASS_DRAFT
- 1;
380 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
381 if (riscv_csr_hash[num] == NULL \
382 && ((define_version == PRIV_SPEC_CLASS_NONE \
383 && abort_version == PRIV_SPEC_CLASS_NONE) \
384 || (default_priv_spec >= define_version \
385 && default_priv_spec < abort_version))) \
386 riscv_csr_hash[num] = #name;
387 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
388 DECLARE_CSR (name, num, class, define_version, abort_version)
389 #include "opcode/riscv-opc.h"
393 if (riscv_csr_hash
[csr
] != NULL
)
394 print (info
->stream
, "%s", riscv_csr_hash
[csr
]);
396 print (info
->stream
, "0x%x", csr
);
401 print (info
->stream
, "%d", rs1
);
405 /* xgettext:c-format */
406 print (info
->stream
, _("# internal error, undefined modifier (%c)"),
413 /* Print the RISC-V instruction at address MEMADDR in debugged memory,
414 on using INFO. Returns length of the instruction, in bytes.
415 BIGENDIAN must be 1 if this is big-endian code, 0 if
416 this is little-endian code. */
419 riscv_disassemble_insn (bfd_vma memaddr
, insn_t word
, disassemble_info
*info
)
421 const struct riscv_opcode
*op
;
422 static bfd_boolean init
= 0;
423 static const struct riscv_opcode
*riscv_hash
[OP_MASK_OP
+ 1];
424 struct riscv_private_data
*pd
;
427 #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
429 /* Build a hash table to shorten the search time. */
432 for (op
= riscv_opcodes
; op
->name
; op
++)
433 if (!riscv_hash
[OP_HASH_IDX (op
->match
)])
434 riscv_hash
[OP_HASH_IDX (op
->match
)] = op
;
439 if (info
->private_data
== NULL
)
443 pd
= info
->private_data
= xcalloc (1, sizeof (struct riscv_private_data
));
446 for (i
= 0; i
< (int)ARRAY_SIZE (pd
->hi_addr
); i
++)
449 for (i
= 0; i
< info
->symtab_size
; i
++)
450 if (strcmp (bfd_asymbol_name (info
->symtab
[i
]), RISCV_GP_SYMBOL
) == 0)
451 pd
->gp
= bfd_asymbol_value (info
->symtab
[i
]);
454 pd
= info
->private_data
;
456 insnlen
= riscv_insn_length (word
);
458 /* RISC-V instructions are always little-endian. */
459 info
->endian_code
= BFD_ENDIAN_LITTLE
;
461 info
->bytes_per_chunk
= insnlen
% 4 == 0 ? 4 : 2;
462 info
->bytes_per_line
= 8;
463 /* We don't support constant pools, so this must be code. */
464 info
->display_endian
= info
->endian_code
;
465 info
->insn_info_valid
= 1;
466 info
->branch_delay_insns
= 0;
468 info
->insn_type
= dis_nonbranch
;
472 op
= riscv_hash
[OP_HASH_IDX (word
)];
477 /* If XLEN is not known, get its value from the ELF class. */
478 if (info
->mach
== bfd_mach_riscv64
)
480 else if (info
->mach
== bfd_mach_riscv32
)
482 else if (info
->section
!= NULL
)
484 Elf_Internal_Ehdr
*ehdr
= elf_elfheader (info
->section
->owner
);
485 xlen
= ehdr
->e_ident
[EI_CLASS
] == ELFCLASS64
? 64 : 32;
488 for (; op
->name
; op
++)
490 /* Does the opcode match? */
491 if (! (op
->match_func
) (op
, word
))
493 /* Is this a pseudo-instruction and may we print it as such? */
494 if (no_aliases
&& (op
->pinfo
& INSN_ALIAS
))
496 /* Is this instruction restricted to a certain value of XLEN? */
497 if ((op
->xlen_requirement
!= 0) && (op
->xlen_requirement
!= xlen
))
501 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
502 print_insn_args (op
->args
, word
, memaddr
, info
);
504 /* Try to disassemble multi-instruction addressing sequences. */
505 if (pd
->print_addr
!= (bfd_vma
)-1)
507 info
->target
= pd
->print_addr
;
508 (*info
->fprintf_func
) (info
->stream
, " # ");
509 (*info
->print_address_func
) (info
->target
, info
);
513 /* Finish filling out insn_info fields. */
514 switch (op
->pinfo
& INSN_TYPE
)
517 info
->insn_type
= dis_branch
;
519 case INSN_CONDBRANCH
:
520 info
->insn_type
= dis_condbranch
;
523 info
->insn_type
= dis_jsr
;
526 info
->insn_type
= dis_dref
;
532 if (op
->pinfo
& INSN_DATA_SIZE
)
534 int size
= ((op
->pinfo
& INSN_DATA_SIZE
)
535 >> INSN_DATA_SIZE_SHIFT
);
536 info
->data_size
= 1 << (size
- 1);
543 /* We did not find a match, so just print the instruction bits. */
544 info
->insn_type
= dis_noninsn
;
545 (*info
->fprintf_func
) (info
->stream
, "0x%llx", (unsigned long long)word
);
550 print_insn_riscv (bfd_vma memaddr
, struct disassemble_info
*info
)
557 if (info
->disassembler_options
!= NULL
)
559 parse_riscv_dis_options (info
->disassembler_options
);
560 /* Avoid repeatedly parsing the options. */
561 info
->disassembler_options
= NULL
;
563 else if (riscv_gpr_names
== NULL
)
564 set_default_riscv_dis_options ();
566 /* Instructions are a sequence of 2-byte packets in little-endian order. */
567 for (n
= 0; n
< sizeof (insn
) && n
< riscv_insn_length (insn
); n
+= 2)
569 status
= (*info
->read_memory_func
) (memaddr
+ n
, packet
, 2, info
);
572 /* Don't fail just because we fell off the end. */
575 (*info
->memory_error_func
) (status
, memaddr
, info
);
579 insn
|= ((insn_t
) bfd_getl16 (packet
)) << (8 * n
);
582 return riscv_disassemble_insn (memaddr
, insn
, info
);
585 /* Prevent use of the fake labels that are generated as part of the DWARF
586 and for relaxable relocations in the assembler. */
589 riscv_symbol_is_valid (asymbol
* sym
,
590 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
597 name
= bfd_asymbol_name (sym
);
599 return (strcmp (name
, RISCV_FAKE_LABEL_NAME
) != 0);
603 print_riscv_disassembler_options (FILE *stream
)
605 fprintf (stream
, _("\n\
606 The following RISC-V-specific disassembler options are supported for use\n\
607 with the -M switch (multiple options should be separated by commas):\n"));
609 fprintf (stream
, _("\n\
610 numeric Print numeric register names, rather than ABI names.\n"));
612 fprintf (stream
, _("\n\
613 no-aliases Disassemble only into canonical instructions, rather\n\
614 than into pseudoinstructions.\n"));
616 fprintf (stream
, _("\n\
617 priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
618 (1.9, 1.9.1, 1.10, 1.11).\n"));
620 fprintf (stream
, _("\n"));