1 /* Support code for various pieces of CGEN simulators.
2 Copyright (C) 1996-2021 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
25 #include "sim-signal.h"
28 #define MEMOPS_DEFINE_INLINE
31 #define SEMOPS_DEFINE_INLINE
34 const char * const cgen_mode_names
[] = {
49 0, /* MODE_TARGET_MAX */
55 /* Opcode table for virtual insns used by the simulator. */
57 #define V CGEN_ATTR_MASK (CGEN_INSN_VIRTUAL)
59 static const CGEN_IBASE virtual_insn_entries
[] =
62 VIRTUAL_INSN_X_INVALID
, "--invalid--", NULL
, 0, { V
, {} }
65 VIRTUAL_INSN_X_BEFORE
, "--before--", NULL
, 0, { V
, {} }
68 VIRTUAL_INSN_X_AFTER
, "--after--", NULL
, 0, { V
, {} }
71 VIRTUAL_INSN_X_BEGIN
, "--begin--", NULL
, 0, { V
, {} }
74 VIRTUAL_INSN_X_CHAIN
, "--chain--", NULL
, 0, { V
, {} }
77 VIRTUAL_INSN_X_CTI_CHAIN
, "--cti-chain--", NULL
, 0, { V
, {} }
83 const CGEN_INSN cgen_virtual_insn_table
[] =
85 { & virtual_insn_entries
[0] },
86 { & virtual_insn_entries
[1] },
87 { & virtual_insn_entries
[2] },
88 { & virtual_insn_entries
[3] },
89 { & virtual_insn_entries
[4] },
90 { & virtual_insn_entries
[5] }
93 /* Return the name of insn number I. */
96 cgen_insn_name (SIM_CPU
*cpu
, int i
)
98 return CGEN_INSN_NAME ((* CPU_GET_IDATA (cpu
)) ((cpu
), (i
)));
101 /* Return the maximum number of extra bytes required for a SIM_CPU struct. */
104 cgen_cpu_max_extra_bytes (SIM_DESC sd
)
106 const SIM_MACH
* const *machp
;
109 SIM_ASSERT (STATE_MACHS (sd
) != NULL
);
111 for (machp
= STATE_MACHS (sd
); *machp
!= NULL
; ++machp
)
113 int size
= IMP_PROPS_SIM_CPU_SIZE (MACH_IMP_PROPS (*machp
));
126 SI ahi
= GETHIDI (a
);
127 SI alo
= GETLODI (a
);
128 SI bhi
= GETHIDI (b
);
129 SI blo
= GETLODI (b
);
130 return MAKEDI (ahi
& bhi
, alo
& blo
);
137 SI ahi
= GETHIDI (a
);
138 SI alo
= GETLODI (a
);
139 SI bhi
= GETHIDI (b
);
140 SI blo
= GETLODI (b
);
141 return MAKEDI (ahi
| bhi
, alo
| blo
);
148 USI ahi
= GETHIDI (a
);
149 USI alo
= GETLODI (a
);
150 USI bhi
= GETHIDI (b
);
151 USI blo
= GETLODI (b
);
153 return MAKEDI (ahi
+ bhi
+ (x
< alo
), x
);
160 USI ahi
= GETHIDI (a
);
161 USI alo
= GETLODI (a
);
162 USI bhi
= GETHIDI (b
);
163 USI blo
= GETLODI (b
);
172 #define SI_TYPE_SIZE 32
173 #define BITS4 (SI_TYPE_SIZE / 4)
174 #define ll_B (1L << (SI_TYPE_SIZE / 2))
175 #define ll_lowpart(t) ((USI) (t) % ll_B)
176 #define ll_highpart(t) ((USI) (t) / ll_B)
177 x1
+= ll_highpart (x0
); /* this can't give carry */
178 x1
+= x2
; /* but this indeed can */
179 if (x1
< x2
) /* did we get it? */
180 x3
+= ll_B
; /* yes, add it in the proper pos. */
182 rhi
= x3
+ ll_highpart (x1
);
183 rlo
= ll_lowpart (x1
) * ll_B
+ ll_lowpart (x0
);
184 return MAKEDI (rhi
+ (alo
* bhi
) + (ahi
* blo
), rlo
);
192 USI hi
= GETHIDI (val
);
193 USI lo
= GETLODI (val
);
194 /* FIXME: Need to worry about shift < 0 || shift >= 32. */
195 return MAKEDI ((hi
<< shift
) | (lo
>> (32 - shift
)), lo
<< shift
);
203 SI hi
= GETHIDI (val
);
204 USI lo
= GETLODI (val
);
205 /* FIXME: Need to worry about shift < 0 || shift >= 32. */
206 return MAKEDI ((hi
<< shift
) | (lo
>> (32 - shift
)), lo
<< shift
);
214 SI hi
= GETHIDI (val
);
215 USI lo
= GETLODI (val
);
216 /* We use SRASI because the result is implementation defined if hi < 0. */
217 /* FIXME: Need to worry about shift < 0 || shift >= 32. */
218 return MAKEDI (SRASI (hi
, shift
), (hi
<< (32 - shift
)) | (lo
>> shift
));
225 SI ahi
= GETHIDI (a
);
226 USI alo
= GETLODI (a
);
227 SI bhi
= GETHIDI (b
);
228 USI blo
= GETLODI (b
);
240 SI ahi
= GETHIDI (a
);
241 USI alo
= GETLODI (a
);
242 SI bhi
= GETHIDI (b
);
243 USI blo
= GETLODI (b
);
256 return MAKEDI (-1, val
);
258 return MAKEDI (0, val
);
266 return MAKEDI (-1, val
);
268 return MAKEDI (0, val
);
275 return GETLODI (val
);
278 #endif /* DI_FN_SUPPORT */
281 RORQI (QI val
, int shift
)
285 int remain
= 8 - shift
;
286 int mask
= (1 << shift
) - 1;
287 QI result
= (val
& mask
) << remain
;
288 mask
= (1 << remain
) - 1;
289 result
|= (val
>> shift
) & mask
;
296 ROLQI (QI val
, int shift
)
300 int remain
= 8 - shift
;
301 int mask
= (1 << remain
) - 1;
302 QI result
= (val
& mask
) << shift
;
303 mask
= (1 << shift
) - 1;
304 result
|= (val
>> remain
) & mask
;
311 RORHI (HI val
, int shift
)
315 int remain
= 16 - shift
;
316 int mask
= (1 << shift
) - 1;
317 HI result
= (val
& mask
) << remain
;
318 mask
= (1 << remain
) - 1;
319 result
|= (val
>> shift
) & mask
;
326 ROLHI (HI val
, int shift
)
330 int remain
= 16 - shift
;
331 int mask
= (1 << remain
) - 1;
332 HI result
= (val
& mask
) << shift
;
333 mask
= (1 << shift
) - 1;
334 result
|= (val
>> remain
) & mask
;
341 RORSI (SI val
, int shift
)
345 int remain
= 32 - shift
;
346 int mask
= (1 << shift
) - 1;
347 SI result
= (val
& mask
) << remain
;
348 mask
= (1 << remain
) - 1;
349 result
|= (val
>> shift
) & mask
;
356 ROLSI (SI val
, int shift
)
360 int remain
= 32 - shift
;
361 int mask
= (1 << remain
) - 1;
362 SI result
= (val
& mask
) << shift
;
363 mask
= (1 << shift
) - 1;
364 result
|= (val
>> remain
) & mask
;
371 /* Emit an error message from CGEN RTL. */
374 cgen_rtx_error (SIM_CPU
*cpu
, const char * msg
)
376 SIM_DESC sd
= CPU_STATE (cpu
);
378 sim_io_printf (sd
, "%s", msg
);
379 sim_io_printf (sd
, "\n");
381 sim_engine_halt (sd
, cpu
, NULL
, CPU_PC_GET (cpu
), sim_stopped
, SIM_SIGTRAP
);