2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
24 #ifdef HAVE_SYS_PARAM_H
25 #include <sys/param.h>
30 #include "gdb/sim-h8300.h"
32 #include "sys/types.h"
33 #include "sim-options.h"
41 static int memory_size
;
43 #define X(op, size) (op * 4 + size)
45 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
47 #define h8_opcodes ops
49 #include "opcode/h8300.h"
51 /* CPU data object: */
54 h8_get_pc (SIM_DESC sd
)
56 return (STATE_CPU (sd
, 0)) -> pc
;
60 h8_set_pc (SIM_DESC sd
, unsigned int val
)
62 (STATE_CPU (sd
, 0)) -> pc
= val
;
66 h8_get_ccr (SIM_DESC sd
)
68 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
72 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
74 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
78 h8_get_exr (SIM_DESC sd
)
80 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
84 h8_set_exr (SIM_DESC sd
, unsigned int val
)
86 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
90 h8_get_sbr (SIM_DESC sd
)
92 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
96 h8_set_sbr (SIM_DESC sd
, int val
)
98 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
102 h8_get_vbr (SIM_DESC sd
)
104 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
108 h8_set_vbr (SIM_DESC sd
, int val
)
110 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
114 h8_get_mask (SIM_DESC sd
)
116 return (STATE_CPU (sd
, 0)) -> mask
;
120 h8_set_mask (SIM_DESC sd
, int val
)
122 (STATE_CPU (sd
, 0)) -> mask
= val
;
126 h8_get_exception (SIM_DESC sd
)
128 return (STATE_CPU (sd
, 0)) -> exception
;
132 h8_set_exception (SIM_DESC sd
, int val
)
134 (STATE_CPU (sd
, 0)) -> exception
= val
;
137 static enum h8300_sim_state
138 h8_get_state (SIM_DESC sd
)
144 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
150 h8_get_cycles (SIM_DESC sd
)
152 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
156 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
158 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
162 h8_get_insts (SIM_DESC sd
)
164 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
168 h8_set_insts (SIM_DESC sd
, unsigned int val
)
170 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
174 h8_get_ticks (SIM_DESC sd
)
176 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
180 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
182 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
186 h8_get_mach (SIM_DESC sd
)
188 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
192 h8_set_mach (SIM_DESC sd
, unsigned int val
)
194 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
198 h8_get_macl (SIM_DESC sd
)
200 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
204 h8_set_macl (SIM_DESC sd
, unsigned int val
)
206 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
209 static unsigned int *
210 h8_get_reg_buf (SIM_DESC sd
)
212 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
216 h8_get_reg (SIM_DESC sd
, int regnum
)
218 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
222 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
224 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
229 h8_get_stats (SIM_DESC sd
, int idx
)
231 return sd
-> stats
[idx
];
235 h8_increment_stats (SIM_DESC sd
, int idx
)
241 static unsigned char *
242 h8_get_memory_buf (SIM_DESC sd
)
244 return (STATE_CPU (sd
, 0)) -> memory
;
248 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
250 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
254 h8_get_memory (SIM_DESC sd
, int idx
)
256 ASSERT (idx
< memory_size
);
257 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
261 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
263 ASSERT (idx
< memory_size
);
264 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
268 h8_get_delayed_branch (SIM_DESC sd
)
270 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
274 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
276 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
280 h8_get_command_line (SIM_DESC sd
)
282 return (STATE_CPU (sd
, 0)) -> command_line
;
286 h8_set_command_line (SIM_DESC sd
, char ** val
)
288 (STATE_CPU (sd
, 0)) -> command_line
= val
;
292 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
294 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
298 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
300 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
303 /* MAC Saturation Mode */
305 h8_get_macS (SIM_DESC sd
)
307 return (STATE_CPU (sd
, 0)) -> macS
;
312 h8_set_macS (SIM_DESC sd
, int val
)
314 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
320 h8_get_macZ (SIM_DESC sd
)
322 return (STATE_CPU (sd
, 0)) -> macZ
;
326 h8_set_macZ (SIM_DESC sd
, int val
)
328 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
331 /* MAC Negative Flag */
333 h8_get_macN (SIM_DESC sd
)
335 return (STATE_CPU (sd
, 0)) -> macN
;
339 h8_set_macN (SIM_DESC sd
, int val
)
341 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
344 /* MAC Overflow Flag */
346 h8_get_macV (SIM_DESC sd
)
348 return (STATE_CPU (sd
, 0)) -> macV
;
352 h8_set_macV (SIM_DESC sd
, int val
)
354 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
357 /* End CPU data object. */
359 /* The rate at which to call the host's poll_quit callback. */
361 enum { POLL_QUIT_INTERVAL
= 0x80000 };
363 #define LOW_BYTE(x) ((x) & 0xff)
364 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
365 #define P(X, Y) ((X << 8) | Y)
374 #define I (intMaskBit != 0)
376 #define BUILDSR(SD) \
377 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
378 | (N << 3) | (Z << 2) | (V << 1) | C)
381 /* Get Status Register (flags). */ \
382 c = (h8_get_ccr (sd) >> 0) & 1; \
383 v = (h8_get_ccr (sd) >> 1) & 1; \
384 nz = !((h8_get_ccr (sd) >> 2) & 1); \
385 n = (h8_get_ccr (sd) >> 3) & 1; \
386 u = (h8_get_ccr (sd) >> 4) & 1; \
387 h = (h8_get_ccr (sd) >> 5) & 1; \
388 ui = ((h8_get_ccr (sd) >> 6) & 1); \
389 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
392 #ifdef __CHAR_IS_SIGNED__
393 #define SEXTCHAR(x) ((char) (x))
397 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
400 #define UEXTCHAR(x) ((x) & 0xff)
401 #define UEXTSHORT(x) ((x) & 0xffff)
402 #define SEXTSHORT(x) ((short) (x))
406 int h8300_normal_mode
= 0;
412 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
434 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
439 /* Simulate an indirection / dereference.
440 return 0 for success, -1 for failure.
444 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
446 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
448 if (val
== NULL
) /* Paranoia. */
454 if (rn
== ZERO_REGNUM
)
455 *val
= X (OP_IMM
, SP
);
457 *val
= X (OP_REG
, SP
);
460 *val
= X (OP_MEM
, SP
);
463 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
470 cmdline_location(void)
472 if (h8300smode
&& !h8300_normal_mode
)
474 else if (h8300hmode
&& !h8300_normal_mode
)
481 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
483 int cst
[3] = {0, 0, 0};
484 int reg
[3] = {0, 0, 0};
485 int rdisp
[3] = {0, 0, 0};
487 const struct h8_opcode
*q
;
492 /* Find the exact opcode/arg combo. */
493 for (q
= h8_opcodes
; q
->name
; q
++)
495 const op_type
*nib
= q
->data
.nib
;
496 unsigned int len
= 0;
498 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
499 (q
->available
== AV_H8S
&& !h8300smode
) ||
500 (q
->available
== AV_H8H
&& !h8300hmode
))
503 cst
[0] = cst
[1] = cst
[2] = 0;
504 reg
[0] = reg
[1] = reg
[2] = 0;
505 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
509 op_type looking_for
= *nib
;
510 int thisnib
= data
[len
/ 2];
512 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
513 opnum
= ((looking_for
& OP3
) ? 2 :
514 (looking_for
& DST
) ? 1 : 0);
516 if (looking_for
< 16 && looking_for
>= 0)
518 if (looking_for
!= thisnib
)
523 if (looking_for
& B31
)
525 if (!((thisnib
& 0x8) != 0))
528 looking_for
= (op_type
) (looking_for
& ~B31
);
531 else if (looking_for
& B30
)
533 if (!((thisnib
& 0x8) == 0))
536 looking_for
= (op_type
) (looking_for
& ~B30
);
539 if (looking_for
& B21
)
541 if (!((thisnib
& 0x4) != 0))
544 looking_for
= (op_type
) (looking_for
& ~B21
);
547 else if (looking_for
& B20
)
549 if (!((thisnib
& 0x4) == 0))
552 looking_for
= (op_type
) (looking_for
& ~B20
);
555 if (looking_for
& B11
)
557 if (!((thisnib
& 0x2) != 0))
560 looking_for
= (op_type
) (looking_for
& ~B11
);
563 else if (looking_for
& B10
)
565 if (!((thisnib
& 0x2) == 0))
568 looking_for
= (op_type
) (looking_for
& ~B10
);
571 if (looking_for
& B01
)
573 if (!((thisnib
& 0x1) != 0))
576 looking_for
= (op_type
) (looking_for
& ~B01
);
579 else if (looking_for
& B00
)
581 if (!((thisnib
& 0x1) == 0))
584 looking_for
= (op_type
) (looking_for
& ~B00
);
587 if (looking_for
& IGNORE
)
589 /* Hitachi has declared that IGNORE must be zero. */
593 else if ((looking_for
& MODE
) == DATA
)
595 ; /* Skip embedded data. */
597 else if ((looking_for
& MODE
) == DBIT
)
599 /* Exclude adds/subs by looking at bit 0 and 2, and
600 make sure the operand size, either w or l,
601 matches by looking at bit 1. */
602 if ((looking_for
& 7) != (thisnib
& 7))
605 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
607 else if ((looking_for
& MODE
) == REG
||
608 (looking_for
& MODE
) == LOWREG
||
609 (looking_for
& MODE
) == IND
||
610 (looking_for
& MODE
) == PREINC
||
611 (looking_for
& MODE
) == POSTINC
||
612 (looking_for
& MODE
) == PREDEC
||
613 (looking_for
& MODE
) == POSTDEC
)
615 reg
[opnum
] = thisnib
;
617 else if (looking_for
& CTRL
)
620 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
621 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
622 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
623 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
624 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
625 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
627 if (((looking_for
& MODE
) == CCR_EXR
&&
628 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
629 ((looking_for
& MODE
) == VBR_SBR
&&
630 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
631 ((looking_for
& MODE
) == MACREG
&&
632 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
634 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
635 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
636 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
639 reg
[opnum
] = thisnib
;
641 else if ((looking_for
& MODE
) == ABS
)
643 /* Absolute addresses are unsigned. */
644 switch (looking_for
& SIZE
)
647 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
651 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
655 (data
[len
/ 2 + 0] << 24) +
656 (data
[len
/ 2 + 1] << 16) +
657 (data
[len
/ 2 + 2] << 8) +
661 printf ("decode: bad size ABS: %d\n",
662 (looking_for
& SIZE
));
666 else if ((looking_for
& MODE
) == DISP
||
667 (looking_for
& MODE
) == PCREL
||
668 (looking_for
& MODE
) == INDEXB
||
669 (looking_for
& MODE
) == INDEXW
||
670 (looking_for
& MODE
) == INDEXL
)
672 switch (looking_for
& SIZE
)
675 cst
[opnum
] = thisnib
& 3;
678 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
681 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
682 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
685 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
689 (data
[len
/ 2 + 0] << 24) +
690 (data
[len
/ 2 + 1] << 16) +
691 (data
[len
/ 2 + 2] << 8) +
695 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
696 (looking_for
& SIZE
));
700 else if ((looking_for
& SIZE
) == L_16
||
701 (looking_for
& SIZE
) == L_16U
)
703 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
704 /* Immediates are always unsigned. */
705 if ((looking_for
& SIZE
) != L_16U
&&
706 (looking_for
& MODE
) != IMM
)
707 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
709 else if (looking_for
& ABSJMP
)
711 switch (looking_for
& SIZE
) {
713 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
717 (data
[len
/ 2 + 0] << 24) +
718 (data
[len
/ 2 + 1] << 16) +
719 (data
[len
/ 2 + 2] << 8) +
723 printf ("decode: bad size ABSJMP: %d\n",
724 (looking_for
& SIZE
));
728 else if ((looking_for
& MODE
) == MEMIND
)
730 cst
[opnum
] = data
[1];
732 else if ((looking_for
& MODE
) == VECIND
)
734 if(h8300_normal_mode
)
735 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
737 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
738 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
740 else if ((looking_for
& SIZE
) == L_32
)
745 (data
[i
+ 0] << 24) |
746 (data
[i
+ 1] << 16) |
750 else if ((looking_for
& SIZE
) == L_24
)
755 (data
[i
+ 0] << 16) |
759 else if (looking_for
& DISPREG
)
761 rdisp
[opnum
] = thisnib
& 0x7;
763 else if ((looking_for
& MODE
) == KBIT
)
780 else if ((looking_for
& SIZE
) == L_8
)
782 if ((looking_for
& MODE
) == ABS
)
784 /* Will be combined with contents of SBR_REGNUM
785 by fetch (). For all modes except h8sx, this
786 will always contain the value 0xFFFFFF00. */
787 cst
[opnum
] = data
[len
/ 2] & 0xff;
791 cst
[opnum
] = data
[len
/ 2] & 0xff;
794 else if ((looking_for
& SIZE
) == L_2
)
796 cst
[opnum
] = thisnib
& 3;
798 else if ((looking_for
& SIZE
) == L_3
||
799 (looking_for
& SIZE
) == L_3NZ
)
801 cst
[opnum
] = thisnib
& 7;
802 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
805 else if ((looking_for
& SIZE
) == L_4
)
807 cst
[opnum
] = thisnib
& 15;
809 else if ((looking_for
& SIZE
) == L_5
)
811 cst
[opnum
] = data
[len
/ 2] & 0x1f;
813 else if (looking_for
== E
)
818 /* Fill in the args. */
820 const op_type
*args
= q
->args
.nib
;
825 nargs
< 3 && *args
!= E
;
831 opnum
= ((x
& OP3
) ? 2 :
840 if ((x
& MODE
) == IMM
||
841 (x
& MODE
) == KBIT
||
844 /* Use the instruction to determine
846 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
847 p
->literal
= cst
[opnum
];
849 else if ((x
& MODE
) == CONST_2
||
850 (x
& MODE
) == CONST_4
||
851 (x
& MODE
) == CONST_8
||
852 (x
& MODE
) == CONST_16
)
854 /* Use the instruction to determine
856 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
858 case CONST_2
: p
->literal
= 2; break;
859 case CONST_4
: p
->literal
= 4; break;
860 case CONST_8
: p
->literal
= 8; break;
861 case CONST_16
: p
->literal
= 16; break;
864 else if ((x
& MODE
) == REG
)
866 p
->type
= X (OP_REG
, bitfrom (x
));
869 else if ((x
& MODE
) == LOWREG
)
871 p
->type
= X (OP_LOWREG
, bitfrom (x
));
874 else if ((x
& MODE
) == PREINC
)
876 /* Use the instruction to determine
878 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
879 p
->reg
= reg
[opnum
] & 0x7;
881 else if ((x
& MODE
) == POSTINC
)
883 /* Use the instruction to determine
885 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
886 p
->reg
= reg
[opnum
] & 0x7;
888 else if ((x
& MODE
) == PREDEC
)
890 /* Use the instruction to determine
892 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
893 p
->reg
= reg
[opnum
] & 0x7;
895 else if ((x
& MODE
) == POSTDEC
)
897 /* Use the instruction to determine
899 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
900 p
->reg
= reg
[opnum
] & 0x7;
902 else if ((x
& MODE
) == IND
)
904 /* Note: an indirect is transformed into
905 a displacement of zero.
907 /* Use the instruction to determine
909 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
910 p
->reg
= reg
[opnum
] & 0x7;
912 if (OP_KIND (q
->how
) == O_JSR
||
913 OP_KIND (q
->how
) == O_JMP
)
914 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
917 else if ((x
& MODE
) == ABS
)
919 /* Note: a 16 or 32 bit ABS is transformed into a
920 displacement from pseudo-register ZERO_REGNUM,
921 which is always zero. An 8 bit ABS becomes
922 a displacement from SBR_REGNUM.
924 /* Use the instruction to determine
926 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
927 p
->literal
= cst
[opnum
];
929 /* 8-bit ABS is displacement from SBR.
930 16 and 32-bit ABS are displacement from ZERO.
931 (SBR will always be zero except for h8/sx)
933 if ((x
& SIZE
) == L_8
)
936 p
->reg
= ZERO_REGNUM
;;
938 else if ((x
& MODE
) == MEMIND
||
939 (x
& MODE
) == VECIND
)
941 /* Size doesn't matter. */
942 p
->type
= X (OP_MEM
, SB
);
943 p
->literal
= cst
[opnum
];
944 if (OP_KIND (q
->how
) == O_JSR
||
945 OP_KIND (q
->how
) == O_JMP
)
946 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
949 else if ((x
& MODE
) == PCREL
)
951 /* Size doesn't matter. */
952 p
->type
= X (OP_PCREL
, SB
);
953 p
->literal
= cst
[opnum
];
957 p
->type
= X (OP_IMM
, SP
);
958 p
->literal
= cst
[opnum
];
960 else if ((x
& MODE
) == INDEXB
)
962 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
963 p
->literal
= cst
[opnum
];
964 p
->reg
= rdisp
[opnum
];
966 else if ((x
& MODE
) == INDEXW
)
968 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
969 p
->literal
= cst
[opnum
];
970 p
->reg
= rdisp
[opnum
];
972 else if ((x
& MODE
) == INDEXL
)
974 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
975 p
->literal
= cst
[opnum
];
976 p
->reg
= rdisp
[opnum
];
978 else if ((x
& MODE
) == DISP
)
980 /* Yuck -- special for mova args. */
981 if (strncmp (q
->name
, "mova", 4) == 0 &&
984 /* Mova can have a DISP2 dest, with an
985 INDEXB or INDEXW src. The multiplier
986 for the displacement value is determined
987 by the src operand, not by the insn. */
989 switch (OP_KIND (dst
->src
.type
))
992 p
->type
= X (OP_DISP
, SB
);
993 p
->literal
= cst
[opnum
];
996 p
->type
= X (OP_DISP
, SW
);
997 p
->literal
= cst
[opnum
] * 2;
1005 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1006 p
->literal
= cst
[opnum
];
1007 /* DISP2 is special. */
1008 if ((x
& SIZE
) == L_2
)
1009 switch (OP_SIZE (q
->how
))
1012 case SW
: p
->literal
*= 2; break;
1013 case SL
: p
->literal
*= 4; break;
1016 p
->reg
= rdisp
[opnum
];
1023 p
->type
= X (OP_CCR
, SB
);
1026 p
->type
= X (OP_EXR
, SB
);
1029 p
->type
= X (OP_MACH
, SL
);
1032 p
->type
= X (OP_MACL
, SL
);
1035 p
->type
= X (OP_VBR
, SL
);
1038 p
->type
= X (OP_SBR
, SL
);
1042 else if ((x
& MODE
) == CCR
)
1046 else if ((x
& MODE
) == EXR
)
1051 printf ("Hmmmm 0x%x...\n", x
);
1057 /* Unary operators: treat src and dst as equivalent. */
1058 if (dst
->dst
.type
== -1)
1059 dst
->dst
= dst
->src
;
1060 if (dst
->src
.type
== -1)
1061 dst
->src
= dst
->dst
;
1063 dst
->opcode
= q
->how
;
1064 dst
->cycles
= q
->time
;
1066 /* And jsr's to these locations are turned into
1069 if (OP_KIND (dst
->opcode
) == O_JSR
)
1071 switch (dst
->src
.literal
)
1074 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1077 dst
->opcode
= O (O_SYS_READ
, SB
);
1080 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1083 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1086 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1089 dst
->opcode
= O (O_SYS_STAT
, SB
);
1092 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1095 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1098 /* End of Processing for system calls. */
1101 dst
->next_pc
= addr
+ len
/ 2;
1105 printf ("Don't understand 0x%x \n", looking_for
);
1116 /* Fell off the end. */
1117 dst
->opcode
= O (O_ILL
, SB
);
1120 static unsigned char *breg
[32];
1121 static unsigned short *wreg
[16];
1123 #define GET_B_REG(X) *(breg[X])
1124 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1125 #define GET_W_REG(X) *(wreg[X])
1126 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1127 #define GET_L_REG(X) h8_get_reg (sd, X)
1128 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1130 #define GET_MEMORY_L(X) \
1131 ((X) < memory_size \
1132 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1133 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1136 #define GET_MEMORY_W(X) \
1137 ((X) < memory_size \
1138 ? ((h8_get_memory (sd, (X)+0) << 8) | (h8_get_memory (sd, (X)+1) << 0)) \
1141 #define GET_MEMORY_B(X) \
1142 ((X) < memory_size ? h8_get_memory (sd, (X)) : 0)
1144 #define SET_MEMORY_L(X, Y) \
1145 { register unsigned char *_p; register int __y = (Y); \
1146 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1147 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1148 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1151 #define SET_MEMORY_W(X, Y) \
1152 { register unsigned char *_p; register int __y = (Y); \
1153 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1154 _p[0] = __y >> 8; _p[1] = __y; \
1157 #define SET_MEMORY_B(X, Y) \
1158 ((X) < memory_size ? h8_set_memory (sd, (X), (Y)) : 0)
1160 /* Simulate a memory fetch.
1161 Return 0 for success, -1 for failure.
1165 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1167 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1169 int abs
= arg
->literal
;
1174 return -1; /* Paranoia. */
1178 /* Indexed register plus displacement mode:
1180 This new family of addressing modes are similar to OP_DISP
1181 (register plus displacement), with two differences:
1182 1) INDEXB uses only the least significant byte of the register,
1183 INDEXW uses only the least significant word, and
1184 INDEXL uses the entire register (just like OP_DISP).
1186 2) The displacement value in abs is multiplied by two
1187 for SW-sized operations, and by four for SL-size.
1189 This gives nine possible variations.
1192 case X (OP_INDEXB
, SB
):
1193 case X (OP_INDEXB
, SW
):
1194 case X (OP_INDEXB
, SL
):
1195 case X (OP_INDEXW
, SB
):
1196 case X (OP_INDEXW
, SW
):
1197 case X (OP_INDEXW
, SL
):
1198 case X (OP_INDEXL
, SB
):
1199 case X (OP_INDEXL
, SW
):
1200 case X (OP_INDEXL
, SL
):
1202 switch (OP_KIND (arg
->type
)) {
1203 case OP_INDEXB
: t
&= 0xff; break;
1204 case OP_INDEXW
: t
&= 0xffff; break;
1208 switch (OP_SIZE (arg
->type
)) {
1210 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1213 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1216 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1221 case X (OP_LOWREG
, SB
):
1222 *val
= GET_L_REG (rn
) & 0xff;
1224 case X (OP_LOWREG
, SW
):
1225 *val
= GET_L_REG (rn
) & 0xffff;
1228 case X (OP_REG
, SB
): /* Register direct, byte. */
1229 *val
= GET_B_REG (rn
);
1231 case X (OP_REG
, SW
): /* Register direct, word. */
1232 *val
= GET_W_REG (rn
);
1234 case X (OP_REG
, SL
): /* Register direct, long. */
1235 *val
= GET_L_REG (rn
);
1237 case X (OP_IMM
, SB
): /* Immediate, byte. */
1238 case X (OP_IMM
, SW
): /* Immediate, word. */
1239 case X (OP_IMM
, SL
): /* Immediate, long. */
1242 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1244 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1250 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1252 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1258 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1260 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1267 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1269 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1275 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1277 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1283 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1285 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1292 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1293 t
= GET_L_REG (rn
) - 1;
1295 t
&= h8_get_mask (sd
);
1296 *val
= GET_MEMORY_B (t
);
1299 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1300 t
= GET_L_REG (rn
) - 2;
1302 t
&= h8_get_mask (sd
);
1303 *val
= GET_MEMORY_W (t
);
1306 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1307 t
= GET_L_REG (rn
) - 4;
1309 t
&= h8_get_mask (sd
);
1310 *val
= GET_MEMORY_L (t
);
1313 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1314 t
= GET_L_REG (rn
) + 1;
1316 t
&= h8_get_mask (sd
);
1317 *val
= GET_MEMORY_B (t
);
1320 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1321 t
= GET_L_REG (rn
) + 2;
1323 t
&= h8_get_mask (sd
);
1324 *val
= GET_MEMORY_W (t
);
1327 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1328 t
= GET_L_REG (rn
) + 4;
1330 t
&= h8_get_mask (sd
);
1331 *val
= GET_MEMORY_L (t
);
1334 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1335 t
= GET_L_REG (rn
) + abs
;
1336 t
&= h8_get_mask (sd
);
1337 *val
= GET_MEMORY_B (t
);
1340 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1341 t
= GET_L_REG (rn
) + abs
;
1342 t
&= h8_get_mask (sd
);
1343 *val
= GET_MEMORY_W (t
);
1346 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1347 t
= GET_L_REG (rn
) + abs
;
1348 t
&= h8_get_mask (sd
);
1349 *val
=GET_MEMORY_L (t
);
1352 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1353 t
= GET_MEMORY_L (abs
);
1354 t
&= h8_get_mask (sd
);
1358 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1359 t
= GET_MEMORY_W (abs
);
1360 t
&= h8_get_mask (sd
);
1364 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1365 case X (OP_PCREL
, SW
):
1366 case X (OP_PCREL
, SL
):
1367 case X (OP_PCREL
, SN
):
1371 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1373 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1376 return 0; /* Success. */
1382 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1384 return fetch_1 (sd
, arg
, val
, 0);
1387 /* Fetch which will be followed by a store to the same location.
1388 The difference being that we don't want to do a post-increment
1389 or post-decrement at this time: we'll do it when we store. */
1392 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1394 return fetch_1 (sd
, arg
, val
, 1);
1397 /* Simulate a memory store.
1398 Return 0 for success, -1 for failure.
1402 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1404 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1406 int abs
= arg
->literal
;
1411 /* Indexed register plus displacement mode:
1413 This new family of addressing modes are similar to OP_DISP
1414 (register plus displacement), with two differences:
1415 1) INDEXB uses only the least significant byte of the register,
1416 INDEXW uses only the least significant word, and
1417 INDEXL uses the entire register (just like OP_DISP).
1419 2) The displacement value in abs is multiplied by two
1420 for SW-sized operations, and by four for SL-size.
1422 This gives nine possible variations.
1425 case X (OP_INDEXB
, SB
):
1426 case X (OP_INDEXB
, SW
):
1427 case X (OP_INDEXB
, SL
):
1428 case X (OP_INDEXW
, SB
):
1429 case X (OP_INDEXW
, SW
):
1430 case X (OP_INDEXW
, SL
):
1431 case X (OP_INDEXL
, SB
):
1432 case X (OP_INDEXL
, SW
):
1433 case X (OP_INDEXL
, SL
):
1435 switch (OP_KIND (arg
->type
)) {
1436 case OP_INDEXB
: t
&= 0xff; break;
1437 case OP_INDEXW
: t
&= 0xffff; break;
1441 switch (OP_SIZE (arg
->type
)) {
1443 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1446 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1449 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1454 case X (OP_REG
, SB
): /* Register direct, byte. */
1457 case X (OP_REG
, SW
): /* Register direct, word. */
1460 case X (OP_REG
, SL
): /* Register direct, long. */
1464 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1469 t
&= h8_get_mask (sd
);
1470 SET_MEMORY_B (t
, n
);
1473 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1478 t
&= h8_get_mask (sd
);
1479 SET_MEMORY_W (t
, n
);
1482 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1487 t
&= h8_get_mask (sd
);
1488 SET_MEMORY_L (t
, n
);
1491 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1496 t
&= h8_get_mask (sd
);
1497 SET_MEMORY_B (t
, n
);
1500 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1505 t
&= h8_get_mask (sd
);
1506 SET_MEMORY_W (t
, n
);
1509 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1514 t
&= h8_get_mask (sd
);
1515 SET_MEMORY_L (t
, n
);
1518 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1520 SET_L_REG (rn
, t
- 1);
1521 t
&= h8_get_mask (sd
);
1522 SET_MEMORY_B (t
, n
);
1525 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1527 SET_L_REG (rn
, t
- 2);
1528 t
&= h8_get_mask (sd
);
1529 SET_MEMORY_W (t
, n
);
1532 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1534 SET_L_REG (rn
, t
- 4);
1535 t
&= h8_get_mask (sd
);
1536 SET_MEMORY_L (t
, n
);
1539 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1541 SET_L_REG (rn
, t
+ 1);
1542 t
&= h8_get_mask (sd
);
1543 SET_MEMORY_B (t
, n
);
1546 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1548 SET_L_REG (rn
, t
+ 2);
1549 t
&= h8_get_mask (sd
);
1550 SET_MEMORY_W (t
, n
);
1553 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1555 SET_L_REG (rn
, t
+ 4);
1556 t
&= h8_get_mask (sd
);
1557 SET_MEMORY_L (t
, n
);
1560 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1561 t
= GET_L_REG (rn
) + abs
;
1562 t
&= h8_get_mask (sd
);
1563 SET_MEMORY_B (t
, n
);
1566 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1567 t
= GET_L_REG (rn
) + abs
;
1568 t
&= h8_get_mask (sd
);
1569 SET_MEMORY_W (t
, n
);
1572 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1573 t
= GET_L_REG (rn
) + abs
;
1574 t
&= h8_get_mask (sd
);
1575 SET_MEMORY_L (t
, n
);
1579 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1580 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1581 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1583 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1592 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1594 return store_1 (sd
, arg
, n
, 0);
1597 /* Store which follows a fetch from the same location.
1598 The difference being that we don't want to do a pre-increment
1599 or pre-decrement at this time: it was already done when we fetched. */
1602 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1604 return store_1 (sd
, arg
, n
, 1);
1607 /* Flag to be set whenever a new SIM_DESC object is created. */
1608 static int init_pointers_needed
= 1;
1611 init_pointers (SIM_DESC sd
)
1613 if (init_pointers_needed
)
1617 if (h8300smode
&& !h8300_normal_mode
)
1618 memory_size
= H8300S_MSIZE
;
1619 else if (h8300hmode
&& !h8300_normal_mode
)
1620 memory_size
= H8300H_MSIZE
;
1622 memory_size
= H8300_MSIZE
;
1623 /* `msize' must be a power of two. */
1624 if ((memory_size
& (memory_size
- 1)) != 0)
1628 "init_pointers: bad memory size %d, defaulting to %d.\n",
1629 memory_size
, H8300S_MSIZE
);
1630 memory_size
= H8300S_MSIZE
;
1633 if (h8_get_memory_buf (sd
))
1634 free (h8_get_memory_buf (sd
));
1636 h8_set_memory_buf (sd
, (unsigned char *)
1637 calloc (sizeof (char), memory_size
));
1638 sd
->memory_size
= memory_size
;
1640 h8_set_mask (sd
, memory_size
- 1);
1642 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1644 for (i
= 0; i
< 8; i
++)
1646 /* FIXME: rewrite using local buffer. */
1647 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1648 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1649 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1650 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1651 h8_set_reg (sd
, i
, 0x00112233);
1666 wreg
[i
] = wreg
[i
+ 8] = 0;
1680 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1681 sim_io_printf (sd
, "init_pointers: internal error.\n");
1683 h8_set_reg (sd
, i
, 0);
1686 init_pointers_needed
= 0;
1690 #define OBITOP(name, f, s, op) \
1691 case O (name, SB): \
1696 if (fetch (sd, &code->dst, &ea)) \
1698 if (fetch (sd, &code->src, &tmp)) \
1700 m = 1 << (tmp & 7); \
1703 if (store (sd, &code->dst,ea)) \
1709 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1713 int tick_start
= get_now ();
1720 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1724 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1728 pc
= h8_get_pc (sd
);
1730 /* The PC should never be odd. */
1733 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1737 /* Get Status Register (flags). */
1740 if (h8300smode
) /* Get exr. */
1742 trace
= (h8_get_exr (sd
) >> 7) & 1;
1743 intMask
= h8_get_exr (sd
) & 7;
1746 oldmask
= h8_get_mask (sd
);
1747 if (!h8300hmode
|| h8300_normal_mode
)
1748 h8_set_mask (sd
, 0xffff);
1751 decoded_inst _code
, *code
= &_code
;
1752 memset (code
, 0, sizeof (*code
));
1753 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, code
);
1759 printf ("%x %d %s\n", pc
, code
->opcode
,
1760 code
->op
? code
->op
->name
: "**");
1762 h8_increment_stats (sd
, code
->opcode
);
1767 cycles
+= code
->cycles
;
1771 switch (code
->opcode
)
1773 case O (O_MOVAB
, SL
):
1774 case O (O_MOVAW
, SL
):
1775 case O (O_MOVAL
, SL
):
1776 /* 1) Evaluate 2nd argument (dst).
1777 2) Mask / zero extend according to whether 1st argument (src)
1778 is INDEXB, INDEXW, or INDEXL.
1779 3) Left-shift the result by 0, 1 or 2, according to size of mova
1780 (mova/b, mova/w, mova/l).
1781 4) Add literal value of 1st argument (src).
1782 5) Store result in 3rd argument (op3).
1785 /* Alas, since this is the only instruction with 3 arguments,
1786 decode doesn't handle them very well. Some fix-up is required.
1788 a) The size of dst is determined by whether src is
1789 INDEXB or INDEXW. */
1791 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1792 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1793 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1794 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1796 /* b) If op3 == null, then this is the short form of the insn.
1797 Dst is the dispreg of src, and op3 is the 32-bit form
1798 of the same register.
1801 if (code
->op3
.type
== 0)
1803 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1804 We get to compose dst and op3 as follows:
1806 op3 is a 32-bit register, ID == src.reg.
1807 dst is the same register, but 8 or 16 bits
1808 depending on whether src is INDEXB or INDEXW.
1811 code
->op3
.type
= X (OP_REG
, SL
);
1812 code
->op3
.reg
= code
->src
.reg
;
1813 code
->op3
.literal
= 0;
1815 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1817 code
->dst
.type
= X (OP_REG
, SB
);
1818 code
->dst
.reg
= code
->op3
.reg
+ 8;
1821 code
->dst
.type
= X (OP_REG
, SW
);
1824 if (fetch (sd
, &code
->dst
, &ea
))
1827 switch (OP_KIND (code
->src
.type
)) {
1828 case OP_INDEXB
: ea
= ea
& 0xff; break;
1829 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1830 case OP_INDEXL
: break;
1831 default: goto illegal
;
1834 switch (code
->opcode
) {
1835 case O (O_MOVAB
, SL
): break;
1836 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1837 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1838 default: goto illegal
;
1841 ea
= ea
+ code
->src
.literal
;
1843 if (store (sd
, &code
->op3
, ea
))
1848 case O (O_SUBX
, SB
): /* subx, extended sub */
1849 if (fetch2 (sd
, &code
->dst
, &rd
))
1851 if (fetch (sd
, &code
->src
, &ea
))
1857 case O (O_SUBX
, SW
): /* subx, extended sub */
1858 if (fetch2 (sd
, &code
->dst
, &rd
))
1860 if (fetch (sd
, &code
->src
, &ea
))
1866 case O (O_SUBX
, SL
): /* subx, extended sub */
1867 if (fetch2 (sd
, &code
->dst
, &rd
))
1869 if (fetch (sd
, &code
->src
, &ea
))
1875 case O (O_ADDX
, SB
): /* addx, extended add */
1876 if (fetch2 (sd
, &code
->dst
, &rd
))
1878 if (fetch (sd
, &code
->src
, &ea
))
1884 case O (O_ADDX
, SW
): /* addx, extended add */
1885 if (fetch2 (sd
, &code
->dst
, &rd
))
1887 if (fetch (sd
, &code
->src
, &ea
))
1893 case O (O_ADDX
, SL
): /* addx, extended add */
1894 if (fetch2 (sd
, &code
->dst
, &rd
))
1896 if (fetch (sd
, &code
->src
, &ea
))
1902 case O (O_SUB
, SB
): /* sub.b */
1903 /* Fetch rd and ea. */
1904 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1910 case O (O_SUB
, SW
): /* sub.w */
1911 /* Fetch rd and ea. */
1912 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1918 case O (O_SUB
, SL
): /* sub.l */
1919 /* Fetch rd and ea. */
1920 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1926 case O (O_NEG
, SB
): /* neg.b */
1928 if (fetch2 (sd
, &code
->src
, &ea
))
1935 case O (O_NEG
, SW
): /* neg.w */
1937 if (fetch2 (sd
, &code
->src
, &ea
))
1944 case O (O_NEG
, SL
): /* neg.l */
1946 if (fetch2 (sd
, &code
->src
, &ea
))
1953 case O (O_ADD
, SB
): /* add.b */
1954 if (fetch2 (sd
, &code
->dst
, &rd
))
1956 if (fetch (sd
, &code
->src
, &ea
))
1961 case O (O_ADD
, SW
): /* add.w */
1962 if (fetch2 (sd
, &code
->dst
, &rd
))
1964 if (fetch (sd
, &code
->src
, &ea
))
1969 case O (O_ADD
, SL
): /* add.l */
1970 if (fetch2 (sd
, &code
->dst
, &rd
))
1972 if (fetch (sd
, &code
->src
, &ea
))
1977 case O (O_AND
, SB
): /* and.b */
1978 /* Fetch rd and ea. */
1979 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1984 case O (O_AND
, SW
): /* and.w */
1985 /* Fetch rd and ea. */
1986 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1991 case O (O_AND
, SL
): /* and.l */
1992 /* Fetch rd and ea. */
1993 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1998 case O (O_OR
, SB
): /* or.b */
1999 /* Fetch rd and ea. */
2000 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2005 case O (O_OR
, SW
): /* or.w */
2006 /* Fetch rd and ea. */
2007 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2012 case O (O_OR
, SL
): /* or.l */
2013 /* Fetch rd and ea. */
2014 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2019 case O (O_XOR
, SB
): /* xor.b */
2020 /* Fetch rd and ea. */
2021 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2026 case O (O_XOR
, SW
): /* xor.w */
2027 /* Fetch rd and ea. */
2028 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2033 case O (O_XOR
, SL
): /* xor.l */
2034 /* Fetch rd and ea. */
2035 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2041 if (fetch (sd
, &code
->src
, &res
))
2043 if (store (sd
, &code
->dst
, res
))
2045 goto just_flags_log8
;
2047 if (fetch (sd
, &code
->src
, &res
))
2049 if (store (sd
, &code
->dst
, res
))
2051 goto just_flags_log16
;
2053 if (fetch (sd
, &code
->src
, &res
))
2055 if (store (sd
, &code
->dst
, res
))
2057 goto just_flags_log32
;
2059 case O (O_MOVMD
, SB
): /* movmd.b */
2066 rd
= GET_MEMORY_B (GET_L_REG (5));
2067 SET_MEMORY_B (GET_L_REG (6), rd
);
2068 SET_L_REG (5, GET_L_REG (5) + 1);
2069 SET_L_REG (6, GET_L_REG (6) + 1);
2074 case O (O_MOVMD
, SW
): /* movmd.w */
2081 rd
= GET_MEMORY_W (GET_L_REG (5));
2082 SET_MEMORY_W (GET_L_REG (6), rd
);
2083 SET_L_REG (5, GET_L_REG (5) + 2);
2084 SET_L_REG (6, GET_L_REG (6) + 2);
2089 case O (O_MOVMD
, SL
): /* movmd.l */
2096 rd
= GET_MEMORY_L (GET_L_REG (5));
2097 SET_MEMORY_L (GET_L_REG (6), rd
);
2098 SET_L_REG (5, GET_L_REG (5) + 4);
2099 SET_L_REG (6, GET_L_REG (6) + 4);
2104 case O (O_MOVSD
, SB
): /* movsd.b */
2105 /* This instruction implements strncpy, with a conditional branch.
2106 r4 contains n, r5 contains src, and r6 contains dst.
2107 The 16-bit displacement operand is added to the pc
2108 if and only if the end of string is reached before
2109 n bytes are transferred. */
2111 ea
= GET_L_REG (4) & 0xffff;
2117 rd
= GET_MEMORY_B (GET_L_REG (5));
2118 SET_MEMORY_B (GET_L_REG (6), rd
);
2119 SET_L_REG (5, GET_L_REG (5) + 1);
2120 SET_L_REG (6, GET_L_REG (6) + 1);
2127 case O (O_EEPMOV
, SB
): /* eepmov.b */
2128 case O (O_EEPMOV
, SW
): /* eepmov.w */
2129 if (h8300hmode
|| h8300smode
)
2131 register unsigned char *_src
, *_dst
;
2132 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2133 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2134 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2136 _src
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
);
2137 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2139 _dst
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
);
2140 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2142 memcpy (_dst
, _src
, count
);
2144 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2145 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2146 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2147 ((code
->opcode
== O (O_EEPMOV
, SW
))
2148 ? (~0xffff) : (~0xff)));
2149 cycles
+= 2 * count
;
2154 case O (O_ADDS
, SL
): /* adds (.l) */
2156 * This insn only uses register operands, but still
2157 * it would be cleaner to use fetch and store... */
2158 SET_L_REG (code
->dst
.reg
,
2159 GET_L_REG (code
->dst
.reg
)
2160 + code
->src
.literal
);
2164 case O (O_SUBS
, SL
): /* subs (.l) */
2166 * This insn only uses register operands, but still
2167 * it would be cleaner to use fetch and store... */
2168 SET_L_REG (code
->dst
.reg
,
2169 GET_L_REG (code
->dst
.reg
)
2170 - code
->src
.literal
);
2173 case O (O_CMP
, SB
): /* cmp.b */
2174 if (fetch (sd
, &code
->dst
, &rd
))
2176 if (fetch (sd
, &code
->src
, &ea
))
2180 goto just_flags_alu8
;
2182 case O (O_CMP
, SW
): /* cmp.w */
2183 if (fetch (sd
, &code
->dst
, &rd
))
2185 if (fetch (sd
, &code
->src
, &ea
))
2189 goto just_flags_alu16
;
2191 case O (O_CMP
, SL
): /* cmp.l */
2192 if (fetch (sd
, &code
->dst
, &rd
))
2194 if (fetch (sd
, &code
->src
, &ea
))
2198 goto just_flags_alu32
;
2200 case O (O_DEC
, SB
): /* dec.b */
2202 * This insn only uses register operands, but still
2203 * it would be cleaner to use fetch and store... */
2204 rd
= GET_B_REG (code
->src
.reg
);
2207 SET_B_REG (code
->src
.reg
, res
);
2208 goto just_flags_inc8
;
2210 case O (O_DEC
, SW
): /* dec.w */
2212 * This insn only uses register operands, but still
2213 * it would be cleaner to use fetch and store... */
2214 rd
= GET_W_REG (code
->dst
.reg
);
2215 ea
= -code
->src
.literal
;
2217 SET_W_REG (code
->dst
.reg
, res
);
2218 goto just_flags_inc16
;
2220 case O (O_DEC
, SL
): /* dec.l */
2222 * This insn only uses register operands, but still
2223 * it would be cleaner to use fetch and store... */
2224 rd
= GET_L_REG (code
->dst
.reg
);
2225 ea
= -code
->src
.literal
;
2227 SET_L_REG (code
->dst
.reg
, res
);
2228 goto just_flags_inc32
;
2230 case O (O_INC
, SB
): /* inc.b */
2232 * This insn only uses register operands, but still
2233 * it would be cleaner to use fetch and store... */
2234 rd
= GET_B_REG (code
->src
.reg
);
2237 SET_B_REG (code
->src
.reg
, res
);
2238 goto just_flags_inc8
;
2240 case O (O_INC
, SW
): /* inc.w */
2242 * This insn only uses register operands, but still
2243 * it would be cleaner to use fetch and store... */
2244 rd
= GET_W_REG (code
->dst
.reg
);
2245 ea
= code
->src
.literal
;
2247 SET_W_REG (code
->dst
.reg
, res
);
2248 goto just_flags_inc16
;
2250 case O (O_INC
, SL
): /* inc.l */
2252 * This insn only uses register operands, but still
2253 * it would be cleaner to use fetch and store... */
2254 rd
= GET_L_REG (code
->dst
.reg
);
2255 ea
= code
->src
.literal
;
2257 SET_L_REG (code
->dst
.reg
, res
);
2258 goto just_flags_inc32
;
2260 case O (O_LDC
, SB
): /* ldc.b */
2261 if (fetch (sd
, &code
->src
, &res
))
2265 case O (O_LDC
, SW
): /* ldc.w */
2266 if (fetch (sd
, &code
->src
, &res
))
2269 /* Word operand, value from MSB, must be shifted. */
2273 case O (O_LDC
, SL
): /* ldc.l */
2274 if (fetch (sd
, &code
->src
, &res
))
2276 switch (code
->dst
.type
) {
2277 case X (OP_SBR
, SL
):
2278 h8_set_sbr (sd
, res
);
2280 case X (OP_VBR
, SL
):
2281 h8_set_vbr (sd
, res
);
2288 case O (O_STC
, SW
): /* stc.w */
2289 case O (O_STC
, SB
): /* stc.b */
2290 if (code
->src
.type
== X (OP_CCR
, SB
))
2293 res
= h8_get_ccr (sd
);
2295 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2298 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2299 res
= h8_get_exr (sd
);
2304 /* Word operand, value to MSB, must be shifted. */
2305 if (code
->opcode
== X (O_STC
, SW
))
2307 if (store (sd
, &code
->dst
, res
))
2310 case O (O_STC
, SL
): /* stc.l */
2311 switch (code
->src
.type
) {
2312 case X (OP_SBR
, SL
):
2313 res
= h8_get_sbr (sd
);
2315 case X (OP_VBR
, SL
):
2316 res
= h8_get_vbr (sd
);
2321 if (store (sd
, &code
->dst
, res
))
2325 case O (O_ANDC
, SB
): /* andc.b */
2326 if (code
->dst
.type
== X (OP_CCR
, SB
))
2329 rd
= h8_get_ccr (sd
);
2331 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2334 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2335 rd
= h8_get_exr (sd
);
2339 ea
= code
->src
.literal
;
2343 case O (O_ORC
, SB
): /* orc.b */
2344 if (code
->dst
.type
== X (OP_CCR
, SB
))
2347 rd
= h8_get_ccr (sd
);
2349 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2352 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2353 rd
= h8_get_exr (sd
);
2357 ea
= code
->src
.literal
;
2361 case O (O_XORC
, SB
): /* xorc.b */
2362 if (code
->dst
.type
== X (OP_CCR
, SB
))
2365 rd
= h8_get_ccr (sd
);
2367 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2370 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2371 rd
= h8_get_exr (sd
);
2375 ea
= code
->src
.literal
;
2379 case O (O_BRAS
, SB
): /* bra/s */
2380 /* This is basically an ordinary branch, with a delay slot. */
2381 if (fetch (sd
, &code
->src
, &res
))
2389 /* Execution continues at next instruction, but
2390 delayed_branch is set up for next cycle. */
2391 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2395 case O (O_BRAB
, SB
): /* bra rd.b */
2396 case O (O_BRAW
, SW
): /* bra rd.w */
2397 case O (O_BRAL
, SL
): /* bra erd.l */
2398 if (fetch (sd
, &code
->src
, &rd
))
2400 switch (OP_SIZE (code
->opcode
)) {
2401 case SB
: rd
&= 0xff; break;
2402 case SW
: rd
&= 0xffff; break;
2403 case SL
: rd
&= 0xffffffff; break;
2405 pc
= code
->next_pc
+ rd
;
2408 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2409 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2410 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2411 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2412 if (fetch (sd
, &code
->dst
, &rd
) ||
2413 fetch (sd
, &code
->src
, &bit
))
2416 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2417 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2419 if ((rd
& (1 << bit
))) /* no branch */
2422 else /* branch/call if set */
2424 if (!(rd
& (1 << bit
))) /* no branch */
2428 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2430 pc
= code
->next_pc
+ res
;
2432 if (code
->opcode
== O (O_BRABC
, SB
) ||
2433 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2441 case O (O_BRA
, SB
): /* bra, branch always */
2446 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2451 case O (O_BHI
, SB
): /* bhi */
2457 case O (O_BLS
, SB
): /* bls */
2462 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2467 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2472 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2476 case O (O_BGT
, SB
): /* bgt */
2477 if (((Z
|| (N
^ V
)) == 0))
2481 case O (O_BLE
, SB
): /* ble */
2482 if (((Z
|| (N
^ V
)) == 1))
2486 case O (O_BGE
, SB
): /* bge */
2490 case O (O_BLT
, SB
): /* blt */
2494 case O (O_BMI
, SB
): /* bmi */
2498 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2503 case O (O_BPL
, SB
): /* bpl */
2507 case O (O_BVC
, SB
): /* bvc */
2511 case O (O_BVS
, SB
): /* bvs */
2516 /* Trap for Command Line setup. */
2517 case O (O_SYS_CMDLINE
, SB
):
2519 int i
= 0; /* Loop counter. */
2520 int j
= 0; /* Loop counter. */
2521 int ind_arg_len
= 0; /* Length of each argument. */
2522 int no_of_args
= 0; /* The no. or cmdline args. */
2523 int current_location
= 0; /* Location of string. */
2524 int old_sp
= 0; /* The Initial Stack Pointer. */
2525 int no_of_slots
= 0; /* No. of slots required on the stack
2526 for storing cmdline args. */
2527 int sp_move
= 0; /* No. of locations by which the stack needs
2529 int new_sp
= 0; /* The final stack pointer location passed
2531 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2532 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2533 args on the stack. */
2534 int char_ptr_size
= 0; /* Size of a character pointer on
2536 int addr_cmdline
= 0; /* Memory location where cmdline has
2538 int size_cmdline
= 0; /* Size of cmdline. */
2540 /* Set the address of 256 free locations where command line is
2542 addr_cmdline
= cmdline_location();
2543 h8_set_reg (sd
, 0, addr_cmdline
);
2545 /* Counting the no. of commandline arguments. */
2546 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2549 /* No. of arguments in the command line. */
2552 /* Current location is just a temporary variable,which we are
2553 setting to the point to the start of our commandline string. */
2554 current_location
= addr_cmdline
;
2556 /* Allocating space for storing pointers of the command line
2558 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2560 /* Setting char_ptr_size to the sizeof (char *) on the different
2562 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2571 for (i
= 0; i
< no_of_args
; i
++)
2575 /* The size of the commandline argument. */
2576 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2578 /* The total size of the command line string. */
2579 size_cmdline
+= ind_arg_len
;
2581 /* As we have only 256 bytes, we need to provide a graceful
2582 exit. Anyways, a program using command line arguments
2583 where we cannot store all the command line arguments
2584 given may behave unpredictably. */
2585 if (size_cmdline
>= 256)
2587 h8_set_reg (sd
, 0, 0);
2592 /* current_location points to the memory where the next
2593 commandline argument is stored. */
2594 argv_ptrs
[i
] = current_location
;
2595 for (j
= 0; j
< ind_arg_len
; j
++)
2597 SET_MEMORY_B ((current_location
+
2598 (sizeof (char) * j
)),
2599 *(h8_get_cmdline_arg (sd
, i
) +
2600 sizeof (char) * j
));
2603 /* Setting current_location to the starting of next
2605 current_location
+= ind_arg_len
;
2609 /* This is the original position of the stack pointer. */
2610 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2612 /* We need space from the stack to store the pointers to argvs. */
2613 /* As we will infringe on the stack, we need to shift the stack
2614 pointer so that the data is not overwritten. We calculate how
2615 much space is required. */
2616 sp_move
= (no_of_args
) * (char_ptr_size
);
2618 /* The final position of stack pointer, we have thus taken some
2619 space from the stack. */
2620 new_sp
= old_sp
- sp_move
;
2622 /* Temporary variable holding value where the argv pointers need
2624 argv_ptrs_location
= new_sp
;
2626 /* The argv pointers are stored at sequential locations. As per
2628 for (i
= 0; i
< no_of_args
; i
++)
2630 /* Saving the argv pointer. */
2631 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2633 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2637 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2640 /* The next location where the pointer to the next argv
2641 string has to be stored. */
2642 argv_ptrs_location
+= char_ptr_size
;
2645 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2647 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2649 SET_MEMORY_L (old_sp
, 0x0);
2653 SET_MEMORY_W (old_sp
, 0x0);
2656 /* Freeing allocated memory. */
2658 for (i
= 0; i
<= no_of_args
; i
++)
2660 free (h8_get_cmdline_arg (sd
, i
));
2662 free (h8_get_command_line (sd
));
2664 /* The no. of argv arguments are returned in Reg 0. */
2665 h8_set_reg (sd
, 0, no_of_args
);
2666 /* The Pointer to argv in Register 1. */
2667 h8_set_reg (sd
, 1, new_sp
);
2668 /* Setting the stack pointer to the new value. */
2669 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2673 /* System call processing starts. */
2674 case O (O_SYS_OPEN
, SB
):
2676 int len
= 0; /* Length of filename. */
2677 char *filename
; /* Filename would go here. */
2678 char temp_char
; /* Temporary character */
2679 int mode
= 0; /* Mode bits for the file. */
2680 int open_return
; /* Return value of open, file descriptor. */
2681 int i
; /* Loop counter */
2682 int filename_ptr
; /* Pointer to filename in cpu memory. */
2684 /* Setting filename_ptr to first argument of open, */
2685 /* and trying to get mode. */
2686 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2688 filename_ptr
= GET_L_REG (0);
2689 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2693 filename_ptr
= GET_W_REG (0);
2694 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2697 /* Trying to find the length of the filename. */
2698 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2701 while (temp_char
!= '\0')
2703 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2707 /* Allocating space for the filename. */
2708 filename
= (char *) malloc (sizeof (char) * len
);
2710 /* String copying the filename from memory. */
2711 for (i
= 0; i
< len
; i
++)
2713 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2714 filename
[i
] = temp_char
;
2717 /* Callback to open and return the file descriptor. */
2718 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2720 /* Return value in register 0. */
2721 h8_set_reg (sd
, 0, open_return
);
2723 /* Freeing memory used for filename. */
2728 case O (O_SYS_READ
, SB
):
2730 char *char_ptr
; /* Where characters read would be stored. */
2731 int fd
; /* File descriptor */
2732 int buf_size
; /* BUF_SIZE parameter in read. */
2733 int i
= 0; /* Temporary Loop counter */
2734 int read_return
= 0; /* Return value from callback to
2737 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2738 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2740 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2742 /* Callback to read and return the no. of characters read. */
2744 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2746 /* The characters read are stored in cpu memory. */
2747 for (i
= 0; i
< buf_size
; i
++)
2749 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2750 *(char_ptr
+ (sizeof (char) * i
)));
2753 /* Return value in Register 0. */
2754 h8_set_reg (sd
, 0, read_return
);
2756 /* Freeing memory used as buffer. */
2761 case O (O_SYS_WRITE
, SB
):
2763 int fd
; /* File descriptor */
2764 char temp_char
; /* Temporary character */
2765 int len
; /* Length of write, Parameter II to write. */
2766 int char_ptr
; /* Character Pointer, Parameter I of write. */
2767 char *ptr
; /* Where characters to be written are stored.
2769 int write_return
; /* Return value from callback to write. */
2770 int i
= 0; /* Loop counter */
2772 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2773 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2774 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2776 /* Allocating space for the characters to be written. */
2777 ptr
= (char *) malloc (sizeof (char) * len
);
2779 /* Fetching the characters from cpu memory. */
2780 for (i
= 0; i
< len
; i
++)
2782 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2786 /* Callback write and return the no. of characters written. */
2787 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2789 /* Return value in Register 0. */
2790 h8_set_reg (sd
, 0, write_return
);
2792 /* Freeing memory used as buffer. */
2797 case O (O_SYS_LSEEK
, SB
):
2799 int fd
; /* File descriptor */
2800 int offset
; /* Offset */
2801 int origin
; /* Origin */
2802 int lseek_return
; /* Return value from callback to lseek. */
2804 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2805 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2806 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2808 /* Callback lseek and return offset. */
2810 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2812 /* Return value in register 0. */
2813 h8_set_reg (sd
, 0, lseek_return
);
2817 case O (O_SYS_CLOSE
, SB
):
2819 int fd
; /* File descriptor */
2820 int close_return
; /* Return value from callback to close. */
2822 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2824 /* Callback close and return. */
2825 close_return
= sim_callback
->close (sim_callback
, fd
);
2827 /* Return value in register 0. */
2828 h8_set_reg (sd
, 0, close_return
);
2832 case O (O_SYS_FSTAT
, SB
):
2834 int fd
; /* File descriptor */
2835 struct stat stat_rec
; /* Stat record */
2836 int fstat_return
; /* Return value from callback to stat. */
2837 int stat_ptr
; /* Pointer to stat record. */
2838 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2840 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2842 /* Setting stat_ptr to second argument of stat. */
2843 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2845 /* Callback stat and return. */
2846 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
2849 /* Have stat_ptr point to starting of stat_rec. */
2850 temp_stat_ptr
= (char *) (&stat_rec
);
2852 /* Setting up the stat structure returned. */
2853 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2855 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2857 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2859 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2861 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2863 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2865 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2867 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2869 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2871 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2873 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2875 /* Return value in register 0. */
2876 h8_set_reg (sd
, 0, fstat_return
);
2880 case O (O_SYS_STAT
, SB
):
2882 int len
= 0; /* Length of filename. */
2883 char *filename
; /* Filename would go here. */
2884 char temp_char
; /* Temporary character */
2885 int filename_ptr
; /* Pointer to filename in cpu memory. */
2886 struct stat stat_rec
; /* Stat record */
2887 int stat_return
; /* Return value from callback to stat */
2888 int stat_ptr
; /* Pointer to stat record. */
2889 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2890 int i
= 0; /* Loop Counter */
2892 /* Setting filename_ptr to first argument of open. */
2893 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2895 /* Trying to find the length of the filename. */
2896 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2899 while (temp_char
!= '\0')
2901 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2905 /* Allocating space for the filename. */
2906 filename
= (char *) malloc (sizeof (char) * len
);
2908 /* String copying the filename from memory. */
2909 for (i
= 0; i
< len
; i
++)
2911 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2912 filename
[i
] = temp_char
;
2915 /* Setting stat_ptr to second argument of stat. */
2916 /* stat_ptr = h8_get_reg (sd, 1); */
2917 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2919 /* Callback stat and return. */
2921 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
2923 /* Have stat_ptr point to starting of stat_rec. */
2924 temp_stat_ptr
= (char *) (&stat_rec
);
2926 /* Freeing memory used for filename. */
2929 /* Setting up the stat structure returned. */
2930 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2932 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2934 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2936 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2938 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2940 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2942 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2944 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2946 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2948 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2950 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2952 /* Return value in register 0. */
2953 h8_set_reg (sd
, 0, stat_return
);
2956 /* End of system call processing. */
2958 case O (O_NOT
, SB
): /* not.b */
2959 if (fetch2 (sd
, &code
->src
, &rd
))
2965 case O (O_NOT
, SW
): /* not.w */
2966 if (fetch2 (sd
, &code
->src
, &rd
))
2972 case O (O_NOT
, SL
): /* not.l */
2973 if (fetch2 (sd
, &code
->src
, &rd
))
2979 case O (O_SHLL
, SB
): /* shll.b */
2980 case O (O_SHLR
, SB
): /* shlr.b */
2981 if (fetch2 (sd
, &code
->dst
, &rd
))
2984 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
2985 ea
= 1; /* unary op */
2986 else /* binary op */
2987 fetch (sd
, &code
->src
, &ea
);
2989 if (code
->opcode
== O (O_SHLL
, SB
))
2992 c
= rd
& (0x80 >> (ea
- 1));
2998 c
= rd
& (1 << (ea
- 1));
2999 rd
= (unsigned char) rd
>> ea
;
3003 case O (O_SHLL
, SW
): /* shll.w */
3004 case O (O_SHLR
, SW
): /* shlr.w */
3005 if (fetch2 (sd
, &code
->dst
, &rd
))
3008 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3009 ea
= 1; /* unary op */
3011 fetch (sd
, &code
->src
, &ea
);
3013 if (code
->opcode
== O (O_SHLL
, SW
))
3016 c
= rd
& (0x8000 >> (ea
- 1));
3022 c
= rd
& (1 << (ea
- 1));
3023 rd
= (unsigned short) rd
>> ea
;
3027 case O (O_SHLL
, SL
): /* shll.l */
3028 case O (O_SHLR
, SL
): /* shlr.l */
3029 if (fetch2 (sd
, &code
->dst
, &rd
))
3032 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3033 ea
= 1; /* unary op */
3035 fetch (sd
, &code
->src
, &ea
);
3037 if (code
->opcode
== O (O_SHLL
, SL
))
3040 c
= rd
& (0x80000000 >> (ea
- 1));
3046 c
= rd
& (1 << (ea
- 1));
3047 rd
= (unsigned int) rd
>> ea
;
3051 case O (O_SHAL
, SB
):
3052 case O (O_SHAR
, SB
):
3053 if (fetch2 (sd
, &code
->dst
, &rd
))
3056 if (code
->src
.type
== X (OP_IMM
, SB
))
3057 fetch (sd
, &code
->src
, &ea
);
3061 if (code
->opcode
== O (O_SHAL
, SB
))
3063 c
= rd
& (0x80 >> (ea
- 1));
3064 res
= rd
>> (7 - ea
);
3065 v
= ((res
& 1) && !(res
& 2))
3066 || (!(res
& 1) && (res
& 2));
3071 c
= rd
& (1 << (ea
- 1));
3073 rd
= ((signed char) rd
) >> ea
;
3077 case O (O_SHAL
, SW
):
3078 case O (O_SHAR
, SW
):
3079 if (fetch2 (sd
, &code
->dst
, &rd
))
3082 if (code
->src
.type
== X (OP_IMM
, SW
))
3083 fetch (sd
, &code
->src
, &ea
);
3087 if (code
->opcode
== O (O_SHAL
, SW
))
3089 c
= rd
& (0x8000 >> (ea
- 1));
3090 res
= rd
>> (15 - ea
);
3091 v
= ((res
& 1) && !(res
& 2))
3092 || (!(res
& 1) && (res
& 2));
3097 c
= rd
& (1 << (ea
- 1));
3099 rd
= ((signed short) rd
) >> ea
;
3103 case O (O_SHAL
, SL
):
3104 case O (O_SHAR
, SL
):
3105 if (fetch2 (sd
, &code
->dst
, &rd
))
3108 if (code
->src
.type
== X (OP_IMM
, SL
))
3109 fetch (sd
, &code
->src
, &ea
);
3113 if (code
->opcode
== O (O_SHAL
, SL
))
3115 c
= rd
& (0x80000000 >> (ea
- 1));
3116 res
= rd
>> (31 - ea
);
3117 v
= ((res
& 1) && !(res
& 2))
3118 || (!(res
& 1) && (res
& 2));
3123 c
= rd
& (1 << (ea
- 1));
3125 rd
= ((signed int) rd
) >> ea
;
3129 case O (O_ROTL
, SB
):
3130 case O (O_ROTR
, SB
):
3131 if (fetch2 (sd
, &code
->dst
, &rd
))
3134 if (code
->src
.type
== X (OP_IMM
, SB
))
3135 fetch (sd
, &code
->src
, &ea
);
3140 if (code
->opcode
== O (O_ROTL
, SB
))
3150 rd
= ((unsigned char) rd
) >> 1;
3158 case O (O_ROTL
, SW
):
3159 case O (O_ROTR
, SW
):
3160 if (fetch2 (sd
, &code
->dst
, &rd
))
3163 if (code
->src
.type
== X (OP_IMM
, SW
))
3164 fetch (sd
, &code
->src
, &ea
);
3169 if (code
->opcode
== O (O_ROTL
, SW
))
3179 rd
= ((unsigned short) rd
) >> 1;
3187 case O (O_ROTL
, SL
):
3188 case O (O_ROTR
, SL
):
3189 if (fetch2 (sd
, &code
->dst
, &rd
))
3192 if (code
->src
.type
== X (OP_IMM
, SL
))
3193 fetch (sd
, &code
->src
, &ea
);
3198 if (code
->opcode
== O (O_ROTL
, SL
))
3200 c
= rd
& 0x80000000;
3208 rd
= ((unsigned int) rd
) >> 1;
3216 case O (O_ROTXL
, SB
):
3217 case O (O_ROTXR
, SB
):
3218 if (fetch2 (sd
, &code
->dst
, &rd
))
3221 if (code
->src
.type
== X (OP_IMM
, SB
))
3222 fetch (sd
, &code
->src
, &ea
);
3227 if (code
->opcode
== O (O_ROTXL
, SB
))
3238 rd
= ((unsigned char) rd
) >> 1;
3247 case O (O_ROTXL
, SW
):
3248 case O (O_ROTXR
, SW
):
3249 if (fetch2 (sd
, &code
->dst
, &rd
))
3252 if (code
->src
.type
== X (OP_IMM
, SW
))
3253 fetch (sd
, &code
->src
, &ea
);
3258 if (code
->opcode
== O (O_ROTXL
, SW
))
3269 rd
= ((unsigned short) rd
) >> 1;
3278 case O (O_ROTXL
, SL
):
3279 case O (O_ROTXR
, SL
):
3280 if (fetch2 (sd
, &code
->dst
, &rd
))
3283 if (code
->src
.type
== X (OP_IMM
, SL
))
3284 fetch (sd
, &code
->src
, &ea
);
3289 if (code
->opcode
== O (O_ROTXL
, SL
))
3291 res
= rd
& 0x80000000;
3300 rd
= ((unsigned int) rd
) >> 1;
3311 case O (O_JMP
, SB
): /* jmp */
3313 fetch (sd
, &code
->src
, &pc
);
3318 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3320 if (fetch (sd
, &code
->src
, &pc
))
3323 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3325 if (h8300hmode
&& !h8300_normal_mode
)
3328 SET_MEMORY_L (tmp
, code
->next_pc
);
3333 SET_MEMORY_W (tmp
, code
->next_pc
);
3335 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3341 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3342 if (fetch (sd
, &code
->src
, &res
))
3344 pc
= code
->next_pc
+ res
;
3347 case O (O_RTE
, SN
): /* rte, return from exception */
3349 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3350 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3352 if (h8300smode
) /* pop exr */
3354 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3357 if (h8300hmode
&& !h8300_normal_mode
)
3359 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3361 pc
= GET_MEMORY_L (tmp
);
3366 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3368 pc
= GET_MEMORY_W (tmp
);
3373 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3376 case O (O_RTS
, SN
): /* rts, return from subroutine */
3378 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3380 if (h8300hmode
&& !h8300_normal_mode
)
3382 pc
= GET_MEMORY_L (tmp
);
3387 pc
= GET_MEMORY_W (tmp
);
3391 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3394 case O (O_ILL
, SB
): /* illegal */
3395 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3398 case O (O_SLEEP
, SN
): /* sleep */
3399 /* Check for magic numbers in r1 and r2. */
3400 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3401 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3402 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3404 /* This trap comes from _exit, not from gdb. */
3405 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3406 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3409 /* Unfortunately this won't really work, because
3410 when we take a breakpoint trap, R0 has a "random",
3411 user-defined value. Don't see any immediate solution. */
3412 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3414 /* Pass the stop signal up to gdb. */
3415 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3416 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3421 /* Treat it as a sigtrap. */
3422 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3426 case O (O_TRAPA
, SB
): /* trapa */
3427 if (fetch (sd
, &code
->src
, &res
))
3428 goto end
; /* res is vector number. */
3430 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3431 if(h8300_normal_mode
)
3434 SET_MEMORY_W (tmp
, code
->next_pc
);
3436 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3441 SET_MEMORY_L (tmp
, code
->next_pc
);
3443 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3451 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3454 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3456 if(h8300_normal_mode
)
3457 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3459 pc
= GET_MEMORY_L (0x20 + res
* 4);
3463 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3466 case O (O_BSETEQ
, SB
):
3471 case O (O_BSETNE
, SB
):
3476 case O (O_BCLREQ
, SB
):
3481 case O (O_BCLRNE
, SB
):
3486 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3487 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3489 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3491 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3492 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3493 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3494 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3495 if (C
) ea
|= m
); /* bst */
3496 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3497 if (!C
) ea
|= m
); /* bist */
3498 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3499 if (Z
) ea
|= m
); /* bstz */
3500 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3501 if (!Z
) ea
|= m
); /* bistz */
3502 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3503 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3504 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3505 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3506 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3507 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3509 case O (O_BFLD
, SB
): /* bfld */
3512 if (fetch (sd
, &code
->src
, &bit
))
3517 if (fetch (sd
, &code
->dst
, &ea
))
3527 if (store (sd
, &code
->op3
, ea
))
3532 case O(O_BFST
, SB
): /* bfst */
3533 /* bitfield store */
3534 /* NOTE: the imm8 value is in dst, and the ea value
3535 (which is actually the destination) is in op3.
3536 It has to be that way, to avoid breaking the assembler. */
3538 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3540 if (bit
== 0) /* noop -- nothing to do. */
3543 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3546 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3549 /* Left-shift the register data into position. */
3550 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3553 /* Combine it with the neighboring bits. */
3554 ea
= (ea
& ~bit
) | (rd
& bit
);
3557 if (store2 (sd
, &code
->op3
, ea
))
3561 case O (O_CLRMAC
, SN
): /* clrmac */
3562 h8_set_mach (sd
, 0);
3563 h8_set_macl (sd
, 0);
3564 h8_set_macZ (sd
, 1);
3565 h8_set_macV (sd
, 0);
3566 h8_set_macN (sd
, 0);
3569 case O (O_STMAC
, SL
): /* stmac, 260 */
3570 switch (code
->src
.type
) {
3571 case X (OP_MACH
, SL
):
3572 res
= h8_get_mach (sd
);
3573 if (res
& 0x200) /* sign extend */
3576 case X (OP_MACL
, SL
):
3577 res
= h8_get_macl (sd
);
3579 default: goto illegal
;
3581 nz
= !h8_get_macZ (sd
);
3582 n
= h8_get_macN (sd
);
3583 v
= h8_get_macV (sd
);
3585 if (store (sd
, &code
->dst
, res
))
3590 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3591 if (fetch (sd
, &code
->src
, &rd
))
3594 switch (code
->dst
.type
) {
3595 case X (OP_MACH
, SL
):
3596 rd
&= 0x3ff; /* Truncate to 10 bits */
3597 h8_set_mach (sd
, rd
);
3599 case X (OP_MACL
, SL
):
3600 h8_set_macl (sd
, rd
);
3602 default: goto illegal
;
3604 h8_set_macV (sd
, 0);
3608 if (fetch (sd
, &code
->src
, &rd
) ||
3609 fetch (sd
, &code
->dst
, &res
))
3612 /* Ye gods, this is non-portable!
3613 However, the existing mul/div code is similar. */
3614 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3616 if (h8_get_macS (sd
)) /* Saturating mode */
3618 long long mac
= h8_get_macl (sd
);
3620 if (mac
& 0x80000000) /* sign extend */
3621 mac
|= 0xffffffff00000000LL
;
3624 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3625 h8_set_macV (sd
, 1);
3626 h8_set_macZ (sd
, (mac
== 0));
3627 h8_set_macN (sd
, (mac
< 0));
3628 h8_set_macl (sd
, (int) mac
);
3630 else /* "Less Saturating" mode */
3632 long long mac
= h8_get_mach (sd
);
3634 mac
+= h8_get_macl (sd
);
3636 if (mac
& 0x20000000000LL
) /* sign extend */
3637 mac
|= 0xfffffc0000000000LL
;
3640 if (mac
> 0x1ffffffffffLL
||
3641 mac
< (long long) 0xfffffe0000000000LL
)
3642 h8_set_macV (sd
, 1);
3643 h8_set_macZ (sd
, (mac
== 0));
3644 h8_set_macN (sd
, (mac
< 0));
3645 h8_set_macl (sd
, (int) mac
);
3647 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3651 case O (O_MULS
, SW
): /* muls.w */
3652 if (fetch (sd
, &code
->src
, &ea
) ||
3653 fetch (sd
, &code
->dst
, &rd
))
3656 ea
= SEXTSHORT (ea
);
3657 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3661 if (store (sd
, &code
->dst
, res
))
3666 case O (O_MULS
, SL
): /* muls.l */
3667 if (fetch (sd
, &code
->src
, &ea
) ||
3668 fetch (sd
, &code
->dst
, &rd
))
3673 n
= res
& 0x80000000;
3674 nz
= res
& 0xffffffff;
3675 if (store (sd
, &code
->dst
, res
))
3679 case O (O_MULSU
, SL
): /* muls/u.l */
3680 if (fetch (sd
, &code
->src
, &ea
) ||
3681 fetch (sd
, &code
->dst
, &rd
))
3684 /* Compute upper 32 bits of the 64-bit result. */
3685 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3687 n
= res
& 0x80000000;
3688 nz
= res
& 0xffffffff;
3689 if (store (sd
, &code
->dst
, res
))
3693 case O (O_MULU
, SW
): /* mulu.w */
3694 if (fetch (sd
, &code
->src
, &ea
) ||
3695 fetch (sd
, &code
->dst
, &rd
))
3698 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3700 /* Don't set Z or N. */
3701 if (store (sd
, &code
->dst
, res
))
3706 case O (O_MULU
, SL
): /* mulu.l */
3707 if (fetch (sd
, &code
->src
, &ea
) ||
3708 fetch (sd
, &code
->dst
, &rd
))
3713 /* Don't set Z or N. */
3714 if (store (sd
, &code
->dst
, res
))
3719 case O (O_MULUU
, SL
): /* mulu/u.l */
3720 if (fetch (sd
, &code
->src
, &ea
) ||
3721 fetch (sd
, &code
->dst
, &rd
))
3724 /* Compute upper 32 bits of the 64-bit result. */
3725 res
= (((unsigned long long) (unsigned) ea
) *
3726 ((unsigned long long) (unsigned) rd
)) >> 32;
3728 /* Don't set Z or N. */
3729 if (store (sd
, &code
->dst
, res
))
3734 case O (O_MULXS
, SB
): /* mulxs.b */
3735 if (fetch (sd
, &code
->src
, &ea
) ||
3736 fetch (sd
, &code
->dst
, &rd
))
3740 res
= ea
* SEXTCHAR (rd
);
3744 if (store (sd
, &code
->dst
, res
))
3749 case O (O_MULXS
, SW
): /* mulxs.w */
3750 if (fetch (sd
, &code
->src
, &ea
) ||
3751 fetch (sd
, &code
->dst
, &rd
))
3754 ea
= SEXTSHORT (ea
);
3755 res
= ea
* SEXTSHORT (rd
& 0xffff);
3757 n
= res
& 0x80000000;
3758 nz
= res
& 0xffffffff;
3759 if (store (sd
, &code
->dst
, res
))
3764 case O (O_MULXU
, SB
): /* mulxu.b */
3765 if (fetch (sd
, &code
->src
, &ea
) ||
3766 fetch (sd
, &code
->dst
, &rd
))
3769 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3771 if (store (sd
, &code
->dst
, res
))
3776 case O (O_MULXU
, SW
): /* mulxu.w */
3777 if (fetch (sd
, &code
->src
, &ea
) ||
3778 fetch (sd
, &code
->dst
, &rd
))
3781 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3783 if (store (sd
, &code
->dst
, res
))
3788 case O (O_TAS
, SB
): /* tas (test and set) */
3789 if (!h8300sxmode
) /* h8sx can use any register. */
3790 switch (code
->src
.reg
)
3801 if (fetch (sd
, &code
->src
, &res
))
3803 if (store (sd
, &code
->src
, res
| 0x80))
3806 goto just_flags_log8
;
3808 case O (O_DIVU
, SW
): /* divu.w */
3809 if (fetch (sd
, &code
->src
, &ea
) ||
3810 fetch (sd
, &code
->dst
, &rd
))
3816 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3820 if (store (sd
, &code
->dst
, res
))
3824 case O (O_DIVU
, SL
): /* divu.l */
3825 if (fetch (sd
, &code
->src
, &ea
) ||
3826 fetch (sd
, &code
->dst
, &rd
))
3829 n
= ea
& 0x80000000;
3830 nz
= ea
& 0xffffffff;
3832 res
= (unsigned) rd
/ ea
;
3836 if (store (sd
, &code
->dst
, res
))
3840 case O (O_DIVS
, SW
): /* divs.w */
3841 if (fetch (sd
, &code
->src
, &ea
) ||
3842 fetch (sd
, &code
->dst
, &rd
))
3847 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3857 if (store (sd
, &code
->dst
, res
))
3861 case O (O_DIVS
, SL
): /* divs.l */
3862 if (fetch (sd
, &code
->src
, &ea
) ||
3863 fetch (sd
, &code
->dst
, &rd
))
3877 n
= res
& 0x80000000;
3878 if (store (sd
, &code
->dst
, res
))
3882 case O (O_DIVXU
, SB
): /* divxu.b */
3883 if (fetch (sd
, &code
->src
, &ea
) ||
3884 fetch (sd
, &code
->dst
, &rd
))
3887 rd
= UEXTSHORT (rd
);
3894 tmp
= (unsigned) rd
% ea
;
3895 res
= (unsigned) rd
/ ea
;
3903 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3907 case O (O_DIVXU
, SW
): /* divxu.w */
3908 if (fetch (sd
, &code
->src
, &ea
) ||
3909 fetch (sd
, &code
->dst
, &rd
))
3912 ea
= UEXTSHORT (ea
);
3918 tmp
= (unsigned) rd
% ea
;
3919 res
= (unsigned) rd
/ ea
;
3927 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3931 case O (O_DIVXS
, SB
): /* divxs.b */
3932 if (fetch (sd
, &code
->src
, &ea
) ||
3933 fetch (sd
, &code
->dst
, &rd
))
3936 rd
= SEXTSHORT (rd
);
3941 tmp
= (int) rd
% (int) ea
;
3942 res
= (int) rd
/ (int) ea
;
3953 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3957 case O (O_DIVXS
, SW
): /* divxs.w */
3958 if (fetch (sd
, &code
->src
, &ea
) ||
3959 fetch (sd
, &code
->dst
, &rd
))
3962 ea
= SEXTSHORT (ea
);
3966 tmp
= (int) rd
% (int) ea
;
3967 res
= (int) rd
/ (int) ea
;
3977 n
= res
& 0x80000000;
3978 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3982 case O (O_EXTS
, SW
): /* exts.w, signed extend */
3983 if (fetch2 (sd
, &code
->dst
, &rd
))
3985 ea
= rd
& 0x80 ? -256 : 0;
3986 res
= (rd
& 0xff) + ea
;
3989 case O (O_EXTS
, SL
): /* exts.l, signed extend */
3990 if (fetch2 (sd
, &code
->dst
, &rd
))
3992 if (code
->src
.type
== X (OP_IMM
, SL
))
3994 if (fetch (sd
, &code
->src
, &ea
))
3997 if (ea
== 2) /* exts.l #2, nn */
3999 /* Sign-extend from 8-bit to 32-bit. */
4000 ea
= rd
& 0x80 ? -256 : 0;
4001 res
= (rd
& 0xff) + ea
;
4005 /* Sign-extend from 16-bit to 32-bit. */
4006 ea
= rd
& 0x8000 ? -65536 : 0;
4007 res
= (rd
& 0xffff) + ea
;
4010 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4011 if (fetch2 (sd
, &code
->dst
, &rd
))
4014 res
= (rd
& 0xff) + ea
;
4017 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4018 if (fetch2 (sd
, &code
->dst
, &rd
))
4020 if (code
->src
.type
== X (OP_IMM
, SL
))
4022 if (fetch (sd
, &code
->src
, &ea
))
4025 if (ea
== 2) /* extu.l #2, nn */
4027 /* Zero-extend from 8-bit to 32-bit. */
4029 res
= (rd
& 0xff) + ea
;
4033 /* Zero-extend from 16-bit to 32-bit. */
4035 res
= (rd
& 0xffff) + ea
;
4038 case O (O_NOP
, SN
): /* nop */
4041 case O (O_STM
, SL
): /* stm, store to memory */
4043 int nregs
, firstreg
, i
;
4045 nregs
= GET_MEMORY_B (pc
+ 1);
4048 firstreg
= code
->src
.reg
;
4050 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4052 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4053 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4058 case O (O_LDM
, SL
): /* ldm, load from memory */
4059 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4060 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4062 int nregs
, firstreg
, i
;
4064 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4065 firstreg
= code
->dst
.reg
& 0xf;
4066 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4068 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4069 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4072 switch (code
->opcode
) {
4073 case O (O_RTEL
, SN
):
4075 case O (O_RTSL
, SN
):
4084 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4085 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4086 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4087 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4088 res
= res
; /* Value added == 0. */
4089 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4090 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4091 res
= res
+ 0x6; /* Value added == 6. */
4092 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4093 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4094 res
= res
+ 0x6; /* Value added == 6. */
4095 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4096 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4097 res
= res
+ 0x60; /* Value added == 60. */
4098 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4099 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4100 res
= res
+ 0x66; /* Value added == 66. */
4101 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4102 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4103 res
= res
+ 0x66; /* Value added == 66. */
4104 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4105 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4106 res
= res
+ 0x60; /* Value added == 60. */
4107 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4108 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4109 res
= res
+ 0x66; /* Value added == 66. */
4110 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4111 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4112 res
= res
+ 0x66; /* Value added == 66. */
4117 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4118 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4119 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4120 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4121 res
= res
; /* Value added == 0. */
4122 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4123 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4124 res
= res
+ 0xfa; /* Value added == 0xfa. */
4125 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4126 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4127 res
= res
+ 0xa0; /* Value added == 0xa0. */
4128 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4129 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4130 res
= res
+ 0x9a; /* Value added == 0x9a. */
4136 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4141 sim_io_printf (sd
, "sim_resume: internal error.\n");
4142 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4146 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4147 code
->dst
.type
== X (OP_CCR
, SW
))
4149 h8_set_ccr (sd
, res
);
4152 else if (h8300smode
&&
4153 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4154 code
->dst
.type
== X (OP_EXR
, SW
)))
4156 h8_set_exr (sd
, res
);
4157 if (h8300smode
) /* Get exr. */
4159 trace
= (h8_get_exr (sd
) >> 7) & 1;
4160 intMask
= h8_get_exr (sd
) & 7;
4169 /* When a branch works */
4170 if (fetch (sd
, &code
->src
, &res
))
4172 if (res
& 1) /* bad address */
4174 pc
= code
->next_pc
+ res
;
4177 /* Set the cond codes from res */
4180 /* Set the flags after an 8 bit inc/dec operation */
4184 v
= (rd
& 0x7f) == 0x7f;
4187 /* Set the flags after an 16 bit inc/dec operation */
4191 v
= (rd
& 0x7fff) == 0x7fff;
4194 /* Set the flags after an 32 bit inc/dec operation */
4196 n
= res
& 0x80000000;
4197 nz
= res
& 0xffffffff;
4198 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4202 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4205 if (store2 (sd
, &code
->dst
, rd
))
4210 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4213 if (store2 (sd
, &code
->dst
, rd
))
4218 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4219 n
= (rd
& 0x80000000);
4220 nz
= rd
& 0xffffffff;
4221 if (store2 (sd
, &code
->dst
, rd
))
4226 if (store2 (sd
, &code
->dst
, res
))
4230 /* flags after a 32bit logical operation */
4231 n
= res
& 0x80000000;
4232 nz
= res
& 0xffffffff;
4237 if (store2 (sd
, &code
->dst
, res
))
4241 /* flags after a 16bit logical operation */
4248 if (store2 (sd
, &code
->dst
, res
))
4258 if (store2 (sd
, &code
->dst
, res
))
4265 switch (code
->opcode
/ 4)
4269 v
= ((rd
& 0x80) == (ea
& 0x80)
4270 && (rd
& 0x80) != (res
& 0x80));
4275 v
= ((rd
& 0x80) != (-ea
& 0x80)
4276 && (rd
& 0x80) != (res
& 0x80));
4283 break; /* No effect on v flag. */
4288 if (store2 (sd
, &code
->dst
, res
))
4294 c
= (res
& 0x10000);
4295 switch (code
->opcode
/ 4)
4299 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4300 && (rd
& 0x8000) != (res
& 0x8000));
4305 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4306 && (rd
& 0x8000) != (res
& 0x8000));
4315 if (store2 (sd
, &code
->dst
, res
))
4319 n
= res
& 0x80000000;
4320 nz
= res
& 0xffffffff;
4321 switch (code
->opcode
/ 4)
4325 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4326 && (rd
& 0x80000000) != (res
& 0x80000000));
4327 c
= ((unsigned) res
< (unsigned) rd
) ||
4328 ((unsigned) res
< (unsigned) ea
);
4333 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4334 && (rd
& 0x80000000) != (res
& 0x80000000));
4335 c
= (unsigned) rd
< (unsigned) -ea
;
4338 v
= (rd
== 0x80000000);
4345 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4348 h8_set_delayed_branch (sd
, 0);
4356 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4357 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4358 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4363 h8_set_exr (sd
, (trace
<<7) | intMask
);
4365 h8_set_mask (sd
, oldmask
);
4369 sim_engine_run (SIM_DESC sd
,
4370 int next_cpu_nr
, /* ignore */
4371 int nr_cpus
, /* ignore */
4376 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4378 cpu
= STATE_CPU (sd
, 0);
4382 step_once (sd
, cpu
);
4383 if (sim_events_tick (sd
))
4384 sim_events_process (sd
);
4389 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4396 for (i
= 0; i
< size
; i
++)
4398 if (addr
< memory_size
)
4400 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4409 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4414 if (addr
+ size
< memory_size
)
4415 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4422 h8300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *value
, int length
)
4427 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4428 shortval
= (value
[0] << 8) | (value
[1]);
4429 intval
= h8300hmode
? longval
: shortval
;
4431 init_pointers (CPU_STATE (cpu
));
4435 if(h8300_normal_mode
)
4436 cpu
->pc
= shortval
; /* PC for Normal mode is 2 bytes */
4456 cpu
->regs
[rn
] = intval
;
4461 cpu
->regs
[rn
] = longval
;
4468 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *buf
, int length
)
4473 init_pointers (CPU_STATE (cpu
));
4475 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4510 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4511 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4528 sim_info (SIM_DESC sd
, int verbose
)
4530 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4531 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4533 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (sd
));
4534 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (sd
));
4535 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4536 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4537 if (timetaken
!= 0.0)
4538 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4541 /* This to be conditional on `what' (aka `verbose'),
4542 however it was never passed as non-zero. */
4546 for (i
= 0; i
< O_LAST
; i
++)
4548 if (h8_get_stats (sd
, i
))
4549 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4555 /* Indicate whether the cpu is an H8/300 or H8/300H.
4556 FLAG is non-zero for the H8/300H. */
4559 set_h8300h (unsigned long machine
)
4561 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4562 This function being replaced by a sim_open:ARGV configuration
4565 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4567 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4570 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4573 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4576 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4577 h8300_normal_mode
= 1;
4580 /* H8300-specific options.
4581 TODO: These really should be merged into the common model modules. */
4589 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4590 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4592 switch ((H8300_OPTIONS
) opt
)
4595 set_h8300h (bfd_mach_h8300h
);
4598 set_h8300h (bfd_mach_h8300s
);
4600 case OPTION_H8300SX
:
4601 set_h8300h (bfd_mach_h8300sx
);
4605 /* We'll actually never get here; the caller handles the error
4607 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4614 static const OPTION h8300_options
[] =
4616 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4617 'h', NULL
, "Indicate the CPU is H8/300H",
4618 h8300_option_handler
},
4619 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4620 'S', NULL
, "Indicate the CPU is H8S",
4621 h8300_option_handler
},
4622 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4623 'x', NULL
, "Indicate the CPU is H8SX",
4624 h8300_option_handler
},
4625 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4629 h8300_pc_get (sim_cpu
*cpu
)
4635 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4640 /* Cover function of sim_state_free to free the cpu buffers as well. */
4643 free_state (SIM_DESC sd
)
4645 if (STATE_MODULES (sd
) != NULL
)
4646 sim_module_uninstall (sd
);
4648 /* Fixme: free buffers in _sim_cpu. */
4649 sim_state_free (sd
);
4653 sim_open (SIM_OPEN_KIND kind
,
4654 struct host_callback_struct
*callback
,
4662 sd
= sim_state_alloc (kind
, callback
);
4664 /* The cpu data is kept in a separately allocated chunk of memory. */
4665 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
4671 cpu
= STATE_CPU (sd
, 0);
4672 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4673 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
4674 /* sim_cpu object is new, so some initialization is needed. */
4675 init_pointers_needed
= 1;
4677 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4683 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4689 /* The parser will print an error message for us, so we silently return. */
4690 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4692 /* Uninstall the modules to avoid memory leaks,
4693 file descriptor leaks, etc. */
4698 /* Check for/establish the a reference program image. */
4699 if (sim_analyze_program (sd
,
4700 (STATE_PROG_ARGV (sd
) != NULL
4701 ? *STATE_PROG_ARGV (sd
)
4702 : NULL
), abfd
) != SIM_RC_OK
)
4708 /* Establish any remaining configuration options. */
4709 if (sim_config (sd
) != SIM_RC_OK
)
4715 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4717 /* Uninstall the modules to avoid memory leaks,
4718 file descriptor leaks, etc. */
4723 /* CPU specific initialization. */
4724 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4726 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4728 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4729 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4730 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4731 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4734 /* sim_hw_configure (sd); */
4736 /* FIXME: Much of the code in sim_load can be moved here. */
4741 /* Called by gdb to load a program into memory. */
4744 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4748 /* FIXME: The code below that sets a specific variant of the H8/300
4749 being simulated should be moved to sim_open(). */
4751 /* See if the file is for the H8/300 or H8/300H. */
4752 /* ??? This may not be the most efficient way. The z8k simulator
4753 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4757 prog_bfd
= bfd_openr (prog
, NULL
);
4758 if (prog_bfd
!= NULL
)
4760 /* Set the cpu type. We ignore failure from bfd_check_format
4761 and bfd_openr as sim_load_file checks too. */
4762 if (bfd_check_format (prog_bfd
, bfd_object
))
4764 set_h8300h (bfd_get_mach (prog_bfd
));
4768 /* If we're using gdb attached to the simulator, then we have to
4769 reallocate memory for the simulator.
4771 When gdb first starts, it calls fetch_registers (among other
4772 functions), which in turn calls init_pointers, which allocates
4775 The problem is when we do that, we don't know whether we're
4776 debugging an H8/300 or H8/300H program.
4778 This is the first point at which we can make that determination,
4779 so we just reallocate memory now; this will also allow us to handle
4780 switching between H8/300 and H8/300H programs without exiting
4783 if (h8300smode
&& !h8300_normal_mode
)
4784 memory_size
= H8300S_MSIZE
;
4785 else if (h8300hmode
&& !h8300_normal_mode
)
4786 memory_size
= H8300H_MSIZE
;
4788 memory_size
= H8300_MSIZE
;
4790 if (h8_get_memory_buf (sd
))
4791 free (h8_get_memory_buf (sd
));
4793 h8_set_memory_buf (sd
, (unsigned char *)
4794 calloc (sizeof (char), memory_size
));
4795 sd
->memory_size
= memory_size
;
4797 /* `msize' must be a power of two. */
4798 if ((memory_size
& (memory_size
- 1)) != 0)
4800 sim_io_printf (sd
, "sim_load: bad memory size.\n");
4803 h8_set_mask (sd
, memory_size
- 1);
4805 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
4806 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
4810 /* Close the bfd if we opened it. */
4811 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4812 bfd_close (prog_bfd
);
4816 /* Close the bfd if we opened it. */
4817 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4818 bfd_close (prog_bfd
);
4823 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
4824 char * const *argv
, char * const *env
)
4831 h8_set_pc (sd
, bfd_get_start_address (abfd
));
4835 /* Command Line support. */
4838 /* Counting the no. of commandline arguments. */
4839 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4842 /* Allocating memory for the argv pointers. */
4843 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
4844 * (no_of_args
+ 1)));
4846 for (i
= 0; i
< no_of_args
; i
++)
4848 /* Copying the argument string. */
4849 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
4851 h8_set_cmdline_arg (sd
, i
, NULL
);