0d7860170bc75e5a3f661dfd83c4cbd162817d0a
1 /* m6811_cpu.c -- 68HC11&68HC12 CPU Emulation
2 Copyright 1999-2021 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GDB, GAS, and the GNU binutils.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "sim-assert.h"
22 #include "sim-module.h"
23 #include "sim-options.h"
28 OPTION_CPU_RESET
= OPTION_START
,
35 static DECLARE_OPTION_HANDLER (cpu_option_handler
);
37 static const OPTION cpu_options
[] =
39 { {"cpu-reset", no_argument
, NULL
, OPTION_CPU_RESET
},
40 '\0', NULL
, "Reset the CPU",
43 { {"emulos", no_argument
, NULL
, OPTION_EMUL_OS
},
44 '\0', NULL
, "Emulate some OS system calls (read, write, ...)",
47 { {"cpu-config", required_argument
, NULL
, OPTION_CPU_CONFIG
},
48 '\0', NULL
, "Specify the initial CPU configuration register",
51 { {"bootstrap", no_argument
, NULL
, OPTION_CPU_BOOTSTRAP
},
52 '\0', NULL
, "Start the processing in bootstrap mode",
55 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
60 cpu_option_handler (SIM_DESC sd
, sim_cpu
*cpu
,
61 int opt
, char *arg
, int is_command
)
65 cpu
= STATE_CPU (sd
, 0);
68 case OPTION_CPU_RESET
:
73 cpu
->cpu_emul_syscall
= 1;
76 case OPTION_CPU_CONFIG
:
77 if (sscanf(arg
, "0x%x", &val
) == 1
78 || sscanf(arg
, "%d", &val
) == 1)
80 cpu
->cpu_config
= val
;
81 cpu
->cpu_use_local_config
= 1;
84 cpu
->cpu_use_local_config
= 0;
87 case OPTION_CPU_BOOTSTRAP
:
88 cpu
->cpu_start_mode
= "bootstrap";
100 cpu_call (sim_cpu
*cpu
, uint16 addr
)
103 cpu_set_pc (cpu
, addr
);
107 cpu_return (sim_cpu
*cpu
)
111 /* Set the stack pointer and re-compute the current frame. */
113 cpu_set_sp (sim_cpu
*cpu
, uint16 val
)
115 cpu
->cpu_regs
.sp
= val
;
119 cpu_get_reg (sim_cpu
*cpu
, uint8 reg
)
124 return cpu_get_x (cpu
);
127 return cpu_get_y (cpu
);
130 return cpu_get_sp (cpu
);
133 return cpu_get_pc (cpu
);
141 cpu_get_src_reg (sim_cpu
*cpu
, uint8 reg
)
146 return cpu_get_a (cpu
);
149 return cpu_get_b (cpu
);
152 return cpu_get_ccr (cpu
);
155 return cpu_get_tmp3 (cpu
);
158 return cpu_get_d (cpu
);
161 return cpu_get_x (cpu
);
164 return cpu_get_y (cpu
);
167 return cpu_get_sp (cpu
);
175 cpu_set_dst_reg (sim_cpu
*cpu
, uint8 reg
, uint16 val
)
180 cpu_set_a (cpu
, val
);
184 cpu_set_b (cpu
, val
);
188 cpu_set_ccr (cpu
, val
);
192 cpu_set_tmp2 (cpu
, val
);
196 cpu_set_d (cpu
, val
);
200 cpu_set_x (cpu
, val
);
204 cpu_set_y (cpu
, val
);
208 cpu_set_sp (cpu
, val
);
217 cpu_set_reg (sim_cpu
*cpu
, uint8 reg
, uint16 val
)
222 cpu_set_x (cpu
, val
);
226 cpu_set_y (cpu
, val
);
230 cpu_set_sp (cpu
, val
);
234 cpu_set_pc (cpu
, val
);
242 /* Returns the address of a 68HC12 indexed operand.
243 Pre and post modifications are handled on the source register. */
245 cpu_get_indexed_operand_addr (sim_cpu
*cpu
, int restricted
)
252 code
= cpu_fetch8 (cpu
);
254 /* n,r with 5-bit signed constant. */
255 if ((code
& 0x20) == 0)
257 reg
= (code
>> 6) & 3;
258 sval
= (code
& 0x1f);
262 addr
= cpu_get_reg (cpu
, reg
);
266 /* Auto pre/post increment/decrement. */
267 else if ((code
& 0xc0) != 0xc0)
269 reg
= (code
>> 6) & 3;
270 sval
= (code
& 0x0f);
279 addr
= cpu_get_reg (cpu
, reg
);
280 cpu_set_reg (cpu
, reg
, addr
+ sval
);
281 if ((code
& 0x10) == 0)
287 /* [n,r] 16-bits offset indexed indirect. */
288 else if ((code
& 0x07) == 3)
294 reg
= (code
>> 3) & 0x03;
295 addr
= cpu_get_reg (cpu
, reg
);
296 addr
+= cpu_fetch16 (cpu
);
297 addr
= memory_read16 (cpu
, addr
);
298 cpu_add_cycles (cpu
, 1);
300 else if ((code
& 0x4) == 0)
306 reg
= (code
>> 3) & 0x03;
307 addr
= cpu_get_reg (cpu
, reg
);
310 sval
= cpu_fetch16 (cpu
);
311 cpu_add_cycles (cpu
, 1);
315 sval
= cpu_fetch8 (cpu
);
318 cpu_add_cycles (cpu
, 1);
324 reg
= (code
>> 3) & 0x03;
325 addr
= cpu_get_reg (cpu
, reg
);
329 addr
+= cpu_get_a (cpu
);
332 addr
+= cpu_get_b (cpu
);
335 addr
+= cpu_get_d (cpu
);
339 addr
+= cpu_get_d (cpu
);
340 addr
= memory_read16 (cpu
, addr
);
341 cpu_add_cycles (cpu
, 1);
350 cpu_get_indexed_operand8 (sim_cpu
*cpu
, int restricted
)
354 addr
= cpu_get_indexed_operand_addr (cpu
, restricted
);
355 return memory_read8 (cpu
, addr
);
359 cpu_get_indexed_operand16 (sim_cpu
*cpu
, int restricted
)
363 addr
= cpu_get_indexed_operand_addr (cpu
, restricted
);
364 return memory_read16 (cpu
, addr
);
368 cpu_move8 (sim_cpu
*cpu
, uint8 code
)
376 src
= cpu_fetch8 (cpu
);
377 addr
= cpu_fetch16 (cpu
);
381 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
382 src
= cpu_fetch8 (cpu
);
386 addr
= cpu_fetch16 (cpu
);
387 src
= memory_read8 (cpu
, addr
);
388 addr
= cpu_fetch16 (cpu
);
392 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
393 src
= memory_read8 (cpu
, cpu_fetch16 (cpu
));
397 src
= cpu_get_indexed_operand8 (cpu
, 1);
398 addr
= cpu_fetch16 (cpu
);
402 src
= cpu_get_indexed_operand8 (cpu
, 1);
403 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
407 sim_engine_abort (CPU_STATE (cpu
), cpu
, 0,
408 "Invalid code 0x%0x -- internal error?", code
);
411 memory_write8 (cpu
, addr
, src
);
415 cpu_move16 (sim_cpu
*cpu
, uint8 code
)
423 src
= cpu_fetch16 (cpu
);
424 addr
= cpu_fetch16 (cpu
);
428 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
429 src
= cpu_fetch16 (cpu
);
433 addr
= cpu_fetch16 (cpu
);
434 src
= memory_read16 (cpu
, addr
);
435 addr
= cpu_fetch16 (cpu
);
439 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
440 src
= memory_read16 (cpu
, cpu_fetch16 (cpu
));
444 src
= cpu_get_indexed_operand16 (cpu
, 1);
445 addr
= cpu_fetch16 (cpu
);
449 src
= cpu_get_indexed_operand16 (cpu
, 1);
450 addr
= cpu_get_indexed_operand_addr (cpu
, 1);
454 sim_engine_abort (CPU_STATE (cpu
), cpu
, 0,
455 "Invalid code 0x%0x -- internal error?", code
);
458 memory_write16 (cpu
, addr
, src
);
462 cpu_initialize (SIM_DESC sd
, sim_cpu
*cpu
)
464 sim_add_option_table (sd
, 0, cpu_options
);
466 memset (&cpu
->cpu_regs
, 0, sizeof(cpu
->cpu_regs
));
468 cpu
->cpu_absolute_cycle
= 0;
469 cpu
->cpu_current_cycle
= 0;
470 cpu
->cpu_emul_syscall
= 1;
471 cpu
->cpu_running
= 1;
472 cpu
->cpu_stop_on_interrupt
= 0;
473 cpu
->cpu_frequency
= 8 * 1000 * 1000;
474 cpu
->cpu_use_elf_start
= 0;
475 cpu
->cpu_elf_start
= 0;
476 cpu
->cpu_use_local_config
= 0;
480 cpu
->cpu_config
= M6811_NOSEC
| M6811_NOCOP
| M6811_ROMON
|
482 interrupts_initialize (sd
, cpu
);
484 cpu
->cpu_is_initialized
= 1;
489 /* Reinitialize the processor after a reset. */
491 cpu_reset (sim_cpu
*cpu
)
493 /* Initialize the config register.
494 It is only initialized at reset time. */
495 memset (cpu
->ios
, 0, sizeof (cpu
->ios
));
496 if (cpu
->cpu_configured_arch
->arch
== bfd_arch_m68hc11
)
497 cpu
->ios
[M6811_INIT
] = 0x1;
499 cpu
->ios
[M6811_INIT
] = 0;
501 /* Output compare registers set to 0xFFFF. */
502 cpu
->ios
[M6811_TOC1_H
] = 0xFF;
503 cpu
->ios
[M6811_TOC1_L
] = 0xFF;
504 cpu
->ios
[M6811_TOC2_H
] = 0xFF;
505 cpu
->ios
[M6811_TOC2_L
] = 0xFF;
506 cpu
->ios
[M6811_TOC3_H
] = 0xFF;
507 cpu
->ios
[M6811_TOC4_L
] = 0xFF;
508 cpu
->ios
[M6811_TOC5_H
] = 0xFF;
509 cpu
->ios
[M6811_TOC5_L
] = 0xFF;
511 /* Setup the processor registers. */
512 memset (&cpu
->cpu_regs
, 0, sizeof(cpu
->cpu_regs
));
513 cpu
->cpu_absolute_cycle
= 0;
514 cpu
->cpu_current_cycle
= 0;
515 cpu
->cpu_is_initialized
= 0;
517 /* Reset interrupts. */
518 interrupts_reset (&cpu
->cpu_interrupts
);
520 /* Reinitialize the CPU operating mode. */
521 cpu
->ios
[M6811_HPRIO
] = cpu
->cpu_mode
;
525 /* Reinitialize the processor after a reset. */
527 cpu_restart (sim_cpu
*cpu
)
531 /* Get CPU starting address depending on the CPU mode. */
532 if (cpu
->cpu_use_elf_start
== 0)
534 switch ((cpu
->ios
[M6811_HPRIO
]) & (M6811_SMOD
| M6811_MDA
))
539 addr
= memory_read16 (cpu
, 0xFFFE);
542 /* Expanded Multiplexed */
544 addr
= memory_read16 (cpu
, 0xFFFE);
547 /* Special Bootstrap */
553 case M6811_MDA
| M6811_SMOD
:
554 addr
= memory_read16 (cpu
, 0xFFFE);
560 addr
= cpu
->cpu_elf_start
;
563 /* Setup the processor registers. */
564 cpu
->cpu_insn_pc
= addr
;
565 cpu
->cpu_regs
.pc
= addr
;
566 cpu
->cpu_regs
.ccr
= M6811_X_BIT
| M6811_I_BIT
| M6811_S_BIT
;
567 cpu
->cpu_absolute_cycle
= 0;
568 cpu
->cpu_is_initialized
= 1;
569 cpu
->cpu_current_cycle
= 0;
571 cpu_call (cpu
, addr
);
577 print_io_reg_desc (SIM_DESC sd
, io_reg_desc
*desc
, int val
, int mode
)
581 if (val
& desc
->mask
)
582 sim_io_printf (sd
, "%s",
583 mode
== 0 ? desc
->short_name
: desc
->long_name
);
589 print_io_byte (SIM_DESC sd
, const char *name
, io_reg_desc
*desc
,
590 uint8 val
, uint16 addr
)
592 sim_io_printf (sd
, " %-9.9s @ 0x%04x 0x%02x ", name
, addr
, val
);
594 print_io_reg_desc (sd
, desc
, val
, 0);
598 print_io_word (SIM_DESC sd
, const char *name
, io_reg_desc
*desc
,
599 uint16 val
, uint16 addr
)
601 sim_io_printf (sd
, " %-9.9s @ 0x%04x 0x%04x ", name
, addr
, val
);
603 print_io_reg_desc (sd
, desc
, val
, 0);
607 cpu_ccr_update_tst8 (sim_cpu
*cpu
, uint8 val
)
609 cpu_set_ccr_V (cpu
, 0);
610 cpu_set_ccr_N (cpu
, val
& 0x80 ? 1 : 0);
611 cpu_set_ccr_Z (cpu
, val
== 0 ? 1 : 0);
616 cpu_fetch_relbranch (sim_cpu
*cpu
)
618 uint16 addr
= (uint16
) cpu_fetch8 (cpu
);
624 addr
+= cpu
->cpu_regs
.pc
;
629 cpu_fetch_relbranch16 (sim_cpu
*cpu
)
631 uint16 addr
= cpu_fetch16 (cpu
);
633 addr
+= cpu
->cpu_regs
.pc
;
637 /* Push all the CPU registers (when an interruption occurs). */
639 cpu_push_all (sim_cpu
*cpu
)
641 if (cpu
->cpu_configured_arch
->arch
== bfd_arch_m68hc11
)
643 cpu_m68hc11_push_uint16 (cpu
, cpu
->cpu_regs
.pc
);
644 cpu_m68hc11_push_uint16 (cpu
, cpu
->cpu_regs
.iy
);
645 cpu_m68hc11_push_uint16 (cpu
, cpu
->cpu_regs
.ix
);
646 cpu_m68hc11_push_uint16 (cpu
, cpu
->cpu_regs
.d
);
647 cpu_m68hc11_push_uint8 (cpu
, cpu
->cpu_regs
.ccr
);
651 cpu_m68hc12_push_uint16 (cpu
, cpu
->cpu_regs
.pc
);
652 cpu_m68hc12_push_uint16 (cpu
, cpu
->cpu_regs
.iy
);
653 cpu_m68hc12_push_uint16 (cpu
, cpu
->cpu_regs
.ix
);
654 cpu_m68hc12_push_uint16 (cpu
, cpu
->cpu_regs
.d
);
655 cpu_m68hc12_push_uint8 (cpu
, cpu
->cpu_regs
.ccr
);
659 /* Simulation of the dbcc/ibcc/tbcc 68HC12 conditional branch operations. */
661 cpu_dbcc (sim_cpu
*cpu
)
668 code
= cpu_fetch8 (cpu
);
671 case 0x80: /* ibcc */
674 case 0x40: /* tbcc */
685 addr
= cpu_fetch8 (cpu
);
689 addr
+= cpu_get_pc (cpu
);
690 reg
= cpu_get_src_reg (cpu
, code
& 0x07);
693 /* Branch according to register value. */
694 if ((reg
!= 0 && (code
& 0x20)) || (reg
== 0 && !(code
& 0x20)))
696 cpu_set_pc (cpu
, addr
);
698 cpu_set_dst_reg (cpu
, code
& 0x07, reg
);
702 cpu_exg (sim_cpu
*cpu
, uint8 code
)
708 r1
= (code
>> 4) & 0x07;
712 src1
= cpu_get_src_reg (cpu
, r1
);
713 src2
= cpu_get_src_reg (cpu
, r2
);
714 if (r2
== 1 || r2
== 2)
717 cpu_set_dst_reg (cpu
, r2
, src1
);
718 cpu_set_dst_reg (cpu
, r1
, src2
);
722 src1
= cpu_get_src_reg (cpu
, r1
);
724 /* Sign extend the 8-bit registers (A, B, CCR). */
725 if ((r1
== 0 || r1
== 1 || r1
== 2) && (src1
& 0x80))
728 cpu_set_dst_reg (cpu
, r2
, src1
);
732 /* Handle special instructions. */
734 cpu_special (sim_cpu
*cpu
, enum M6811_Special special
)
742 ccr
= cpu_m68hc11_pop_uint8 (cpu
);
743 cpu_set_ccr (cpu
, ccr
);
744 cpu_set_d (cpu
, cpu_m68hc11_pop_uint16 (cpu
));
745 cpu_set_x (cpu
, cpu_m68hc11_pop_uint16 (cpu
));
746 cpu_set_y (cpu
, cpu_m68hc11_pop_uint16 (cpu
));
747 cpu_set_pc (cpu
, cpu_m68hc11_pop_uint16 (cpu
));
756 ccr
= cpu_m68hc12_pop_uint8 (cpu
);
757 cpu_set_ccr (cpu
, ccr
);
758 cpu_set_d (cpu
, cpu_m68hc12_pop_uint16 (cpu
));
759 cpu_set_x (cpu
, cpu_m68hc12_pop_uint16 (cpu
));
760 cpu_set_y (cpu
, cpu_m68hc12_pop_uint16 (cpu
));
761 cpu_set_pc (cpu
, cpu_m68hc12_pop_uint16 (cpu
));
767 /* In the ELF-start mode, we are in a special mode where
768 the WAI corresponds to an exit. */
769 if (cpu
->cpu_use_elf_start
)
771 cpu_set_pc (cpu
, cpu
->cpu_insn_pc
);
772 sim_engine_halt (CPU_STATE (cpu
), cpu
,
773 NULL
, NULL_CIA
, sim_exited
,
777 /* SCz: not correct... */
782 interrupts_raise (&cpu
->cpu_interrupts
, M6811_INT_SWI
);
783 interrupts_process (&cpu
->cpu_interrupts
);
786 case M6811_EMUL_SYSCALL
:
788 if (cpu
->cpu_emul_syscall
)
790 uint8 op
= memory_read8 (cpu
,
791 cpu_get_pc (cpu
) - 1);
794 cpu_set_pc (cpu
, cpu
->cpu_insn_pc
);
795 sim_engine_halt (CPU_STATE (cpu
), cpu
,
796 NULL
, NULL_CIA
, sim_exited
,
807 interrupts_raise (&cpu
->cpu_interrupts
, M6811_INT_ILLEGAL
);
808 interrupts_process (&cpu
->cpu_interrupts
);
816 sd
= CPU_STATE (cpu
);
818 /* Breakpoint instruction if we are under gdb. */
819 if (STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
)
822 sim_engine_halt (CPU_STATE (cpu
), cpu
,
823 0, cpu_get_pc (cpu
), sim_stopped
,
826 /* else this is a nop but not in test factory mode. */
832 int32 src1
= (int16
) cpu_get_d (cpu
);
833 int32 src2
= (int16
) cpu_get_x (cpu
);
837 cpu_set_ccr_C (cpu
, 1);
841 cpu_set_d (cpu
, src1
% src2
);
843 cpu_set_x (cpu
, src1
);
844 cpu_set_ccr_C (cpu
, 0);
845 cpu_set_ccr_Z (cpu
, src1
== 0);
846 cpu_set_ccr_N (cpu
, src1
& 0x8000);
847 cpu_set_ccr_V (cpu
, src1
>= 32768 || src1
< -32768);
854 uint32 src1
= (uint32
) cpu_get_x (cpu
);
855 uint32 src2
= (uint32
) (cpu_get_y (cpu
) << 16)
856 | (uint32
) (cpu_get_d (cpu
));
860 cpu_set_ccr_C (cpu
, 1);
864 cpu_set_ccr_C (cpu
, 0);
865 cpu_set_d (cpu
, src2
% src1
);
867 cpu_set_y (cpu
, src2
);
868 cpu_set_ccr_Z (cpu
, src2
== 0);
869 cpu_set_ccr_N (cpu
, (src2
& 0x8000) != 0);
870 cpu_set_ccr_V (cpu
, (src2
& 0xffff0000) != 0);
877 int32 src1
= (int16
) cpu_get_x (cpu
);
878 int32 src2
= (uint32
) (cpu_get_y (cpu
) << 16)
879 | (uint32
) (cpu_get_d (cpu
));
883 cpu_set_ccr_C (cpu
, 1);
887 cpu_set_ccr_C (cpu
, 0);
888 cpu_set_d (cpu
, src2
% src1
);
890 cpu_set_y (cpu
, src2
);
891 cpu_set_ccr_Z (cpu
, src2
== 0);
892 cpu_set_ccr_N (cpu
, (src2
& 0x8000) != 0);
893 cpu_set_ccr_V (cpu
, src2
> 32767 || src2
< -32768);
902 src1
= (int16
) cpu_get_d (cpu
);
903 src2
= (int16
) cpu_get_y (cpu
);
905 cpu_set_d (cpu
, src1
& 0x0ffff);
906 cpu_set_y (cpu
, src1
>> 16);
907 cpu_set_ccr_Z (cpu
, src1
== 0);
908 cpu_set_ccr_N (cpu
, (src1
& 0x80000000) != 0);
909 cpu_set_ccr_C (cpu
, (src1
& 0x00008000) != 0);
918 addr
= cpu_fetch16 (cpu
);
919 src1
= (int16
) memory_read16 (cpu
, cpu_get_x (cpu
));
920 src2
= (int16
) memory_read16 (cpu
, cpu_get_y (cpu
));
922 src2
= (((uint32
) memory_read16 (cpu
, addr
)) << 16)
923 | (uint32
) memory_read16 (cpu
, addr
+ 2);
925 memory_write16 (cpu
, addr
, (src1
+ src2
) >> 16);
926 memory_write16 (cpu
, addr
+ 2, (src1
+ src2
));
937 addr
= cpu_fetch16 (cpu
);
938 page
= cpu_fetch8 (cpu
);
940 cpu_m68hc12_push_uint16 (cpu
, cpu_get_pc (cpu
));
941 cpu_m68hc12_push_uint8 (cpu
, cpu_get_page (cpu
));
943 cpu_set_page (cpu
, page
);
944 cpu_set_pc (cpu
, addr
);
948 case M6812_CALL_INDIRECT
:
954 code
= memory_read8 (cpu
, cpu_get_pc (cpu
));
955 /* Indirect addressing call has the page specified in the
956 memory location pointed to by the address. */
957 if ((code
& 0xE3) == 0xE3)
959 addr
= cpu_get_indexed_operand_addr (cpu
, 0);
960 page
= memory_read8 (cpu
, addr
+ 2);
961 addr
= memory_read16 (cpu
, addr
);
965 /* Otherwise, page is in the opcode. */
966 addr
= cpu_get_indexed_operand16 (cpu
, 0);
967 page
= cpu_fetch8 (cpu
);
969 cpu_m68hc12_push_uint16 (cpu
, cpu_get_pc (cpu
));
970 cpu_m68hc12_push_uint8 (cpu
, cpu_get_page (cpu
));
971 cpu_set_page (cpu
, page
);
972 cpu_set_pc (cpu
, addr
);
978 uint8 page
= cpu_m68hc12_pop_uint8 (cpu
);
979 uint16 addr
= cpu_m68hc12_pop_uint16 (cpu
);
981 cpu_set_page (cpu
, page
);
982 cpu_set_pc (cpu
, addr
);
988 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
,
989 cpu_get_pc (cpu
), sim_stopped
,
997 cpu_single_step (sim_cpu
*cpu
)
999 cpu
->cpu_current_cycle
= 0;
1000 cpu
->cpu_insn_pc
= cpu_get_pc (cpu
);
1002 /* Handle the pending interrupts. If an interrupt is handled,
1003 treat this as an single step. */
1004 if (interrupts_process (&cpu
->cpu_interrupts
))
1006 cpu
->cpu_absolute_cycle
+= cpu
->cpu_current_cycle
;
1010 /* printf("PC = 0x%04x\n", cpu_get_pc (cpu));*/
1011 cpu
->cpu_interpretor (cpu
);
1012 cpu
->cpu_absolute_cycle
+= cpu
->cpu_current_cycle
;
1017 sim_memory_error (sim_cpu
*cpu
, SIM_SIGNAL excep
,
1018 uint16 addr
, const char *message
, ...)
1023 va_start (args
, message
);
1024 vsprintf (buf
, message
, args
);
1027 sim_io_printf (CPU_STATE (cpu
), "%s\n", buf
);
1028 cpu_memory_exception (cpu
, excep
, addr
, buf
);
1033 cpu_memory_exception (sim_cpu
*cpu
, SIM_SIGNAL excep
,
1034 uint16 addr
, const char *message
)
1036 if (cpu
->cpu_running
== 0)
1039 cpu_set_pc (cpu
, cpu
->cpu_insn_pc
);
1040 sim_engine_halt (CPU_STATE (cpu
), cpu
, NULL
,
1041 cpu_get_pc (cpu
), sim_stopped
, excep
);
1044 cpu
->mem_exception
= excep
;
1045 cpu
->fault_addr
= addr
;
1046 cpu
->fault_msg
= strdup (message
);
1048 if (cpu
->cpu_use_handler
)
1050 longjmp (&cpu
->cpu_exception_handler
, 1);
1052 (* cpu
->callback
->printf_filtered
)
1053 (cpu
->callback
, "Fault at 0x%04x: %s\n", addr
, message
);
1058 cpu_info (SIM_DESC sd
, sim_cpu
*cpu
)
1060 sim_io_printf (sd
, "CPU info:\n");
1061 sim_io_printf (sd
, " Absolute cycle: %s\n",
1062 cycle_to_string (cpu
, cpu
->cpu_absolute_cycle
,
1063 PRINT_TIME
| PRINT_CYCLE
));
1065 sim_io_printf (sd
, " Syscall emulation: %s\n",
1066 cpu
->cpu_emul_syscall
? "yes, via 0xcd <n>" : "no");
1067 sim_io_printf (sd
, " Memory errors detection: %s\n",
1068 cpu
->cpu_check_memory
? "yes" : "no");
1069 sim_io_printf (sd
, " Stop on interrupt: %s\n",
1070 cpu
->cpu_stop_on_interrupt
? "yes" : "no");
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