1 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
3 * mips.igen (MULT, MULTU): Add syntax for two operand version.
4 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
7 1999-05-08 Felix Lee <flee@cygnus.com>
9 * configure: Regenerated to track ../common/aclocal.m4 changes.
11 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
13 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
15 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
17 * configure.in: Any mips64vr5*-*-* target should have
19 (default_endian): Any mips64vr*el-*-* target should default to
21 * configure: Re-generate.
23 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
25 * mips.igen (ldl): Extend from _16_, not 32.
27 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
29 * interp.c (sim_store_register): Force registers written to by GDB
30 into an un-interpreted state.
32 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
34 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
35 CPU, start periodic background I/O polls.
36 (tx3904sio_poll): New function: periodic I/O poller.
38 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
40 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
42 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
44 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
47 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
49 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
50 (load_word): Call SIM_CORE_SIGNAL hook on error.
51 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
52 starting. For exception dispatching, pass PC instead of NULL_CIA.
53 (decode_coproc): Use COP0_BADVADDR to store faulting address.
54 * sim-main.h (COP0_BADVADDR): Define.
55 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
56 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
57 (_sim_cpu): Add exc_* fields to store register value snapshots.
58 * mips.igen (*): Replace memory-related SignalException* calls
59 with references to SIM_CORE_SIGNAL hook.
61 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
63 * sim-main.c (*): Minor warning cleanups.
65 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
67 * m16.igen (DADDIU5): Correct type-o.
69 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
71 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
74 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
76 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
78 (interp.o): Add dependency on itable.h
79 (oengine.c, gencode): Delete remaining references.
80 (BUILT_SRC_FROM_GEN): Clean up.
82 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
85 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
86 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
88 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
89 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
90 Drop the "64" qualifier to get the HACK generator working.
91 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
92 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
93 qualifier to get the hack generator working.
94 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
96 (DSLLV): Use do_dsllv.
99 (DSRLV): Use do_dsrlv.
100 (BC1): Move *vr4100 to get the HACK generator working.
101 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
102 get the HACK generator working.
103 (MACC) Rename to get the HACK generator working.
104 (DMACC,MACCS,DMACCS): Add the 64.
106 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
108 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
109 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
111 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
113 * mips/interp.c (DEBUG): Cleanups.
115 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
117 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
118 (tx3904sio_tickle): fflush after a stdout character output.
120 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
122 * interp.c (sim_close): Uninstall modules.
124 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
126 * sim-main.h, interp.c (sim_monitor): Change to global
129 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
131 * configure.in (vr4100): Only include vr4100 instructions in
133 * configure: Re-generate.
134 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
136 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
138 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
139 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
142 * configure.in (sim_default_gen, sim_use_gen): Replace with
144 (--enable-sim-igen): Delete config option. Always using IGEN.
145 * configure: Re-generate.
147 * Makefile.in (gencode): Kill, kill, kill.
150 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
152 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
153 bit mips16 igen simulator.
154 * configure: Re-generate.
156 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
157 as part of vr4100 ISA.
158 * vr.igen: Mark all instructions as 64 bit only.
160 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
162 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
165 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
167 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
168 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
169 * configure: Re-generate.
171 * m16.igen (BREAK): Define breakpoint instruction.
172 (JALX32): Mark instruction as mips16 and not r3900.
173 * mips.igen (C.cond.fmt): Fix typo in instruction format.
175 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
177 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
179 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
180 insn as a debug breakpoint.
182 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
184 (PENDING_SCHED): Clean up trace statement.
185 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
186 (PENDING_FILL): Delay write by only one cycle.
187 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
189 * sim-main.c (pending_tick): Clean up trace statements. Add trace
191 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
193 (pending_tick): Move incrementing of index to FOR statement.
194 (pending_tick): Only update PENDING_OUT after a write has occured.
196 * configure.in: Add explicit mips-lsi-* target. Use gencode to
198 * configure: Re-generate.
200 * interp.c (sim_engine_run OLD): Delete explicit call to
201 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
203 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
205 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
206 interrupt level number to match changed SignalExceptionInterrupt
209 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
211 * interp.c: #include "itable.h" if WITH_IGEN.
212 (get_insn_name): New function.
213 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
214 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
216 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
218 * configure: Rebuilt to inhale new common/aclocal.m4.
220 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
222 * dv-tx3904sio.c: Include sim-assert.h.
224 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
226 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
227 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
228 Reorganize target-specific sim-hardware checks.
229 * configure: rebuilt.
230 * interp.c (sim_open): For tx39 target boards, set
231 OPERATING_ENVIRONMENT, add tx3904sio devices.
232 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
233 ROM executables. Install dv-sockser into sim-modules list.
235 * dv-tx3904irc.c: Compiler warning clean-up.
236 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
237 frequent hw-trace messages.
239 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
241 * vr.igen (MulAcc): Identify as a vr4100 specific function.
243 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
245 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
248 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
249 * mips.igen: Define vr4100 model. Include vr.igen.
250 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
252 * mips.igen (check_mf_hilo): Correct check.
254 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
256 * sim-main.h (interrupt_event): Add prototype.
258 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
259 register_ptr, register_value.
260 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
262 * sim-main.h (tracefh): Make extern.
264 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
266 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
267 Reduce unnecessarily high timer event frequency.
268 * dv-tx3904cpu.c: Ditto for interrupt event.
270 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
272 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
274 (interrupt_event): Made non-static.
276 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
277 interchange of configuration values for external vs. internal
280 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
282 * mips.igen (BREAK): Moved code to here for
283 simulator-reserved break instructions.
284 * gencode.c (build_instruction): Ditto.
285 * interp.c (signal_exception): Code moved from here. Non-
286 reserved instructions now use exception vector, rather
288 * sim-main.h: Moved magic constants to here.
290 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
292 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
293 register upon non-zero interrupt event level, clear upon zero
295 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
296 by passing zero event value.
297 (*_io_{read,write}_buffer): Endianness fixes.
298 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
299 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
301 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
302 serial I/O and timer module at base address 0xFFFF0000.
304 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
306 * mips.igen (SWC1) : Correct the handling of ReverseEndian
309 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
311 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
315 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
317 * dv-tx3904tmr.c: New file - implements tx3904 timer.
318 * dv-tx3904{irc,cpu}.c: Mild reformatting.
319 * configure.in: Include tx3904tmr in hw_device list.
320 * configure: Rebuilt.
321 * interp.c (sim_open): Instantiate three timer instances.
322 Fix address typo of tx3904irc instance.
324 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
326 * interp.c (signal_exception): SystemCall exception now uses
327 the exception vector.
329 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
331 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
334 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
336 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
338 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
340 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
342 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
343 sim-main.h. Declare a struct hw_descriptor instead of struct
344 hw_device_descriptor.
346 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
348 * mips.igen (do_store_left, do_load_left): Compute nr of left and
349 right bits and then re-align left hand bytes to correct byte
350 lanes. Fix incorrect computation in do_store_left when loading
351 bytes from second word.
353 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
355 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
356 * interp.c (sim_open): Only create a device tree when HW is
359 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
360 * interp.c (signal_exception): Ditto.
362 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
364 * gencode.c: Mark BEGEZALL as LIKELY.
366 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
368 * sim-main.h (ALU32_END): Sign extend 32 bit results.
369 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
371 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
373 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
374 modules. Recognize TX39 target with "mips*tx39" pattern.
375 * configure: Rebuilt.
376 * sim-main.h (*): Added many macros defining bits in
377 TX39 control registers.
378 (SignalInterrupt): Send actual PC instead of NULL.
379 (SignalNMIReset): New exception type.
380 * interp.c (board): New variable for future use to identify
381 a particular board being simulated.
382 (mips_option_handler,mips_options): Added "--board" option.
383 (interrupt_event): Send actual PC.
384 (sim_open): Make memory layout conditional on board setting.
385 (signal_exception): Initial implementation of hardware interrupt
386 handling. Accept another break instruction variant for simulator
388 (decode_coproc): Implement RFE instruction for TX39.
389 (mips.igen): Decode RFE instruction as such.
390 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
391 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
392 bbegin to implement memory map.
393 * dv-tx3904cpu.c: New file.
394 * dv-tx3904irc.c: New file.
396 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
398 * mips.igen (check_mt_hilo): Create a separate r3900 version.
400 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
402 * tx.igen (madd,maddu): Replace calls to check_op_hilo
403 with calls to check_div_hilo.
405 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
407 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
408 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
409 Add special r3900 version of do_mult_hilo.
410 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
411 with calls to check_mult_hilo.
412 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
413 with calls to check_div_hilo.
415 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
417 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
418 Document a replacement.
420 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
422 * interp.c (sim_monitor): Make mon_printf work.
424 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
426 * sim-main.h (INSN_NAME): New arg `cpu'.
428 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
430 * configure: Regenerated to track ../common/aclocal.m4 changes.
432 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
434 * configure: Regenerated to track ../common/aclocal.m4 changes.
437 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
439 * acconfig.h: New file.
440 * configure.in: Reverted change of Apr 24; use sinclude again.
442 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
444 * configure: Regenerated to track ../common/aclocal.m4 changes.
447 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
449 * configure.in: Don't call sinclude.
451 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
453 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
455 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
457 * mips.igen (ERET): Implement.
459 * interp.c (decode_coproc): Return sign-extended EPC.
461 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
463 * interp.c (signal_exception): Do not ignore Trap.
464 (signal_exception): On TRAP, restart at exception address.
465 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
466 (signal_exception): Update.
467 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
468 so that TRAP instructions are caught.
470 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
472 * sim-main.h (struct hilo_access, struct hilo_history): Define,
473 contains HI/LO access history.
474 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
475 (HIACCESS, LOACCESS): Delete, replace with
476 (HIHISTORY, LOHISTORY): New macros.
477 (CHECKHILO): Delete all, moved to mips.igen
479 * gencode.c (build_instruction): Do not generate checks for
480 correct HI/LO register usage.
482 * interp.c (old_engine_run): Delete checks for correct HI/LO
485 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
486 check_mf_cycles): New functions.
487 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
488 do_divu, domultx, do_mult, do_multu): Use.
490 * tx.igen ("madd", "maddu"): Use.
492 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
494 * mips.igen (DSRAV): Use function do_dsrav.
495 (SRAV): Use new function do_srav.
497 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
498 (B): Sign extend 11 bit immediate.
499 (EXT-B*): Shift 16 bit immediate left by 1.
500 (ADDIU*): Don't sign extend immediate value.
502 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
504 * m16run.c (sim_engine_run): Restore CIA after handling an event.
506 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
509 * mips.igen (delayslot32, nullify_next_insn): New functions.
510 (m16.igen): Always include.
511 (do_*): Add more tracing.
513 * m16.igen (delayslot16): Add NIA argument, could be called by a
514 32 bit MIPS16 instruction.
516 * interp.c (ifetch16): Move function from here.
517 * sim-main.c (ifetch16): To here.
519 * sim-main.c (ifetch16, ifetch32): Update to match current
520 implementations of LH, LW.
521 (signal_exception): Don't print out incorrect hex value of illegal
524 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
526 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
529 * m16.igen: Implement MIPS16 instructions.
531 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
532 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
533 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
534 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
535 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
536 bodies of corresponding code from 32 bit insn to these. Also used
537 by MIPS16 versions of functions.
539 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
540 (IMEM16): Drop NR argument from macro.
542 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
544 * Makefile.in (SIM_OBJS): Add sim-main.o.
546 * sim-main.h (address_translation, load_memory, store_memory,
547 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
549 (pr_addr, pr_uword64): Declare.
550 (sim-main.c): Include when H_REVEALS_MODULE_P.
552 * interp.c (address_translation, load_memory, store_memory,
553 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
555 * sim-main.c: To here. Fix compilation problems.
557 * configure.in: Enable inlining.
558 * configure: Re-config.
560 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
562 * configure: Regenerated to track ../common/aclocal.m4 changes.
564 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
566 * mips.igen: Include tx.igen.
567 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
568 * tx.igen: New file, contains MADD and MADDU.
570 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
571 the hardwired constant `7'.
572 (store_memory): Ditto.
573 (LOADDRMASK): Move definition to sim-main.h.
575 mips.igen (MTC0): Enable for r3900.
578 mips.igen (do_load_byte): Delete.
579 (do_load, do_store, do_load_left, do_load_write, do_store_left,
580 do_store_right): New functions.
581 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
583 configure.in: Let the tx39 use igen again.
586 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
588 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
589 not an address sized quantity. Return zero for cache sizes.
591 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
593 * mips.igen (r3900): r3900 does not support 64 bit integer
596 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
598 * configure.in (mipstx39*-*-*): Use gencode simulator rather
600 * configure : Rebuild.
602 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
604 * configure: Regenerated to track ../common/aclocal.m4 changes.
606 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
608 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
610 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
612 * configure: Regenerated to track ../common/aclocal.m4 changes.
613 * config.in: Regenerated to track ../common/aclocal.m4 changes.
615 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
617 * configure: Regenerated to track ../common/aclocal.m4 changes.
619 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
621 * interp.c (Max, Min): Comment out functions. Not yet used.
623 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
625 * configure: Regenerated to track ../common/aclocal.m4 changes.
627 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
629 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
630 configurable settings for stand-alone simulator.
632 * configure.in: Added X11 search, just in case.
634 * configure: Regenerated.
636 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
638 * interp.c (sim_write, sim_read, load_memory, store_memory):
639 Replace sim_core_*_map with read_map, write_map, exec_map resp.
641 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
643 * sim-main.h (GETFCC): Return an unsigned value.
645 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
647 * mips.igen (DIV): Fix check for -1 / MIN_INT.
648 (DADD): Result destination is RD not RT.
650 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
652 * sim-main.h (HIACCESS, LOACCESS): Always define.
654 * mdmx.igen (Maxi, Mini): Rename Max, Min.
656 * interp.c (sim_info): Delete.
658 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
660 * interp.c (DECLARE_OPTION_HANDLER): Use it.
661 (mips_option_handler): New argument `cpu'.
662 (sim_open): Update call to sim_add_option_table.
664 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
666 * mips.igen (CxC1): Add tracing.
668 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
670 * sim-main.h (Max, Min): Declare.
672 * interp.c (Max, Min): New functions.
674 * mips.igen (BC1): Add tracing.
676 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
678 * interp.c Added memory map for stack in vr4100
680 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
682 * interp.c (load_memory): Add missing "break"'s.
684 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
686 * interp.c (sim_store_register, sim_fetch_register): Pass in
687 length parameter. Return -1.
689 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
691 * interp.c: Added hardware init hook, fixed warnings.
693 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
695 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
697 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
699 * interp.c (ifetch16): New function.
701 * sim-main.h (IMEM32): Rename IMEM.
702 (IMEM16_IMMED): Define.
704 (DELAY_SLOT): Update.
706 * m16run.c (sim_engine_run): New file.
708 * m16.igen: All instructions except LB.
709 (LB): Call do_load_byte.
710 * mips.igen (do_load_byte): New function.
711 (LB): Call do_load_byte.
713 * mips.igen: Move spec for insn bit size and high bit from here.
714 * Makefile.in (tmp-igen, tmp-m16): To here.
716 * m16.dc: New file, decode mips16 instructions.
718 * Makefile.in (SIM_NO_ALL): Define.
719 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
721 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
723 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
724 point unit to 32 bit registers.
725 * configure: Re-generate.
727 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
729 * configure.in (sim_use_gen): Make IGEN the default simulator
730 generator for generic 32 and 64 bit mips targets.
731 * configure: Re-generate.
733 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
735 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
738 * interp.c (sim_fetch_register, sim_store_register): Read/write
739 FGR from correct location.
740 (sim_open): Set size of FGR's according to
741 WITH_TARGET_FLOATING_POINT_BITSIZE.
743 * sim-main.h (FGR): Store floating point registers in a separate
746 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
748 * configure: Regenerated to track ../common/aclocal.m4 changes.
750 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
752 * interp.c (ColdReset): Call PENDING_INVALIDATE.
754 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
756 * interp.c (pending_tick): New function. Deliver pending writes.
758 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
759 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
760 it can handle mixed sized quantites and single bits.
762 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
764 * interp.c (oengine.h): Do not include when building with IGEN.
765 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
766 (sim_info): Ditto for PROCESSOR_64BIT.
767 (sim_monitor): Replace ut_reg with unsigned_word.
768 (*): Ditto for t_reg.
769 (LOADDRMASK): Define.
770 (sim_open): Remove defunct check that host FP is IEEE compliant,
771 using software to emulate floating point.
772 (value_fpr, ...): Always compile, was conditional on HASFPU.
774 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
776 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
779 * interp.c (SD, CPU): Define.
780 (mips_option_handler): Set flags in each CPU.
781 (interrupt_event): Assume CPU 0 is the one being iterrupted.
782 (sim_close): Do not clear STATE, deleted anyway.
783 (sim_write, sim_read): Assume CPU zero's vm should be used for
785 (sim_create_inferior): Set the PC for all processors.
786 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
788 (mips16_entry): Pass correct nr of args to store_word, load_word.
789 (ColdReset): Cold reset all cpu's.
790 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
791 (sim_monitor, load_memory, store_memory, signal_exception): Use
792 `CPU' instead of STATE_CPU.
795 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
798 * sim-main.h (signal_exception): Add sim_cpu arg.
799 (SignalException*): Pass both SD and CPU to signal_exception.
800 * interp.c (signal_exception): Update.
802 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
804 (sync_operation, prefetch, cache_op, store_memory, load_memory,
805 address_translation): Ditto
806 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
808 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
810 * configure: Regenerated to track ../common/aclocal.m4 changes.
812 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
814 * interp.c (sim_engine_run): Add `nr_cpus' argument.
816 * mips.igen (model): Map processor names onto BFD name.
818 * sim-main.h (CPU_CIA): Delete.
819 (SET_CIA, GET_CIA): Define
821 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
823 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
826 * configure.in (default_endian): Configure a big-endian simulator
828 * configure: Re-generate.
830 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
832 * configure: Regenerated to track ../common/aclocal.m4 changes.
834 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
836 * interp.c (sim_monitor): Handle Densan monitor outbyte
837 and inbyte functions.
839 1997-12-29 Felix Lee <flee@cygnus.com>
841 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
843 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
845 * Makefile.in (tmp-igen): Arrange for $zero to always be
846 reset to zero after every instruction.
848 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
850 * configure: Regenerated to track ../common/aclocal.m4 changes.
853 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
855 * mips.igen (MSUB): Fix to work like MADD.
856 * gencode.c (MSUB): Similarly.
858 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
860 * configure: Regenerated to track ../common/aclocal.m4 changes.
862 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
864 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
866 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
868 * sim-main.h (sim-fpu.h): Include.
870 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
871 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
872 using host independant sim_fpu module.
874 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
876 * interp.c (signal_exception): Report internal errors with SIGABRT
879 * sim-main.h (C0_CONFIG): New register.
880 (signal.h): No longer include.
882 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
884 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
886 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
888 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
890 * mips.igen: Tag vr5000 instructions.
891 (ANDI): Was missing mipsIV model, fix assembler syntax.
892 (do_c_cond_fmt): New function.
893 (C.cond.fmt): Handle mips I-III which do not support CC field
895 (bc1): Handle mips IV which do not have a delaed FCC separatly.
896 (SDR): Mask paddr when BigEndianMem, not the converse as specified
898 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
899 vr5000 which saves LO in a GPR separatly.
901 * configure.in (enable-sim-igen): For vr5000, select vr5000
902 specific instructions.
903 * configure: Re-generate.
905 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
907 * Makefile.in (SIM_OBJS): Add sim-fpu module.
909 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
910 fmt_uninterpreted_64 bit cases to switch. Convert to
913 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
915 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
916 as specified in IV3.2 spec.
917 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
919 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
921 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
922 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
923 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
924 PENDING_FILL versions of instructions. Simplify.
926 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
928 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
930 (MTHI, MFHI): Disable code checking HI-LO.
932 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
934 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
936 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
938 * gencode.c (build_mips16_operands): Replace IPC with cia.
940 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
941 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
943 (UndefinedResult): Replace function with macro/function
945 (sim_engine_run): Don't save PC in IPC.
947 * sim-main.h (IPC): Delete.
950 * interp.c (signal_exception, store_word, load_word,
951 address_translation, load_memory, store_memory, cache_op,
952 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
953 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
954 current instruction address - cia - argument.
955 (sim_read, sim_write): Call address_translation directly.
956 (sim_engine_run): Rename variable vaddr to cia.
957 (signal_exception): Pass cia to sim_monitor
959 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
960 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
961 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
963 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
964 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
967 * interp.c (signal_exception): Pass restart address to
970 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
971 idecode.o): Add dependency.
973 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
975 (DELAY_SLOT): Update NIA not PC with branch address.
976 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
978 * mips.igen: Use CIA not PC in branch calculations.
979 (illegal): Call SignalException.
980 (BEQ, ADDIU): Fix assembler.
982 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
984 * m16.igen (JALX): Was missing.
986 * configure.in (enable-sim-igen): New configuration option.
987 * configure: Re-generate.
989 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
991 * interp.c (load_memory, store_memory): Delete parameter RAW.
992 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
993 bypassing {load,store}_memory.
995 * sim-main.h (ByteSwapMem): Delete definition.
997 * Makefile.in (SIM_OBJS): Add sim-memopt module.
999 * interp.c (sim_do_command, sim_commands): Delete mips specific
1000 commands. Handled by module sim-options.
1002 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1003 (WITH_MODULO_MEMORY): Define.
1005 * interp.c (sim_info): Delete code printing memory size.
1007 * interp.c (mips_size): Nee sim_size, delete function.
1009 (monitor, monitor_base, monitor_size): Delete global variables.
1010 (sim_open, sim_close): Delete code creating monitor and other
1011 memory regions. Use sim-memopts module, via sim_do_commandf, to
1012 manage memory regions.
1013 (load_memory, store_memory): Use sim-core for memory model.
1015 * interp.c (address_translation): Delete all memory map code
1016 except line forcing 32 bit addresses.
1018 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1020 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1023 * interp.c (logfh, logfile): Delete globals.
1024 (sim_open, sim_close): Delete code opening & closing log file.
1025 (mips_option_handler): Delete -l and -n options.
1026 (OPTION mips_options): Ditto.
1028 * interp.c (OPTION mips_options): Rename option trace to dinero.
1029 (mips_option_handler): Update.
1031 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1033 * interp.c (fetch_str): New function.
1034 (sim_monitor): Rewrite using sim_read & sim_write.
1035 (sim_open): Check magic number.
1036 (sim_open): Write monitor vectors into memory using sim_write.
1037 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1038 (sim_read, sim_write): Simplify - transfer data one byte at a
1040 (load_memory, store_memory): Clarify meaning of parameter RAW.
1042 * sim-main.h (isHOST): Defete definition.
1043 (isTARGET): Mark as depreciated.
1044 (address_translation): Delete parameter HOST.
1046 * interp.c (address_translation): Delete parameter HOST.
1048 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1052 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1053 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1055 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1057 * mips.igen: Add model filter field to records.
1059 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1061 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1063 interp.c (sim_engine_run): Do not compile function sim_engine_run
1064 when WITH_IGEN == 1.
1066 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1067 target architecture.
1069 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1070 igen. Replace with configuration variables sim_igen_flags /
1073 * m16.igen: New file. Copy mips16 insns here.
1074 * mips.igen: From here.
1076 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1078 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1080 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1082 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1084 * gencode.c (build_instruction): Follow sim_write's lead in using
1085 BigEndianMem instead of !ByteSwapMem.
1087 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1089 * configure.in (sim_gen): Dependent on target, select type of
1090 generator. Always select old style generator.
1092 configure: Re-generate.
1094 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1096 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1097 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1098 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1099 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1100 SIM_@sim_gen@_*, set by autoconf.
1102 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1104 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1106 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1107 CURRENT_FLOATING_POINT instead.
1109 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1110 (address_translation): Raise exception InstructionFetch when
1111 translation fails and isINSTRUCTION.
1113 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1114 sim_engine_run): Change type of of vaddr and paddr to
1116 (address_translation, prefetch, load_memory, store_memory,
1117 cache_op): Change type of vAddr and pAddr to address_word.
1119 * gencode.c (build_instruction): Change type of vaddr and paddr to
1122 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1124 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1125 macro to obtain result of ALU op.
1127 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1129 * interp.c (sim_info): Call profile_print.
1131 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1133 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1135 * sim-main.h (WITH_PROFILE): Do not define, defined in
1136 common/sim-config.h. Use sim-profile module.
1137 (simPROFILE): Delete defintion.
1139 * interp.c (PROFILE): Delete definition.
1140 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1141 (sim_close): Delete code writing profile histogram.
1142 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1144 (sim_engine_run): Delete code profiling the PC.
1146 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1148 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1150 * interp.c (sim_monitor): Make register pointers of type
1153 * sim-main.h: Make registers of type unsigned_word not
1156 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1158 * interp.c (sync_operation): Rename from SyncOperation, make
1159 global, add SD argument.
1160 (prefetch): Rename from Prefetch, make global, add SD argument.
1161 (decode_coproc): Make global.
1163 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1165 * gencode.c (build_instruction): Generate DecodeCoproc not
1166 decode_coproc calls.
1168 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1169 (SizeFGR): Move to sim-main.h
1170 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1171 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1172 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1174 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1175 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1176 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1177 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1178 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1179 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1181 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1183 (sim-alu.h): Include.
1184 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1185 (sim_cia): Typedef to instruction_address.
1187 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1189 * Makefile.in (interp.o): Rename generated file engine.c to
1194 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1196 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1198 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1200 * gencode.c (build_instruction): For "FPSQRT", output correct
1201 number of arguments to Recip.
1203 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1205 * Makefile.in (interp.o): Depends on sim-main.h
1207 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1209 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1210 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1211 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1212 STATE, DSSTATE): Define
1213 (GPR, FGRIDX, ..): Define.
1215 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1216 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1217 (GPR, FGRIDX, ...): Delete macros.
1219 * interp.c: Update names to match defines from sim-main.h
1221 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1223 * interp.c (sim_monitor): Add SD argument.
1224 (sim_warning): Delete. Replace calls with calls to
1226 (sim_error): Delete. Replace calls with sim_io_error.
1227 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1228 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1229 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1231 (mips_size): Rename from sim_size. Add SD argument.
1233 * interp.c (simulator): Delete global variable.
1234 (callback): Delete global variable.
1235 (mips_option_handler, sim_open, sim_write, sim_read,
1236 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1237 sim_size,sim_monitor): Use sim_io_* not callback->*.
1238 (sim_open): ZALLOC simulator struct.
1239 (PROFILE): Do not define.
1241 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1243 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1244 support.h with corresponding code.
1246 * sim-main.h (word64, uword64), support.h: Move definition to
1248 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1251 * Makefile.in: Update dependencies
1252 * interp.c: Do not include.
1254 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1256 * interp.c (address_translation, load_memory, store_memory,
1257 cache_op): Rename to from AddressTranslation et.al., make global,
1260 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1263 * interp.c (SignalException): Rename to signal_exception, make
1266 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1268 * sim-main.h (SignalException, SignalExceptionInterrupt,
1269 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1270 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1271 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1274 * interp.c, support.h: Use.
1276 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1278 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1279 to value_fpr / store_fpr. Add SD argument.
1280 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1281 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1283 * sim-main.h (ValueFPR, StoreFPR): Define.
1285 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1287 * interp.c (sim_engine_run): Check consistency between configure
1288 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1291 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1292 (mips_fpu): Configure WITH_FLOATING_POINT.
1293 (mips_endian): Configure WITH_TARGET_ENDIAN.
1294 * configure: Update.
1296 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1298 * configure: Regenerated to track ../common/aclocal.m4 changes.
1300 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1302 * configure: Regenerated.
1304 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1306 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1308 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1310 * gencode.c (print_igen_insn_models): Assume certain architectures
1311 include all mips* instructions.
1312 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1315 * Makefile.in (tmp.igen): Add target. Generate igen input from
1318 * gencode.c (FEATURE_IGEN): Define.
1319 (main): Add --igen option. Generate output in igen format.
1320 (process_instructions): Format output according to igen option.
1321 (print_igen_insn_format): New function.
1322 (print_igen_insn_models): New function.
1323 (process_instructions): Only issue warnings and ignore
1324 instructions when no FEATURE_IGEN.
1326 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1328 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1331 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1333 * configure: Regenerated to track ../common/aclocal.m4 changes.
1335 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1337 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1338 SIM_RESERVED_BITS): Delete, moved to common.
1339 (SIM_EXTRA_CFLAGS): Update.
1341 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1343 * configure.in: Configure non-strict memory alignment.
1344 * configure: Regenerated to track ../common/aclocal.m4 changes.
1346 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1348 * configure: Regenerated to track ../common/aclocal.m4 changes.
1350 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1352 * gencode.c (SDBBP,DERET): Added (3900) insns.
1353 (RFE): Turn on for 3900.
1354 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1355 (dsstate): Made global.
1356 (SUBTARGET_R3900): Added.
1357 (CANCELDELAYSLOT): New.
1358 (SignalException): Ignore SystemCall rather than ignore and
1359 terminate. Add DebugBreakPoint handling.
1360 (decode_coproc): New insns RFE, DERET; and new registers Debug
1361 and DEPC protected by SUBTARGET_R3900.
1362 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1364 * Makefile.in,configure.in: Add mips subtarget option.
1365 * configure: Update.
1367 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1369 * gencode.c: Add r3900 (tx39).
1372 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1374 * gencode.c (build_instruction): Don't need to subtract 4 for
1377 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1379 * interp.c: Correct some HASFPU problems.
1381 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1383 * configure: Regenerated to track ../common/aclocal.m4 changes.
1385 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1387 * interp.c (mips_options): Fix samples option short form, should
1390 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1392 * interp.c (sim_info): Enable info code. Was just returning.
1394 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1396 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1399 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1401 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1403 (build_instruction): Ditto for LL.
1405 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1407 * configure: Regenerated to track ../common/aclocal.m4 changes.
1409 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1411 * configure: Regenerated to track ../common/aclocal.m4 changes.
1414 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1416 * interp.c (sim_open): Add call to sim_analyze_program, update
1419 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1421 * interp.c (sim_kill): Delete.
1422 (sim_create_inferior): Add ABFD argument. Set PC from same.
1423 (sim_load): Move code initializing trap handlers from here.
1424 (sim_open): To here.
1425 (sim_load): Delete, use sim-hload.c.
1427 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1429 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1431 * configure: Regenerated to track ../common/aclocal.m4 changes.
1434 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1436 * interp.c (sim_open): Add ABFD argument.
1437 (sim_load): Move call to sim_config from here.
1438 (sim_open): To here. Check return status.
1440 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1442 * gencode.c (build_instruction): Two arg MADD should
1443 not assign result to $0.
1445 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1447 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1448 * sim/mips/configure.in: Regenerate.
1450 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1452 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1453 signed8, unsigned8 et.al. types.
1455 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1456 hosts when selecting subreg.
1458 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1460 * interp.c (sim_engine_run): Reset the ZERO register to zero
1461 regardless of FEATURE_WARN_ZERO.
1462 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1464 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1466 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1467 (SignalException): For BreakPoints ignore any mode bits and just
1469 (SignalException): Always set the CAUSE register.
1471 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1473 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1474 exception has been taken.
1476 * interp.c: Implement the ERET and mt/f sr instructions.
1478 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1480 * interp.c (SignalException): Don't bother restarting an
1483 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1485 * interp.c (SignalException): Really take an interrupt.
1486 (interrupt_event): Only deliver interrupts when enabled.
1488 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1490 * interp.c (sim_info): Only print info when verbose.
1491 (sim_info) Use sim_io_printf for output.
1493 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1495 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1498 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1500 * interp.c (sim_do_command): Check for common commands if a
1501 simulator specific command fails.
1503 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1505 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1506 and simBE when DEBUG is defined.
1508 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510 * interp.c (interrupt_event): New function. Pass exception event
1511 onto exception handler.
1513 * configure.in: Check for stdlib.h.
1514 * configure: Regenerate.
1516 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1517 variable declaration.
1518 (build_instruction): Initialize memval1.
1519 (build_instruction): Add UNUSED attribute to byte, bigend,
1521 (build_operands): Ditto.
1523 * interp.c: Fix GCC warnings.
1524 (sim_get_quit_code): Delete.
1526 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1527 * Makefile.in: Ditto.
1528 * configure: Re-generate.
1530 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1532 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1534 * interp.c (mips_option_handler): New function parse argumes using
1536 (myname): Replace with STATE_MY_NAME.
1537 (sim_open): Delete check for host endianness - performed by
1539 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1540 (sim_open): Move much of the initialization from here.
1541 (sim_load): To here. After the image has been loaded and
1543 (sim_open): Move ColdReset from here.
1544 (sim_create_inferior): To here.
1545 (sim_open): Make FP check less dependant on host endianness.
1547 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1549 * interp.c (sim_set_callbacks): Delete.
1551 * interp.c (membank, membank_base, membank_size): Replace with
1552 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1553 (sim_open): Remove call to callback->init. gdb/run do this.
1557 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1559 * interp.c (big_endian_p): Delete, replaced by
1560 current_target_byte_order.
1562 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1564 * interp.c (host_read_long, host_read_word, host_swap_word,
1565 host_swap_long): Delete. Using common sim-endian.
1566 (sim_fetch_register, sim_store_register): Use H2T.
1567 (pipeline_ticks): Delete. Handled by sim-events.
1569 (sim_engine_run): Update.
1571 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1573 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1575 (SignalException): To here. Signal using sim_engine_halt.
1576 (sim_stop_reason): Delete, moved to common.
1578 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1580 * interp.c (sim_open): Add callback argument.
1581 (sim_set_callbacks): Delete SIM_DESC argument.
1584 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1586 * Makefile.in (SIM_OBJS): Add common modules.
1588 * interp.c (sim_set_callbacks): Also set SD callback.
1589 (set_endianness, xfer_*, swap_*): Delete.
1590 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1591 Change to functions using sim-endian macros.
1592 (control_c, sim_stop): Delete, use common version.
1593 (simulate): Convert into.
1594 (sim_engine_run): This function.
1595 (sim_resume): Delete.
1597 * interp.c (simulation): New variable - the simulator object.
1598 (sim_kind): Delete global - merged into simulation.
1599 (sim_load): Cleanup. Move PC assignment from here.
1600 (sim_create_inferior): To here.
1602 * sim-main.h: New file.
1603 * interp.c (sim-main.h): Include.
1605 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1607 * configure: Regenerated to track ../common/aclocal.m4 changes.
1609 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1611 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1613 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1615 * gencode.c (build_instruction): DIV instructions: check
1616 for division by zero and integer overflow before using
1617 host's division operation.
1619 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1621 * Makefile.in (SIM_OBJS): Add sim-load.o.
1622 * interp.c: #include bfd.h.
1623 (target_byte_order): Delete.
1624 (sim_kind, myname, big_endian_p): New static locals.
1625 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1626 after argument parsing. Recognize -E arg, set endianness accordingly.
1627 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1628 load file into simulator. Set PC from bfd.
1629 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1630 (set_endianness): Use big_endian_p instead of target_byte_order.
1632 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1634 * interp.c (sim_size): Delete prototype - conflicts with
1635 definition in remote-sim.h. Correct definition.
1637 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1639 * configure: Regenerated to track ../common/aclocal.m4 changes.
1642 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1644 * interp.c (sim_open): New arg `kind'.
1646 * configure: Regenerated to track ../common/aclocal.m4 changes.
1648 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1650 * configure: Regenerated to track ../common/aclocal.m4 changes.
1652 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1654 * interp.c (sim_open): Set optind to 0 before calling getopt.
1656 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1658 * configure: Regenerated to track ../common/aclocal.m4 changes.
1660 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1662 * interp.c : Replace uses of pr_addr with pr_uword64
1663 where the bit length is always 64 independent of SIM_ADDR.
1664 (pr_uword64) : added.
1666 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1668 * configure: Re-generate.
1670 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1672 * configure: Regenerate to track ../common/aclocal.m4 changes.
1674 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1676 * interp.c (sim_open): New SIM_DESC result. Argument is now
1678 (other sim_*): New SIM_DESC argument.
1680 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1682 * interp.c: Fix printing of addresses for non-64-bit targets.
1683 (pr_addr): Add function to print address based on size.
1685 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1687 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1689 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1691 * gencode.c (build_mips16_operands): Correct computation of base
1692 address for extended PC relative instruction.
1694 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1696 * interp.c (mips16_entry): Add support for floating point cases.
1697 (SignalException): Pass floating point cases to mips16_entry.
1698 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1700 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1702 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1703 and then set the state to fmt_uninterpreted.
1704 (COP_SW): Temporarily set the state to fmt_word while calling
1707 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1709 * gencode.c (build_instruction): The high order may be set in the
1710 comparison flags at any ISA level, not just ISA 4.
1712 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1714 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1715 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1716 * configure.in: sinclude ../common/aclocal.m4.
1717 * configure: Regenerated.
1719 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1721 * configure: Rebuild after change to aclocal.m4.
1723 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1725 * configure configure.in Makefile.in: Update to new configure
1726 scheme which is more compatible with WinGDB builds.
1727 * configure.in: Improve comment on how to run autoconf.
1728 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1729 * Makefile.in: Use autoconf substitution to install common
1732 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1734 * gencode.c (build_instruction): Use BigEndianCPU instead of
1737 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1739 * interp.c (sim_monitor): Make output to stdout visible in
1740 wingdb's I/O log window.
1742 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1744 * support.h: Undo previous change to SIGTRAP
1747 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1749 * interp.c (store_word, load_word): New static functions.
1750 (mips16_entry): New static function.
1751 (SignalException): Look for mips16 entry and exit instructions.
1752 (simulate): Use the correct index when setting fpr_state after
1753 doing a pending move.
1755 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1757 * interp.c: Fix byte-swapping code throughout to work on
1758 both little- and big-endian hosts.
1760 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1762 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1763 with gdb/config/i386/xm-windows.h.
1765 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1767 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1768 that messes up arithmetic shifts.
1770 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1772 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1773 SIGTRAP and SIGQUIT for _WIN32.
1775 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1777 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1778 force a 64 bit multiplication.
1779 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1780 destination register is 0, since that is the default mips16 nop
1783 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1785 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1786 (build_endian_shift): Don't check proc64.
1787 (build_instruction): Always set memval to uword64. Cast op2 to
1788 uword64 when shifting it left in memory instructions. Always use
1789 the same code for stores--don't special case proc64.
1791 * gencode.c (build_mips16_operands): Fix base PC value for PC
1793 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1795 * interp.c (simJALDELAYSLOT): Define.
1796 (JALDELAYSLOT): Define.
1797 (INDELAYSLOT, INJALDELAYSLOT): Define.
1798 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1800 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1802 * interp.c (sim_open): add flush_cache as a PMON routine
1803 (sim_monitor): handle flush_cache by ignoring it
1805 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1807 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1809 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1810 (BigEndianMem): Rename to ByteSwapMem and change sense.
1811 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1812 BigEndianMem references to !ByteSwapMem.
1813 (set_endianness): New function, with prototype.
1814 (sim_open): Call set_endianness.
1815 (sim_info): Use simBE instead of BigEndianMem.
1816 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1817 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1818 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1819 ifdefs, keeping the prototype declaration.
1820 (swap_word): Rewrite correctly.
1821 (ColdReset): Delete references to CONFIG. Delete endianness related
1822 code; moved to set_endianness.
1824 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1826 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1827 * interp.c (CHECKHILO): Define away.
1828 (simSIGINT): New macro.
1829 (membank_size): Increase from 1MB to 2MB.
1830 (control_c): New function.
1831 (sim_resume): Rename parameter signal to signal_number. Add local
1832 variable prev. Call signal before and after simulate.
1833 (sim_stop_reason): Add simSIGINT support.
1834 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1836 (sim_warning): Delete call to SignalException. Do call printf_filtered
1838 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1839 a call to sim_warning.
1841 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1843 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1844 16 bit instructions.
1846 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1848 Add support for mips16 (16 bit MIPS implementation):
1849 * gencode.c (inst_type): Add mips16 instruction encoding types.
1850 (GETDATASIZEINSN): Define.
1851 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1852 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1854 (MIPS16_DECODE): New table, for mips16 instructions.
1855 (bitmap_val): New static function.
1856 (struct mips16_op): Define.
1857 (mips16_op_table): New table, for mips16 operands.
1858 (build_mips16_operands): New static function.
1859 (process_instructions): If PC is odd, decode a mips16
1860 instruction. Break out instruction handling into new
1861 build_instruction function.
1862 (build_instruction): New static function, broken out of
1863 process_instructions. Check modifiers rather than flags for SHIFT
1864 bit count and m[ft]{hi,lo} direction.
1865 (usage): Pass program name to fprintf.
1866 (main): Remove unused variable this_option_optind. Change
1867 ``*loptarg++'' to ``loptarg++''.
1868 (my_strtoul): Parenthesize && within ||.
1869 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1870 (simulate): If PC is odd, fetch a 16 bit instruction, and
1871 increment PC by 2 rather than 4.
1872 * configure.in: Add case for mips16*-*-*.
1873 * configure: Rebuild.
1875 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1877 * interp.c: Allow -t to enable tracing in standalone simulator.
1878 Fix garbage output in trace file and error messages.
1880 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1882 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1883 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1884 * configure.in: Simplify using macros in ../common/aclocal.m4.
1885 * configure: Regenerated.
1886 * tconfig.in: New file.
1888 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1890 * interp.c: Fix bugs in 64-bit port.
1891 Use ansi function declarations for msvc compiler.
1892 Initialize and test file pointer in trace code.
1893 Prevent duplicate definition of LAST_EMED_REGNUM.
1895 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1897 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1899 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1901 * interp.c (SignalException): Check for explicit terminating
1903 * gencode.c: Pass instruction value through SignalException()
1904 calls for Trap, Breakpoint and Syscall.
1906 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1908 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1909 only used on those hosts that provide it.
1910 * configure.in: Add sqrt() to list of functions to be checked for.
1911 * config.in: Re-generated.
1912 * configure: Re-generated.
1914 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1916 * gencode.c (process_instructions): Call build_endian_shift when
1917 expanding STORE RIGHT, to fix swr.
1918 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1919 clear the high bits.
1920 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1921 Fix float to int conversions to produce signed values.
1923 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1925 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1926 (process_instructions): Correct handling of nor instruction.
1927 Correct shift count for 32 bit shift instructions. Correct sign
1928 extension for arithmetic shifts to not shift the number of bits in
1929 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1930 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1932 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1933 It's OK to have a mult follow a mult. What's not OK is to have a
1934 mult follow an mfhi.
1935 (Convert): Comment out incorrect rounding code.
1937 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1939 * interp.c (sim_monitor): Improved monitor printf
1940 simulation. Tidied up simulator warnings, and added "--log" option
1941 for directing warning message output.
1942 * gencode.c: Use sim_warning() rather than WARNING macro.
1944 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1946 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1947 getopt1.o, rather than on gencode.c. Link objects together.
1948 Don't link against -liberty.
1949 (gencode.o, getopt.o, getopt1.o): New targets.
1950 * gencode.c: Include <ctype.h> and "ansidecl.h".
1951 (AND): Undefine after including "ansidecl.h".
1952 (ULONG_MAX): Define if not defined.
1953 (OP_*): Don't define macros; now defined in opcode/mips.h.
1954 (main): Call my_strtoul rather than strtoul.
1955 (my_strtoul): New static function.
1957 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1959 * gencode.c (process_instructions): Generate word64 and uword64
1960 instead of `long long' and `unsigned long long' data types.
1961 * interp.c: #include sysdep.h to get signals, and define default
1963 * (Convert): Work around for Visual-C++ compiler bug with type
1965 * support.h: Make things compile under Visual-C++ by using
1966 __int64 instead of `long long'. Change many refs to long long
1967 into word64/uword64 typedefs.
1969 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
1971 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1972 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1974 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1975 (AC_PROG_INSTALL): Added.
1976 (AC_PROG_CC): Moved to before configure.host call.
1977 * configure: Rebuilt.
1979 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
1981 * configure.in: Define @SIMCONF@ depending on mips target.
1982 * configure: Rebuild.
1983 * Makefile.in (run): Add @SIMCONF@ to control simulator
1985 * gencode.c: Change LOADDRMASK to 64bit memory model only.
1986 * interp.c: Remove some debugging, provide more detailed error
1987 messages, update memory accesses to use LOADDRMASK.
1989 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
1991 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
1992 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
1994 * configure: Rebuild.
1995 * config.in: New file, generated by autoheader.
1996 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
1997 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
1998 HAVE_ANINT and HAVE_AINT, as appropriate.
1999 * Makefile.in (run): Use @LIBS@ rather than -lm.
2000 (interp.o): Depend upon config.h.
2001 (Makefile): Just rebuild Makefile.
2002 (clean): Remove stamp-h.
2003 (mostlyclean): Make the same as clean, not as distclean.
2004 (config.h, stamp-h): New targets.
2006 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2008 * interp.c (ColdReset): Fix boolean test. Make all simulator
2011 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2013 * interp.c (xfer_direct_word, xfer_direct_long,
2014 swap_direct_word, swap_direct_long, xfer_big_word,
2015 xfer_big_long, xfer_little_word, xfer_little_long,
2016 swap_word,swap_long): Added.
2017 * interp.c (ColdReset): Provide function indirection to
2018 host<->simulated_target transfer routines.
2019 * interp.c (sim_store_register, sim_fetch_register): Updated to
2020 make use of indirected transfer routines.
2022 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2024 * gencode.c (process_instructions): Ensure FP ABS instruction
2026 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2027 system call support.
2029 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2031 * interp.c (sim_do_command): Complain if callback structure not
2034 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2036 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2037 support for Sun hosts.
2038 * Makefile.in (gencode): Ensure the host compiler and libraries
2039 used for cross-hosted build.
2041 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2043 * interp.c, gencode.c: Some more (TODO) tidying.
2045 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2047 * gencode.c, interp.c: Replaced explicit long long references with
2048 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2049 * support.h (SET64LO, SET64HI): Macros added.
2051 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2053 * configure: Regenerate with autoconf 2.7.
2055 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2057 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2058 * support.h: Remove superfluous "1" from #if.
2059 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2061 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2063 * interp.c (StoreFPR): Control UndefinedResult() call on
2064 WARN_RESULT manifest.
2066 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2068 * gencode.c: Tidied instruction decoding, and added FP instruction
2071 * interp.c: Added dineroIII, and BSD profiling support. Also
2072 run-time FP handling.
2074 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2076 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2077 gencode.c, interp.c, support.h: created.