sound/soc/intel/skylake/bxt-sst.c

   1 /*
   2  *  bxt-sst.c - DSP library functions for BXT platform
   3  *
   4  *  Copyright (C) 2015-16 Intel Corp
   5  *  Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
   6  *         Jeeja KP <jeeja.kp@intel.com>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; version 2 of the License.
  11  *
  12  *  This program is distributed in the hope that it will be useful, but
  13  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  *  General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/delay.h>
  20 #include <linux/firmware.h>
  21 #include <linux/device.h>
  22
  23 #include "../common/sst-dsp.h"
  24 #include "../common/sst-dsp-priv.h"
  25 #include "skl-sst-ipc.h"
  26
  27 #define BXT_BASEFW_TIMEOUT      3000
  28 #define BXT_INIT_TIMEOUT        500
  29 #define BXT_IPC_PURGE_FW        0x01004000
  30
  31 #define BXT_ROM_INIT            0x5
  32 #define BXT_ADSP_SRAM0_BASE     0x80000
  33
  34 /* Firmware status window */
  35 #define BXT_ADSP_FW_STATUS      BXT_ADSP_SRAM0_BASE
  36 #define BXT_ADSP_ERROR_CODE     (BXT_ADSP_FW_STATUS + 0x4)
  37
  38 #define BXT_ADSP_SRAM1_BASE     0xA0000
  39
  40 static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
  41 {
  42          return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
  43 }
  44
  45 static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
  46                         const void *fwdata, u32 fwsize)
  47 {
  48         int stream_tag, ret, i;
  49         u32 reg;
  50
  51         stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
  52         if (stream_tag < 0) {
  53                 dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
  54                                 stream_tag);
  55                 return stream_tag;
  56         }
  57
  58         ctx->dsp_ops.stream_tag = stream_tag;
  59         memcpy(ctx->dmab.area, fwdata, fwsize);
  60
  61         /* Purge FW request */
  62         sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
  63                                          BXT_IPC_PURGE_FW | (stream_tag - 1));
  64
  65         ret = skl_dsp_enable_core(ctx);
  66         if (ret < 0) {
  67                 dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret);
  68                 ret = -EIO;
  69                 goto base_fw_load_failed;
  70         }
  71
  72         for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
  73                 reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE);
  74
  75                 if (reg & SKL_ADSP_REG_HIPCIE_DONE) {
  76                         sst_dsp_shim_update_bits_forced(ctx,
  77                                         SKL_ADSP_REG_HIPCIE,
  78                                         SKL_ADSP_REG_HIPCIE_DONE,
  79                                         SKL_ADSP_REG_HIPCIE_DONE);
  80                         break;
  81                 }
  82                 mdelay(1);
  83         }
  84         if (!i) {
  85                 dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg);
  86                 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE,
  87                                 SKL_ADSP_REG_HIPCIE_DONE,
  88                                 SKL_ADSP_REG_HIPCIE_DONE);
  89         }
  90
  91         /* enable Interrupt */
  92         skl_ipc_int_enable(ctx);
  93         skl_ipc_op_int_enable(ctx);
  94
  95         for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
  96                 if (SKL_FW_INIT ==
  97                                 (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) &
  98                                 SKL_FW_STS_MASK)) {
  99
 100                         dev_info(ctx->dev, "ROM loaded, continue FW loading\n");
 101                         break;
 102                 }
 103                 mdelay(1);
 104         }
 105         if (!i) {
 106                 dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg);
 107                 ret = -EIO;
 108                 goto base_fw_load_failed;
 109         }
 110
 111         return ret;
 112
 113 base_fw_load_failed:
 114         ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
 115         skl_dsp_disable_core(ctx);
 116         return ret;
 117 }
 118
 119 static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
 120 {
 121         int ret;
 122
 123         ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
 124         ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
 125                         BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
 126
 127         ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
 128         ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
 129
 130         return ret;
 131 }
 132
 133 static int bxt_load_base_firmware(struct sst_dsp *ctx)
 134 {
 135         const struct firmware *fw = NULL;
 136         struct skl_sst *skl = ctx->thread_context;
 137         int ret;
 138
 139         ret = request_firmware(&fw, ctx->fw_name, ctx->dev);
 140         if (ret < 0) {
 141                 dev_err(ctx->dev, "Request firmware failed %d\n", ret);
 142                 goto sst_load_base_firmware_failed;
 143         }
 144
 145         ret = sst_bxt_prepare_fw(ctx, fw->data, fw->size);
 146         /* Retry Enabling core and ROM load. Retry seemed to help */
 147         if (ret < 0) {
 148                 ret = sst_bxt_prepare_fw(ctx, fw->data, fw->size);
 149                 if (ret < 0) {
 150                         dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
 151                         goto sst_load_base_firmware_failed;
 152                 }
 153         }
 154
 155         ret = sst_transfer_fw_host_dma(ctx);
 156         if (ret < 0) {
 157                 dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
 158                 dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
 159                         sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
 160                         sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
 161
 162                 skl_dsp_disable_core(ctx);
 163         } else {
 164                 dev_dbg(ctx->dev, "Firmware download successful\n");
 165                 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
 166                                         msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
 167                 if (ret == 0) {
 168                         dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
 169                         skl_dsp_disable_core(ctx);
 170                         ret = -EIO;
 171                 } else {
 172                         skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
 173                         ret = 0;
 174                 }
 175         }
 176
 177 sst_load_base_firmware_failed:
 178         release_firmware(fw);
 179         return ret;
 180 }
 181
 182 static int bxt_set_dsp_D0(struct sst_dsp *ctx)
 183 {
 184         struct skl_sst *skl = ctx->thread_context;
 185         int ret;
 186
 187         skl->boot_complete = false;
 188
 189         ret = skl_dsp_enable_core(ctx);
 190         if (ret < 0) {
 191                 dev_err(ctx->dev, "enable dsp core failed ret: %d\n", ret);
 192                 return ret;
 193         }
 194
 195         /* enable interrupt */
 196         skl_ipc_int_enable(ctx);
 197         skl_ipc_op_int_enable(ctx);
 198
 199         ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
 200                                         msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
 201         if (ret == 0) {
 202                 dev_err(ctx->dev, "ipc: error DSP boot timeout\n");
 203                 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
 204                         sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
 205                         sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
 206                 return -EIO;
 207         }
 208
 209         skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
 210         return 0;
 211 }
 212
 213 static int bxt_set_dsp_D3(struct sst_dsp *ctx)
 214 {
 215         struct skl_ipc_dxstate_info dx;
 216         struct skl_sst *skl = ctx->thread_context;
 217         int ret = 0;
 218
 219         if (!is_skl_dsp_running(ctx))
 220                 return ret;
 221
 222         dx.core_mask = SKL_DSP_CORE0_MASK;
 223         dx.dx_mask = SKL_IPC_D3_MASK;
 224
 225         ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID,
 226                                 SKL_BASE_FW_MODULE_ID, &dx);
 227         if (ret < 0) {
 228                 dev_err(ctx->dev, "Failed to set DSP to D3 state: %d\n", ret);
 229                 return ret;
 230         }
 231
 232         ret = skl_dsp_disable_core(ctx);
 233         if (ret < 0) {
 234                 dev_err(ctx->dev, "disbale dsp core failed: %d\n", ret);
 235                 ret = -EIO;
 236         }
 237
 238         skl_dsp_set_state_locked(ctx, SKL_DSP_RESET);
 239         return 0;
 240 }
 241
 242 static struct skl_dsp_fw_ops bxt_fw_ops = {
 243         .set_state_D0 = bxt_set_dsp_D0,
 244         .set_state_D3 = bxt_set_dsp_D3,
 245         .load_fw = bxt_load_base_firmware,
 246         .get_fw_errcode = bxt_get_errorcode,
 247 };
 248
 249 static struct sst_ops skl_ops = {
 250         .irq_handler = skl_dsp_sst_interrupt,
 251         .write = sst_shim32_write,
 252         .read = sst_shim32_read,
 253         .ram_read = sst_memcpy_fromio_32,
 254         .ram_write = sst_memcpy_toio_32,
 255         .free = skl_dsp_free,
 256 };
 257
 258 static struct sst_dsp_device skl_dev = {
 259         .thread = skl_dsp_irq_thread_handler,
 260         .ops = &skl_ops,
 261 };
 262
 263 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 264                         const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 265                         struct skl_sst **dsp)
 266 {
 267         struct skl_sst *skl;
 268         struct sst_dsp *sst;
 269         int ret;
 270
 271         skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
 272         if (skl == NULL)
 273                 return -ENOMEM;
 274
 275         skl->dev = dev;
 276         skl_dev.thread_context = skl;
 277
 278         skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
 279         if (!skl->dsp) {
 280                 dev_err(skl->dev, "skl_dsp_ctx_init failed\n");
 281                 return -ENODEV;
 282         }
 283
 284         sst = skl->dsp;
 285         sst->fw_name = fw_name;
 286         sst->dsp_ops = dsp_ops;
 287         sst->fw_ops = bxt_fw_ops;
 288         sst->addr.lpe = mmio_base;
 289         sst->addr.shim = mmio_base;
 290
 291         sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
 292                         SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
 293
 294         INIT_LIST_HEAD(&sst->module_list);
 295         ret = skl_ipc_init(dev, skl);
 296         if (ret)
 297                 return ret;
 298
 299         skl->boot_complete = false;
 300         init_waitqueue_head(&skl->boot_wait);
 301
 302         ret = sst->fw_ops.load_fw(sst);
 303         if (ret < 0) {
 304                 dev_err(dev, "Load base fw failed: %x", ret);
 305                 return ret;
 306         }
 307
 308         if (dsp)
 309                 *dsp = skl;
 310
 311         return 0;
 312 }
 313 EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
 314
 315
 316 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
 317 {
 318         skl_ipc_free(&ctx->ipc);
 319         ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
 320
 321         if (ctx->dsp->addr.lpe)
 322                 iounmap(ctx->dsp->addr.lpe);
 323
 324         ctx->dsp->ops->free(ctx->dsp);
 325 }
 326 EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
 327
 328 MODULE_LICENSE("GPL v2");
 329 MODULE_DESCRIPTION("Intel Broxton IPC driver");