ARM: dts: Add CPU OPP properties for exynos542x/5800

[deliverable/linux.git] / arch / arm / boot / dts / exynos5422-cpus.dtsi

diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index b7f60c855459126bf63bb3ffe120ab6f87f37dfe..9b46b9fbac4e774b1542cde204f949bcc791b730 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -4,78 +4,98 @@
  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com
  *
- * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The
- * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting
- * from Cortex-A15 core.
+ * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
  *
- * EXYNOS5422 based board files can include this file to provide cpu ordering
- * which could boot a cortex-a7 from cpu0.
+ * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
+ * but particular boards choose different booting order.
+ *
+ * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
+ * booting cluster (big or LITTLE) is chosen by IROM code by reading
+ * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
+ * from the LITTLE: Cortex-A7.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-&cpu0 {
-       device_type = "cpu";
-       compatible = "arm,cortex-a7";
-       reg = <0x100>;
-       clock-frequency = <1000000000>;
-       cci-control-port = <&cci_control0>;
-};
+/ {
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
 
-&cpu1 {
-       device_type = "cpu";
-       compatible = "arm,cortex-a7";
-       reg = <0x101>;
-       clock-frequency = <1000000000>;
-       cci-control-port = <&cci_control0>;
-};
+               cpu0: cpu@100 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x100>;
+                       clocks = <&clock CLK_KFC_CLK>;
+                       clock-frequency = <1000000000>;
+                       cci-control-port = <&cci_control0>;
+                       operating-points-v2 = <&cluster_a7_opp_table>;
+               };
 
-&cpu2 {
-       device_type = "cpu";
-       compatible = "arm,cortex-a7";
-       reg = <0x102>;
-       clock-frequency = <1000000000>;
-       cci-control-port = <&cci_control0>;
-};
+               cpu1: cpu@101 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x101>;
+                       clock-frequency = <1000000000>;
+                       cci-control-port = <&cci_control0>;
+                       operating-points-v2 = <&cluster_a7_opp_table>;
+               };
 
-&cpu3 {
-       device_type = "cpu";
-       compatible = "arm,cortex-a7";
-       reg = <0x103>;
-       clock-frequency = <1000000000>;
-       cci-control-port = <&cci_control0>;
-};
+               cpu2: cpu@102 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x102>;
+                       clock-frequency = <1000000000>;
+                       cci-control-port = <&cci_control0>;
+                       operating-points-v2 = <&cluster_a7_opp_table>;
+               };
 
-&cpu4 {
-       device_type = "cpu";
-       compatible = "arm,cortex-a15";
-       reg = <0x0>;
-       clock-frequency = <1800000000>;
-       cci-control-port = <&cci_control1>;
-};
+               cpu3: cpu@103 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x103>;
+                       clock-frequency = <1000000000>;
+                       cci-control-port = <&cci_control0>;
+                       operating-points-v2 = <&cluster_a7_opp_table>;
+               };
 
-&cpu5 {
-       device_type = "cpu";
-       compatible = "arm,cortex-a15";
-       reg = <0x1>;
-       clock-frequency = <1800000000>;
-       cci-control-port = <&cci_control1>;
-};
+               cpu4: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       clocks = <&clock CLK_ARM_CLK>;
+                       reg = <0x0>;
+                       clock-frequency = <1800000000>;
+                       cci-control-port = <&cci_control1>;
+                       operating-points-v2 = <&cluster_a15_opp_table>;
+               };
 
-&cpu6 {
-       device_type = "cpu";
-       compatible = "arm,cortex-a15";
-       reg = <0x2>;
-       clock-frequency = <1800000000>;
-       cci-control-port = <&cci_control1>;
-};
+               cpu5: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0x1>;
+                       clock-frequency = <1800000000>;
+                       cci-control-port = <&cci_control1>;
+                       operating-points-v2 = <&cluster_a15_opp_table>;
+               };
+
+               cpu6: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0x2>;
+                       clock-frequency = <1800000000>;
+                       cci-control-port = <&cci_control1>;
+                       operating-points-v2 = <&cluster_a15_opp_table>;
+               };
 
-&cpu7 {
-       device_type = "cpu";
-       compatible = "arm,cortex-a15";
-       reg = <0x3>;
-       clock-frequency = <1800000000>;
-       cci-control-port = <&cci_control1>;
+               cpu7: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0x3>;
+                       clock-frequency = <1800000000>;
+                       cci-control-port = <&cci_control1>;
+                       operating-points-v2 = <&cluster_a15_opp_table>;
+               };
+       };
 };