#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/r4kcache.h>
+#include <asm/sections.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/war.h>
static inline void local_r4k_flush_cache_all(void * args)
{
r4k_blast_dcache();
- r4k_blast_icache();
}
static void r4k_flush_cache_all(void)
static inline void local_r4k___flush_cache_all(void * args)
{
+#if defined(CONFIG_CPU_LOONGSON2)
+ r4k_blast_scache();
+ return;
+#endif
r4k_blast_dcache();
r4k_blast_icache();
static inline void local_r4k_flush_cache_range(void * args)
{
struct vm_area_struct *vma = args;
- int exec;
if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
return;
- exec = vma->vm_flags & VM_EXEC;
- if (cpu_has_dc_aliases || exec)
- r4k_blast_dcache();
- if (exec)
- r4k_blast_icache();
+ r4k_blast_dcache();
}
static void r4k_flush_cache_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
+ if (!cpu_has_dc_aliases)
+ return;
+
r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
}
if (!cpu_context(smp_processor_id(), mm))
return;
- r4k_blast_dcache();
- r4k_blast_icache();
-
/*
* Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
* only flush the primary caches but R10000 and R12000 behave sane ...
+ * R4000SC and R4400SC indexed S-cache ops also invalidate primary
+ * caches, so we can bail out early.
*/
if (current_cpu_data.cputype == CPU_R4000SC ||
current_cpu_data.cputype == CPU_R4000MC ||
current_cpu_data.cputype == CPU_R4400SC ||
- current_cpu_data.cputype == CPU_R4400MC)
+ current_cpu_data.cputype == CPU_R4400MC) {
r4k_blast_scache();
+ return;
+ }
+
+ r4k_blast_dcache();
}
static void r4k_flush_cache_mm(struct mm_struct *mm)
instruction_hazard();
}
-/*
- * Ok, this seriously sucks. We use them to flush a user page but don't
- * know the virtual address, so we have to blast away the whole icache
- * which is significantly more expensive than the real thing. Otoh we at
- * least know the kernel address of the page so we can flush it
- * selectivly.
- */
-
-struct flush_icache_page_args {
- struct vm_area_struct *vma;
- struct page *page;
-};
-
-static inline void local_r4k_flush_icache_page(void *args)
-{
- struct flush_icache_page_args *fip_args = args;
- struct vm_area_struct *vma = fip_args->vma;
- struct page *page = fip_args->page;
-
- /*
- * Tricky ... Because we don't know the virtual address we've got the
- * choice of either invalidating the entire primary and secondary
- * caches or invalidating the secondary caches also. With the subset
- * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
- * secondary cache will result in any entries in the primary caches
- * also getting invalidated which hopefully is a bit more economical.
- */
- if (cpu_has_inclusive_pcaches) {
- unsigned long addr = (unsigned long) page_address(page);
-
- r4k_blast_scache_page(addr);
- ClearPageDcacheDirty(page);
-
- return;
- }
-
- if (!cpu_has_ic_fills_f_dc) {
- unsigned long addr = (unsigned long) page_address(page);
- r4k_blast_dcache_page(addr);
- if (!cpu_icache_snoops_remote_store)
- r4k_blast_scache_page(addr);
- ClearPageDcacheDirty(page);
- }
-
- /*
- * We're not sure of the virtual address(es) involved here, so
- * we have to flush the entire I-cache.
- */
- if (cpu_has_vtag_icache && vma->vm_mm == current->active_mm) {
- int cpu = smp_processor_id();
-
- if (cpu_context(cpu, vma->vm_mm) != 0)
- drop_mmu_context(vma->vm_mm, cpu);
- } else
- r4k_blast_icache();
-}
-
-static void r4k_flush_icache_page(struct vm_area_struct *vma,
- struct page *page)
-{
- struct flush_icache_page_args args;
-
- /*
- * If there's no context yet, or the page isn't executable, no I-cache
- * flush is needed.
- */
- if (!(vma->vm_flags & VM_EXEC))
- return;
-
- args.vma = vma;
- args.page = page;
-
- r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
-}
-
-
#ifdef CONFIG_DMA_NONCOHERENT
static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
c->options |= MIPS_CPU_PREFETCH;
break;
+ case CPU_LOONGSON2:
+ icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
+ c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
+ if (prid & 0x3)
+ c->icache.ways = 4;
+ else
+ c->icache.ways = 2;
+ c->icache.waybit = 0;
+
+ dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
+ c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
+ if (prid & 0x3)
+ c->dcache.ways = 4;
+ else
+ c->dcache.ways = 2;
+ c->dcache.waybit = 0;
+ break;
+
default:
if (!(config & MIPS_CONF_M))
panic("Don't know how to probe P-caches on this cpu.");
break;
}
+#ifdef CONFIG_CPU_LOONGSON2
+ /*
+ * LOONGSON2 has 4 way icache, but when using indexed cache op,
+ * one op will act on all 4 ways
+ */
+ c->icache.ways = 1;
+#endif
+
printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
icache_size >> 10,
cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
*/
static int __init probe_scache(void)
{
- extern unsigned long stext;
unsigned long flags, addr, begin, end, pow2;
unsigned int config = read_c0_config();
struct cpuinfo_mips *c = ¤t_cpu_data;
if (config & CONF_SC)
return 0;
- begin = (unsigned long) &stext;
+ begin = (unsigned long) &_stext;
begin &= ~((4 * 1024 * 1024) - 1);
end = begin + (4 * 1024 * 1024);
return 1;
}
+#if defined(CONFIG_CPU_LOONGSON2)
+static void __init loongson2_sc_init(void)
+{
+ struct cpuinfo_mips *c = ¤t_cpu_data;
+
+ scache_size = 512*1024;
+ c->scache.linesz = 32;
+ c->scache.ways = 4;
+ c->scache.waybit = 0;
+ c->scache.waysize = scache_size / (c->scache.ways);
+ c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
+ pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
+ scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
+
+ c->options |= MIPS_CPU_INCLUSIVE_CACHES;
+}
+#endif
+
extern int r5k_sc_init(void);
extern int rm7k_sc_init(void);
extern int mips_sc_init(void);
#endif
return;
+#if defined(CONFIG_CPU_LOONGSON2)
+ case CPU_LOONGSON2:
+ loongson2_sc_init();
+ return;
+#endif
+
default:
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
c->isa_level == MIPS_CPU_ISA_M32R2 ||
__flush_cache_all = r4k___flush_cache_all;
flush_cache_mm = r4k_flush_cache_mm;
flush_cache_page = r4k_flush_cache_page;
- __flush_icache_page = r4k_flush_icache_page;
flush_cache_range = r4k_flush_cache_range;
flush_cache_sigtramp = r4k_flush_cache_sigtramp;
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