+2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Add VexSwapSources.
+ * i386-opc.h (VexSwapSources): New.
+ (i386_opcode_modifier): Add vexswapsources.
+ * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
+ with two source operands swapped.
+ * i386-tbl.h: Regenerated.
+
+2020-06-30 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
+ unprivileged CSR can also be initialized.
+
+2020-06-29 Alan Modra <amodra@gmail.com>
+
+ * arm-dis.c: Use C style comments.
+ * cr16-opc.c: Likewise.
+ * ft32-dis.c: Likewise.
+ * moxie-opc.c: Likewise.
+ * tic54x-dis.c: Likewise.
+ * s12z-opc.c: Remove useless comment.
+ * xgate-dis.c: Likewise.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add a blank line.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
+ (VecSIB128): Renamed to ...
+ (VECSIB128): This.
+ (VecSIB256): Renamed to ...
+ (VECSIB256): This.
+ (VecSIB512): Renamed to ...
+ (VECSIB512): This.
+ (VecSIB): Renamed to ...
+ (SIB): This.
+ (i386_opcode_modifier): Replace vecsib with sib.
+ * i386-opc.tbl (VecSIB128): New.
+ (VecSIB256): Likewise.
+ (VecSIB512): Likewise.
+ Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
+ and VecSIB512, respectively.
+
+2020-06-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: Adjust description of I macro.
+ (x86_64_table): Drop use of I.
+ (float_mem): Replace use of I.
+ (putop): Remove handling of I. Adjust setting/clearing of "alt".
+
+2020-06-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: (print_insn): Avoid straight assignment to
+ priv.orig_sizeflag when processing -M sub-options.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: Adjust description of J macro.
+ (dis386, x86_64_table, mod_table): Replace J.
+ (putop): Remove handling of J.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: Adjust description of "LQ" macro.
+ (dis386_twobyte): Use LQ for sysret.
+ (putop): Adjust handling of LQ.
+
+2020-06-22 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
+ * riscv-dis.c: Include elfxx-riscv.h.
+
+2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (prefix_table): Revert the last vmgexit change.
+
+2020-06-17 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
+
+2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26115
+ * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
+ * i386-opc.tbl: Likewise.
+ * i386-tbl.h: Regenerated.
+
+2020-06-12 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
+
+2020-06-11 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-opc.c (SYSREG): New macro for describing system registers.
+ (SR_CORE): Likewise.
+ (SR_FEAT): Likewise.
+ (SR_RNG): Likewise.
+ (SR_V8_1): Likewise.
+ (SR_V8_2): Likewise.
+ (SR_V8_3): Likewise.
+ (SR_V8_4): Likewise.
+ (SR_PAN): Likewise.
+ (SR_RAS): Likewise.
+ (SR_SSBS): Likewise.
+ (SR_SVE): Likewise.
+ (SR_ID_PFR2): Likewise.
+ (SR_PROFILE): Likewise.
+ (SR_MEMTAG): Likewise.
+ (SR_SCXTNUM): Likewise.
+ (aarch64_sys_regs): Refactor to store feature information in the table.
+ (aarch64_sys_reg_supported_p): Collapse logic for system registers
+ that now describe their own features.
+ (aarch64_pstatefield_supported_p): Likewise.
+
+2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (prefix_table): Fix a typo in comments.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (rex_ignored): Delete.
+ (ckprefix): Drop rex_ignored initialization.
+ (get_valid_dis386): Drop setting of rex_ignored.
+ (print_insn): Drop checking of rex_ignored. Don't record data
+ size prefix as used with VEX-and-alike encodings.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
+ MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
+ (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
+ (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
+ (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
+ VEX_0F12, and VEX_0F16.
+ (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
+ VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
+ (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
+ from movlps and movhlps. New MOD_0F12_PREFIX_2,
+ MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
+ MOD_VEX_0F16_PREFIX_2 entries.
+
2020-06-09 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
projects / deliverable / binutils-gdb.git / blobdiff