PowerPC disassembly of pcrel references

[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.h

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index ffb3b8317c83d0ebfb8b34ab485b9b2464aa4032..a4a2b6f209a8b2eec60d70795e858a8816dbd27e 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -1,5 +1,5 @@
 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
-   Copyright (C) 2012-2019 Free Software Foundation, Inc.
+   Copyright (C) 2012-2021 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
@@ -78,6 +78,7 @@ enum aarch64_field_kind
   FLD_imm12,
   FLD_imm14,
   FLD_imm16,
+  FLD_imm16_2,
   FLD_imm26,
   FLD_imms,
   FLD_immr,
@@ -121,6 +122,9 @@ enum aarch64_field_kind
   FLD_SVE_Zt,
   FLD_SVE_i1,
   FLD_SVE_i3h,
+  FLD_SVE_i3l,
+  FLD_SVE_i3h2,
+  FLD_SVE_i2h,
   FLD_SVE_imm3,
   FLD_SVE_imm4,
   FLD_SVE_imm5,
@@ -136,7 +140,10 @@ enum aarch64_field_kind
   FLD_SVE_prfop,
   FLD_SVE_rot1,
   FLD_SVE_rot2,
+  FLD_SVE_rot3,
   FLD_SVE_sz,
+  FLD_SVE_size,
+  FLD_SVE_sz2,
   FLD_SVE_tsz,
   FLD_SVE_tszh,
   FLD_SVE_tszl_8,
@@ -146,7 +153,9 @@ enum aarch64_field_kind
   FLD_rotate1,
   FLD_rotate2,
   FLD_rotate3,
-  FLD_SM3_imm2
+  FLD_SM3_imm2,
+  FLD_sz,
+  FLD_CRm_dsb_nxs
 };
 
 /* Field description.  */
@@ -186,7 +195,7 @@ extern const aarch64_operand aarch64_operands[];
 
 enum err_type
 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
-                   bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
+                   bool, aarch64_operand_error *, aarch64_instr_sequence*);
 
 /* Operand flags.  */
 
@@ -233,40 +242,40 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 #define HINT_FLAG(val) (val >> 8)
 #define HINT_VAL(val) (val & 0xff)
 
-static inline bfd_boolean
+static inline bool
 operand_has_inserter (const aarch64_operand *operand)
 {
-  return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
+  return (operand->flags & OPD_F_HAS_INSERTER) != 0;
 }
 
-static inline bfd_boolean
+static inline bool
 operand_has_extractor (const aarch64_operand *operand)
 {
-  return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
+  return (operand->flags & OPD_F_HAS_EXTRACTOR) != 0;
 }
 
-static inline bfd_boolean
+static inline bool
 operand_need_sign_extension (const aarch64_operand *operand)
 {
-  return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
+  return (operand->flags & OPD_F_SEXT) != 0;
 }
 
-static inline bfd_boolean
+static inline bool
 operand_need_shift_by_two (const aarch64_operand *operand)
 {
-  return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
+  return (operand->flags & OPD_F_SHIFT_BY_2) != 0;
 }
 
-static inline bfd_boolean
+static inline bool
 operand_need_shift_by_four (const aarch64_operand *operand)
 {
-  return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
+  return (operand->flags & OPD_F_SHIFT_BY_4) != 0;
 }
 
-static inline bfd_boolean
+static inline bool
 operand_maybe_stack_pointer (const aarch64_operand *operand)
 {
-  return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
+  return (operand->flags & OPD_F_MAYBE_SP) != 0;
 }
 
 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
@@ -475,11 +484,11 @@ int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 
 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 enum aarch64_modifier_kind
-aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
+aarch64_get_operand_modifier_from_value (aarch64_insn, bool);
 
 
-bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
-bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
+bool aarch64_wide_constant_p (uint64_t, int, unsigned int *);
+bool aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 int aarch64_shrink_expanded_imm8 (uint64_t);
 
 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */