X-Git-Url: https://git.efficios.com/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=c0a3db699c7175c45b408fd6d119677f3d20b810;hb=c2ecccb33c307faa21f4d2f47348e7346b032d94;hp=542b2c10867340da358bca88e5bd470cba7597da;hpb=d27c357a5b83773054e85ff3ea5dbfe18b9dd3c0;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 542b2c1086..c0a3db699c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,82 @@
+2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-gen.c (opcode_modifiers): Add VexSwapSources.
+	* i386-opc.h (VexSwapSources): New.
+	(i386_opcode_modifier): Add vexswapsources.
+	* i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
+	with two source operands swapped.
+	* i386-tbl.h: Regenerated.
+
+2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
+
+	* riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
+	unprivileged CSR can also be initialized.
+
+2020-06-29  Alan Modra  <amodra@gmail.com>
+
+	* arm-dis.c: Use C style comments.
+	* cr16-opc.c: Likewise.
+	* ft32-dis.c: Likewise.
+	* moxie-opc.c: Likewise.
+	* tic54x-dis.c: Likewise.
+	* s12z-opc.c: Remove useless comment.
+	* xgate-dis.c: Likewise.
+
+2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-opc.tbl: Add a blank line.
+
+2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
+	(VecSIB128): Renamed to ...
+	(VECSIB128): This.
+	(VecSIB256): Renamed to ...
+	(VECSIB256): This.
+	(VecSIB512): Renamed to ...
+	(VECSIB512): This.
+	(VecSIB): Renamed to ...
+	(SIB): This.
+	(i386_opcode_modifier): Replace vecsib with sib.
+	* i386-opc.tbl (VecSIB128): New.
+	(VecSIB256): Likewise.
+	(VecSIB512): Likewise.
+	Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
+	and VecSIB512, respectively.
+
+2020-06-26  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c: Adjust description of I macro.
+	(x86_64_table): Drop use of I.
+	(float_mem): Replace use of I.
+	(putop): Remove handling of I. Adjust setting/clearing of "alt".
+
+2020-06-26  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c: (print_insn): Avoid straight assignment to
+	priv.orig_sizeflag when processing -M sub-options.
+
+2020-06-25  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c: Adjust description of J macro.
+	(dis386, x86_64_table, mod_table): Replace J.
+	(putop): Remove handling of J.
+
+2020-06-25  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
+
+2020-06-25  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c: Adjust description of "LQ" macro.
+	(dis386_twobyte): Use LQ for sysret.
+	(putop): Adjust handling of LQ.
+
+2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
+
+	* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
+	* riscv-dis.c: Include elfxx-riscv.h.
+
 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-dis.c (prefix_table): Revert the last vmgexit change.