drm/i915: Don't allow ring tail to reach the same cacheline as head
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 3 Dec 2012 16:43:32 +0000 (18:43 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 3 Dec 2012 17:31:20 +0000 (18:31 +0100)
commit633cf8f5056c3e72158e4dbc387b3d65926d2d55
tree6cc390a59636d26d70165322bbab2ebed155cd17
parenta2165e312381f35b8abd7dcb8a8ab955bc60d867
drm/i915: Don't allow ring tail to reach the same cacheline as head

From BSpec:
"If the Ring Buffer Head Pointer and the Tail Pointer are on the same
cacheline, the Head Pointer must not be greater than the Tail
Pointer."

The easiest way to enforce this is to reduce the reported ring space.

References:
Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"

v2: Include the exact BSpec references in the description

v3: s/64/I915_RING_FREE_SPACE, and add the BSpec information to the code

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_ringbuffer.h
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