drm/i915/tv: extract set_tv_mode_timings

intel_tv_mode_set is just too big.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index bafe92e317d5d24c103bc83ea93a846cfadf19d0..04bf8caaac0c19d399de83a2d604086ee03dfac4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -934,6 +934,65 @@ intel_tv_compute_config(struct intel_encoder *encoder,
        return true;
 }
 
+static void
+set_tv_mode_timings(struct drm_i915_private *dev_priv,
+                   const struct tv_mode *tv_mode,
+                   bool burst_ena)
+{
+       u32 hctl1, hctl2, hctl3;
+       u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
+
+       hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
+               (tv_mode->htotal << TV_HTOTAL_SHIFT);
+
+       hctl2 = (tv_mode->hburst_start << 16) |
+               (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
+
+       if (burst_ena)
+               hctl2 |= TV_BURST_ENA;
+
+       hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
+               (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
+
+       vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
+               (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
+               (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
+
+       vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
+               (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
+               (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
+
+       vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
+               (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
+               (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
+
+       if (tv_mode->veq_ena)
+               vctl3 |= TV_EQUAL_ENA;
+
+       vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
+               (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
+
+       vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
+               (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
+
+       vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
+               (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
+
+       vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
+               (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
+
+       I915_WRITE(TV_H_CTL_1, hctl1);
+       I915_WRITE(TV_H_CTL_2, hctl2);
+       I915_WRITE(TV_H_CTL_3, hctl3);
+       I915_WRITE(TV_V_CTL_1, vctl1);
+       I915_WRITE(TV_V_CTL_2, vctl2);
+       I915_WRITE(TV_V_CTL_3, vctl3);
+       I915_WRITE(TV_V_CTL_4, vctl4);
+       I915_WRITE(TV_V_CTL_5, vctl5);
+       I915_WRITE(TV_V_CTL_6, vctl6);
+       I915_WRITE(TV_V_CTL_7, vctl7);
+}
+
 static void intel_tv_mode_set(struct intel_encoder *encoder)
 {
        struct drm_device *dev = encoder->base.dev;
@@ -942,8 +1001,6 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
        struct intel_tv *intel_tv = enc_to_tv(encoder);
        const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
        u32 tv_ctl;
-       u32 hctl1, hctl2, hctl3;
-       u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
        u32 scctl1, scctl2, scctl3;
        int i, j;
        const struct video_levels *video_levels;
@@ -982,44 +1039,6 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
                burst_ena = tv_mode->burst_ena;
                break;
        }
-       hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
-               (tv_mode->htotal << TV_HTOTAL_SHIFT);
-
-       hctl2 = (tv_mode->hburst_start << 16) |
-               (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
-
-       if (burst_ena)
-               hctl2 |= TV_BURST_ENA;
-
-       hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
-               (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
-
-       vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
-               (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
-               (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
-
-       vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
-               (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
-               (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
-
-       vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
-               (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
-               (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
-
-       if (tv_mode->veq_ena)
-               vctl3 |= TV_EQUAL_ENA;
-
-       vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
-               (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
-
-       vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
-               (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
-
-       vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
-               (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
-
-       vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
-               (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
 
        if (intel_crtc->pipe == 1)
                tv_ctl |= TV_ENC_PIPEB_SELECT;
@@ -1054,16 +1073,8 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
        if (dev->pdev->device < 0x2772)
                tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
 
-       I915_WRITE(TV_H_CTL_1, hctl1);
-       I915_WRITE(TV_H_CTL_2, hctl2);
-       I915_WRITE(TV_H_CTL_3, hctl3);
-       I915_WRITE(TV_V_CTL_1, vctl1);
-       I915_WRITE(TV_V_CTL_2, vctl2);
-       I915_WRITE(TV_V_CTL_3, vctl3);
-       I915_WRITE(TV_V_CTL_4, vctl4);
-       I915_WRITE(TV_V_CTL_5, vctl5);
-       I915_WRITE(TV_V_CTL_6, vctl6);
-       I915_WRITE(TV_V_CTL_7, vctl7);
+       set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
+
        I915_WRITE(TV_SC_CTL_1, scctl1);
        I915_WRITE(TV_SC_CTL_2, scctl2);
        I915_WRITE(TV_SC_CTL_3, scctl3);