projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 41e69778 RC |
1 | Qualcomm adreno/snapdragon hdmi output |
| 2 | ||
| 3 | Required properties: | |
| 4 | - compatible: one of the following | |
| 0afbe59e | 5 | * "qcom,hdmi-tx-8996" |
| 3a84f846 | 6 | * "qcom,hdmi-tx-8994" |
| efbd349a | 7 | * "qcom,hdmi-tx-8084" |
| 5cf3a455 | 8 | * "qcom,hdmi-tx-8974" |
| 41e69778 RC |
9 | * "qcom,hdmi-tx-8660" |
| 10 | * "qcom,hdmi-tx-8960" | |
| 11 | - reg: Physical base address and length of the controller's registers | |
| 12 | - reg-names: "core_physical" | |
| 13 | - interrupts: The interrupt signal from the hdmi block. | |
| f31d12af | 14 | - power-domains: Should be <&mmcc MDSS_GDSC>. |
| 41e69778 RC |
15 | - clocks: device clocks |
| 16 | See ../clocks/clock-bindings.txt for details. | |
| 17 | - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin | |
| 18 | - qcom,hdmi-tx-ddc-data-gpio: ddc data pin | |
| 19 | - qcom,hdmi-tx-hpd-gpio: hpd pin | |
| 20 | - core-vdda-supply: phandle to supply regulator | |
| 21 | - hdmi-mux-supply: phandle to mux regulator | |
| f31d12af AT |
22 | - phys: the phandle for the HDMI PHY device |
| 23 | - phy-names: the name of the corresponding PHY device | |
| 41e69778 RC |
24 | |
| 25 | Optional properties: | |
| 26 | - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin | |
| 27 | - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin | |
| 0afbe59e | 28 | - power-domains: reference to the power domain(s), if available. |
| 865807d0 SV |
29 | - pinctrl-names: the pin control state names; should contain "default" |
| 30 | - pinctrl-0: the default pinctrl state (active) | |
| 31 | - pinctrl-1: the "sleep" pinctrl state | |
| 41e69778 | 32 | |
| f31d12af AT |
33 | HDMI PHY: |
| 34 | Required properties: | |
| 35 | - compatible: Could be the following | |
| 36 | * "qcom,hdmi-phy-8660" | |
| 37 | * "qcom,hdmi-phy-8960" | |
| 38 | * "qcom,hdmi-phy-8974" | |
| 39 | * "qcom,hdmi-phy-8084" | |
| 40 | * "qcom,hdmi-phy-8996" | |
| 41 | - #phy-cells: Number of cells in a PHY specifier; Should be 0. | |
| 42 | - reg: Physical base address and length of the registers of the PHY sub blocks. | |
| 43 | - reg-names: The names of register regions. The following regions are required: | |
| 44 | * "hdmi_phy" | |
| 45 | * "hdmi_pll" | |
| 46 | For HDMI PHY on msm8996, these additional register regions are required: | |
| 47 | * "hdmi_tx_l0" | |
| 48 | * "hdmi_tx_l1" | |
| 49 | * "hdmi_tx_l3" | |
| 50 | * "hdmi_tx_l4" | |
| 51 | - power-domains: Should be <&mmcc MDSS_GDSC>. | |
| 52 | - clocks: device clocks | |
| 53 | See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. | |
| 54 | - core-vdda-supply: phandle to vdda regulator device node | |
| 55 | ||
| 41e69778 RC |
56 | Example: |
| 57 | ||
| 58 | / { | |
| 59 | ... | |
| 60 | ||
| f31d12af | 61 | hdmi: hdmi@4a00000 { |
| 41e69778 RC |
62 | compatible = "qcom,hdmi-tx-8960"; |
| 63 | reg-names = "core_physical"; | |
| f31d12af | 64 | reg = <0x04a00000 0x2f0>; |
| 41e69778 | 65 | interrupts = <GIC_SPI 79 0>; |
| 0afbe59e | 66 | power-domains = <&mmcc MDSS_GDSC>; |
| 41e69778 RC |
67 | clock-names = |
| 68 | "core_clk", | |
| 69 | "master_iface_clk", | |
| 70 | "slave_iface_clk"; | |
| 71 | clocks = | |
| 72 | <&mmcc HDMI_APP_CLK>, | |
| 73 | <&mmcc HDMI_M_AHB_CLK>, | |
| 74 | <&mmcc HDMI_S_AHB_CLK>; | |
| 75 | qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; | |
| 76 | qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; | |
| 77 | qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; | |
| 78 | core-vdda-supply = <&pm8921_hdmi_mvs>; | |
| 79 | hdmi-mux-supply = <&ext_3p3v>; | |
| 865807d0 SV |
80 | pinctrl-names = "default", "sleep"; |
| 81 | pinctrl-0 = <&hpd_active &ddc_active &cec_active>; | |
| 82 | pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; | |
| f31d12af AT |
83 | |
| 84 | phys = <&hdmi_phy>; | |
| 85 | phy-names = "hdmi_phy"; | |
| 86 | }; | |
| 87 | ||
| 88 | hdmi_phy: phy@4a00400 { | |
| 89 | compatible = "qcom,hdmi-phy-8960"; | |
| 90 | reg-names = "hdmi_phy", | |
| 91 | "hdmi_pll"; | |
| 92 | reg = <0x4a00400 0x60>, | |
| 93 | <0x4a00500 0x100>; | |
| 94 | #phy-cells = <0>; | |
| 95 | power-domains = <&mmcc MDSS_GDSC>; | |
| 96 | clock-names = "slave_iface_clk"; | |
| 97 | clocks = <&mmcc HDMI_S_AHB_CLK>; | |
| 98 | core-vdda-supply = <&pm8921_hdmi_mvs>; | |
| 41e69778 RC |
99 | }; |
| 100 | }; |