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perf/x86/intel: Add Haswell PEBS support
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
de0428a7 15
3a632cb2 16#include <asm/cpufeature.h>
de0428a7
KW		 17#include <asm/hardirq.h>
18#include <asm/apic.h>
19
20#include "perf_event.h"
a7e3ed1e 21
f22f54f4 22/*
b622d644 23 * Intel PerfMon, used on Core and later.
f22f54f4 24 */
ec75a716 25static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 26{
c3b7cdf1
PE		 27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 35};
36
5c543e3c 37static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 38{
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
45 EVENT_CONSTRAINT_END
46};
47
5c543e3c 48static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 49{
b622d644
PZ		 50 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
51 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 52 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64};
65
5c543e3c 66static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 67{
b622d644
PZ		 68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 70 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80};
81
5c543e3c 82static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 83{
efc9f05d 84 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 85 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 86 EVENT_EXTRA_END
87};
88
5c543e3c 89static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 90{
b622d644
PZ		 91 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
92 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 93 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 94 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
95 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
96 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 97 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 98 EVENT_CONSTRAINT_END
99};
100
5c543e3c 101static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 102{
103 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
104 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 105 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 106 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
107 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
108 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
109 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 110 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 111 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
112 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 113 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
b06b3d49
LM		 115 EVENT_CONSTRAINT_END
116};
117
69943182
SE		 118static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
119{
120 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
121 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
122 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
123 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
124 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
125 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
126 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
127 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
128 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
129 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
130 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
131 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
741a698f
PZ		 132 /*
133 * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
134 * siblings; disable these events because they can corrupt unrelated
135 * counters.
136 */
137 INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
138 INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
139 INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
140 INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
69943182
SE		 141 EVENT_CONSTRAINT_END
142};
143
5c543e3c 144static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 145{
efc9f05d
SE		 146 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
147 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 148 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 149 EVENT_EXTRA_END
150};
151
0af3ac1f
AK		 152static struct event_constraint intel_v1_event_constraints[] __read_mostly =
153{
154 EVENT_CONSTRAINT_END
155};
156
5c543e3c 157static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 158{
b622d644
PZ		 159 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
160 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 161 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 162 EVENT_CONSTRAINT_END
163};
164
ee89cbc2 165static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
f1923820
SE		 166 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
167 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 168 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 169 EVENT_EXTRA_END
170};
171
172static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
173 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
174 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 175 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 176 EVENT_EXTRA_END
177};
178
f20093ee
SE		 179EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
180EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
9ad64c0f 181EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 182
183struct attribute *nhm_events_attrs[] = {
184 EVENT_PTR(mem_ld_nhm),
185 NULL,
186};
187
188struct attribute *snb_events_attrs[] = {
189 EVENT_PTR(mem_ld_snb),
9ad64c0f 190 EVENT_PTR(mem_st_snb),
f20093ee
SE		 191 NULL,
192};
193
3a632cb2
AK		 194static struct event_constraint intel_hsw_event_constraints[] = {
195 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
196 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
197 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
198 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
199 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
200 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
201 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
202 INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
203 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
204 INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
205 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
206 INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
207 EVENT_CONSTRAINT_END
208};
209
f22f54f4
PZ		 210static u64 intel_pmu_event_map(int hw_event)
211{
212 return intel_perfmon_event_map[hw_event];
213}
214
74e6543f
YZ		 215#define SNB_DMND_DATA_RD (1ULL << 0)
216#define SNB_DMND_RFO (1ULL << 1)
217#define SNB_DMND_IFETCH (1ULL << 2)
218#define SNB_DMND_WB (1ULL << 3)
219#define SNB_PF_DATA_RD (1ULL << 4)
220#define SNB_PF_RFO (1ULL << 5)
221#define SNB_PF_IFETCH (1ULL << 6)
222#define SNB_LLC_DATA_RD (1ULL << 7)
223#define SNB_LLC_RFO (1ULL << 8)
224#define SNB_LLC_IFETCH (1ULL << 9)
225#define SNB_BUS_LOCKS (1ULL << 10)
226#define SNB_STRM_ST (1ULL << 11)
227#define SNB_OTHER (1ULL << 15)
228#define SNB_RESP_ANY (1ULL << 16)
229#define SNB_NO_SUPP (1ULL << 17)
230#define SNB_LLC_HITM (1ULL << 18)
231#define SNB_LLC_HITE (1ULL << 19)
232#define SNB_LLC_HITS (1ULL << 20)
233#define SNB_LLC_HITF (1ULL << 21)
234#define SNB_LOCAL (1ULL << 22)
235#define SNB_REMOTE (0xffULL << 23)
236#define SNB_SNP_NONE (1ULL << 31)
237#define SNB_SNP_NOT_NEEDED (1ULL << 32)
238#define SNB_SNP_MISS (1ULL << 33)
239#define SNB_NO_FWD (1ULL << 34)
240#define SNB_SNP_FWD (1ULL << 35)
241#define SNB_HITM (1ULL << 36)
242#define SNB_NON_DRAM (1ULL << 37)
243
244#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
245#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
246#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
247
248#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
249 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
250 SNB_HITM)
251
252#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
253#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
254
255#define SNB_L3_ACCESS SNB_RESP_ANY
256#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
257
258static __initconst const u64 snb_hw_cache_extra_regs
259 [PERF_COUNT_HW_CACHE_MAX]
260 [PERF_COUNT_HW_CACHE_OP_MAX]
261 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
262{
263 [ C(LL ) ] = {
264 [ C(OP_READ) ] = {
265 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
266 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
267 },
268 [ C(OP_WRITE) ] = {
269 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
270 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
271 },
272 [ C(OP_PREFETCH) ] = {
273 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
274 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
275 },
276 },
277 [ C(NODE) ] = {
278 [ C(OP_READ) ] = {
279 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
280 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
281 },
282 [ C(OP_WRITE) ] = {
283 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
284 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
285 },
286 [ C(OP_PREFETCH) ] = {
287 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
288 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
289 },
290 },
291};
292
b06b3d49
LM		 293static __initconst const u64 snb_hw_cache_event_ids
294 [PERF_COUNT_HW_CACHE_MAX]
295 [PERF_COUNT_HW_CACHE_OP_MAX]
296 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
297{
298 [ C(L1D) ] = {
299 [ C(OP_READ) ] = {
300 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
301 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
302 },
303 [ C(OP_WRITE) ] = {
304 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
305 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
306 },
307 [ C(OP_PREFETCH) ] = {
308 [ C(RESULT_ACCESS) ] = 0x0,
309 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
310 },
311 },
312 [ C(L1I ) ] = {
313 [ C(OP_READ) ] = {
314 [ C(RESULT_ACCESS) ] = 0x0,
315 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
316 },
317 [ C(OP_WRITE) ] = {
318 [ C(RESULT_ACCESS) ] = -1,
319 [ C(RESULT_MISS) ] = -1,
320 },
321 [ C(OP_PREFETCH) ] = {
322 [ C(RESULT_ACCESS) ] = 0x0,
323 [ C(RESULT_MISS) ] = 0x0,
324 },
325 },
326 [ C(LL ) ] = {
b06b3d49 327 [ C(OP_READ) ] = {
63b6a675 328 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 329 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 330 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
331 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 332 },
333 [ C(OP_WRITE) ] = {
63b6a675 334 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 335 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 336 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
337 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 338 },
339 [ C(OP_PREFETCH) ] = {
63b6a675 340 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 341 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 342 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
343 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 344 },
345 },
346 [ C(DTLB) ] = {
347 [ C(OP_READ) ] = {
348 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
349 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
350 },
351 [ C(OP_WRITE) ] = {
352 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
353 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
354 },
355 [ C(OP_PREFETCH) ] = {
356 [ C(RESULT_ACCESS) ] = 0x0,
357 [ C(RESULT_MISS) ] = 0x0,
358 },
359 },
360 [ C(ITLB) ] = {
361 [ C(OP_READ) ] = {
362 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
363 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
364 },
365 [ C(OP_WRITE) ] = {
366 [ C(RESULT_ACCESS) ] = -1,
367 [ C(RESULT_MISS) ] = -1,
368 },
369 [ C(OP_PREFETCH) ] = {
370 [ C(RESULT_ACCESS) ] = -1,
371 [ C(RESULT_MISS) ] = -1,
372 },
373 },
374 [ C(BPU ) ] = {
375 [ C(OP_READ) ] = {
376 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
377 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
378 },
379 [ C(OP_WRITE) ] = {
380 [ C(RESULT_ACCESS) ] = -1,
381 [ C(RESULT_MISS) ] = -1,
382 },
383 [ C(OP_PREFETCH) ] = {
384 [ C(RESULT_ACCESS) ] = -1,
385 [ C(RESULT_MISS) ] = -1,
386 },
387 },
89d6c0b5
PZ		 388 [ C(NODE) ] = {
389 [ C(OP_READ) ] = {
74e6543f
YZ		 390 [ C(RESULT_ACCESS) ] = 0x01b7,
391 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 392 },
393 [ C(OP_WRITE) ] = {
74e6543f
YZ		 394 [ C(RESULT_ACCESS) ] = 0x01b7,
395 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 396 },
397 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 398 [ C(RESULT_ACCESS) ] = 0x01b7,
399 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 400 },
401 },
402
b06b3d49
LM		 403};
404
caaa8be3 405static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 406 [PERF_COUNT_HW_CACHE_MAX]
407 [PERF_COUNT_HW_CACHE_OP_MAX]
408 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
409{
410 [ C(L1D) ] = {
411 [ C(OP_READ) ] = {
412 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
413 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
414 },
415 [ C(OP_WRITE) ] = {
416 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
417 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
418 },
419 [ C(OP_PREFETCH) ] = {
420 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
421 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
422 },
423 },
424 [ C(L1I ) ] = {
425 [ C(OP_READ) ] = {
426 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
427 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
428 },
429 [ C(OP_WRITE) ] = {
430 [ C(RESULT_ACCESS) ] = -1,
431 [ C(RESULT_MISS) ] = -1,
432 },
433 [ C(OP_PREFETCH) ] = {
434 [ C(RESULT_ACCESS) ] = 0x0,
435 [ C(RESULT_MISS) ] = 0x0,
436 },
437 },
438 [ C(LL ) ] = {
439 [ C(OP_READ) ] = {
63b6a675 440 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 441 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 442 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
443 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 444 },
e994d7d2
AK		 445 /*
446 * Use RFO, not WRITEBACK, because a write miss would typically occur
447 * on RFO.
448 */
f22f54f4 449 [ C(OP_WRITE) ] = {
63b6a675
PZ		 450 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
451 [ C(RESULT_ACCESS) ] = 0x01b7,
452 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 453 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 454 },
455 [ C(OP_PREFETCH) ] = {
63b6a675 456 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 457 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 458 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
459 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 460 },
461 },
462 [ C(DTLB) ] = {
463 [ C(OP_READ) ] = {
464 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
465 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
466 },
467 [ C(OP_WRITE) ] = {
468 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
469 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
470 },
471 [ C(OP_PREFETCH) ] = {
472 [ C(RESULT_ACCESS) ] = 0x0,
473 [ C(RESULT_MISS) ] = 0x0,
474 },
475 },
476 [ C(ITLB) ] = {
477 [ C(OP_READ) ] = {
478 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
479 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
480 },
481 [ C(OP_WRITE) ] = {
482 [ C(RESULT_ACCESS) ] = -1,
483 [ C(RESULT_MISS) ] = -1,
484 },
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = -1,
487 [ C(RESULT_MISS) ] = -1,
488 },
489 },
490 [ C(BPU ) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
493 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = -1,
497 [ C(RESULT_MISS) ] = -1,
498 },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = -1,
501 [ C(RESULT_MISS) ] = -1,
502 },
503 },
89d6c0b5
PZ		 504 [ C(NODE) ] = {
505 [ C(OP_READ) ] = {
506 [ C(RESULT_ACCESS) ] = 0x01b7,
507 [ C(RESULT_MISS) ] = 0x01b7,
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = 0x01b7,
511 [ C(RESULT_MISS) ] = 0x01b7,
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = 0x01b7,
515 [ C(RESULT_MISS) ] = 0x01b7,
516 },
517 },
f22f54f4
PZ		 518};
519
e994d7d2 520/*
63b6a675
PZ		 521 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
522 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 523 */
524
63b6a675
PZ		 525#define NHM_DMND_DATA_RD (1 << 0)
526#define NHM_DMND_RFO (1 << 1)
527#define NHM_DMND_IFETCH (1 << 2)
528#define NHM_DMND_WB (1 << 3)
529#define NHM_PF_DATA_RD (1 << 4)
530#define NHM_PF_DATA_RFO (1 << 5)
531#define NHM_PF_IFETCH (1 << 6)
532#define NHM_OFFCORE_OTHER (1 << 7)
533#define NHM_UNCORE_HIT (1 << 8)
534#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
535#define NHM_OTHER_CORE_HITM (1 << 10)
536 /* reserved */
537#define NHM_REMOTE_CACHE_FWD (1 << 12)
538#define NHM_REMOTE_DRAM (1 << 13)
539#define NHM_LOCAL_DRAM (1 << 14)
540#define NHM_NON_DRAM (1 << 15)
541
87e24f4b
PZ		 542#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
543#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 544
545#define NHM_DMND_READ (NHM_DMND_DATA_RD)
546#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
547#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
548
549#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 550#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 551#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 552
553static __initconst const u64 nehalem_hw_cache_extra_regs
554 [PERF_COUNT_HW_CACHE_MAX]
555 [PERF_COUNT_HW_CACHE_OP_MAX]
556 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
557{
558 [ C(LL ) ] = {
559 [ C(OP_READ) ] = {
63b6a675
PZ		 560 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
561 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 562 },
563 [ C(OP_WRITE) ] = {
63b6a675
PZ		 564 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
565 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 566 },
567 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 568 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
569 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 570 },
89d6c0b5
PZ		 571 },
572 [ C(NODE) ] = {
573 [ C(OP_READ) ] = {
87e24f4b
PZ		 574 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
575 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 576 },
577 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 578 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
579 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 580 },
581 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 582 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
583 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 584 },
585 },
e994d7d2
AK		 586};
587
caaa8be3 588static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 589 [PERF_COUNT_HW_CACHE_MAX]
590 [PERF_COUNT_HW_CACHE_OP_MAX]
591 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
592{
593 [ C(L1D) ] = {
594 [ C(OP_READ) ] = {
f4929bd3
PZ		 595 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
596 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 597 },
598 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 599 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
600 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 601 },
602 [ C(OP_PREFETCH) ] = {
603 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
604 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
605 },
606 },
607 [ C(L1I ) ] = {
608 [ C(OP_READ) ] = {
609 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
610 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
611 },
612 [ C(OP_WRITE) ] = {
613 [ C(RESULT_ACCESS) ] = -1,
614 [ C(RESULT_MISS) ] = -1,
615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = 0x0,
618 [ C(RESULT_MISS) ] = 0x0,
619 },
620 },
621 [ C(LL ) ] = {
622 [ C(OP_READ) ] = {
e994d7d2
AK		 623 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
624 [ C(RESULT_ACCESS) ] = 0x01b7,
625 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
626 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 627 },
e994d7d2
AK		 628 /*
629 * Use RFO, not WRITEBACK, because a write miss would typically occur
630 * on RFO.
631 */
f22f54f4 632 [ C(OP_WRITE) ] = {
e994d7d2
AK		 633 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
634 [ C(RESULT_ACCESS) ] = 0x01b7,
635 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
636 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 637 },
638 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 639 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
640 [ C(RESULT_ACCESS) ] = 0x01b7,
641 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
642 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 643 },
644 },
645 [ C(DTLB) ] = {
646 [ C(OP_READ) ] = {
647 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
648 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
649 },
650 [ C(OP_WRITE) ] = {
651 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
652 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
653 },
654 [ C(OP_PREFETCH) ] = {
655 [ C(RESULT_ACCESS) ] = 0x0,
656 [ C(RESULT_MISS) ] = 0x0,
657 },
658 },
659 [ C(ITLB) ] = {
660 [ C(OP_READ) ] = {
661 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
662 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
663 },
664 [ C(OP_WRITE) ] = {
665 [ C(RESULT_ACCESS) ] = -1,
666 [ C(RESULT_MISS) ] = -1,
667 },
668 [ C(OP_PREFETCH) ] = {
669 [ C(RESULT_ACCESS) ] = -1,
670 [ C(RESULT_MISS) ] = -1,
671 },
672 },
673 [ C(BPU ) ] = {
674 [ C(OP_READ) ] = {
675 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
676 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
677 },
678 [ C(OP_WRITE) ] = {
679 [ C(RESULT_ACCESS) ] = -1,
680 [ C(RESULT_MISS) ] = -1,
681 },
682 [ C(OP_PREFETCH) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
685 },
686 },
89d6c0b5
PZ		 687 [ C(NODE) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = 0x01b7,
690 [ C(RESULT_MISS) ] = 0x01b7,
691 },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = 0x01b7,
694 [ C(RESULT_MISS) ] = 0x01b7,
695 },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = 0x01b7,
698 [ C(RESULT_MISS) ] = 0x01b7,
699 },
700 },
f22f54f4
PZ		 701};
702
caaa8be3 703static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 704 [PERF_COUNT_HW_CACHE_MAX]
705 [PERF_COUNT_HW_CACHE_OP_MAX]
706 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
707{
708 [ C(L1D) ] = {
709 [ C(OP_READ) ] = {
710 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
711 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
712 },
713 [ C(OP_WRITE) ] = {
714 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
715 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
716 },
717 [ C(OP_PREFETCH) ] = {
718 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
719 [ C(RESULT_MISS) ] = 0,
720 },
721 },
722 [ C(L1I ) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
725 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = -1,
729 [ C(RESULT_MISS) ] = -1,
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0,
733 [ C(RESULT_MISS) ] = 0,
734 },
735 },
736 [ C(LL ) ] = {
737 [ C(OP_READ) ] = {
738 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
739 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
740 },
741 [ C(OP_WRITE) ] = {
742 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
743 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
744 },
745 [ C(OP_PREFETCH) ] = {
746 [ C(RESULT_ACCESS) ] = 0,
747 [ C(RESULT_MISS) ] = 0,
748 },
749 },
750 [ C(DTLB) ] = {
751 [ C(OP_READ) ] = {
752 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
753 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
754 },
755 [ C(OP_WRITE) ] = {
756 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
757 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
758 },
759 [ C(OP_PREFETCH) ] = {
760 [ C(RESULT_ACCESS) ] = 0,
761 [ C(RESULT_MISS) ] = 0,
762 },
763 },
764 [ C(ITLB) ] = {
765 [ C(OP_READ) ] = {
766 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
767 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
768 },
769 [ C(OP_WRITE) ] = {
770 [ C(RESULT_ACCESS) ] = -1,
771 [ C(RESULT_MISS) ] = -1,
772 },
773 [ C(OP_PREFETCH) ] = {
774 [ C(RESULT_ACCESS) ] = -1,
775 [ C(RESULT_MISS) ] = -1,
776 },
777 },
778 [ C(BPU ) ] = {
779 [ C(OP_READ) ] = {
780 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
781 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
782 },
783 [ C(OP_WRITE) ] = {
784 [ C(RESULT_ACCESS) ] = -1,
785 [ C(RESULT_MISS) ] = -1,
786 },
787 [ C(OP_PREFETCH) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 },
792};
793
caaa8be3 794static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 795 [PERF_COUNT_HW_CACHE_MAX]
796 [PERF_COUNT_HW_CACHE_OP_MAX]
797 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
798{
799 [ C(L1D) ] = {
800 [ C(OP_READ) ] = {
801 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
802 [ C(RESULT_MISS) ] = 0,
803 },
804 [ C(OP_WRITE) ] = {
805 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
806 [ C(RESULT_MISS) ] = 0,
807 },
808 [ C(OP_PREFETCH) ] = {
809 [ C(RESULT_ACCESS) ] = 0x0,
810 [ C(RESULT_MISS) ] = 0,
811 },
812 },
813 [ C(L1I ) ] = {
814 [ C(OP_READ) ] = {
815 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
816 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
817 },
818 [ C(OP_WRITE) ] = {
819 [ C(RESULT_ACCESS) ] = -1,
820 [ C(RESULT_MISS) ] = -1,
821 },
822 [ C(OP_PREFETCH) ] = {
823 [ C(RESULT_ACCESS) ] = 0,
824 [ C(RESULT_MISS) ] = 0,
825 },
826 },
827 [ C(LL ) ] = {
828 [ C(OP_READ) ] = {
829 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
830 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
831 },
832 [ C(OP_WRITE) ] = {
833 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
834 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
835 },
836 [ C(OP_PREFETCH) ] = {
837 [ C(RESULT_ACCESS) ] = 0,
838 [ C(RESULT_MISS) ] = 0,
839 },
840 },
841 [ C(DTLB) ] = {
842 [ C(OP_READ) ] = {
843 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
844 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
845 },
846 [ C(OP_WRITE) ] = {
847 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
848 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
849 },
850 [ C(OP_PREFETCH) ] = {
851 [ C(RESULT_ACCESS) ] = 0,
852 [ C(RESULT_MISS) ] = 0,
853 },
854 },
855 [ C(ITLB) ] = {
856 [ C(OP_READ) ] = {
857 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
858 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
859 },
860 [ C(OP_WRITE) ] = {
861 [ C(RESULT_ACCESS) ] = -1,
862 [ C(RESULT_MISS) ] = -1,
863 },
864 [ C(OP_PREFETCH) ] = {
865 [ C(RESULT_ACCESS) ] = -1,
866 [ C(RESULT_MISS) ] = -1,
867 },
868 },
869 [ C(BPU ) ] = {
870 [ C(OP_READ) ] = {
871 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
872 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
873 },
874 [ C(OP_WRITE) ] = {
875 [ C(RESULT_ACCESS) ] = -1,
876 [ C(RESULT_MISS) ] = -1,
877 },
878 [ C(OP_PREFETCH) ] = {
879 [ C(RESULT_ACCESS) ] = -1,
880 [ C(RESULT_MISS) ] = -1,
881 },
882 },
883};
884
60ce0fbd
SE		 885static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
886{
887 /* user explicitly requested branch sampling */
888 if (has_branch_stack(event))
889 return true;
890
891 /* implicit branch sampling to correct PEBS skid */
3044318f
AK		 892 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
893 x86_pmu.intel_cap.pebs_format < 2)
60ce0fbd
SE		 894 return true;
895
896 return false;
897}
898
f22f54f4
PZ		 899static void intel_pmu_disable_all(void)
900{
901 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
902
903 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
904
15c7ad51 905 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 906 intel_pmu_disable_bts();
ca037701
PZ		 907
908 intel_pmu_pebs_disable_all();
caff2bef 909 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 910}
911
11164cd4 912static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 913{
914 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
915
d329527e
PZ		 916 intel_pmu_pebs_enable_all();
917 intel_pmu_lbr_enable_all();
144d31e6
GN		 918 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
919 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 920
15c7ad51 921 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 922 struct perf_event *event =
15c7ad51 923 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 924
925 if (WARN_ON_ONCE(!event))
926 return;
927
928 intel_pmu_enable_bts(event->hw.config);
929 }
930}
931
11164cd4
PZ		 932/*
933 * Workaround for:
934 * Intel Errata AAK100 (model 26)
935 * Intel Errata AAP53 (model 30)
40b91cd1 936 * Intel Errata BD53 (model 44)
11164cd4 937 *
351af072
ZY		 938 * The official story:
939 * These chips need to be 'reset' when adding counters by programming the
940 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
941 * in sequence on the same PMC or on different PMCs.
942 *
943 * In practise it appears some of these events do in fact count, and
944 * we need to programm all 4 events.
11164cd4 945 */
351af072 946static void intel_pmu_nhm_workaround(void)
11164cd4 947{
351af072
ZY		 948 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
949 static const unsigned long nhm_magic[4] = {
950 0x4300B5,
951 0x4300D2,
952 0x4300B1,
953 0x4300B1
954 };
955 struct perf_event *event;
956 int i;
11164cd4 957
351af072
ZY		 958 /*
959 * The Errata requires below steps:
960 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
961 * 2) Configure 4 PERFEVTSELx with the magic events and clear
962 * the corresponding PMCx;
963 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
964 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
965 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
966 */
11164cd4 967
351af072
ZY		 968 /*
969 * The real steps we choose are a little different from above.
970 * A) To reduce MSR operations, we don't run step 1) as they
971 * are already cleared before this function is called;
972 * B) Call x86_perf_event_update to save PMCx before configuring
973 * PERFEVTSELx with magic number;
974 * C) With step 5), we do clear only when the PERFEVTSELx is
975 * not used currently.
976 * D) Call x86_perf_event_set_period to restore PMCx;
977 */
11164cd4 978
351af072
ZY		 979 /* We always operate 4 pairs of PERF Counters */
980 for (i = 0; i < 4; i++) {
981 event = cpuc->events[i];
982 if (event)
983 x86_perf_event_update(event);
984 }
11164cd4 985
351af072
ZY		 986 for (i = 0; i < 4; i++) {
987 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
988 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
989 }
990
991 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
992 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 993
351af072
ZY		 994 for (i = 0; i < 4; i++) {
995 event = cpuc->events[i];
996
997 if (event) {
998 x86_perf_event_set_period(event);
31fa58af 999 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1000 ARCH_PERFMON_EVENTSEL_ENABLE);
1001 } else
1002 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1003 }
351af072
ZY		 1004}
1005
1006static void intel_pmu_nhm_enable_all(int added)
1007{
1008 if (added)
1009 intel_pmu_nhm_workaround();
11164cd4
PZ		 1010 intel_pmu_enable_all(added);
1011}
1012
f22f54f4
PZ		 1013static inline u64 intel_pmu_get_status(void)
1014{
1015 u64 status;
1016
1017 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1018
1019 return status;
1020}
1021
1022static inline void intel_pmu_ack_status(u64 ack)
1023{
1024 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1025}
1026
ca037701 1027static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1028{
15c7ad51 1029 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1030 u64 ctrl_val, mask;
1031
1032 mask = 0xfULL << (idx * 4);
1033
1034 rdmsrl(hwc->config_base, ctrl_val);
1035 ctrl_val &= ~mask;
7645a24c 1036 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1037}
1038
ca037701 1039static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1040{
aff3d91a 1041 struct hw_perf_event *hwc = &event->hw;
144d31e6 1042 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1043
15c7ad51 1044 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1045 intel_pmu_disable_bts();
1046 intel_pmu_drain_bts_buffer();
1047 return;
1048 }
1049
144d31e6
GN		 1050 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1051 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1052
60ce0fbd
SE		 1053 /*
1054 * must disable before any actual event
1055 * because any event may be combined with LBR
1056 */
1057 if (intel_pmu_needs_lbr_smpl(event))
1058 intel_pmu_lbr_disable(event);
1059
f22f54f4 1060 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1061 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1062 return;
1063 }
1064
aff3d91a 1065 x86_pmu_disable_event(event);
ca037701 1066
ab608344 1067 if (unlikely(event->attr.precise_ip))
ef21f683 1068 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1069}
1070
ca037701 1071static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1072{
15c7ad51 1073 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1074 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1075
1076 /*
1077 * Enable IRQ generation (0x8),
1078 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1079 * if requested:
1080 */
1081 bits = 0x8ULL;
1082 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1083 bits |= 0x2;
1084 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1085 bits |= 0x1;
1086
1087 /*
1088 * ANY bit is supported in v3 and up
1089 */
1090 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1091 bits |= 0x4;
1092
1093 bits <<= (idx * 4);
1094 mask = 0xfULL << (idx * 4);
1095
1096 rdmsrl(hwc->config_base, ctrl_val);
1097 ctrl_val &= ~mask;
1098 ctrl_val |= bits;
7645a24c 1099 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1100}
1101
aff3d91a 1102static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1103{
aff3d91a 1104 struct hw_perf_event *hwc = &event->hw;
144d31e6 1105 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1106
15c7ad51 1107 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1108 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1109 return;
1110
1111 intel_pmu_enable_bts(hwc->config);
1112 return;
1113 }
60ce0fbd
SE		 1114 /*
1115 * must enabled before any actual event
1116 * because any event may be combined with LBR
1117 */
1118 if (intel_pmu_needs_lbr_smpl(event))
1119 intel_pmu_lbr_enable(event);
f22f54f4 1120
144d31e6
GN		 1121 if (event->attr.exclude_host)
1122 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1123 if (event->attr.exclude_guest)
1124 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1125
f22f54f4 1126 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1127 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1128 return;
1129 }
1130
ab608344 1131 if (unlikely(event->attr.precise_ip))
ef21f683 1132 intel_pmu_pebs_enable(event);
ca037701 1133
31fa58af 1134 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1135}
1136
1137/*
1138 * Save and restart an expired event. Called by NMI contexts,
1139 * so it has to be careful about preempting normal event ops:
1140 */
de0428a7 1141int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1142{
cc2ad4ba
PZ		 1143 x86_perf_event_update(event);
1144 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1145}
1146
1147static void intel_pmu_reset(void)
1148{
0a3aee0d 1149 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1150 unsigned long flags;
1151 int idx;
1152
948b1bb8 1153 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1154 return;
1155
1156 local_irq_save(flags);
1157
c767a54b 1158 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1159
948b1bb8 1160 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1161 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1162 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1163 }
948b1bb8 1164 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1165 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1166
f22f54f4
PZ		 1167 if (ds)
1168 ds->bts_index = ds->bts_buffer_base;
1169
1170 local_irq_restore(flags);
1171}
1172
1173/*
1174 * This handler is triggered by the local APIC, so the APIC IRQ handling
1175 * rules apply:
1176 */
1177static int intel_pmu_handle_irq(struct pt_regs *regs)
1178{
1179 struct perf_sample_data data;
1180 struct cpu_hw_events *cpuc;
1181 int bit, loops;
2e556b5b 1182 u64 status;
b0b2072d 1183 int handled;
f22f54f4 1184
f22f54f4
PZ		 1185 cpuc = &__get_cpu_var(cpu_hw_events);
1186
2bce5dac
DZ		 1187 /*
1188 * Some chipsets need to unmask the LVTPC in a particular spot
1189 * inside the nmi handler. As a result, the unmasking was pushed
1190 * into all the nmi handlers.
1191 *
1192 * This handler doesn't seem to have any issues with the unmasking
1193 * so it was left at the top.
1194 */
1195 apic_write(APIC_LVTPC, APIC_DM_NMI);
1196
3fb2b8dd 1197 intel_pmu_disable_all();
b0b2072d 1198 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 1199 status = intel_pmu_get_status();
1200 if (!status) {
11164cd4 1201 intel_pmu_enable_all(0);
b0b2072d 1202 return handled;
f22f54f4
PZ		 1203 }
1204
1205 loops = 0;
1206again:
2e556b5b 1207 intel_pmu_ack_status(status);
f22f54f4 1208 if (++loops > 100) {
ae0def05
DH		 1209 static bool warned = false;
1210 if (!warned) {
1211 WARN(1, "perfevents: irq loop stuck!\n");
1212 perf_event_print_debug();
1213 warned = true;
1214 }
f22f54f4 1215 intel_pmu_reset();
3fb2b8dd 1216 goto done;
f22f54f4
PZ		 1217 }
1218
1219 inc_irq_stat(apic_perf_irqs);
ca037701 1220
caff2bef
PZ		 1221 intel_pmu_lbr_read();
1222
ca037701
PZ		 1223 /*
1224 * PEBS overflow sets bit 62 in the global status register
1225 */
de725dec
PZ		 1226 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1227 handled++;
ca037701 1228 x86_pmu.drain_pebs(regs);
de725dec 1229 }
ca037701 1230
984b3f57 1231 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1232 struct perf_event *event = cpuc->events[bit];
1233
de725dec
PZ		 1234 handled++;
1235
f22f54f4
PZ		 1236 if (!test_bit(bit, cpuc->active_mask))
1237 continue;
1238
1239 if (!intel_pmu_save_and_restart(event))
1240 continue;
1241
fd0d000b 1242 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1243
60ce0fbd
SE		 1244 if (has_branch_stack(event))
1245 data.br_stack = &cpuc->lbr_stack;
1246
a8b0ca17 1247 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1248 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1249 }
1250
f22f54f4
PZ		 1251 /*
1252 * Repeat if there is more work to be done:
1253 */
1254 status = intel_pmu_get_status();
1255 if (status)
1256 goto again;
1257
3fb2b8dd 1258done:
11164cd4 1259 intel_pmu_enable_all(0);
de725dec 1260 return handled;
f22f54f4
PZ		 1261}
1262
f22f54f4 1263static struct event_constraint *
ca037701 1264intel_bts_constraints(struct perf_event *event)
f22f54f4 1265{
ca037701
PZ		 1266 struct hw_perf_event *hwc = &event->hw;
1267 unsigned int hw_event, bts_event;
f22f54f4 1268
18a073a3
PZ		 1269 if (event->attr.freq)
1270 return NULL;
1271
ca037701
PZ		 1272 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1273 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1274
ca037701 1275 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1276 return &bts_constraint;
ca037701 1277
f22f54f4
PZ		 1278 return NULL;
1279}
1280
5a425294 1281static int intel_alt_er(int idx)
b79e8941
PZ		 1282{
1283 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
5a425294 1284 return idx;
b79e8941 1285
5a425294
PZ		 1286 if (idx == EXTRA_REG_RSP_0)
1287 return EXTRA_REG_RSP_1;
1288
1289 if (idx == EXTRA_REG_RSP_1)
1290 return EXTRA_REG_RSP_0;
1291
1292 return idx;
1293}
1294
1295static void intel_fixup_er(struct perf_event *event, int idx)
1296{
1297 event->hw.extra_reg.idx = idx;
1298
1299 if (idx == EXTRA_REG_RSP_0) {
b79e8941
PZ		 1300 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1301 event->hw.config |= 0x01b7;
b79e8941 1302 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1303 } else if (idx == EXTRA_REG_RSP_1) {
1304 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1305 event->hw.config |= 0x01bb;
1306 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1307 }
b79e8941
PZ		 1308}
1309
efc9f05d
SE		 1310/*
1311 * manage allocation of shared extra msr for certain events
1312 *
1313 * sharing can be:
1314 * per-cpu: to be shared between the various events on a single PMU
1315 * per-core: per-cpu + shared by HT threads
1316 */
a7e3ed1e 1317static struct event_constraint *
efc9f05d 1318__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1319 struct perf_event *event,
1320 struct hw_perf_event_extra *reg)
a7e3ed1e 1321{
efc9f05d 1322 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1323 struct er_account *era;
cd8a38d3 1324 unsigned long flags;
5a425294 1325 int idx = reg->idx;
a7e3ed1e 1326
5a425294
PZ		 1327 /*
1328 * reg->alloc can be set due to existing state, so for fake cpuc we
1329 * need to ignore this, otherwise we might fail to allocate proper fake
1330 * state for this extra reg constraint. Also see the comment below.
1331 */
1332 if (reg->alloc && !cpuc->is_fake)
b36817e8 1333 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1334
b79e8941 1335again:
5a425294 1336 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1337 /*
1338 * we use spin_lock_irqsave() to avoid lockdep issues when
1339 * passing a fake cpuc
1340 */
1341 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1342
1343 if (!atomic_read(&era->ref) || era->config == reg->config) {
1344
5a425294
PZ		 1345 /*
1346 * If its a fake cpuc -- as per validate_{group,event}() we
1347 * shouldn't touch event state and we can avoid doing so
1348 * since both will only call get_event_constraints() once
1349 * on each event, this avoids the need for reg->alloc.
1350 *
1351 * Not doing the ER fixup will only result in era->reg being
1352 * wrong, but since we won't actually try and program hardware
1353 * this isn't a problem either.
1354 */
1355 if (!cpuc->is_fake) {
1356 if (idx != reg->idx)
1357 intel_fixup_er(event, idx);
1358
1359 /*
1360 * x86_schedule_events() can call get_event_constraints()
1361 * multiple times on events in the case of incremental
1362 * scheduling(). reg->alloc ensures we only do the ER
1363 * allocation once.
1364 */
1365 reg->alloc = 1;
1366 }
1367
efc9f05d
SE		 1368 /* lock in msr value */
1369 era->config = reg->config;
1370 era->reg = reg->reg;
1371
1372 /* one more user */
1373 atomic_inc(&era->ref);
1374
a7e3ed1e 1375 /*
b36817e8
SE		 1376 * need to call x86_get_event_constraint()
1377 * to check if associated event has constraints
a7e3ed1e 1378 */
b36817e8 1379 c = NULL;
5a425294
PZ		 1380 } else {
1381 idx = intel_alt_er(idx);
1382 if (idx != reg->idx) {
1383 raw_spin_unlock_irqrestore(&era->lock, flags);
1384 goto again;
1385 }
a7e3ed1e 1386 }
cd8a38d3 1387 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1388
efc9f05d
SE		 1389 return c;
1390}
1391
1392static void
1393__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1394 struct hw_perf_event_extra *reg)
1395{
1396 struct er_account *era;
1397
1398 /*
5a425294
PZ		 1399 * Only put constraint if extra reg was actually allocated. Also takes
1400 * care of event which do not use an extra shared reg.
1401 *
1402 * Also, if this is a fake cpuc we shouldn't touch any event state
1403 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1404 * either since it'll be thrown out.
efc9f05d 1405 */
5a425294 1406 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1407 return;
1408
1409 era = &cpuc->shared_regs->regs[reg->idx];
1410
1411 /* one fewer user */
1412 atomic_dec(&era->ref);
1413
1414 /* allocate again next time */
1415 reg->alloc = 0;
1416}
1417
1418static struct event_constraint *
1419intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1420 struct perf_event *event)
1421{
b36817e8
SE		 1422 struct event_constraint *c = NULL, *d;
1423 struct hw_perf_event_extra *xreg, *breg;
1424
1425 xreg = &event->hw.extra_reg;
1426 if (xreg->idx != EXTRA_REG_NONE) {
1427 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1428 if (c == &emptyconstraint)
1429 return c;
1430 }
1431 breg = &event->hw.branch_reg;
1432 if (breg->idx != EXTRA_REG_NONE) {
1433 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1434 if (d == &emptyconstraint) {
1435 __intel_shared_reg_put_constraints(cpuc, xreg);
1436 c = d;
1437 }
1438 }
efc9f05d 1439 return c;
a7e3ed1e
AK		 1440}
1441
de0428a7
KW		 1442struct event_constraint *
1443x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1444{
1445 struct event_constraint *c;
1446
1447 if (x86_pmu.event_constraints) {
1448 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3
SE		 1449 if ((event->hw.config & c->cmask) == c->code) {
1450 /* hw.flags zeroed at initialization */
1451 event->hw.flags |= c->flags;
de0428a7 1452 return c;
9fac2cf3 1453 }
de0428a7
KW		 1454 }
1455 }
1456
1457 return &unconstrained;
1458}
1459
f22f54f4
PZ		 1460static struct event_constraint *
1461intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1462{
1463 struct event_constraint *c;
1464
ca037701
PZ		 1465 c = intel_bts_constraints(event);
1466 if (c)
1467 return c;
1468
1469 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1470 if (c)
1471 return c;
1472
efc9f05d 1473 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1474 if (c)
1475 return c;
1476
f22f54f4
PZ		 1477 return x86_get_event_constraints(cpuc, event);
1478}
1479
efc9f05d
SE		 1480static void
1481intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1482 struct perf_event *event)
1483{
efc9f05d 1484 struct hw_perf_event_extra *reg;
a7e3ed1e 1485
efc9f05d
SE		 1486 reg = &event->hw.extra_reg;
1487 if (reg->idx != EXTRA_REG_NONE)
1488 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 1489
1490 reg = &event->hw.branch_reg;
1491 if (reg->idx != EXTRA_REG_NONE)
1492 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 1493}
a7e3ed1e 1494
efc9f05d
SE		 1495static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1496 struct perf_event *event)
1497{
9fac2cf3 1498 event->hw.flags = 0;
efc9f05d 1499 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1500}
1501
0780c927 1502static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 1503{
0780c927 1504 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 1505 /*
1506 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1507 * (0x003c) so that we can use it with PEBS.
1508 *
1509 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1510 * PEBS capable. However we can use INST_RETIRED.ANY_P
1511 * (0x00c0), which is a PEBS capable event, to get the same
1512 * count.
1513 *
1514 * INST_RETIRED.ANY_P counts the number of cycles that retires
1515 * CNTMASK instructions. By setting CNTMASK to a value (16)
1516 * larger than the maximum number of instructions that can be
1517 * retired per cycle (4) and then inverting the condition, we
1518 * count all cycles that retire 16 or less instructions, which
1519 * is every cycle.
1520 *
1521 * Thereby we gain a PEBS capable cycle counter.
1522 */
f9b4eeb8
PZ		 1523 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1524
0780c927
PZ		 1525 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1526 event->hw.config = alt_config;
1527 }
1528}
1529
1530static void intel_pebs_aliases_snb(struct perf_event *event)
1531{
1532 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1533 /*
1534 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1535 * (0x003c) so that we can use it with PEBS.
1536 *
1537 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1538 * PEBS capable. However we can use UOPS_RETIRED.ALL
1539 * (0x01c2), which is a PEBS capable event, to get the same
1540 * count.
1541 *
1542 * UOPS_RETIRED.ALL counts the number of cycles that retires
1543 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1544 * larger than the maximum number of micro-ops that can be
1545 * retired per cycle (4) and then inverting the condition, we
1546 * count all cycles that retire 16 or less micro-ops, which
1547 * is every cycle.
1548 *
1549 * Thereby we gain a PEBS capable cycle counter.
1550 */
1551 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 1552
1553 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1554 event->hw.config = alt_config;
1555 }
0780c927
PZ		 1556}
1557
1558static int intel_pmu_hw_config(struct perf_event *event)
1559{
1560 int ret = x86_pmu_hw_config(event);
1561
1562 if (ret)
1563 return ret;
1564
1565 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1566 x86_pmu.pebs_aliases(event);
7639dae0 1567
60ce0fbd
SE		 1568 if (intel_pmu_needs_lbr_smpl(event)) {
1569 ret = intel_pmu_setup_lbr_filter(event);
1570 if (ret)
1571 return ret;
1572 }
1573
b4cdc5c2
PZ		 1574 if (event->attr.type != PERF_TYPE_RAW)
1575 return 0;
1576
1577 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1578 return 0;
1579
1580 if (x86_pmu.version < 3)
1581 return -EINVAL;
1582
1583 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1584 return -EACCES;
1585
1586 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1587
1588 return 0;
1589}
1590
144d31e6
GN		 1591struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1592{
1593 if (x86_pmu.guest_get_msrs)
1594 return x86_pmu.guest_get_msrs(nr);
1595 *nr = 0;
1596 return NULL;
1597}
1598EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1599
1600static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1601{
1602 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1603 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1604
1605 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1606 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1607 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 1608 /*
1609 * If PMU counter has PEBS enabled it is not enough to disable counter
1610 * on a guest entry since PEBS memory write can overshoot guest entry
1611 * and corrupt guest memory. Disabling PEBS solves the problem.
1612 */
1613 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1614 arr[1].host = cpuc->pebs_enabled;
1615 arr[1].guest = 0;
144d31e6 1616
26a4f3c0 1617 *nr = 2;
144d31e6
GN		 1618 return arr;
1619}
1620
1621static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1622{
1623 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1624 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1625 int idx;
1626
1627 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1628 struct perf_event *event = cpuc->events[idx];
1629
1630 arr[idx].msr = x86_pmu_config_addr(idx);
1631 arr[idx].host = arr[idx].guest = 0;
1632
1633 if (!test_bit(idx, cpuc->active_mask))
1634 continue;
1635
1636 arr[idx].host = arr[idx].guest =
1637 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1638
1639 if (event->attr.exclude_host)
1640 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1641 else if (event->attr.exclude_guest)
1642 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1643 }
1644
1645 *nr = x86_pmu.num_counters;
1646 return arr;
1647}
1648
1649static void core_pmu_enable_event(struct perf_event *event)
1650{
1651 if (!event->attr.exclude_host)
1652 x86_pmu_enable_event(event);
1653}
1654
1655static void core_pmu_enable_all(int added)
1656{
1657 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1658 int idx;
1659
1660 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1661 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1662
1663 if (!test_bit(idx, cpuc->active_mask) ||
1664 cpuc->events[idx]->attr.exclude_host)
1665 continue;
1666
1667 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1668 }
1669}
1670
3a632cb2
AK		 1671static int hsw_hw_config(struct perf_event *event)
1672{
1673 int ret = intel_pmu_hw_config(event);
1674
1675 if (ret)
1676 return ret;
1677 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
1678 return 0;
1679 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
1680
1681 /*
1682 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
1683 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
1684 * this combination.
1685 */
1686 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
1687 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
1688 event->attr.precise_ip > 0))
1689 return -EOPNOTSUPP;
1690
1691 return 0;
1692}
1693
1694static struct event_constraint counter2_constraint =
1695 EVENT_CONSTRAINT(0, 0x4, 0);
1696
1697static struct event_constraint *
1698hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1699{
1700 struct event_constraint *c = intel_get_event_constraints(cpuc, event);
1701
1702 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
1703 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
1704 if (c->idxmsk64 & (1U << 2))
1705 return &counter2_constraint;
1706 return &emptyconstraint;
1707 }
1708
1709 return c;
1710}
1711
641cc938
JO		 1712PMU_FORMAT_ATTR(event, "config:0-7" );
1713PMU_FORMAT_ATTR(umask, "config:8-15" );
1714PMU_FORMAT_ATTR(edge, "config:18" );
1715PMU_FORMAT_ATTR(pc, "config:19" );
1716PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1717PMU_FORMAT_ATTR(inv, "config:23" );
1718PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 1719PMU_FORMAT_ATTR(in_tx, "config:32");
1720PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 1721
1722static struct attribute *intel_arch_formats_attr[] = {
1723 &format_attr_event.attr,
1724 &format_attr_umask.attr,
1725 &format_attr_edge.attr,
1726 &format_attr_pc.attr,
1727 &format_attr_inv.attr,
1728 &format_attr_cmask.attr,
1729 NULL,
1730};
1731
0bf79d44
JO		 1732ssize_t intel_event_sysfs_show(char *page, u64 config)
1733{
1734 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1735
1736 return x86_event_sysfs_show(page, config, event);
1737}
1738
caaa8be3 1739static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1740 .name = "core",
1741 .handle_irq = x86_pmu_handle_irq,
1742 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 1743 .enable_all = core_pmu_enable_all,
1744 .enable = core_pmu_enable_event,
f22f54f4 1745 .disable = x86_pmu_disable_event,
b4cdc5c2 1746 .hw_config = x86_pmu_hw_config,
a072738e 1747 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1748 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1749 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1750 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1751 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1752 .apic = 1,
1753 /*
1754 * Intel PMCs cannot be accessed sanely above 32 bit width,
1755 * so we install an artificial 1<<31 period regardless of
1756 * the generic event period:
1757 */
1758 .max_period = (1ULL << 31) - 1,
1759 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1760 .put_event_constraints = intel_put_event_constraints,
f22f54f4 1761 .event_constraints = intel_core_event_constraints,
144d31e6 1762 .guest_get_msrs = core_guest_get_msrs,
641cc938 1763 .format_attrs = intel_arch_formats_attr,
0bf79d44 1764 .events_sysfs_show = intel_event_sysfs_show,
f22f54f4
PZ		 1765};
1766
de0428a7 1767struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 1768{
1769 struct intel_shared_regs *regs;
1770 int i;
1771
1772 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1773 GFP_KERNEL, cpu_to_node(cpu));
1774 if (regs) {
1775 /*
1776 * initialize the locks to keep lockdep happy
1777 */
1778 for (i = 0; i < EXTRA_REG_MAX; i++)
1779 raw_spin_lock_init(&regs->regs[i].lock);
1780
1781 regs->core_id = -1;
1782 }
1783 return regs;
1784}
1785
a7e3ed1e
AK		 1786static int intel_pmu_cpu_prepare(int cpu)
1787{
1788 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1789
b36817e8 1790 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
69092624
LM		 1791 return NOTIFY_OK;
1792
efc9f05d
SE		 1793 cpuc->shared_regs = allocate_shared_regs(cpu);
1794 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1795 return NOTIFY_BAD;
1796
a7e3ed1e
AK		 1797 return NOTIFY_OK;
1798}
1799
74846d35
PZ		 1800static void intel_pmu_cpu_starting(int cpu)
1801{
a7e3ed1e
AK		 1802 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1803 int core_id = topology_core_id(cpu);
1804 int i;
1805
69092624
LM		 1806 init_debug_store_on_cpu(cpu);
1807 /*
1808 * Deal with CPUs that don't clear their LBRs on power-up.
1809 */
1810 intel_pmu_lbr_reset();
1811
b36817e8
SE		 1812 cpuc->lbr_sel = NULL;
1813
1814 if (!cpuc->shared_regs)
69092624
LM		 1815 return;
1816
b36817e8
SE		 1817 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1818 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1819 struct intel_shared_regs *pc;
a7e3ed1e 1820
b36817e8
SE		 1821 pc = per_cpu(cpu_hw_events, i).shared_regs;
1822 if (pc && pc->core_id == core_id) {
1823 cpuc->kfree_on_online = cpuc->shared_regs;
1824 cpuc->shared_regs = pc;
1825 break;
1826 }
a7e3ed1e 1827 }
b36817e8
SE		 1828 cpuc->shared_regs->core_id = core_id;
1829 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 1830 }
1831
b36817e8
SE		 1832 if (x86_pmu.lbr_sel_map)
1833 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
74846d35
PZ		 1834}
1835
1836static void intel_pmu_cpu_dying(int cpu)
1837{
a7e3ed1e 1838 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 1839 struct intel_shared_regs *pc;
a7e3ed1e 1840
efc9f05d 1841 pc = cpuc->shared_regs;
a7e3ed1e
AK		 1842 if (pc) {
1843 if (pc->core_id == -1 || --pc->refcnt == 0)
1844 kfree(pc);
efc9f05d 1845 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 1846 }
1847
74846d35
PZ		 1848 fini_debug_store_on_cpu(cpu);
1849}
1850
d010b332
SE		 1851static void intel_pmu_flush_branch_stack(void)
1852{
1853 /*
1854 * Intel LBR does not tag entries with the
1855 * PID of the current task, then we need to
1856 * flush it on ctxsw
1857 * For now, we simply reset it
1858 */
1859 if (x86_pmu.lbr_nr)
1860 intel_pmu_lbr_reset();
1861}
1862
641cc938
JO		 1863PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1864
a63fcab4
SE		 1865PMU_FORMAT_ATTR(ldlat, "config1:0-15");
1866
641cc938
JO		 1867static struct attribute *intel_arch3_formats_attr[] = {
1868 &format_attr_event.attr,
1869 &format_attr_umask.attr,
1870 &format_attr_edge.attr,
1871 &format_attr_pc.attr,
1872 &format_attr_any.attr,
1873 &format_attr_inv.attr,
1874 &format_attr_cmask.attr,
3a632cb2
AK		 1875 &format_attr_in_tx.attr,
1876 &format_attr_in_tx_cp.attr,
641cc938
JO		 1877
1878 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 1879 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 1880 NULL,
1881};
1882
caaa8be3 1883static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 1884 .name = "Intel",
1885 .handle_irq = intel_pmu_handle_irq,
1886 .disable_all = intel_pmu_disable_all,
1887 .enable_all = intel_pmu_enable_all,
1888 .enable = intel_pmu_enable_event,
1889 .disable = intel_pmu_disable_event,
b4cdc5c2 1890 .hw_config = intel_pmu_hw_config,
a072738e 1891 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1892 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1893 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1894 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1895 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1896 .apic = 1,
1897 /*
1898 * Intel PMCs cannot be accessed sanely above 32 bit width,
1899 * so we install an artificial 1<<31 period regardless of
1900 * the generic event period:
1901 */
1902 .max_period = (1ULL << 31) - 1,
3f6da390 1903 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1904 .put_event_constraints = intel_put_event_constraints,
0780c927 1905 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 1906
641cc938 1907 .format_attrs = intel_arch3_formats_attr,
0bf79d44 1908 .events_sysfs_show = intel_event_sysfs_show,
641cc938 1909
a7e3ed1e 1910 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 1911 .cpu_starting = intel_pmu_cpu_starting,
1912 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 1913 .guest_get_msrs = intel_guest_get_msrs,
d010b332 1914 .flush_branch_stack = intel_pmu_flush_branch_stack,
f22f54f4
PZ		 1915};
1916
c1d6f42f 1917static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 1918{
1919 /*
1920 * PEBS is unreliable due to:
1921 *
1922 * AJ67 - PEBS may experience CPL leaks
1923 * AJ68 - PEBS PMI may be delayed by one event
1924 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1925 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1926 *
1927 * AJ67 could be worked around by restricting the OS/USR flags.
1928 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1929 *
1930 * AJ106 could possibly be worked around by not allowing LBR
1931 * usage from PEBS, including the fixup.
1932 * AJ68 could possibly be worked around by always programming
ec75a716 1933 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 1934 *
1935 * But taken together it might just make sense to not enable PEBS on
1936 * these chips.
1937 */
c767a54b 1938 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 1939 x86_pmu.pebs = 0;
1940 x86_pmu.pebs_constraints = NULL;
1941}
1942
c93dc84c
PZ		 1943static int intel_snb_pebs_broken(int cpu)
1944{
1945 u32 rev = UINT_MAX; /* default to broken for unknown models */
1946
1947 switch (cpu_data(cpu).x86_model) {
1948 case 42: /* SNB */
1949 rev = 0x28;
1950 break;
1951
1952 case 45: /* SNB-EP */
1953 switch (cpu_data(cpu).x86_mask) {
1954 case 6: rev = 0x618; break;
1955 case 7: rev = 0x70c; break;
1956 }
1957 }
1958
1959 return (cpu_data(cpu).microcode < rev);
1960}
1961
1962static void intel_snb_check_microcode(void)
1963{
1964 int pebs_broken = 0;
1965 int cpu;
1966
1967 get_online_cpus();
1968 for_each_online_cpu(cpu) {
1969 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1970 break;
1971 }
1972 put_online_cpus();
1973
1974 if (pebs_broken == x86_pmu.pebs_broken)
1975 return;
1976
1977 /*
1978 * Serialized by the microcode lock..
1979 */
1980 if (x86_pmu.pebs_broken) {
1981 pr_info("PEBS enabled due to microcode update\n");
1982 x86_pmu.pebs_broken = 0;
1983 } else {
1984 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1985 x86_pmu.pebs_broken = 1;
1986 }
1987}
1988
c1d6f42f 1989static __init void intel_sandybridge_quirk(void)
6a600a8b 1990{
c93dc84c
PZ		 1991 x86_pmu.check_microcode = intel_snb_check_microcode;
1992 intel_snb_check_microcode();
6a600a8b
PZ		 1993}
1994
c1d6f42f
PZ		 1995static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1996 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1997 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1998 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
1999 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2000 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2001 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2002 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 2003};
2004
c1d6f42f
PZ		 2005static __init void intel_arch_events_quirk(void)
2006{
2007 int bit;
2008
2009 /* disable event that reported as not presend by cpuid */
2010 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2011 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 2012 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2013 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 2014 }
2015}
2016
2017static __init void intel_nehalem_quirk(void)
2018{
2019 union cpuid10_ebx ebx;
2020
2021 ebx.full = x86_pmu.events_maskl;
2022 if (ebx.split.no_branch_misses_retired) {
2023 /*
2024 * Erratum AAJ80 detected, we work it around by using
2025 * the BR_MISP_EXEC.ANY event. This will over-count
2026 * branch-misses, but it's still much better than the
2027 * architectural event which is often completely bogus:
2028 */
2029 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2030 ebx.split.no_branch_misses_retired = 0;
2031 x86_pmu.events_maskl = ebx.full;
c767a54b 2032 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 2033 }
2034}
2035
de0428a7 2036__init int intel_pmu_init(void)
f22f54f4
PZ		 2037{
2038 union cpuid10_edx edx;
2039 union cpuid10_eax eax;
ffb871bc 2040 union cpuid10_ebx ebx;
a1eac7ac 2041 struct event_constraint *c;
f22f54f4 2042 unsigned int unused;
f22f54f4
PZ		 2043 int version;
2044
2045 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 2046 switch (boot_cpu_data.x86) {
2047 case 0x6:
2048 return p6_pmu_init();
e717bf4e
VW		 2049 case 0xb:
2050 return knc_pmu_init();
a072738e
CG		 2051 case 0xf:
2052 return p4_pmu_init();
2053 }
f22f54f4 2054 return -ENODEV;
f22f54f4
PZ		 2055 }
2056
2057 /*
2058 * Check whether the Architectural PerfMon supports
2059 * Branch Misses Retired hw_event or not.
2060 */
ffb871bc
GN		 2061 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2062 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 2063 return -ENODEV;
2064
2065 version = eax.split.version_id;
2066 if (version < 2)
2067 x86_pmu = core_pmu;
2068 else
2069 x86_pmu = intel_pmu;
2070
2071 x86_pmu.version = version;
948b1bb8
RR		 2072 x86_pmu.num_counters = eax.split.num_counters;
2073 x86_pmu.cntval_bits = eax.split.bit_width;
2074 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 2075
c1d6f42f
PZ		 2076 x86_pmu.events_maskl = ebx.full;
2077 x86_pmu.events_mask_len = eax.split.mask_length;
2078
70ab7003
AK		 2079 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2080
f22f54f4
PZ		 2081 /*
2082 * Quirk: v2 perfmon does not report fixed-purpose events, so
2083 * assume at least 3 events:
2084 */
2085 if (version > 1)
948b1bb8 2086 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 2087
8db909a7
PZ		 2088 /*
2089 * v2 and above have a perf capabilities MSR
2090 */
2091 if (version > 1) {
2092 u64 capabilities;
2093
2094 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2095 x86_pmu.intel_cap.capabilities = capabilities;
2096 }
2097
ca037701
PZ		 2098 intel_ds_init();
2099
c1d6f42f
PZ		 2100 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2101
f22f54f4
PZ		 2102 /*
2103 * Install the hw-cache-events table:
2104 */
2105 switch (boot_cpu_data.x86_model) {
2106 case 14: /* 65 nm core solo/duo, "Yonah" */
2107 pr_cont("Core events, ");
2108 break;
2109
2110 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
c1d6f42f 2111 x86_add_quirk(intel_clovertown_quirk);
f22f54f4
PZ		 2112 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2113 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2114 case 29: /* six-core 45 nm xeon "Dunnington" */
2115 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2116 sizeof(hw_cache_event_ids));
2117
caff2bef
PZ		 2118 intel_pmu_lbr_init_core();
2119
f22f54f4 2120 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 2121 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 2122 pr_cont("Core2 events, ");
2123 break;
2124
2125 case 26: /* 45 nm nehalem, "Bloomfield" */
2126 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 2127 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 2128 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2129 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2130 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2131 sizeof(hw_cache_extra_regs));
f22f54f4 2132
caff2bef
PZ		 2133 intel_pmu_lbr_init_nhm();
2134
f22f54f4 2135 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 2136 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 2137 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 2138 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 2139
f20093ee
SE		 2140 x86_pmu.cpu_events = nhm_events_attrs;
2141
91fc4cc0 2142 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2143 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2144 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 2145 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2146 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2147 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 2148
c1d6f42f 2149 x86_add_quirk(intel_nehalem_quirk);
ec75a716 2150
11164cd4 2151 pr_cont("Nehalem events, ");
f22f54f4 2152 break;
caff2bef 2153
b622d644 2154 case 28: /* Atom */
0927b482
SL		 2155 case 38: /* Lincroft */
2156 case 39: /* Penwell */
2157 case 53: /* Cloverview */
2158 case 54: /* Cedarview */
f22f54f4
PZ		 2159 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2160 sizeof(hw_cache_event_ids));
2161
caff2bef
PZ		 2162 intel_pmu_lbr_init_atom();
2163
f22f54f4 2164 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 2165 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 2166 pr_cont("Atom events, ");
2167 break;
2168
2169 case 37: /* 32 nm nehalem, "Clarkdale" */
2170 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 2171 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 2172 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2173 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2174 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2175 sizeof(hw_cache_extra_regs));
f22f54f4 2176
caff2bef
PZ		 2177 intel_pmu_lbr_init_nhm();
2178
f22f54f4 2179 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 2180 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 2181 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 2182 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 2183 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039 2184
f20093ee
SE		 2185 x86_pmu.cpu_events = nhm_events_attrs;
2186
30112039 2187 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2188 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2189 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 2190 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2191 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2192 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 2193
f22f54f4
PZ		 2194 pr_cont("Westmere events, ");
2195 break;
b622d644 2196
b06b3d49 2197 case 42: /* SandyBridge */
a34668f6 2198 case 45: /* SandyBridge, "Romely-EP" */
47a8863d 2199 x86_add_quirk(intel_sandybridge_quirk);
b06b3d49
LM		 2200 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2201 sizeof(hw_cache_event_ids));
74e6543f
YZ		 2202 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2203 sizeof(hw_cache_extra_regs));
b06b3d49 2204
c5cc2cd9 2205 intel_pmu_lbr_init_snb();
b06b3d49
LM		 2206
2207 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 2208 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 2209 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2210 if (boot_cpu_data.x86_model == 45)
2211 x86_pmu.extra_regs = intel_snbep_extra_regs;
2212 else
2213 x86_pmu.extra_regs = intel_snb_extra_regs;
ee89cbc2 2214 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 2215 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2216 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23 2217
f20093ee
SE		 2218 x86_pmu.cpu_events = snb_events_attrs;
2219
e04d1b23 2220 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 2221 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2222 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2223 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 2224 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2225 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2226
b06b3d49
LM		 2227 pr_cont("SandyBridge events, ");
2228 break;
20a36e39 2229 case 58: /* IvyBridge */
923d8697 2230 case 62: /* IvyBridge EP */
20a36e39
SE		 2231 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2232 sizeof(hw_cache_event_ids));
2233 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2234 sizeof(hw_cache_extra_regs));
2235
2236 intel_pmu_lbr_init_snb();
2237
69943182 2238 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 2239 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2240 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2241 if (boot_cpu_data.x86_model == 62)
2242 x86_pmu.extra_regs = intel_snbep_extra_regs;
2243 else
2244 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39
SE		 2245 /* all extra regs are per-cpu when HT is on */
2246 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2247 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2248
f20093ee
SE		 2249 x86_pmu.cpu_events = snb_events_attrs;
2250
20a36e39
SE		 2251 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2252 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2253 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2254
2255 pr_cont("IvyBridge events, ");
2256 break;
2257
b06b3d49 2258
3a632cb2
AK		 2259 case 60: /* Haswell Client */
2260 case 70:
2261 case 71:
2262 case 63:
2263 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2264 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2265
2266 intel_pmu_lbr_init_snb();
2267
2268 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 2269 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3a632cb2 2270 x86_pmu.extra_regs = intel_snb_extra_regs;
3044318f 2271 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3a632cb2
AK		 2272 /* all extra regs are per-cpu when HT is on */
2273 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2274 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2275
2276 x86_pmu.hw_config = hsw_hw_config;
2277 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2278 pr_cont("Haswell events, ");
2279 break;
2280
f22f54f4 2281 default:
0af3ac1f
AK		 2282 switch (x86_pmu.version) {
2283 case 1:
2284 x86_pmu.event_constraints = intel_v1_event_constraints;
2285 pr_cont("generic architected perfmon v1, ");
2286 break;
2287 default:
2288 /*
2289 * default constraints for v2 and up
2290 */
2291 x86_pmu.event_constraints = intel_gen_event_constraints;
2292 pr_cont("generic architected perfmon, ");
2293 break;
2294 }
f22f54f4 2295 }
ffb871bc 2296
a1eac7ac
RR		 2297 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2298 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2299 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2300 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2301 }
2302 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2303
2304 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2305 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2306 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2307 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2308 }
2309
2310 x86_pmu.intel_ctrl |=
2311 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2312
2313 if (x86_pmu.event_constraints) {
2314 /*
2315 * event on fixed counter2 (REF_CYCLES) only works on this
2316 * counter, so do not extend mask to generic counters
2317 */
2318 for_each_event_constraint(c, x86_pmu.event_constraints) {
3a632cb2 2319 if (c->cmask != FIXED_EVENT_FLAGS
a1eac7ac
RR		 2320 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2321 continue;
2322 }
2323
2324 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2325 c->weight += x86_pmu.num_counters;
2326 }
2327 }
2328
f22f54f4
PZ		 2329 return 0;
2330}
Linux kernel - Deliverables
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