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KVM: SVM: Add support for AMD's OSVW feature in guests
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
98918833 60#include <asm/xcr.h>
1d5f066e 61#include <asm/pvclock.h>
217fc9cf 62#include <asm/div64.h>
043405e1 63
313a3dc7 64#define MAX_IO_MSRS 256
890ca9ae 65#define KVM_MAX_MCE_BANKS 32
5854dbca 66#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 67
0f65dd70
AK		 68#define emul_to_vcpu(ctxt) \
69 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
1260edbe
LJ		 76static
77u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 78#else
1260edbe 79static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 86static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
476bc001
RR		 91static bool ignore_msrs = 0;
92module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 93
92a1f12d
JR		 94bool kvm_has_tsc_control;
95EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96u32 kvm_max_guest_tsc_khz;
97EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
98
18863bdd
AK		 99#define KVM_NR_SHARED_MSRS 16
100
101struct kvm_shared_msrs_global {
102 int nr;
2bf78fa7 103 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106struct kvm_shared_msrs {
107 struct user_return_notifier urn;
108 bool registered;
2bf78fa7
SY		 109 struct kvm_shared_msr_values {
110 u64 host;
111 u64 curr;
112 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 113};
114
115static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
117
417bc304 118struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 131 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 139 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 140 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 148 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 150 { "largepages", VM_STAT(lpages) },
417bc304
HB		 151 { NULL }
152};
153
2acf923e
DC		 154u64 __read_mostly host_xcr0;
155
d6aa1000
AK		 156int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
157
af585b92
GN		 158static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
159{
160 int i;
161 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
162 vcpu->arch.apf.gfns[i] = ~0;
163}
164
18863bdd
AK		 165static void kvm_on_user_return(struct user_return_notifier *urn)
166{
167 unsigned slot;
18863bdd
AK		 168 struct kvm_shared_msrs *locals
169 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 170 struct kvm_shared_msr_values *values;
18863bdd
AK		 171
172 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 173 values = &locals->values[slot];
174 if (values->host != values->curr) {
175 wrmsrl(shared_msrs_global.msrs[slot], values->host);
176 values->curr = values->host;
18863bdd
AK		 177 }
178 }
179 locals->registered = false;
180 user_return_notifier_unregister(urn);
181}
182
2bf78fa7 183static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 184{
2bf78fa7 185 struct kvm_shared_msrs *smsr;
18863bdd
AK		 186 u64 value;
187
2bf78fa7
SY		 188 smsr = &__get_cpu_var(shared_msrs);
189 /* only read, and nobody should modify it at this time,
190 * so don't need lock */
191 if (slot >= shared_msrs_global.nr) {
192 printk(KERN_ERR "kvm: invalid MSR slot!");
193 return;
194 }
195 rdmsrl_safe(msr, &value);
196 smsr->values[slot].host = value;
197 smsr->values[slot].curr = value;
198}
199
200void kvm_define_shared_msr(unsigned slot, u32 msr)
201{
18863bdd
AK		 202 if (slot >= shared_msrs_global.nr)
203 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 204 shared_msrs_global.msrs[slot] = msr;
205 /* we need ensured the shared_msr_global have been updated */
206 smp_wmb();
18863bdd
AK		 207}
208EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
209
210static void kvm_shared_msr_cpu_online(void)
211{
212 unsigned i;
18863bdd
AK		 213
214 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 215 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 216}
217
d5696725 218void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
2bf78fa7 222 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 223 return;
2bf78fa7
SY		 224 smsr->values[slot].curr = value;
225 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 226 if (!smsr->registered) {
227 smsr->urn.on_user_return = kvm_on_user_return;
228 user_return_notifier_register(&smsr->urn);
229 smsr->registered = true;
230 }
231}
232EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
233
3548bab5
AK		 234static void drop_user_return_notifiers(void *ignore)
235{
236 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
237
238 if (smsr->registered)
239 kvm_on_user_return(&smsr->urn);
240}
241
6866b83e
CO		 242u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
243{
244 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e 246 else
ad312c7c 247 return vcpu->arch.apic_base;
6866b83e
CO		 248}
249EXPORT_SYMBOL_GPL(kvm_get_apic_base);
250
251void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
252{
253 /* TODO: reserve bits check */
254 if (irqchip_in_kernel(vcpu->kvm))
255 kvm_lapic_set_base(vcpu, data);
256 else
ad312c7c 257 vcpu->arch.apic_base = data;
6866b83e
CO		 258}
259EXPORT_SYMBOL_GPL(kvm_set_apic_base);
260
3fd28fce
ED		 261#define EXCPT_BENIGN 0
262#define EXCPT_CONTRIBUTORY 1
263#define EXCPT_PF 2
264
265static int exception_class(int vector)
266{
267 switch (vector) {
268 case PF_VECTOR:
269 return EXCPT_PF;
270 case DE_VECTOR:
271 case TS_VECTOR:
272 case NP_VECTOR:
273 case SS_VECTOR:
274 case GP_VECTOR:
275 return EXCPT_CONTRIBUTORY;
276 default:
277 break;
278 }
279 return EXCPT_BENIGN;
280}
281
282static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 283 unsigned nr, bool has_error, u32 error_code,
284 bool reinject)
3fd28fce
ED		 285{
286 u32 prev_nr;
287 int class1, class2;
288
3842d135
AK		 289 kvm_make_request(KVM_REQ_EVENT, vcpu);
290
3fd28fce
ED		 291 if (!vcpu->arch.exception.pending) {
292 queue:
293 vcpu->arch.exception.pending = true;
294 vcpu->arch.exception.has_error_code = has_error;
295 vcpu->arch.exception.nr = nr;
296 vcpu->arch.exception.error_code = error_code;
3f0fd292 297 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 298 return;
299 }
300
301 /* to check exception */
302 prev_nr = vcpu->arch.exception.nr;
303 if (prev_nr == DF_VECTOR) {
304 /* triple fault -> shutdown */
a8eeb04a 305 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 306 return;
307 }
308 class1 = exception_class(prev_nr);
309 class2 = exception_class(nr);
310 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
311 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
312 /* generate double fault per SDM Table 5-5 */
313 vcpu->arch.exception.pending = true;
314 vcpu->arch.exception.has_error_code = true;
315 vcpu->arch.exception.nr = DF_VECTOR;
316 vcpu->arch.exception.error_code = 0;
317 } else
318 /* replace previous exception with a new one in a hope
319 that instruction re-execution will regenerate lost
320 exception */
321 goto queue;
322}
323
298101da
AK		 324void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
ce7ddec4 326 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 327}
328EXPORT_SYMBOL_GPL(kvm_queue_exception);
329
ce7ddec4
JR		 330void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331{
332 kvm_multiple_exception(vcpu, nr, false, 0, true);
333}
334EXPORT_SYMBOL_GPL(kvm_requeue_exception);
335
db8fcefa 336void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 337{
db8fcefa
AP		 338 if (err)
339 kvm_inject_gp(vcpu, 0);
340 else
341 kvm_x86_ops->skip_emulated_instruction(vcpu);
342}
343EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 344
6389ee94 345void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 346{
347 ++vcpu->stat.pf_guest;
6389ee94
AK		 348 vcpu->arch.cr2 = fault->address;
349 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 350}
27d6c865 351EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 352
6389ee94 353void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 354{
6389ee94
AK		 355 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
356 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 357 else
6389ee94 358 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 359}
360
3419ffc8
SY		 361void kvm_inject_nmi(struct kvm_vcpu *vcpu)
362{
7460fb4a
AK		 363 atomic_inc(&vcpu->arch.nmi_queued);
364 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 365}
366EXPORT_SYMBOL_GPL(kvm_inject_nmi);
367
298101da
AK		 368void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
369{
ce7ddec4 370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 371}
372EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
373
ce7ddec4
JR		 374void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375{
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
377}
378EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
379
0a79b009
AK		 380/*
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
383 */
384bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 385{
0a79b009
AK		 386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
387 return true;
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
389 return false;
298101da 390}
0a79b009 391EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 392
ec92fe44
JR		 393/*
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
397 */
398int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
400 u32 access)
401{
402 gfn_t real_gfn;
403 gpa_t ngpa;
404
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
408 return -EFAULT;
409
410 real_gfn = gpa_to_gfn(real_gfn);
411
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
413}
414EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
415
3d06b8bf
JR		 416int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
418{
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
421}
422
a03490ed
CO		 423/*
424 * Load the pae pdptrs. Return true is they are all valid.
425 */
ff03a073 426int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 427{
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
430 int i;
431 int ret;
ff03a073 432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 433
ff03a073
JR		 434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 437 if (ret < 0) {
438 ret = 0;
439 goto out;
440 }
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 442 if (is_present_gpte(pdpte[i]) &&
20c466b5 443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 444 ret = 0;
445 goto out;
446 }
447 }
448 ret = 1;
449
ff03a073 450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 455out:
a03490ed
CO		 456
457 return ret;
458}
cc4b6871 459EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 460
d835dfec
AK		 461static bool pdptrs_changed(struct kvm_vcpu *vcpu)
462{
ff03a073 463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 464 bool changed = true;
3d06b8bf
JR		 465 int offset;
466 gfn_t gfn;
d835dfec
AK		 467 int r;
468
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
470 return false;
471
6de4f3ad
AK		 472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
474 return true;
475
9f8fe504
AK		 476 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
477 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 480 if (r < 0)
481 goto out;
ff03a073 482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 483out:
d835dfec
AK		 484
485 return changed;
486}
487
49a9b07e 488int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 489{
aad82703
SY		 490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
493
f9a48e6a
AK		 494 cr0 |= X86_CR0_ET;
495
ab344828 496#ifdef CONFIG_X86_64
0f12244f
GN		 497 if (cr0 & 0xffffffff00000000UL)
498 return 1;
ab344828
GN		 499#endif
500
501 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 502
0f12244f
GN		 503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
504 return 1;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
507 return 1;
a03490ed
CO		 508
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
510#ifdef CONFIG_X86_64
f6801dff 511 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 512 int cs_db, cs_l;
513
0f12244f
GN		 514 if (!is_pae(vcpu))
515 return 1;
a03490ed 516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 517 if (cs_l)
518 return 1;
a03490ed
CO		 519 } else
520#endif
ff03a073 521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 522 kvm_read_cr3(vcpu)))
0f12244f 523 return 1;
a03490ed
CO		 524 }
525
526 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 527
d170c419 528 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 529 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 530 kvm_async_pf_hash_reset(vcpu);
531 }
e5f3f027 532
aad82703
SY		 533 if ((cr0 ^ old_cr0) & update_bits)
534 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 535 return 0;
536}
2d3ad1f4 537EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 538
2d3ad1f4 539void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 540{
49a9b07e 541 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 542}
2d3ad1f4 543EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 544
2acf923e
DC		 545int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
546{
547 u64 xcr0;
548
549 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
550 if (index != XCR_XFEATURE_ENABLED_MASK)
551 return 1;
552 xcr0 = xcr;
553 if (kvm_x86_ops->get_cpl(vcpu) != 0)
554 return 1;
555 if (!(xcr0 & XSTATE_FP))
556 return 1;
557 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
558 return 1;
559 if (xcr0 & ~host_xcr0)
560 return 1;
561 vcpu->arch.xcr0 = xcr0;
562 vcpu->guest_xcr0_loaded = 0;
563 return 0;
564}
565
566int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
567{
568 if (__kvm_set_xcr(vcpu, index, xcr)) {
569 kvm_inject_gp(vcpu, 0);
570 return 1;
571 }
572 return 0;
573}
574EXPORT_SYMBOL_GPL(kvm_set_xcr);
575
a83b29c6 576int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 577{
fc78f519 578 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 579 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
580 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 581 if (cr4 & CR4_RESERVED_BITS)
582 return 1;
a03490ed 583
2acf923e
DC		 584 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
585 return 1;
586
c68b734f
YW		 587 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
588 return 1;
589
74dc2b4f
YW		 590 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
591 return 1;
592
a03490ed 593 if (is_long_mode(vcpu)) {
0f12244f
GN		 594 if (!(cr4 & X86_CR4_PAE))
595 return 1;
a2edf57f
AK		 596 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
597 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 598 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
599 kvm_read_cr3(vcpu)))
0f12244f
GN		 600 return 1;
601
5e1746d6 602 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 603 return 1;
a03490ed 604
aad82703
SY		 605 if ((cr4 ^ old_cr4) & pdptr_bits)
606 kvm_mmu_reset_context(vcpu);
0f12244f 607
2acf923e 608 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 609 kvm_update_cpuid(vcpu);
2acf923e 610
0f12244f
GN		 611 return 0;
612}
2d3ad1f4 613EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 614
2390218b 615int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 616{
9f8fe504 617 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 618 kvm_mmu_sync_roots(vcpu);
d835dfec 619 kvm_mmu_flush_tlb(vcpu);
0f12244f 620 return 0;
d835dfec
AK		 621 }
622
a03490ed 623 if (is_long_mode(vcpu)) {
0f12244f
GN		 624 if (cr3 & CR3_L_MODE_RESERVED_BITS)
625 return 1;
a03490ed
CO		 626 } else {
627 if (is_pae(vcpu)) {
0f12244f
GN		 628 if (cr3 & CR3_PAE_RESERVED_BITS)
629 return 1;
ff03a073
JR		 630 if (is_paging(vcpu) &&
631 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 632 return 1;
a03490ed
CO		 633 }
634 /*
635 * We don't check reserved bits in nonpae mode, because
636 * this isn't enforced, and VMware depends on this.
637 */
638 }
639
a03490ed
CO		 640 /*
641 * Does the new cr3 value map to physical memory? (Note, we
642 * catch an invalid cr3 even in real-mode, because it would
643 * cause trouble later on when we turn on paging anyway.)
644 *
645 * A real CPU would silently accept an invalid cr3 and would
646 * attempt to use it - with largely undefined (and often hard
647 * to debug) behavior on the guest side.
648 */
649 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 650 return 1;
651 vcpu->arch.cr3 = cr3;
aff48baa 652 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 653 vcpu->arch.mmu.new_cr3(vcpu);
654 return 0;
655}
2d3ad1f4 656EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 657
eea1cff9 658int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 659{
0f12244f
GN		 660 if (cr8 & CR8_RESERVED_BITS)
661 return 1;
a03490ed
CO		 662 if (irqchip_in_kernel(vcpu->kvm))
663 kvm_lapic_set_tpr(vcpu, cr8);
664 else
ad312c7c 665 vcpu->arch.cr8 = cr8;
0f12244f
GN		 666 return 0;
667}
2d3ad1f4 668EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 669
2d3ad1f4 670unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 671{
672 if (irqchip_in_kernel(vcpu->kvm))
673 return kvm_lapic_get_cr8(vcpu);
674 else
ad312c7c 675 return vcpu->arch.cr8;
a03490ed 676}
2d3ad1f4 677EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 678
338dbc97 679static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 680{
681 switch (dr) {
682 case 0 ... 3:
683 vcpu->arch.db[dr] = val;
684 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
685 vcpu->arch.eff_db[dr] = val;
686 break;
687 case 4:
338dbc97
GN		 688 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
689 return 1; /* #UD */
020df079
GN		 690 /* fall through */
691 case 6:
338dbc97
GN		 692 if (val & 0xffffffff00000000ULL)
693 return -1; /* #GP */
020df079
GN		 694 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
695 break;
696 case 5:
338dbc97
GN		 697 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
698 return 1; /* #UD */
020df079
GN		 699 /* fall through */
700 default: /* 7 */
338dbc97
GN		 701 if (val & 0xffffffff00000000ULL)
702 return -1; /* #GP */
020df079
GN		 703 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
704 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
705 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
706 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
707 }
708 break;
709 }
710
711 return 0;
712}
338dbc97
GN		 713
714int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
715{
716 int res;
717
718 res = __kvm_set_dr(vcpu, dr, val);
719 if (res > 0)
720 kvm_queue_exception(vcpu, UD_VECTOR);
721 else if (res < 0)
722 kvm_inject_gp(vcpu, 0);
723
724 return res;
725}
020df079
GN		 726EXPORT_SYMBOL_GPL(kvm_set_dr);
727
338dbc97 728static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 729{
730 switch (dr) {
731 case 0 ... 3:
732 *val = vcpu->arch.db[dr];
733 break;
734 case 4:
338dbc97 735 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 736 return 1;
020df079
GN		 737 /* fall through */
738 case 6:
739 *val = vcpu->arch.dr6;
740 break;
741 case 5:
338dbc97 742 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 743 return 1;
020df079
GN		 744 /* fall through */
745 default: /* 7 */
746 *val = vcpu->arch.dr7;
747 break;
748 }
749
750 return 0;
751}
338dbc97
GN		 752
753int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
754{
755 if (_kvm_get_dr(vcpu, dr, val)) {
756 kvm_queue_exception(vcpu, UD_VECTOR);
757 return 1;
758 }
759 return 0;
760}
020df079
GN		 761EXPORT_SYMBOL_GPL(kvm_get_dr);
762
022cd0e8
AK		 763bool kvm_rdpmc(struct kvm_vcpu *vcpu)
764{
765 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
766 u64 data;
767 int err;
768
769 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
770 if (err)
771 return err;
772 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
773 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
774 return err;
775}
776EXPORT_SYMBOL_GPL(kvm_rdpmc);
777
043405e1
CO		 778/*
779 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
780 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
781 *
782 * This list is modified at module load time to reflect the
e3267cbb
GC		 783 * capabilities of the host cpu. This capabilities test skips MSRs that are
784 * kvm-specific. Those are put in the beginning of the list.
043405e1 785 */
e3267cbb 786
c9aaa895 787#define KVM_SAVE_MSRS_BEGIN 9
043405e1 788static u32 msrs_to_save[] = {
e3267cbb 789 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 790 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 791 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 792 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 793 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 794 MSR_STAR,
043405e1
CO		 795#ifdef CONFIG_X86_64
796 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
797#endif
e90aa41e 798 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 799};
800
801static unsigned num_msrs_to_save;
802
803static u32 emulated_msrs[] = {
a3e06bbe 804 MSR_IA32_TSCDEADLINE,
043405e1 805 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 806 MSR_IA32_MCG_STATUS,
807 MSR_IA32_MCG_CTL,
043405e1
CO		 808};
809
b69e8cae 810static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 811{
aad82703
SY		 812 u64 old_efer = vcpu->arch.efer;
813
b69e8cae
RJ		 814 if (efer & efer_reserved_bits)
815 return 1;
15c4a640
CO		 816
817 if (is_paging(vcpu)
b69e8cae
RJ		 818 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
819 return 1;
15c4a640 820
1b2fd70c
AG		 821 if (efer & EFER_FFXSR) {
822 struct kvm_cpuid_entry2 *feat;
823
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 825 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
826 return 1;
1b2fd70c
AG		 827 }
828
d8017474
AG		 829 if (efer & EFER_SVME) {
830 struct kvm_cpuid_entry2 *feat;
831
832 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 833 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
834 return 1;
d8017474
AG		 835 }
836
15c4a640 837 efer &= ~EFER_LMA;
f6801dff 838 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 839
a3d204e2
SY		 840 kvm_x86_ops->set_efer(vcpu, efer);
841
9645bb56 842 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 843
aad82703
SY		 844 /* Update reserved bits */
845 if ((efer ^ old_efer) & EFER_NX)
846 kvm_mmu_reset_context(vcpu);
847
b69e8cae 848 return 0;
15c4a640
CO		 849}
850
f2b4b7dd
JR		 851void kvm_enable_efer_bits(u64 mask)
852{
853 efer_reserved_bits &= ~mask;
854}
855EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
856
857
15c4a640
CO		 858/*
859 * Writes msr value into into the appropriate "register".
860 * Returns 0 on success, non-0 otherwise.
861 * Assumes vcpu_load() was already called.
862 */
863int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
864{
865 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
866}
867
313a3dc7
CO		 868/*
869 * Adapt set_msr() to msr_io()'s calling convention
870 */
871static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
872{
873 return kvm_set_msr(vcpu, index, *data);
874}
875
18068523
GOC		 876static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
877{
9ed3c444
AK		 878 int version;
879 int r;
50d0a0f9 880 struct pvclock_wall_clock wc;
923de3cf 881 struct timespec boot;
18068523
GOC		 882
883 if (!wall_clock)
884 return;
885
9ed3c444
AK		 886 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
887 if (r)
888 return;
889
890 if (version & 1)
891 ++version; /* first time write, random junk */
892
893 ++version;
18068523 894
18068523
GOC		 895 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
896
50d0a0f9
GH		 897 /*
898 * The guest calculates current wall clock time by adding
34c238a1 899 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 900 * wall clock specified here. guest system time equals host
901 * system time for us, thus we must fill in host boot time here.
902 */
923de3cf 903 getboottime(&boot);
50d0a0f9
GH		 904
905 wc.sec = boot.tv_sec;
906 wc.nsec = boot.tv_nsec;
907 wc.version = version;
18068523
GOC		 908
909 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
910
911 version++;
912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 913}
914
50d0a0f9
GH		 915static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
916{
917 uint32_t quotient, remainder;
918
919 /* Don't try to replace with do_div(), this one calculates
920 * "(dividend << 32) / divisor" */
921 __asm__ ( "divl %4"
922 : "=a" (quotient), "=d" (remainder)
923 : "0" (0), "1" (dividend), "r" (divisor) );
924 return quotient;
925}
926
5f4e3f88
ZA		 927static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
928 s8 *pshift, u32 *pmultiplier)
50d0a0f9 929{
5f4e3f88 930 uint64_t scaled64;
50d0a0f9
GH		 931 int32_t shift = 0;
932 uint64_t tps64;
933 uint32_t tps32;
934
5f4e3f88
ZA		 935 tps64 = base_khz * 1000LL;
936 scaled64 = scaled_khz * 1000LL;
50933623 937 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 938 tps64 >>= 1;
939 shift--;
940 }
941
942 tps32 = (uint32_t)tps64;
50933623
JK		 943 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
944 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 945 scaled64 >>= 1;
946 else
947 tps32 <<= 1;
50d0a0f9
GH		 948 shift++;
949 }
950
5f4e3f88
ZA		 951 *pshift = shift;
952 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 953
5f4e3f88
ZA		 954 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
955 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 956}
957
759379dd
ZA		 958static inline u64 get_kernel_ns(void)
959{
960 struct timespec ts;
961
962 WARN_ON(preemptible());
963 ktime_get_ts(&ts);
964 monotonic_to_bootbased(&ts);
965 return timespec_to_ns(&ts);
50d0a0f9
GH		 966}
967
c8076604 968static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 969unsigned long max_tsc_khz;
c8076604 970
8cfdc000
ZA		 971static inline int kvm_tsc_changes_freq(void)
972{
973 int cpu = get_cpu();
974 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
975 cpufreq_quick_get(cpu) != 0;
976 put_cpu();
977 return ret;
978}
979
a3e06bbe 980u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1e993611
JR		 981{
982 if (vcpu->arch.virtual_tsc_khz)
983 return vcpu->arch.virtual_tsc_khz;
984 else
985 return __this_cpu_read(cpu_tsc_khz);
986}
987
857e4099 988static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 989{
217fc9cf
AK		 990 u64 ret;
991
759379dd
ZA		 992 WARN_ON(preemptible());
993 if (kvm_tsc_changes_freq())
994 printk_once(KERN_WARNING
995 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 996 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 997 do_div(ret, USEC_PER_SEC);
998 return ret;
759379dd
ZA		 999}
1000
1e993611 1001static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1002{
1003 /* Compute a scale to convert nanoseconds in TSC cycles */
1004 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1005 &vcpu->arch.tsc_catchup_shift,
1006 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1007}
1008
1009static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1010{
1011 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1012 vcpu->arch.tsc_catchup_mult,
1013 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1014 tsc += vcpu->arch.last_tsc_write;
1015 return tsc;
1016}
1017
99e3e30a
ZA		 1018void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1019{
1020 struct kvm *kvm = vcpu->kvm;
f38e098f 1021 u64 offset, ns, elapsed;
99e3e30a 1022 unsigned long flags;
46543ba4 1023 s64 sdiff;
99e3e30a 1024
038f8c11 1025 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1026 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1027 ns = get_kernel_ns();
f38e098f 1028 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1029 sdiff = data - kvm->arch.last_tsc_write;
1030 if (sdiff < 0)
1031 sdiff = -sdiff;
f38e098f
ZA		 1032
1033 /*
46543ba4 1034 * Special case: close write to TSC within 5 seconds of
f38e098f 1035 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1036 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1037 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1038 *
1039 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1040 * or make a best guest using elapsed value.
f38e098f 1041 */
857e4099 1042 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1043 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1044 if (!check_tsc_unstable()) {
1045 offset = kvm->arch.last_tsc_offset;
1046 pr_debug("kvm: matched tsc offset for %llu\n", data);
1047 } else {
857e4099 1048 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1049 offset += delta;
1050 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1051 }
1052 ns = kvm->arch.last_tsc_nsec;
1053 }
1054 kvm->arch.last_tsc_nsec = ns;
1055 kvm->arch.last_tsc_write = data;
1056 kvm->arch.last_tsc_offset = offset;
99e3e30a 1057 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1058 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1059
1060 /* Reset of TSC must disable overshoot protection below */
1061 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1062 vcpu->arch.last_tsc_write = data;
1063 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1064}
1065EXPORT_SYMBOL_GPL(kvm_write_tsc);
1066
34c238a1 1067static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1068{
18068523
GOC		 1069 unsigned long flags;
1070 struct kvm_vcpu_arch *vcpu = &v->arch;
1071 void *shared_kaddr;
463656c0 1072 unsigned long this_tsc_khz;
1d5f066e
ZA		 1073 s64 kernel_ns, max_kernel_ns;
1074 u64 tsc_timestamp;
18068523 1075
18068523
GOC		 1076 /* Keep irq disabled to prevent changes to the clock */
1077 local_irq_save(flags);
d5c1785d 1078 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1079 kernel_ns = get_kernel_ns();
1e993611 1080 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1081 if (unlikely(this_tsc_khz == 0)) {
c285545f 1082 local_irq_restore(flags);
34c238a1 1083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1084 return 1;
1085 }
18068523 1086
c285545f
ZA		 1087 /*
1088 * We may have to catch up the TSC to match elapsed wall clock
1089 * time for two reasons, even if kvmclock is used.
1090 * 1) CPU could have been running below the maximum TSC rate
1091 * 2) Broken TSC compensation resets the base at each VCPU
1092 * entry to avoid unknown leaps of TSC even when running
1093 * again on the same CPU. This may cause apparent elapsed
1094 * time to disappear, and the guest to stand still or run
1095 * very slowly.
1096 */
1097 if (vcpu->tsc_catchup) {
1098 u64 tsc = compute_guest_tsc(v, kernel_ns);
1099 if (tsc > tsc_timestamp) {
1100 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1101 tsc_timestamp = tsc;
1102 }
50d0a0f9
GH		 1103 }
1104
18068523
GOC		 1105 local_irq_restore(flags);
1106
c285545f
ZA		 1107 if (!vcpu->time_page)
1108 return 0;
18068523 1109
1d5f066e
ZA		 1110 /*
1111 * Time as measured by the TSC may go backwards when resetting the base
1112 * tsc_timestamp. The reason for this is that the TSC resolution is
1113 * higher than the resolution of the other clock scales. Thus, many
1114 * possible measurments of the TSC correspond to one measurement of any
1115 * other clock, and so a spread of values is possible. This is not a
1116 * problem for the computation of the nanosecond clock; with TSC rates
1117 * around 1GHZ, there can only be a few cycles which correspond to one
1118 * nanosecond value, and any path through this code will inevitably
1119 * take longer than that. However, with the kernel_ns value itself,
1120 * the precision may be much lower, down to HZ granularity. If the
1121 * first sampling of TSC against kernel_ns ends in the low part of the
1122 * range, and the second in the high end of the range, we can get:
1123 *
1124 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1125 *
1126 * As the sampling errors potentially range in the thousands of cycles,
1127 * it is possible such a time value has already been observed by the
1128 * guest. To protect against this, we must compute the system time as
1129 * observed by the guest and ensure the new system time is greater.
1130 */
1131 max_kernel_ns = 0;
1132 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1133 max_kernel_ns = vcpu->last_guest_tsc -
1134 vcpu->hv_clock.tsc_timestamp;
1135 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1136 vcpu->hv_clock.tsc_to_system_mul,
1137 vcpu->hv_clock.tsc_shift);
1138 max_kernel_ns += vcpu->last_kernel_ns;
1139 }
afbcf7ab 1140
e48672fa 1141 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1142 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1143 &vcpu->hv_clock.tsc_shift,
1144 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1145 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1146 }
1147
1d5f066e
ZA		 1148 if (max_kernel_ns > kernel_ns)
1149 kernel_ns = max_kernel_ns;
1150
8cfdc000 1151 /* With all the info we got, fill in the values */
1d5f066e 1152 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1153 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1154 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1155 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1156 vcpu->hv_clock.flags = 0;
1157
18068523
GOC		 1158 /*
1159 * The interface expects us to write an even number signaling that the
1160 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1161 * state, we just increase by 2 at the end.
18068523 1162 */
50d0a0f9 1163 vcpu->hv_clock.version += 2;
18068523
GOC		 1164
1165 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1166
1167 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1168 sizeof(vcpu->hv_clock));
18068523
GOC		 1169
1170 kunmap_atomic(shared_kaddr, KM_USER0);
1171
1172 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1173 return 0;
c8076604
GH		 1174}
1175
9ba075a6
AK		 1176static bool msr_mtrr_valid(unsigned msr)
1177{
1178 switch (msr) {
1179 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1180 case MSR_MTRRfix64K_00000:
1181 case MSR_MTRRfix16K_80000:
1182 case MSR_MTRRfix16K_A0000:
1183 case MSR_MTRRfix4K_C0000:
1184 case MSR_MTRRfix4K_C8000:
1185 case MSR_MTRRfix4K_D0000:
1186 case MSR_MTRRfix4K_D8000:
1187 case MSR_MTRRfix4K_E0000:
1188 case MSR_MTRRfix4K_E8000:
1189 case MSR_MTRRfix4K_F0000:
1190 case MSR_MTRRfix4K_F8000:
1191 case MSR_MTRRdefType:
1192 case MSR_IA32_CR_PAT:
1193 return true;
1194 case 0x2f8:
1195 return true;
1196 }
1197 return false;
1198}
1199
d6289b93
MT		 1200static bool valid_pat_type(unsigned t)
1201{
1202 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1203}
1204
1205static bool valid_mtrr_type(unsigned t)
1206{
1207 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1208}
1209
1210static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1211{
1212 int i;
1213
1214 if (!msr_mtrr_valid(msr))
1215 return false;
1216
1217 if (msr == MSR_IA32_CR_PAT) {
1218 for (i = 0; i < 8; i++)
1219 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1220 return false;
1221 return true;
1222 } else if (msr == MSR_MTRRdefType) {
1223 if (data & ~0xcff)
1224 return false;
1225 return valid_mtrr_type(data & 0xff);
1226 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1227 for (i = 0; i < 8 ; i++)
1228 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1229 return false;
1230 return true;
1231 }
1232
1233 /* variable MTRRs */
1234 return valid_mtrr_type(data & 0xff);
1235}
1236
9ba075a6
AK		 1237static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1238{
0bed3b56
SY		 1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1240
d6289b93 1241 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1242 return 1;
1243
0bed3b56
SY		 1244 if (msr == MSR_MTRRdefType) {
1245 vcpu->arch.mtrr_state.def_type = data;
1246 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1247 } else if (msr == MSR_MTRRfix64K_00000)
1248 p[0] = data;
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1253 else if (msr == MSR_IA32_CR_PAT)
1254 vcpu->arch.pat = data;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1257 u64 *pt;
1258
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1261 if (!is_mtrr_mask)
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1264 else
1265 pt =
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1267 *pt = data;
1268 }
1269
1270 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1271 return 0;
1272}
15c4a640 1273
890ca9ae 1274static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1275{
890ca9ae
HY		 1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
1278
15c4a640 1279 switch (msr) {
15c4a640 1280 case MSR_IA32_MCG_STATUS:
890ca9ae 1281 vcpu->arch.mcg_status = data;
15c4a640 1282 break;
c7ac679c 1283 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1284 if (!(mcg_cap & MCG_CTL_P))
1285 return 1;
1286 if (data != 0 && data != ~(u64)0)
1287 return -1;
1288 vcpu->arch.mcg_ctl = data;
1289 break;
1290 default:
1291 if (msr >= MSR_IA32_MC0_CTL &&
1292 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1293 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1294 /* only 0 or all 1s can be written to IA32_MCi_CTL
1295 * some Linux kernels though clear bit 10 in bank 4 to
1296 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1297 * this to avoid an uncatched #GP in the guest
1298 */
890ca9ae 1299 if ((offset & 0x3) == 0 &&
114be429 1300 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1301 return -1;
1302 vcpu->arch.mce_banks[offset] = data;
1303 break;
1304 }
1305 return 1;
1306 }
1307 return 0;
1308}
1309
ffde22ac
ES		 1310static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1311{
1312 struct kvm *kvm = vcpu->kvm;
1313 int lm = is_long_mode(vcpu);
1314 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1315 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1316 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1317 : kvm->arch.xen_hvm_config.blob_size_32;
1318 u32 page_num = data & ~PAGE_MASK;
1319 u64 page_addr = data & PAGE_MASK;
1320 u8 *page;
1321 int r;
1322
1323 r = -E2BIG;
1324 if (page_num >= blob_size)
1325 goto out;
1326 r = -ENOMEM;
ff5c2c03
SL		 1327 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1328 if (IS_ERR(page)) {
1329 r = PTR_ERR(page);
ffde22ac 1330 goto out;
ff5c2c03 1331 }
ffde22ac
ES		 1332 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1333 goto out_free;
1334 r = 0;
1335out_free:
1336 kfree(page);
1337out:
1338 return r;
1339}
1340
55cd8e5a
GN		 1341static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1342{
1343 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1344}
1345
1346static bool kvm_hv_msr_partition_wide(u32 msr)
1347{
1348 bool r = false;
1349 switch (msr) {
1350 case HV_X64_MSR_GUEST_OS_ID:
1351 case HV_X64_MSR_HYPERCALL:
1352 r = true;
1353 break;
1354 }
1355
1356 return r;
1357}
1358
1359static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1360{
1361 struct kvm *kvm = vcpu->kvm;
1362
1363 switch (msr) {
1364 case HV_X64_MSR_GUEST_OS_ID:
1365 kvm->arch.hv_guest_os_id = data;
1366 /* setting guest os id to zero disables hypercall page */
1367 if (!kvm->arch.hv_guest_os_id)
1368 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1369 break;
1370 case HV_X64_MSR_HYPERCALL: {
1371 u64 gfn;
1372 unsigned long addr;
1373 u8 instructions[4];
1374
1375 /* if guest os id is not set hypercall should remain disabled */
1376 if (!kvm->arch.hv_guest_os_id)
1377 break;
1378 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1379 kvm->arch.hv_hypercall = data;
1380 break;
1381 }
1382 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1383 addr = gfn_to_hva(kvm, gfn);
1384 if (kvm_is_error_hva(addr))
1385 return 1;
1386 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1387 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1388 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1389 return 1;
1390 kvm->arch.hv_hypercall = data;
1391 break;
1392 }
1393 default:
1394 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1395 "data 0x%llx\n", msr, data);
1396 return 1;
1397 }
1398 return 0;
1399}
1400
1401static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1402{
10388a07
GN		 1403 switch (msr) {
1404 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1405 unsigned long addr;
55cd8e5a 1406
10388a07
GN		 1407 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1408 vcpu->arch.hv_vapic = data;
1409 break;
1410 }
1411 addr = gfn_to_hva(vcpu->kvm, data >>
1412 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1413 if (kvm_is_error_hva(addr))
1414 return 1;
8b0cedff 1415 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1416 return 1;
1417 vcpu->arch.hv_vapic = data;
1418 break;
1419 }
1420 case HV_X64_MSR_EOI:
1421 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1422 case HV_X64_MSR_ICR:
1423 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1424 case HV_X64_MSR_TPR:
1425 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1426 default:
1427 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1428 "data 0x%llx\n", msr, data);
1429 return 1;
1430 }
1431
1432 return 0;
55cd8e5a
GN		 1433}
1434
344d9588
GN		 1435static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1436{
1437 gpa_t gpa = data & ~0x3f;
1438
6adba527
GN		 1439 /* Bits 2:5 are resrved, Should be zero */
1440 if (data & 0x3c)
344d9588
GN		 1441 return 1;
1442
1443 vcpu->arch.apf.msr_val = data;
1444
1445 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1446 kvm_clear_async_pf_completion_queue(vcpu);
1447 kvm_async_pf_hash_reset(vcpu);
1448 return 0;
1449 }
1450
1451 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1452 return 1;
1453
6adba527 1454 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1455 kvm_async_pf_wakeup_all(vcpu);
1456 return 0;
1457}
1458
12f9a48f
GC		 1459static void kvmclock_reset(struct kvm_vcpu *vcpu)
1460{
1461 if (vcpu->arch.time_page) {
1462 kvm_release_page_dirty(vcpu->arch.time_page);
1463 vcpu->arch.time_page = NULL;
1464 }
1465}
1466
c9aaa895
GC		 1467static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1468{
1469 u64 delta;
1470
1471 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1472 return;
1473
1474 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1475 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1476 vcpu->arch.st.accum_steal = delta;
1477}
1478
1479static void record_steal_time(struct kvm_vcpu *vcpu)
1480{
1481 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1482 return;
1483
1484 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1485 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1486 return;
1487
1488 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1489 vcpu->arch.st.steal.version += 2;
1490 vcpu->arch.st.accum_steal = 0;
1491
1492 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1493 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1494}
1495
15c4a640
CO		 1496int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1497{
5753785f
GN		 1498 bool pr = false;
1499
15c4a640 1500 switch (msr) {
15c4a640 1501 case MSR_EFER:
b69e8cae 1502 return set_efer(vcpu, data);
8f1589d9
AP		 1503 case MSR_K7_HWCR:
1504 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1505 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1506 if (data != 0) {
1507 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1508 data);
1509 return 1;
1510 }
15c4a640 1511 break;
f7c6d140
AP		 1512 case MSR_FAM10H_MMIO_CONF_BASE:
1513 if (data != 0) {
1514 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1515 "0x%llx\n", data);
1516 return 1;
1517 }
15c4a640 1518 break;
c323c0e5 1519 case MSR_AMD64_NB_CFG:
c7ac679c 1520 break;
b5e2fec0
AG		 1521 case MSR_IA32_DEBUGCTLMSR:
1522 if (!data) {
1523 /* We support the non-activated case already */
1524 break;
1525 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1526 /* Values other than LBR and BTF are vendor-specific,
1527 thus reserved and should throw a #GP */
1528 return 1;
1529 }
1530 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1531 __func__, data);
1532 break;
15c4a640
CO		 1533 case MSR_IA32_UCODE_REV:
1534 case MSR_IA32_UCODE_WRITE:
61a6bd67 1535 case MSR_VM_HSAVE_PA:
6098ca93 1536 case MSR_AMD64_PATCH_LOADER:
15c4a640 1537 break;
9ba075a6
AK		 1538 case 0x200 ... 0x2ff:
1539 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1540 case MSR_IA32_APICBASE:
1541 kvm_set_apic_base(vcpu, data);
1542 break;
0105d1a5
GN		 1543 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1544 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1545 case MSR_IA32_TSCDEADLINE:
1546 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1547 break;
15c4a640 1548 case MSR_IA32_MISC_ENABLE:
ad312c7c 1549 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1550 break;
11c6bffa 1551 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1552 case MSR_KVM_WALL_CLOCK:
1553 vcpu->kvm->arch.wall_clock = data;
1554 kvm_write_wall_clock(vcpu->kvm, data);
1555 break;
11c6bffa 1556 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1557 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1558 kvmclock_reset(vcpu);
18068523
GOC		 1559
1560 vcpu->arch.time = data;
c285545f 1561 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1562
1563 /* we verify if the enable bit is set... */
1564 if (!(data & 1))
1565 break;
1566
1567 /* ...but clean it before doing the actual write */
1568 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1569
18068523
GOC		 1570 vcpu->arch.time_page =
1571 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1572
1573 if (is_error_page(vcpu->arch.time_page)) {
1574 kvm_release_page_clean(vcpu->arch.time_page);
1575 vcpu->arch.time_page = NULL;
1576 }
18068523
GOC		 1577 break;
1578 }
344d9588
GN		 1579 case MSR_KVM_ASYNC_PF_EN:
1580 if (kvm_pv_enable_async_pf(vcpu, data))
1581 return 1;
1582 break;
c9aaa895
GC		 1583 case MSR_KVM_STEAL_TIME:
1584
1585 if (unlikely(!sched_info_on()))
1586 return 1;
1587
1588 if (data & KVM_STEAL_RESERVED_MASK)
1589 return 1;
1590
1591 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1592 data & KVM_STEAL_VALID_BITS))
1593 return 1;
1594
1595 vcpu->arch.st.msr_val = data;
1596
1597 if (!(data & KVM_MSR_ENABLED))
1598 break;
1599
1600 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1601
1602 preempt_disable();
1603 accumulate_steal_time(vcpu);
1604 preempt_enable();
1605
1606 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1607
1608 break;
1609
890ca9ae
HY		 1610 case MSR_IA32_MCG_CTL:
1611 case MSR_IA32_MCG_STATUS:
1612 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1613 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1614
1615 /* Performance counters are not protected by a CPUID bit,
1616 * so we should check all of them in the generic path for the sake of
1617 * cross vendor migration.
1618 * Writing a zero into the event select MSRs disables them,
1619 * which we perfectly emulate ;-). Any other value should be at least
1620 * reported, some guests depend on them.
1621 */
71db6023
AP		 1622 case MSR_K7_EVNTSEL0:
1623 case MSR_K7_EVNTSEL1:
1624 case MSR_K7_EVNTSEL2:
1625 case MSR_K7_EVNTSEL3:
1626 if (data != 0)
1627 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1628 "0x%x data 0x%llx\n", msr, data);
1629 break;
1630 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1631 * so we ignore writes to make it happy.
1632 */
71db6023
AP		 1633 case MSR_K7_PERFCTR0:
1634 case MSR_K7_PERFCTR1:
1635 case MSR_K7_PERFCTR2:
1636 case MSR_K7_PERFCTR3:
1637 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1638 "0x%x data 0x%llx\n", msr, data);
1639 break;
5753785f
GN		 1640 case MSR_P6_PERFCTR0:
1641 case MSR_P6_PERFCTR1:
1642 pr = true;
1643 case MSR_P6_EVNTSEL0:
1644 case MSR_P6_EVNTSEL1:
1645 if (kvm_pmu_msr(vcpu, msr))
1646 return kvm_pmu_set_msr(vcpu, msr, data);
1647
1648 if (pr || data != 0)
1649 pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1650 "0x%x data 0x%llx\n", msr, data);
1651 break;
84e0cefa
JS		 1652 case MSR_K7_CLK_CTL:
1653 /*
1654 * Ignore all writes to this no longer documented MSR.
1655 * Writes are only relevant for old K7 processors,
1656 * all pre-dating SVM, but a recommended workaround from
1657 * AMD for these chips. It is possible to speicify the
1658 * affected processor models on the command line, hence
1659 * the need to ignore the workaround.
1660 */
1661 break;
55cd8e5a
GN		 1662 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1663 if (kvm_hv_msr_partition_wide(msr)) {
1664 int r;
1665 mutex_lock(&vcpu->kvm->lock);
1666 r = set_msr_hyperv_pw(vcpu, msr, data);
1667 mutex_unlock(&vcpu->kvm->lock);
1668 return r;
1669 } else
1670 return set_msr_hyperv(vcpu, msr, data);
1671 break;
91c9c3ed 1672 case MSR_IA32_BBL_CR_CTL3:
1673 /* Drop writes to this legacy MSR -- see rdmsr
1674 * counterpart for further detail.
1675 */
1676 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1677 break;
2b036c6b
BO		 1678 case MSR_AMD64_OSVW_ID_LENGTH:
1679 if (!guest_cpuid_has_osvw(vcpu))
1680 return 1;
1681 vcpu->arch.osvw.length = data;
1682 break;
1683 case MSR_AMD64_OSVW_STATUS:
1684 if (!guest_cpuid_has_osvw(vcpu))
1685 return 1;
1686 vcpu->arch.osvw.status = data;
1687 break;
15c4a640 1688 default:
ffde22ac
ES		 1689 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1690 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1691 if (kvm_pmu_msr(vcpu, msr))
1692 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068
AP		 1693 if (!ignore_msrs) {
1694 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1695 msr, data);
1696 return 1;
1697 } else {
1698 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1699 msr, data);
1700 break;
1701 }
15c4a640
CO		 1702 }
1703 return 0;
1704}
1705EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1706
1707
1708/*
1709 * Reads an msr value (of 'msr_index') into 'pdata'.
1710 * Returns 0 on success, non-0 otherwise.
1711 * Assumes vcpu_load() was already called.
1712 */
1713int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1714{
1715 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1716}
1717
9ba075a6
AK		 1718static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1719{
0bed3b56
SY		 1720 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1721
9ba075a6
AK		 1722 if (!msr_mtrr_valid(msr))
1723 return 1;
1724
0bed3b56
SY		 1725 if (msr == MSR_MTRRdefType)
1726 *pdata = vcpu->arch.mtrr_state.def_type +
1727 (vcpu->arch.mtrr_state.enabled << 10);
1728 else if (msr == MSR_MTRRfix64K_00000)
1729 *pdata = p[0];
1730 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1731 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1732 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1733 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1734 else if (msr == MSR_IA32_CR_PAT)
1735 *pdata = vcpu->arch.pat;
1736 else { /* Variable MTRRs */
1737 int idx, is_mtrr_mask;
1738 u64 *pt;
1739
1740 idx = (msr - 0x200) / 2;
1741 is_mtrr_mask = msr - 0x200 - 2 * idx;
1742 if (!is_mtrr_mask)
1743 pt =
1744 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1745 else
1746 pt =
1747 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1748 *pdata = *pt;
1749 }
1750
9ba075a6
AK		 1751 return 0;
1752}
1753
890ca9ae 1754static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1755{
1756 u64 data;
890ca9ae
HY		 1757 u64 mcg_cap = vcpu->arch.mcg_cap;
1758 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1759
1760 switch (msr) {
15c4a640
CO		 1761 case MSR_IA32_P5_MC_ADDR:
1762 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1763 data = 0;
1764 break;
15c4a640 1765 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1766 data = vcpu->arch.mcg_cap;
1767 break;
c7ac679c 1768 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1769 if (!(mcg_cap & MCG_CTL_P))
1770 return 1;
1771 data = vcpu->arch.mcg_ctl;
1772 break;
1773 case MSR_IA32_MCG_STATUS:
1774 data = vcpu->arch.mcg_status;
1775 break;
1776 default:
1777 if (msr >= MSR_IA32_MC0_CTL &&
1778 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1779 u32 offset = msr - MSR_IA32_MC0_CTL;
1780 data = vcpu->arch.mce_banks[offset];
1781 break;
1782 }
1783 return 1;
1784 }
1785 *pdata = data;
1786 return 0;
1787}
1788
55cd8e5a
GN		 1789static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1790{
1791 u64 data = 0;
1792 struct kvm *kvm = vcpu->kvm;
1793
1794 switch (msr) {
1795 case HV_X64_MSR_GUEST_OS_ID:
1796 data = kvm->arch.hv_guest_os_id;
1797 break;
1798 case HV_X64_MSR_HYPERCALL:
1799 data = kvm->arch.hv_hypercall;
1800 break;
1801 default:
1802 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1803 return 1;
1804 }
1805
1806 *pdata = data;
1807 return 0;
1808}
1809
1810static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1811{
1812 u64 data = 0;
1813
1814 switch (msr) {
1815 case HV_X64_MSR_VP_INDEX: {
1816 int r;
1817 struct kvm_vcpu *v;
1818 kvm_for_each_vcpu(r, v, vcpu->kvm)
1819 if (v == vcpu)
1820 data = r;
1821 break;
1822 }
10388a07
GN		 1823 case HV_X64_MSR_EOI:
1824 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1825 case HV_X64_MSR_ICR:
1826 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1827 case HV_X64_MSR_TPR:
1828 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1829 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1830 data = vcpu->arch.hv_vapic;
1831 break;
55cd8e5a
GN		 1832 default:
1833 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1834 return 1;
1835 }
1836 *pdata = data;
1837 return 0;
1838}
1839
890ca9ae
HY		 1840int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1841{
1842 u64 data;
1843
1844 switch (msr) {
890ca9ae 1845 case MSR_IA32_PLATFORM_ID:
15c4a640 1846 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1847 case MSR_IA32_DEBUGCTLMSR:
1848 case MSR_IA32_LASTBRANCHFROMIP:
1849 case MSR_IA32_LASTBRANCHTOIP:
1850 case MSR_IA32_LASTINTFROMIP:
1851 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1852 case MSR_K8_SYSCFG:
1853 case MSR_K7_HWCR:
61a6bd67 1854 case MSR_VM_HSAVE_PA:
9e699624 1855 case MSR_K7_EVNTSEL0:
1f3ee616 1856 case MSR_K7_PERFCTR0:
1fdbd48c 1857 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1858 case MSR_AMD64_NB_CFG:
f7c6d140 1859 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1860 data = 0;
1861 break;
5753785f
GN		 1862 case MSR_P6_PERFCTR0:
1863 case MSR_P6_PERFCTR1:
1864 case MSR_P6_EVNTSEL0:
1865 case MSR_P6_EVNTSEL1:
1866 if (kvm_pmu_msr(vcpu, msr))
1867 return kvm_pmu_get_msr(vcpu, msr, pdata);
1868 data = 0;
1869 break;
742bc670
MT		 1870 case MSR_IA32_UCODE_REV:
1871 data = 0x100000000ULL;
1872 break;
9ba075a6
AK		 1873 case MSR_MTRRcap:
1874 data = 0x500 | KVM_NR_VAR_MTRR;
1875 break;
1876 case 0x200 ... 0x2ff:
1877 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1878 case 0xcd: /* fsb frequency */
1879 data = 3;
1880 break;
7b914098
JS		 1881 /*
1882 * MSR_EBC_FREQUENCY_ID
1883 * Conservative value valid for even the basic CPU models.
1884 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1885 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1886 * and 266MHz for model 3, or 4. Set Core Clock
1887 * Frequency to System Bus Frequency Ratio to 1 (bits
1888 * 31:24) even though these are only valid for CPU
1889 * models > 2, however guests may end up dividing or
1890 * multiplying by zero otherwise.
1891 */
1892 case MSR_EBC_FREQUENCY_ID:
1893 data = 1 << 24;
1894 break;
15c4a640
CO		 1895 case MSR_IA32_APICBASE:
1896 data = kvm_get_apic_base(vcpu);
1897 break;
0105d1a5
GN		 1898 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1899 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1900 break;
a3e06bbe
LJ		 1901 case MSR_IA32_TSCDEADLINE:
1902 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1903 break;
15c4a640 1904 case MSR_IA32_MISC_ENABLE:
ad312c7c 1905 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1906 break;
847f0ad8
AG		 1907 case MSR_IA32_PERF_STATUS:
1908 /* TSC increment by tick */
1909 data = 1000ULL;
1910 /* CPU multiplier */
1911 data |= (((uint64_t)4ULL) << 40);
1912 break;
15c4a640 1913 case MSR_EFER:
f6801dff 1914 data = vcpu->arch.efer;
15c4a640 1915 break;
18068523 1916 case MSR_KVM_WALL_CLOCK:
11c6bffa 1917 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1918 data = vcpu->kvm->arch.wall_clock;
1919 break;
1920 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1921 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1922 data = vcpu->arch.time;
1923 break;
344d9588
GN		 1924 case MSR_KVM_ASYNC_PF_EN:
1925 data = vcpu->arch.apf.msr_val;
1926 break;
c9aaa895
GC		 1927 case MSR_KVM_STEAL_TIME:
1928 data = vcpu->arch.st.msr_val;
1929 break;
890ca9ae
HY		 1930 case MSR_IA32_P5_MC_ADDR:
1931 case MSR_IA32_P5_MC_TYPE:
1932 case MSR_IA32_MCG_CAP:
1933 case MSR_IA32_MCG_CTL:
1934 case MSR_IA32_MCG_STATUS:
1935 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1936 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1937 case MSR_K7_CLK_CTL:
1938 /*
1939 * Provide expected ramp-up count for K7. All other
1940 * are set to zero, indicating minimum divisors for
1941 * every field.
1942 *
1943 * This prevents guest kernels on AMD host with CPU
1944 * type 6, model 8 and higher from exploding due to
1945 * the rdmsr failing.
1946 */
1947 data = 0x20000000;
1948 break;
55cd8e5a
GN		 1949 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1950 if (kvm_hv_msr_partition_wide(msr)) {
1951 int r;
1952 mutex_lock(&vcpu->kvm->lock);
1953 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1954 mutex_unlock(&vcpu->kvm->lock);
1955 return r;
1956 } else
1957 return get_msr_hyperv(vcpu, msr, pdata);
1958 break;
91c9c3ed 1959 case MSR_IA32_BBL_CR_CTL3:
1960 /* This legacy MSR exists but isn't fully documented in current
1961 * silicon. It is however accessed by winxp in very narrow
1962 * scenarios where it sets bit #19, itself documented as
1963 * a "reserved" bit. Best effort attempt to source coherent
1964 * read data here should the balance of the register be
1965 * interpreted by the guest:
1966 *
1967 * L2 cache control register 3: 64GB range, 256KB size,
1968 * enabled, latency 0x1, configured
1969 */
1970 data = 0xbe702111;
1971 break;
2b036c6b
BO		 1972 case MSR_AMD64_OSVW_ID_LENGTH:
1973 if (!guest_cpuid_has_osvw(vcpu))
1974 return 1;
1975 data = vcpu->arch.osvw.length;
1976 break;
1977 case MSR_AMD64_OSVW_STATUS:
1978 if (!guest_cpuid_has_osvw(vcpu))
1979 return 1;
1980 data = vcpu->arch.osvw.status;
1981 break;
15c4a640 1982 default:
f5132b01
GN		 1983 if (kvm_pmu_msr(vcpu, msr))
1984 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068
AP		 1985 if (!ignore_msrs) {
1986 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1987 return 1;
1988 } else {
1989 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1990 data = 0;
1991 }
1992 break;
15c4a640
CO		 1993 }
1994 *pdata = data;
1995 return 0;
1996}
1997EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1998
313a3dc7
CO		 1999/*
2000 * Read or write a bunch of msrs. All parameters are kernel addresses.
2001 *
2002 * @return number of msrs set successfully.
2003 */
2004static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2005 struct kvm_msr_entry *entries,
2006 int (*do_msr)(struct kvm_vcpu *vcpu,
2007 unsigned index, u64 *data))
2008{
f656ce01 2009 int i, idx;
313a3dc7 2010
f656ce01 2011 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2012 for (i = 0; i < msrs->nmsrs; ++i)
2013 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2014 break;
f656ce01 2015 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2016
313a3dc7
CO		 2017 return i;
2018}
2019
2020/*
2021 * Read or write a bunch of msrs. Parameters are user addresses.
2022 *
2023 * @return number of msrs set successfully.
2024 */
2025static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2026 int (*do_msr)(struct kvm_vcpu *vcpu,
2027 unsigned index, u64 *data),
2028 int writeback)
2029{
2030 struct kvm_msrs msrs;
2031 struct kvm_msr_entry *entries;
2032 int r, n;
2033 unsigned size;
2034
2035 r = -EFAULT;
2036 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2037 goto out;
2038
2039 r = -E2BIG;
2040 if (msrs.nmsrs >= MAX_IO_MSRS)
2041 goto out;
2042
313a3dc7 2043 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2044 entries = memdup_user(user_msrs->entries, size);
2045 if (IS_ERR(entries)) {
2046 r = PTR_ERR(entries);
313a3dc7 2047 goto out;
ff5c2c03 2048 }
313a3dc7
CO		 2049
2050 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2051 if (r < 0)
2052 goto out_free;
2053
2054 r = -EFAULT;
2055 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2056 goto out_free;
2057
2058 r = n;
2059
2060out_free:
7a73c028 2061 kfree(entries);
313a3dc7
CO		 2062out:
2063 return r;
2064}
2065
018d00d2
ZX		 2066int kvm_dev_ioctl_check_extension(long ext)
2067{
2068 int r;
2069
2070 switch (ext) {
2071 case KVM_CAP_IRQCHIP:
2072 case KVM_CAP_HLT:
2073 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2074 case KVM_CAP_SET_TSS_ADDR:
07716717 2075 case KVM_CAP_EXT_CPUID:
c8076604 2076 case KVM_CAP_CLOCKSOURCE:
7837699f 2077 case KVM_CAP_PIT:
a28e4f5a 2078 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2079 case KVM_CAP_MP_STATE:
ed848624 2080 case KVM_CAP_SYNC_MMU:
a355c85c 2081 case KVM_CAP_USER_NMI:
52d939a0 2082 case KVM_CAP_REINJECT_CONTROL:
4925663a 2083 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2084 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2085 case KVM_CAP_IRQFD:
d34e6b17 2086 case KVM_CAP_IOEVENTFD:
c5ff41ce 2087 case KVM_CAP_PIT2:
e9f42757 2088 case KVM_CAP_PIT_STATE2:
b927a3ce 2089 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2090 case KVM_CAP_XEN_HVM:
afbcf7ab 2091 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2092 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2093 case KVM_CAP_HYPERV:
10388a07 2094 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2095 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2096 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2097 case KVM_CAP_DEBUGREGS:
d2be1651 2098 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2099 case KVM_CAP_XSAVE:
344d9588 2100 case KVM_CAP_ASYNC_PF:
92a1f12d 2101 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2102 r = 1;
2103 break;
542472b5
LV		 2104 case KVM_CAP_COALESCED_MMIO:
2105 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2106 break;
774ead3a
AK		 2107 case KVM_CAP_VAPIC:
2108 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2109 break;
f725230a 2110 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2111 r = KVM_SOFT_MAX_VCPUS;
2112 break;
2113 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2114 r = KVM_MAX_VCPUS;
2115 break;
a988b910
AK		 2116 case KVM_CAP_NR_MEMSLOTS:
2117 r = KVM_MEMORY_SLOTS;
2118 break;
a68a6a72
MT		 2119 case KVM_CAP_PV_MMU: /* obsolete */
2120 r = 0;
2f333bcb 2121 break;
62c476c7 2122 case KVM_CAP_IOMMU:
a1b60c1c 2123 r = iommu_present(&pci_bus_type);
62c476c7 2124 break;
890ca9ae
HY		 2125 case KVM_CAP_MCE:
2126 r = KVM_MAX_MCE_BANKS;
2127 break;
2d5b5a66
SY		 2128 case KVM_CAP_XCRS:
2129 r = cpu_has_xsave;
2130 break;
92a1f12d
JR		 2131 case KVM_CAP_TSC_CONTROL:
2132 r = kvm_has_tsc_control;
2133 break;
4d25a066
JK		 2134 case KVM_CAP_TSC_DEADLINE_TIMER:
2135 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2136 break;
018d00d2
ZX		 2137 default:
2138 r = 0;
2139 break;
2140 }
2141 return r;
2142
2143}
2144
043405e1
CO		 2145long kvm_arch_dev_ioctl(struct file *filp,
2146 unsigned int ioctl, unsigned long arg)
2147{
2148 void __user *argp = (void __user *)arg;
2149 long r;
2150
2151 switch (ioctl) {
2152 case KVM_GET_MSR_INDEX_LIST: {
2153 struct kvm_msr_list __user *user_msr_list = argp;
2154 struct kvm_msr_list msr_list;
2155 unsigned n;
2156
2157 r = -EFAULT;
2158 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2159 goto out;
2160 n = msr_list.nmsrs;
2161 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2162 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2163 goto out;
2164 r = -E2BIG;
e125e7b6 2165 if (n < msr_list.nmsrs)
043405e1
CO		 2166 goto out;
2167 r = -EFAULT;
2168 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2169 num_msrs_to_save * sizeof(u32)))
2170 goto out;
e125e7b6 2171 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2172 &emulated_msrs,
2173 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2174 goto out;
2175 r = 0;
2176 break;
2177 }
674eea0f
AK		 2178 case KVM_GET_SUPPORTED_CPUID: {
2179 struct kvm_cpuid2 __user *cpuid_arg = argp;
2180 struct kvm_cpuid2 cpuid;
2181
2182 r = -EFAULT;
2183 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2184 goto out;
2185 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2186 cpuid_arg->entries);
674eea0f
AK		 2187 if (r)
2188 goto out;
2189
2190 r = -EFAULT;
2191 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2192 goto out;
2193 r = 0;
2194 break;
2195 }
890ca9ae
HY		 2196 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2197 u64 mce_cap;
2198
2199 mce_cap = KVM_MCE_CAP_SUPPORTED;
2200 r = -EFAULT;
2201 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2202 goto out;
2203 r = 0;
2204 break;
2205 }
043405e1
CO		 2206 default:
2207 r = -EINVAL;
2208 }
2209out:
2210 return r;
2211}
2212
f5f48ee1
SY		 2213static void wbinvd_ipi(void *garbage)
2214{
2215 wbinvd();
2216}
2217
2218static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2219{
2220 return vcpu->kvm->arch.iommu_domain &&
2221 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2222}
2223
313a3dc7
CO		 2224void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2225{
f5f48ee1
SY		 2226 /* Address WBINVD may be executed by guest */
2227 if (need_emulate_wbinvd(vcpu)) {
2228 if (kvm_x86_ops->has_wbinvd_exit())
2229 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2230 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2231 smp_call_function_single(vcpu->cpu,
2232 wbinvd_ipi, NULL, 1);
2233 }
2234
313a3dc7 2235 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2236 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2237 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2238 s64 tsc_delta;
2239 u64 tsc;
2240
d5c1785d 2241 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
8f6055cb
JR		 2242 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2243 tsc - vcpu->arch.last_guest_tsc;
2244
e48672fa
ZA		 2245 if (tsc_delta < 0)
2246 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2247 if (check_tsc_unstable()) {
e48672fa 2248 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2249 vcpu->arch.tsc_catchup = 1;
c285545f 2250 }
1aa8ceef 2251 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2252 if (vcpu->cpu != cpu)
2253 kvm_migrate_timers(vcpu);
e48672fa 2254 vcpu->cpu = cpu;
6b7d7e76 2255 }
c9aaa895
GC		 2256
2257 accumulate_steal_time(vcpu);
2258 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2259}
2260
2261void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2262{
02daab21 2263 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2264 kvm_put_guest_fpu(vcpu);
d5c1785d 2265 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
313a3dc7
CO		 2266}
2267
313a3dc7
CO		 2268static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2269 struct kvm_lapic_state *s)
2270{
ad312c7c 2271 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2272
2273 return 0;
2274}
2275
2276static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2277 struct kvm_lapic_state *s)
2278{
ad312c7c 2279 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2280 kvm_apic_post_state_restore(vcpu);
cb142eb7 2281 update_cr8_intercept(vcpu);
313a3dc7
CO		 2282
2283 return 0;
2284}
2285
f77bc6a4
ZX		 2286static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2287 struct kvm_interrupt *irq)
2288{
2289 if (irq->irq < 0 || irq->irq >= 256)
2290 return -EINVAL;
2291 if (irqchip_in_kernel(vcpu->kvm))
2292 return -ENXIO;
f77bc6a4 2293
66fd3f7f 2294 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2295 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2296
f77bc6a4
ZX		 2297 return 0;
2298}
2299
c4abb7c9
JK		 2300static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2301{
c4abb7c9 2302 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2303
2304 return 0;
2305}
2306
b209749f
AK		 2307static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2308 struct kvm_tpr_access_ctl *tac)
2309{
2310 if (tac->flags)
2311 return -EINVAL;
2312 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2313 return 0;
2314}
2315
890ca9ae
HY		 2316static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2317 u64 mcg_cap)
2318{
2319 int r;
2320 unsigned bank_num = mcg_cap & 0xff, bank;
2321
2322 r = -EINVAL;
a9e38c3e 2323 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2324 goto out;
2325 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2326 goto out;
2327 r = 0;
2328 vcpu->arch.mcg_cap = mcg_cap;
2329 /* Init IA32_MCG_CTL to all 1s */
2330 if (mcg_cap & MCG_CTL_P)
2331 vcpu->arch.mcg_ctl = ~(u64)0;
2332 /* Init IA32_MCi_CTL to all 1s */
2333 for (bank = 0; bank < bank_num; bank++)
2334 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2335out:
2336 return r;
2337}
2338
2339static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2340 struct kvm_x86_mce *mce)
2341{
2342 u64 mcg_cap = vcpu->arch.mcg_cap;
2343 unsigned bank_num = mcg_cap & 0xff;
2344 u64 *banks = vcpu->arch.mce_banks;
2345
2346 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2347 return -EINVAL;
2348 /*
2349 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2350 * reporting is disabled
2351 */
2352 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2353 vcpu->arch.mcg_ctl != ~(u64)0)
2354 return 0;
2355 banks += 4 * mce->bank;
2356 /*
2357 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2358 * reporting is disabled for the bank
2359 */
2360 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2361 return 0;
2362 if (mce->status & MCI_STATUS_UC) {
2363 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2364 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2365 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2366 return 0;
2367 }
2368 if (banks[1] & MCI_STATUS_VAL)
2369 mce->status |= MCI_STATUS_OVER;
2370 banks[2] = mce->addr;
2371 banks[3] = mce->misc;
2372 vcpu->arch.mcg_status = mce->mcg_status;
2373 banks[1] = mce->status;
2374 kvm_queue_exception(vcpu, MC_VECTOR);
2375 } else if (!(banks[1] & MCI_STATUS_VAL)
2376 || !(banks[1] & MCI_STATUS_UC)) {
2377 if (banks[1] & MCI_STATUS_VAL)
2378 mce->status |= MCI_STATUS_OVER;
2379 banks[2] = mce->addr;
2380 banks[3] = mce->misc;
2381 banks[1] = mce->status;
2382 } else
2383 banks[1] |= MCI_STATUS_OVER;
2384 return 0;
2385}
2386
3cfc3092
JK		 2387static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2388 struct kvm_vcpu_events *events)
2389{
7460fb4a 2390 process_nmi(vcpu);
03b82a30
JK		 2391 events->exception.injected =
2392 vcpu->arch.exception.pending &&
2393 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2394 events->exception.nr = vcpu->arch.exception.nr;
2395 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2396 events->exception.pad = 0;
3cfc3092
JK		 2397 events->exception.error_code = vcpu->arch.exception.error_code;
2398
03b82a30
JK		 2399 events->interrupt.injected =
2400 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2401 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2402 events->interrupt.soft = 0;
48005f64
JK		 2403 events->interrupt.shadow =
2404 kvm_x86_ops->get_interrupt_shadow(vcpu,
2405 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2406
2407 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2408 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2409 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2410 events->nmi.pad = 0;
3cfc3092
JK		 2411
2412 events->sipi_vector = vcpu->arch.sipi_vector;
2413
dab4b911 2414 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2415 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2416 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2417 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2418}
2419
2420static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2421 struct kvm_vcpu_events *events)
2422{
dab4b911 2423 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2424 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2425 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2426 return -EINVAL;
2427
7460fb4a 2428 process_nmi(vcpu);
3cfc3092
JK		 2429 vcpu->arch.exception.pending = events->exception.injected;
2430 vcpu->arch.exception.nr = events->exception.nr;
2431 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2432 vcpu->arch.exception.error_code = events->exception.error_code;
2433
2434 vcpu->arch.interrupt.pending = events->interrupt.injected;
2435 vcpu->arch.interrupt.nr = events->interrupt.nr;
2436 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2437 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2438 kvm_x86_ops->set_interrupt_shadow(vcpu,
2439 events->interrupt.shadow);
3cfc3092
JK		 2440
2441 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2442 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2443 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2444 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2445
dab4b911
JK		 2446 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2447 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2448
3842d135
AK		 2449 kvm_make_request(KVM_REQ_EVENT, vcpu);
2450
3cfc3092
JK		 2451 return 0;
2452}
2453
a1efbe77
JK		 2454static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2455 struct kvm_debugregs *dbgregs)
2456{
a1efbe77
JK		 2457 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2458 dbgregs->dr6 = vcpu->arch.dr6;
2459 dbgregs->dr7 = vcpu->arch.dr7;
2460 dbgregs->flags = 0;
97e69aa6 2461 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2462}
2463
2464static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2465 struct kvm_debugregs *dbgregs)
2466{
2467 if (dbgregs->flags)
2468 return -EINVAL;
2469
a1efbe77
JK		 2470 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2471 vcpu->arch.dr6 = dbgregs->dr6;
2472 vcpu->arch.dr7 = dbgregs->dr7;
2473
a1efbe77
JK		 2474 return 0;
2475}
2476
2d5b5a66
SY		 2477static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2478 struct kvm_xsave *guest_xsave)
2479{
2480 if (cpu_has_xsave)
2481 memcpy(guest_xsave->region,
2482 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2483 xstate_size);
2d5b5a66
SY		 2484 else {
2485 memcpy(guest_xsave->region,
2486 &vcpu->arch.guest_fpu.state->fxsave,
2487 sizeof(struct i387_fxsave_struct));
2488 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2489 XSTATE_FPSSE;
2490 }
2491}
2492
2493static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2494 struct kvm_xsave *guest_xsave)
2495{
2496 u64 xstate_bv =
2497 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2498
2499 if (cpu_has_xsave)
2500 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2501 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2502 else {
2503 if (xstate_bv & ~XSTATE_FPSSE)
2504 return -EINVAL;
2505 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2506 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2507 }
2508 return 0;
2509}
2510
2511static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2512 struct kvm_xcrs *guest_xcrs)
2513{
2514 if (!cpu_has_xsave) {
2515 guest_xcrs->nr_xcrs = 0;
2516 return;
2517 }
2518
2519 guest_xcrs->nr_xcrs = 1;
2520 guest_xcrs->flags = 0;
2521 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2522 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2523}
2524
2525static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2526 struct kvm_xcrs *guest_xcrs)
2527{
2528 int i, r = 0;
2529
2530 if (!cpu_has_xsave)
2531 return -EINVAL;
2532
2533 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2534 return -EINVAL;
2535
2536 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2537 /* Only support XCR0 currently */
2538 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2539 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2540 guest_xcrs->xcrs[0].value);
2541 break;
2542 }
2543 if (r)
2544 r = -EINVAL;
2545 return r;
2546}
2547
313a3dc7
CO		 2548long kvm_arch_vcpu_ioctl(struct file *filp,
2549 unsigned int ioctl, unsigned long arg)
2550{
2551 struct kvm_vcpu *vcpu = filp->private_data;
2552 void __user *argp = (void __user *)arg;
2553 int r;
d1ac91d8
AK		 2554 union {
2555 struct kvm_lapic_state *lapic;
2556 struct kvm_xsave *xsave;
2557 struct kvm_xcrs *xcrs;
2558 void *buffer;
2559 } u;
2560
2561 u.buffer = NULL;
313a3dc7
CO		 2562 switch (ioctl) {
2563 case KVM_GET_LAPIC: {
2204ae3c
MT		 2564 r = -EINVAL;
2565 if (!vcpu->arch.apic)
2566 goto out;
d1ac91d8 2567 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2568
b772ff36 2569 r = -ENOMEM;
d1ac91d8 2570 if (!u.lapic)
b772ff36 2571 goto out;
d1ac91d8 2572 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2573 if (r)
2574 goto out;
2575 r = -EFAULT;
d1ac91d8 2576 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2577 goto out;
2578 r = 0;
2579 break;
2580 }
2581 case KVM_SET_LAPIC: {
2204ae3c
MT		 2582 r = -EINVAL;
2583 if (!vcpu->arch.apic)
2584 goto out;
ff5c2c03
SL		 2585 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2586 if (IS_ERR(u.lapic)) {
2587 r = PTR_ERR(u.lapic);
313a3dc7 2588 goto out;
ff5c2c03
SL		 2589 }
2590
d1ac91d8 2591 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2592 if (r)
2593 goto out;
2594 r = 0;
2595 break;
2596 }
f77bc6a4
ZX		 2597 case KVM_INTERRUPT: {
2598 struct kvm_interrupt irq;
2599
2600 r = -EFAULT;
2601 if (copy_from_user(&irq, argp, sizeof irq))
2602 goto out;
2603 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2604 if (r)
2605 goto out;
2606 r = 0;
2607 break;
2608 }
c4abb7c9
JK		 2609 case KVM_NMI: {
2610 r = kvm_vcpu_ioctl_nmi(vcpu);
2611 if (r)
2612 goto out;
2613 r = 0;
2614 break;
2615 }
313a3dc7
CO		 2616 case KVM_SET_CPUID: {
2617 struct kvm_cpuid __user *cpuid_arg = argp;
2618 struct kvm_cpuid cpuid;
2619
2620 r = -EFAULT;
2621 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2622 goto out;
2623 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2624 if (r)
2625 goto out;
2626 break;
2627 }
07716717
DK		 2628 case KVM_SET_CPUID2: {
2629 struct kvm_cpuid2 __user *cpuid_arg = argp;
2630 struct kvm_cpuid2 cpuid;
2631
2632 r = -EFAULT;
2633 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2634 goto out;
2635 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2636 cpuid_arg->entries);
07716717
DK		 2637 if (r)
2638 goto out;
2639 break;
2640 }
2641 case KVM_GET_CPUID2: {
2642 struct kvm_cpuid2 __user *cpuid_arg = argp;
2643 struct kvm_cpuid2 cpuid;
2644
2645 r = -EFAULT;
2646 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2647 goto out;
2648 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2649 cpuid_arg->entries);
07716717
DK		 2650 if (r)
2651 goto out;
2652 r = -EFAULT;
2653 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2654 goto out;
2655 r = 0;
2656 break;
2657 }
313a3dc7
CO		 2658 case KVM_GET_MSRS:
2659 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2660 break;
2661 case KVM_SET_MSRS:
2662 r = msr_io(vcpu, argp, do_set_msr, 0);
2663 break;
b209749f
AK		 2664 case KVM_TPR_ACCESS_REPORTING: {
2665 struct kvm_tpr_access_ctl tac;
2666
2667 r = -EFAULT;
2668 if (copy_from_user(&tac, argp, sizeof tac))
2669 goto out;
2670 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2671 if (r)
2672 goto out;
2673 r = -EFAULT;
2674 if (copy_to_user(argp, &tac, sizeof tac))
2675 goto out;
2676 r = 0;
2677 break;
2678 };
b93463aa
AK		 2679 case KVM_SET_VAPIC_ADDR: {
2680 struct kvm_vapic_addr va;
2681
2682 r = -EINVAL;
2683 if (!irqchip_in_kernel(vcpu->kvm))
2684 goto out;
2685 r = -EFAULT;
2686 if (copy_from_user(&va, argp, sizeof va))
2687 goto out;
2688 r = 0;
2689 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2690 break;
2691 }
890ca9ae
HY		 2692 case KVM_X86_SETUP_MCE: {
2693 u64 mcg_cap;
2694
2695 r = -EFAULT;
2696 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2697 goto out;
2698 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2699 break;
2700 }
2701 case KVM_X86_SET_MCE: {
2702 struct kvm_x86_mce mce;
2703
2704 r = -EFAULT;
2705 if (copy_from_user(&mce, argp, sizeof mce))
2706 goto out;
2707 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2708 break;
2709 }
3cfc3092
JK		 2710 case KVM_GET_VCPU_EVENTS: {
2711 struct kvm_vcpu_events events;
2712
2713 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2714
2715 r = -EFAULT;
2716 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2717 break;
2718 r = 0;
2719 break;
2720 }
2721 case KVM_SET_VCPU_EVENTS: {
2722 struct kvm_vcpu_events events;
2723
2724 r = -EFAULT;
2725 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2726 break;
2727
2728 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2729 break;
2730 }
a1efbe77
JK		 2731 case KVM_GET_DEBUGREGS: {
2732 struct kvm_debugregs dbgregs;
2733
2734 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2735
2736 r = -EFAULT;
2737 if (copy_to_user(argp, &dbgregs,
2738 sizeof(struct kvm_debugregs)))
2739 break;
2740 r = 0;
2741 break;
2742 }
2743 case KVM_SET_DEBUGREGS: {
2744 struct kvm_debugregs dbgregs;
2745
2746 r = -EFAULT;
2747 if (copy_from_user(&dbgregs, argp,
2748 sizeof(struct kvm_debugregs)))
2749 break;
2750
2751 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2752 break;
2753 }
2d5b5a66 2754 case KVM_GET_XSAVE: {
d1ac91d8 2755 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2756 r = -ENOMEM;
d1ac91d8 2757 if (!u.xsave)
2d5b5a66
SY		 2758 break;
2759
d1ac91d8 2760 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2761
2762 r = -EFAULT;
d1ac91d8 2763 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2764 break;
2765 r = 0;
2766 break;
2767 }
2768 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2769 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2770 if (IS_ERR(u.xsave)) {
2771 r = PTR_ERR(u.xsave);
2772 goto out;
2773 }
2d5b5a66 2774
d1ac91d8 2775 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2776 break;
2777 }
2778 case KVM_GET_XCRS: {
d1ac91d8 2779 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2780 r = -ENOMEM;
d1ac91d8 2781 if (!u.xcrs)
2d5b5a66
SY		 2782 break;
2783
d1ac91d8 2784 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2785
2786 r = -EFAULT;
d1ac91d8 2787 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2788 sizeof(struct kvm_xcrs)))
2789 break;
2790 r = 0;
2791 break;
2792 }
2793 case KVM_SET_XCRS: {
ff5c2c03
SL		 2794 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2795 if (IS_ERR(u.xcrs)) {
2796 r = PTR_ERR(u.xcrs);
2797 goto out;
2798 }
2d5b5a66 2799
d1ac91d8 2800 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2801 break;
2802 }
92a1f12d
JR		 2803 case KVM_SET_TSC_KHZ: {
2804 u32 user_tsc_khz;
2805
2806 r = -EINVAL;
2807 if (!kvm_has_tsc_control)
2808 break;
2809
2810 user_tsc_khz = (u32)arg;
2811
2812 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2813 goto out;
2814
2815 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
2816
2817 r = 0;
2818 goto out;
2819 }
2820 case KVM_GET_TSC_KHZ: {
2821 r = -EIO;
2822 if (check_tsc_unstable())
2823 goto out;
2824
2825 r = vcpu_tsc_khz(vcpu);
2826
2827 goto out;
2828 }
313a3dc7
CO		 2829 default:
2830 r = -EINVAL;
2831 }
2832out:
d1ac91d8 2833 kfree(u.buffer);
313a3dc7
CO		 2834 return r;
2835}
2836
5b1c1493
CO		 2837int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2838{
2839 return VM_FAULT_SIGBUS;
2840}
2841
1fe779f8
CO		 2842static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2843{
2844 int ret;
2845
2846 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2847 return -1;
2848 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2849 return ret;
2850}
2851
b927a3ce
SY		 2852static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2853 u64 ident_addr)
2854{
2855 kvm->arch.ept_identity_map_addr = ident_addr;
2856 return 0;
2857}
2858
1fe779f8
CO		 2859static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2860 u32 kvm_nr_mmu_pages)
2861{
2862 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2863 return -EINVAL;
2864
79fac95e 2865 mutex_lock(&kvm->slots_lock);
7c8a83b7 2866 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2867
2868 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2869 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2870
7c8a83b7 2871 spin_unlock(&kvm->mmu_lock);
79fac95e 2872 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2873 return 0;
2874}
2875
2876static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2877{
39de71ec 2878 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2879}
2880
1fe779f8
CO		 2881static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2882{
2883 int r;
2884
2885 r = 0;
2886 switch (chip->chip_id) {
2887 case KVM_IRQCHIP_PIC_MASTER:
2888 memcpy(&chip->chip.pic,
2889 &pic_irqchip(kvm)->pics[0],
2890 sizeof(struct kvm_pic_state));
2891 break;
2892 case KVM_IRQCHIP_PIC_SLAVE:
2893 memcpy(&chip->chip.pic,
2894 &pic_irqchip(kvm)->pics[1],
2895 sizeof(struct kvm_pic_state));
2896 break;
2897 case KVM_IRQCHIP_IOAPIC:
eba0226b 2898 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2899 break;
2900 default:
2901 r = -EINVAL;
2902 break;
2903 }
2904 return r;
2905}
2906
2907static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2908{
2909 int r;
2910
2911 r = 0;
2912 switch (chip->chip_id) {
2913 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 2914 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2915 memcpy(&pic_irqchip(kvm)->pics[0],
2916 &chip->chip.pic,
2917 sizeof(struct kvm_pic_state));
f4f51050 2918 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2919 break;
2920 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 2921 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2922 memcpy(&pic_irqchip(kvm)->pics[1],
2923 &chip->chip.pic,
2924 sizeof(struct kvm_pic_state));
f4f51050 2925 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2926 break;
2927 case KVM_IRQCHIP_IOAPIC:
eba0226b 2928 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2929 break;
2930 default:
2931 r = -EINVAL;
2932 break;
2933 }
2934 kvm_pic_update_irq(pic_irqchip(kvm));
2935 return r;
2936}
2937
e0f63cb9
SY		 2938static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2939{
2940 int r = 0;
2941
894a9c55 2942 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2943 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2944 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2945 return r;
2946}
2947
2948static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2949{
2950 int r = 0;
2951
894a9c55 2952 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2953 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2954 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2955 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2956 return r;
2957}
2958
2959static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2960{
2961 int r = 0;
2962
2963 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2964 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2965 sizeof(ps->channels));
2966 ps->flags = kvm->arch.vpit->pit_state.flags;
2967 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 2968 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 2969 return r;
2970}
2971
2972static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2973{
2974 int r = 0, start = 0;
2975 u32 prev_legacy, cur_legacy;
2976 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2977 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2978 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2979 if (!prev_legacy && cur_legacy)
2980 start = 1;
2981 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2982 sizeof(kvm->arch.vpit->pit_state.channels));
2983 kvm->arch.vpit->pit_state.flags = ps->flags;
2984 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2985 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2986 return r;
2987}
2988
52d939a0
MT		 2989static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2990 struct kvm_reinject_control *control)
2991{
2992 if (!kvm->arch.vpit)
2993 return -ENXIO;
894a9c55 2994 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2995 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2996 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2997 return 0;
2998}
2999
95d4c16c
TY		 3000/**
3001 * write_protect_slot - write protect a slot for dirty logging
3002 * @kvm: the kvm instance
3003 * @memslot: the slot we protect
3004 * @dirty_bitmap: the bitmap indicating which pages are dirty
3005 * @nr_dirty_pages: the number of dirty pages
3006 *
3007 * We have two ways to find all sptes to protect:
3008 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
3009 * checks ones that have a spte mapping a page in the slot.
3010 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
3011 *
3012 * Generally speaking, if there are not so many dirty pages compared to the
3013 * number of shadow pages, we should use the latter.
3014 *
3015 * Note that letting others write into a page marked dirty in the old bitmap
3016 * by using the remaining tlb entry is not a problem. That page will become
3017 * write protected again when we flush the tlb and then be reported dirty to
3018 * the user space by copying the old bitmap.
3019 */
3020static void write_protect_slot(struct kvm *kvm,
3021 struct kvm_memory_slot *memslot,
3022 unsigned long *dirty_bitmap,
3023 unsigned long nr_dirty_pages)
3024{
3025 /* Not many dirty pages compared to # of shadow pages. */
3026 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
3027 unsigned long gfn_offset;
3028
3029 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
3030 unsigned long gfn = memslot->base_gfn + gfn_offset;
3031
3032 spin_lock(&kvm->mmu_lock);
3033 kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
3034 spin_unlock(&kvm->mmu_lock);
3035 }
3036 kvm_flush_remote_tlbs(kvm);
3037 } else {
3038 spin_lock(&kvm->mmu_lock);
3039 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
3040 spin_unlock(&kvm->mmu_lock);
3041 }
3042}
3043
5bb064dc
ZX		 3044/*
3045 * Get (and clear) the dirty memory log for a memory slot.
3046 */
3047int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3048 struct kvm_dirty_log *log)
3049{
7850ac54 3050 int r;
5bb064dc 3051 struct kvm_memory_slot *memslot;
95d4c16c 3052 unsigned long n, nr_dirty_pages;
5bb064dc 3053
79fac95e 3054 mutex_lock(&kvm->slots_lock);
5bb064dc 3055
b050b015
MT		 3056 r = -EINVAL;
3057 if (log->slot >= KVM_MEMORY_SLOTS)
3058 goto out;
3059
28a37544 3060 memslot = id_to_memslot(kvm->memslots, log->slot);
b050b015
MT		 3061 r = -ENOENT;
3062 if (!memslot->dirty_bitmap)
3063 goto out;
3064
87bf6e7d 3065 n = kvm_dirty_bitmap_bytes(memslot);
95d4c16c 3066 nr_dirty_pages = memslot->nr_dirty_pages;
b050b015 3067
5bb064dc 3068 /* If nothing is dirty, don't bother messing with page tables. */
95d4c16c 3069 if (nr_dirty_pages) {
b050b015 3070 struct kvm_memslots *slots, *old_slots;
28a37544 3071 unsigned long *dirty_bitmap, *dirty_bitmap_head;
b050b015 3072
28a37544
XG		 3073 dirty_bitmap = memslot->dirty_bitmap;
3074 dirty_bitmap_head = memslot->dirty_bitmap_head;
3075 if (dirty_bitmap == dirty_bitmap_head)
3076 dirty_bitmap_head += n / sizeof(long);
3077 memset(dirty_bitmap_head, 0, n);
b050b015 3078
914ebccd 3079 r = -ENOMEM;
cdfca7b3 3080 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
515a0127 3081 if (!slots)
914ebccd 3082 goto out;
cdfca7b3 3083
28a37544 3084 memslot = id_to_memslot(slots, log->slot);
95d4c16c 3085 memslot->nr_dirty_pages = 0;
28a37544 3086 memslot->dirty_bitmap = dirty_bitmap_head;
be593d62 3087 update_memslots(slots, NULL);
b050b015
MT		 3088
3089 old_slots = kvm->memslots;
3090 rcu_assign_pointer(kvm->memslots, slots);
3091 synchronize_srcu_expedited(&kvm->srcu);
b050b015 3092 kfree(old_slots);
914ebccd 3093
95d4c16c 3094 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
edde99ce 3095
914ebccd 3096 r = -EFAULT;
515a0127 3097 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3098 goto out;
914ebccd
TY		 3099 } else {
3100 r = -EFAULT;
3101 if (clear_user(log->dirty_bitmap, n))
3102 goto out;
5bb064dc 3103 }
b050b015 3104
5bb064dc
ZX		 3105 r = 0;
3106out:
79fac95e 3107 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3108 return r;
3109}
3110
1fe779f8
CO		 3111long kvm_arch_vm_ioctl(struct file *filp,
3112 unsigned int ioctl, unsigned long arg)
3113{
3114 struct kvm *kvm = filp->private_data;
3115 void __user *argp = (void __user *)arg;
367e1319 3116 int r = -ENOTTY;
f0d66275
DH		 3117 /*
3118 * This union makes it completely explicit to gcc-3.x
3119 * that these two variables' stack usage should be
3120 * combined, not added together.
3121 */
3122 union {
3123 struct kvm_pit_state ps;
e9f42757 3124 struct kvm_pit_state2 ps2;
c5ff41ce 3125 struct kvm_pit_config pit_config;
f0d66275 3126 } u;
1fe779f8
CO		 3127
3128 switch (ioctl) {
3129 case KVM_SET_TSS_ADDR:
3130 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3131 if (r < 0)
3132 goto out;
3133 break;
b927a3ce
SY		 3134 case KVM_SET_IDENTITY_MAP_ADDR: {
3135 u64 ident_addr;
3136
3137 r = -EFAULT;
3138 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3139 goto out;
3140 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3141 if (r < 0)
3142 goto out;
3143 break;
3144 }
1fe779f8
CO		 3145 case KVM_SET_NR_MMU_PAGES:
3146 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3147 if (r)
3148 goto out;
3149 break;
3150 case KVM_GET_NR_MMU_PAGES:
3151 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3152 break;
3ddea128
MT		 3153 case KVM_CREATE_IRQCHIP: {
3154 struct kvm_pic *vpic;
3155
3156 mutex_lock(&kvm->lock);
3157 r = -EEXIST;
3158 if (kvm->arch.vpic)
3159 goto create_irqchip_unlock;
1fe779f8 3160 r = -ENOMEM;
3ddea128
MT		 3161 vpic = kvm_create_pic(kvm);
3162 if (vpic) {
1fe779f8
CO		 3163 r = kvm_ioapic_init(kvm);
3164 if (r) {
175504cd 3165 mutex_lock(&kvm->slots_lock);
72bb2fcd 3166 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3167 &vpic->dev_master);
3168 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3169 &vpic->dev_slave);
3170 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3171 &vpic->dev_eclr);
175504cd 3172 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3173 kfree(vpic);
3174 goto create_irqchip_unlock;
1fe779f8
CO		 3175 }
3176 } else
3ddea128
MT		 3177 goto create_irqchip_unlock;
3178 smp_wmb();
3179 kvm->arch.vpic = vpic;
3180 smp_wmb();
399ec807
AK		 3181 r = kvm_setup_default_irq_routing(kvm);
3182 if (r) {
175504cd 3183 mutex_lock(&kvm->slots_lock);
3ddea128 3184 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3185 kvm_ioapic_destroy(kvm);
3186 kvm_destroy_pic(kvm);
3ddea128 3187 mutex_unlock(&kvm->irq_lock);
175504cd 3188 mutex_unlock(&kvm->slots_lock);
399ec807 3189 }
3ddea128
MT		 3190 create_irqchip_unlock:
3191 mutex_unlock(&kvm->lock);
1fe779f8 3192 break;
3ddea128 3193 }
7837699f 3194 case KVM_CREATE_PIT:
c5ff41ce
JK		 3195 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3196 goto create_pit;
3197 case KVM_CREATE_PIT2:
3198 r = -EFAULT;
3199 if (copy_from_user(&u.pit_config, argp,
3200 sizeof(struct kvm_pit_config)))
3201 goto out;
3202 create_pit:
79fac95e 3203 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3204 r = -EEXIST;
3205 if (kvm->arch.vpit)
3206 goto create_pit_unlock;
7837699f 3207 r = -ENOMEM;
c5ff41ce 3208 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3209 if (kvm->arch.vpit)
3210 r = 0;
269e05e4 3211 create_pit_unlock:
79fac95e 3212 mutex_unlock(&kvm->slots_lock);
7837699f 3213 break;
4925663a 3214 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3215 case KVM_IRQ_LINE: {
3216 struct kvm_irq_level irq_event;
3217
3218 r = -EFAULT;
3219 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3220 goto out;
160d2f6c 3221 r = -ENXIO;
1fe779f8 3222 if (irqchip_in_kernel(kvm)) {
4925663a 3223 __s32 status;
4925663a
GN		 3224 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3225 irq_event.irq, irq_event.level);
4925663a 3226 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3227 r = -EFAULT;
4925663a
GN		 3228 irq_event.status = status;
3229 if (copy_to_user(argp, &irq_event,
3230 sizeof irq_event))
3231 goto out;
3232 }
1fe779f8
CO		 3233 r = 0;
3234 }
3235 break;
3236 }
3237 case KVM_GET_IRQCHIP: {
3238 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3239 struct kvm_irqchip *chip;
1fe779f8 3240
ff5c2c03
SL		 3241 chip = memdup_user(argp, sizeof(*chip));
3242 if (IS_ERR(chip)) {
3243 r = PTR_ERR(chip);
1fe779f8 3244 goto out;
ff5c2c03
SL		 3245 }
3246
1fe779f8
CO		 3247 r = -ENXIO;
3248 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3249 goto get_irqchip_out;
3250 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3251 if (r)
f0d66275 3252 goto get_irqchip_out;
1fe779f8 3253 r = -EFAULT;
f0d66275
DH		 3254 if (copy_to_user(argp, chip, sizeof *chip))
3255 goto get_irqchip_out;
1fe779f8 3256 r = 0;
f0d66275
DH		 3257 get_irqchip_out:
3258 kfree(chip);
3259 if (r)
3260 goto out;
1fe779f8
CO		 3261 break;
3262 }
3263 case KVM_SET_IRQCHIP: {
3264 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3265 struct kvm_irqchip *chip;
1fe779f8 3266
ff5c2c03
SL		 3267 chip = memdup_user(argp, sizeof(*chip));
3268 if (IS_ERR(chip)) {
3269 r = PTR_ERR(chip);
1fe779f8 3270 goto out;
ff5c2c03
SL		 3271 }
3272
1fe779f8
CO		 3273 r = -ENXIO;
3274 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3275 goto set_irqchip_out;
3276 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3277 if (r)
f0d66275 3278 goto set_irqchip_out;
1fe779f8 3279 r = 0;
f0d66275
DH		 3280 set_irqchip_out:
3281 kfree(chip);
3282 if (r)
3283 goto out;
1fe779f8
CO		 3284 break;
3285 }
e0f63cb9 3286 case KVM_GET_PIT: {
e0f63cb9 3287 r = -EFAULT;
f0d66275 3288 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3289 goto out;
3290 r = -ENXIO;
3291 if (!kvm->arch.vpit)
3292 goto out;
f0d66275 3293 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3294 if (r)
3295 goto out;
3296 r = -EFAULT;
f0d66275 3297 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3298 goto out;
3299 r = 0;
3300 break;
3301 }
3302 case KVM_SET_PIT: {
e0f63cb9 3303 r = -EFAULT;
f0d66275 3304 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3305 goto out;
3306 r = -ENXIO;
3307 if (!kvm->arch.vpit)
3308 goto out;
f0d66275 3309 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3310 if (r)
3311 goto out;
3312 r = 0;
3313 break;
3314 }
e9f42757
BK		 3315 case KVM_GET_PIT2: {
3316 r = -ENXIO;
3317 if (!kvm->arch.vpit)
3318 goto out;
3319 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3320 if (r)
3321 goto out;
3322 r = -EFAULT;
3323 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3324 goto out;
3325 r = 0;
3326 break;
3327 }
3328 case KVM_SET_PIT2: {
3329 r = -EFAULT;
3330 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3331 goto out;
3332 r = -ENXIO;
3333 if (!kvm->arch.vpit)
3334 goto out;
3335 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3336 if (r)
3337 goto out;
3338 r = 0;
3339 break;
3340 }
52d939a0
MT		 3341 case KVM_REINJECT_CONTROL: {
3342 struct kvm_reinject_control control;
3343 r = -EFAULT;
3344 if (copy_from_user(&control, argp, sizeof(control)))
3345 goto out;
3346 r = kvm_vm_ioctl_reinject(kvm, &control);
3347 if (r)
3348 goto out;
3349 r = 0;
3350 break;
3351 }
ffde22ac
ES		 3352 case KVM_XEN_HVM_CONFIG: {
3353 r = -EFAULT;
3354 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3355 sizeof(struct kvm_xen_hvm_config)))
3356 goto out;
3357 r = -EINVAL;
3358 if (kvm->arch.xen_hvm_config.flags)
3359 goto out;
3360 r = 0;
3361 break;
3362 }
afbcf7ab 3363 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3364 struct kvm_clock_data user_ns;
3365 u64 now_ns;
3366 s64 delta;
3367
3368 r = -EFAULT;
3369 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3370 goto out;
3371
3372 r = -EINVAL;
3373 if (user_ns.flags)
3374 goto out;
3375
3376 r = 0;
395c6b0a 3377 local_irq_disable();
759379dd 3378 now_ns = get_kernel_ns();
afbcf7ab 3379 delta = user_ns.clock - now_ns;
395c6b0a 3380 local_irq_enable();
afbcf7ab
GC		 3381 kvm->arch.kvmclock_offset = delta;
3382 break;
3383 }
3384 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3385 struct kvm_clock_data user_ns;
3386 u64 now_ns;
3387
395c6b0a 3388 local_irq_disable();
759379dd 3389 now_ns = get_kernel_ns();
afbcf7ab 3390 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3391 local_irq_enable();
afbcf7ab 3392 user_ns.flags = 0;
97e69aa6 3393 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3394
3395 r = -EFAULT;
3396 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3397 goto out;
3398 r = 0;
3399 break;
3400 }
3401
1fe779f8
CO		 3402 default:
3403 ;
3404 }
3405out:
3406 return r;
3407}
3408
a16b043c 3409static void kvm_init_msr_list(void)
043405e1
CO		 3410{
3411 u32 dummy[2];
3412 unsigned i, j;
3413
e3267cbb
GC		 3414 /* skip the first msrs in the list. KVM-specific */
3415 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3416 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3417 continue;
3418 if (j < i)
3419 msrs_to_save[j] = msrs_to_save[i];
3420 j++;
3421 }
3422 num_msrs_to_save = j;
3423}
3424
bda9020e
MT		 3425static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3426 const void *v)
bbd9b64e 3427{
70252a10
AK		 3428 int handled = 0;
3429 int n;
3430
3431 do {
3432 n = min(len, 8);
3433 if (!(vcpu->arch.apic &&
3434 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3435 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3436 break;
3437 handled += n;
3438 addr += n;
3439 len -= n;
3440 v += n;
3441 } while (len);
bbd9b64e 3442
70252a10 3443 return handled;
bbd9b64e
CO		 3444}
3445
bda9020e 3446static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3447{
70252a10
AK		 3448 int handled = 0;
3449 int n;
3450
3451 do {
3452 n = min(len, 8);
3453 if (!(vcpu->arch.apic &&
3454 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3455 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3456 break;
3457 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3458 handled += n;
3459 addr += n;
3460 len -= n;
3461 v += n;
3462 } while (len);
bbd9b64e 3463
70252a10 3464 return handled;
bbd9b64e
CO		 3465}
3466
2dafc6c2
GN		 3467static void kvm_set_segment(struct kvm_vcpu *vcpu,
3468 struct kvm_segment *var, int seg)
3469{
3470 kvm_x86_ops->set_segment(vcpu, var, seg);
3471}
3472
3473void kvm_get_segment(struct kvm_vcpu *vcpu,
3474 struct kvm_segment *var, int seg)
3475{
3476 kvm_x86_ops->get_segment(vcpu, var, seg);
3477}
3478
e459e322 3479gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3480{
3481 gpa_t t_gpa;
ab9ae313 3482 struct x86_exception exception;
02f59dc9
JR		 3483
3484 BUG_ON(!mmu_is_nested(vcpu));
3485
3486 /* NPT walks are always user-walks */
3487 access |= PFERR_USER_MASK;
ab9ae313 3488 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3489
3490 return t_gpa;
3491}
3492
ab9ae313
AK		 3493gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3494 struct x86_exception *exception)
1871c602
GN		 3495{
3496 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3497 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3498}
3499
ab9ae313
AK		 3500 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3501 struct x86_exception *exception)
1871c602
GN		 3502{
3503 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3504 access |= PFERR_FETCH_MASK;
ab9ae313 3505 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3506}
3507
ab9ae313
AK		 3508gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3509 struct x86_exception *exception)
1871c602
GN		 3510{
3511 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3512 access |= PFERR_WRITE_MASK;
ab9ae313 3513 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3514}
3515
3516/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3517gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3518 struct x86_exception *exception)
1871c602 3519{
ab9ae313 3520 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3521}
3522
3523static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3524 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3525 struct x86_exception *exception)
bbd9b64e
CO		 3526{
3527 void *data = val;
10589a46 3528 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3529
3530 while (bytes) {
14dfe855 3531 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3532 exception);
bbd9b64e 3533 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3534 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3535 int ret;
3536
bcc55cba 3537 if (gpa == UNMAPPED_GVA)
ab9ae313 3538 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3539 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3540 if (ret < 0) {
c3cd7ffa 3541 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3542 goto out;
3543 }
bbd9b64e 3544
77c2002e
IE		 3545 bytes -= toread;
3546 data += toread;
3547 addr += toread;
bbd9b64e 3548 }
10589a46 3549out:
10589a46 3550 return r;
bbd9b64e 3551}
77c2002e 3552
1871c602 3553/* used for instruction fetching */
0f65dd70
AK		 3554static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3555 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3556 struct x86_exception *exception)
1871c602 3557{
0f65dd70 3558 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3559 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3560
1871c602 3561 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3562 access | PFERR_FETCH_MASK,
3563 exception);
1871c602
GN		 3564}
3565
064aea77 3566int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3567 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3568 struct x86_exception *exception)
1871c602 3569{
0f65dd70 3570 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3571 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3572
1871c602 3573 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3574 exception);
1871c602 3575}
064aea77 3576EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3577
0f65dd70
AK		 3578static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3579 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3580 struct x86_exception *exception)
1871c602 3581{
0f65dd70 3582 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3583 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3584}
3585
6a4d7550 3586int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3587 gva_t addr, void *val,
2dafc6c2 3588 unsigned int bytes,
bcc55cba 3589 struct x86_exception *exception)
77c2002e 3590{
0f65dd70 3591 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3592 void *data = val;
3593 int r = X86EMUL_CONTINUE;
3594
3595 while (bytes) {
14dfe855
JR		 3596 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3597 PFERR_WRITE_MASK,
ab9ae313 3598 exception);
77c2002e
IE		 3599 unsigned offset = addr & (PAGE_SIZE-1);
3600 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3601 int ret;
3602
bcc55cba 3603 if (gpa == UNMAPPED_GVA)
ab9ae313 3604 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3605 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3606 if (ret < 0) {
c3cd7ffa 3607 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3608 goto out;
3609 }
3610
3611 bytes -= towrite;
3612 data += towrite;
3613 addr += towrite;
3614 }
3615out:
3616 return r;
3617}
6a4d7550 3618EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3619
af7cc7d1
XG		 3620static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3621 gpa_t *gpa, struct x86_exception *exception,
3622 bool write)
3623{
3624 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3625
bebb106a
XG		 3626 if (vcpu_match_mmio_gva(vcpu, gva) &&
3627 check_write_user_access(vcpu, write, access,
3628 vcpu->arch.access)) {
3629 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3630 (gva & (PAGE_SIZE - 1));
4f022648 3631 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3632 return 1;
3633 }
3634
af7cc7d1
XG		 3635 if (write)
3636 access |= PFERR_WRITE_MASK;
3637
3638 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3639
3640 if (*gpa == UNMAPPED_GVA)
3641 return -1;
3642
3643 /* For APIC access vmexit */
3644 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3645 return 1;
3646
4f022648
XG		 3647 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3648 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3649 return 1;
4f022648 3650 }
bebb106a 3651
af7cc7d1
XG		 3652 return 0;
3653}
3654
3200f405 3655int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3656 const void *val, int bytes)
bbd9b64e
CO		 3657{
3658 int ret;
3659
3660 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3661 if (ret < 0)
bbd9b64e 3662 return 0;
f57f2ef5 3663 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3664 return 1;
3665}
3666
77d197b2
XG		 3667struct read_write_emulator_ops {
3668 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3669 int bytes);
3670 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3671 void *val, int bytes);
3672 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3673 int bytes, void *val);
3674 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3675 void *val, int bytes);
3676 bool write;
3677};
3678
3679static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3680{
3681 if (vcpu->mmio_read_completed) {
3682 memcpy(val, vcpu->mmio_data, bytes);
3683 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3684 vcpu->mmio_phys_addr, *(u64 *)val);
3685 vcpu->mmio_read_completed = 0;
3686 return 1;
3687 }
3688
3689 return 0;
3690}
3691
3692static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3693 void *val, int bytes)
3694{
3695 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3696}
3697
3698static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3699 void *val, int bytes)
3700{
3701 return emulator_write_phys(vcpu, gpa, val, bytes);
3702}
3703
3704static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3705{
3706 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3707 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3708}
3709
3710static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3711 void *val, int bytes)
3712{
3713 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3714 return X86EMUL_IO_NEEDED;
3715}
3716
3717static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3718 void *val, int bytes)
3719{
3720 memcpy(vcpu->mmio_data, val, bytes);
3721 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3722 return X86EMUL_CONTINUE;
3723}
3724
3725static struct read_write_emulator_ops read_emultor = {
3726 .read_write_prepare = read_prepare,
3727 .read_write_emulate = read_emulate,
3728 .read_write_mmio = vcpu_mmio_read,
3729 .read_write_exit_mmio = read_exit_mmio,
3730};
3731
3732static struct read_write_emulator_ops write_emultor = {
3733 .read_write_emulate = write_emulate,
3734 .read_write_mmio = write_mmio,
3735 .read_write_exit_mmio = write_exit_mmio,
3736 .write = true,
3737};
3738
22388a3c
XG		 3739static int emulator_read_write_onepage(unsigned long addr, void *val,
3740 unsigned int bytes,
3741 struct x86_exception *exception,
3742 struct kvm_vcpu *vcpu,
3743 struct read_write_emulator_ops *ops)
bbd9b64e 3744{
af7cc7d1
XG		 3745 gpa_t gpa;
3746 int handled, ret;
22388a3c
XG		 3747 bool write = ops->write;
3748
3749 if (ops->read_write_prepare &&
3750 ops->read_write_prepare(vcpu, val, bytes))
3751 return X86EMUL_CONTINUE;
10589a46 3752
22388a3c 3753 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3754
af7cc7d1 3755 if (ret < 0)
bbd9b64e 3756 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3757
3758 /* For APIC access vmexit */
af7cc7d1 3759 if (ret)
bbd9b64e
CO		 3760 goto mmio;
3761
22388a3c 3762 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3763 return X86EMUL_CONTINUE;
3764
3765mmio:
3766 /*
3767 * Is this MMIO handled locally?
3768 */
22388a3c 3769 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3770 if (handled == bytes)
bbd9b64e 3771 return X86EMUL_CONTINUE;
bbd9b64e 3772
70252a10
AK		 3773 gpa += handled;
3774 bytes -= handled;
3775 val += handled;
3776
bbd9b64e 3777 vcpu->mmio_needed = 1;
411c35b7
GN		 3778 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3779 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3780 vcpu->mmio_size = bytes;
3781 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 3782 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 3783 vcpu->mmio_index = 0;
bbd9b64e 3784
22388a3c 3785 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3786}
3787
22388a3c
XG		 3788int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3789 void *val, unsigned int bytes,
3790 struct x86_exception *exception,
3791 struct read_write_emulator_ops *ops)
bbd9b64e 3792{
0f65dd70
AK		 3793 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3794
bbd9b64e
CO		 3795 /* Crossing a page boundary? */
3796 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3797 int rc, now;
3798
3799 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3800 rc = emulator_read_write_onepage(addr, val, now, exception,
3801 vcpu, ops);
3802
bbd9b64e
CO		 3803 if (rc != X86EMUL_CONTINUE)
3804 return rc;
3805 addr += now;
3806 val += now;
3807 bytes -= now;
3808 }
22388a3c
XG		 3809
3810 return emulator_read_write_onepage(addr, val, bytes, exception,
3811 vcpu, ops);
3812}
3813
3814static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3815 unsigned long addr,
3816 void *val,
3817 unsigned int bytes,
3818 struct x86_exception *exception)
3819{
3820 return emulator_read_write(ctxt, addr, val, bytes,
3821 exception, &read_emultor);
3822}
3823
3824int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3825 unsigned long addr,
3826 const void *val,
3827 unsigned int bytes,
3828 struct x86_exception *exception)
3829{
3830 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3831 exception, &write_emultor);
bbd9b64e 3832}
bbd9b64e 3833
daea3e73
AK		 3834#define CMPXCHG_TYPE(t, ptr, old, new) \
3835 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3836
3837#ifdef CONFIG_X86_64
3838# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3839#else
3840# define CMPXCHG64(ptr, old, new) \
9749a6c0 3841 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3842#endif
3843
0f65dd70
AK		 3844static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3845 unsigned long addr,
bbd9b64e
CO		 3846 const void *old,
3847 const void *new,
3848 unsigned int bytes,
0f65dd70 3849 struct x86_exception *exception)
bbd9b64e 3850{
0f65dd70 3851 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3852 gpa_t gpa;
3853 struct page *page;
3854 char *kaddr;
3855 bool exchanged;
2bacc55c 3856
daea3e73
AK		 3857 /* guests cmpxchg8b have to be emulated atomically */
3858 if (bytes > 8 || (bytes & (bytes - 1)))
3859 goto emul_write;
10589a46 3860
daea3e73 3861 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3862
daea3e73
AK		 3863 if (gpa == UNMAPPED_GVA ||
3864 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3865 goto emul_write;
2bacc55c 3866
daea3e73
AK		 3867 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3868 goto emul_write;
72dc67a6 3869
daea3e73 3870 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3871 if (is_error_page(page)) {
3872 kvm_release_page_clean(page);
3873 goto emul_write;
3874 }
72dc67a6 3875
daea3e73
AK		 3876 kaddr = kmap_atomic(page, KM_USER0);
3877 kaddr += offset_in_page(gpa);
3878 switch (bytes) {
3879 case 1:
3880 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3881 break;
3882 case 2:
3883 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3884 break;
3885 case 4:
3886 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3887 break;
3888 case 8:
3889 exchanged = CMPXCHG64(kaddr, old, new);
3890 break;
3891 default:
3892 BUG();
2bacc55c 3893 }
daea3e73
AK		 3894 kunmap_atomic(kaddr, KM_USER0);
3895 kvm_release_page_dirty(page);
3896
3897 if (!exchanged)
3898 return X86EMUL_CMPXCHG_FAILED;
3899
f57f2ef5 3900 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3901
3902 return X86EMUL_CONTINUE;
4a5f48f6 3903
3200f405 3904emul_write:
daea3e73 3905 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3906
0f65dd70 3907 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3908}
3909
cf8f70bf
GN		 3910static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3911{
3912 /* TODO: String I/O for in kernel device */
3913 int r;
3914
3915 if (vcpu->arch.pio.in)
3916 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3917 vcpu->arch.pio.size, pd);
3918 else
3919 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3920 vcpu->arch.pio.port, vcpu->arch.pio.size,
3921 pd);
3922 return r;
3923}
3924
6f6fbe98
XG		 3925static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3926 unsigned short port, void *val,
3927 unsigned int count, bool in)
cf8f70bf 3928{
6f6fbe98 3929 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3930
3931 vcpu->arch.pio.port = port;
6f6fbe98 3932 vcpu->arch.pio.in = in;
7972995b 3933 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3934 vcpu->arch.pio.size = size;
3935
3936 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3937 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3938 return 1;
3939 }
3940
3941 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 3942 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 3943 vcpu->run->io.size = size;
3944 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3945 vcpu->run->io.count = count;
3946 vcpu->run->io.port = port;
3947
3948 return 0;
3949}
3950
6f6fbe98
XG		 3951static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
3952 int size, unsigned short port, void *val,
3953 unsigned int count)
cf8f70bf 3954{
ca1d4a9e 3955 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 3956 int ret;
ca1d4a9e 3957
6f6fbe98
XG		 3958 if (vcpu->arch.pio.count)
3959 goto data_avail;
cf8f70bf 3960
6f6fbe98
XG		 3961 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
3962 if (ret) {
3963data_avail:
3964 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3965 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3966 return 1;
3967 }
3968
cf8f70bf
GN		 3969 return 0;
3970}
3971
6f6fbe98
XG		 3972static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
3973 int size, unsigned short port,
3974 const void *val, unsigned int count)
3975{
3976 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3977
3978 memcpy(vcpu->arch.pio_data, val, size * count);
3979 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
3980}
3981
bbd9b64e
CO		 3982static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3983{
3984 return kvm_x86_ops->get_segment_base(vcpu, seg);
3985}
3986
3cb16fe7 3987static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 3988{
3cb16fe7 3989 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 3990}
3991
f5f48ee1
SY		 3992int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3993{
3994 if (!need_emulate_wbinvd(vcpu))
3995 return X86EMUL_CONTINUE;
3996
3997 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 3998 int cpu = get_cpu();
3999
4000 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4001 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4002 wbinvd_ipi, NULL, 1);
2eec7343 4003 put_cpu();
f5f48ee1 4004 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4005 } else
4006 wbinvd();
f5f48ee1
SY		 4007 return X86EMUL_CONTINUE;
4008}
4009EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4010
bcaf5cc5
AK		 4011static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4012{
4013 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4014}
4015
717746e3 4016int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4017{
717746e3 4018 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4019}
4020
717746e3 4021int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4022{
338dbc97 4023
717746e3 4024 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4025}
4026
52a46617 4027static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4028{
52a46617 4029 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4030}
4031
717746e3 4032static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4033{
717746e3 4034 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4035 unsigned long value;
4036
4037 switch (cr) {
4038 case 0:
4039 value = kvm_read_cr0(vcpu);
4040 break;
4041 case 2:
4042 value = vcpu->arch.cr2;
4043 break;
4044 case 3:
9f8fe504 4045 value = kvm_read_cr3(vcpu);
52a46617
GN		 4046 break;
4047 case 4:
4048 value = kvm_read_cr4(vcpu);
4049 break;
4050 case 8:
4051 value = kvm_get_cr8(vcpu);
4052 break;
4053 default:
4054 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4055 return 0;
4056 }
4057
4058 return value;
4059}
4060
717746e3 4061static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4062{
717746e3 4063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4064 int res = 0;
4065
52a46617
GN		 4066 switch (cr) {
4067 case 0:
49a9b07e 4068 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4069 break;
4070 case 2:
4071 vcpu->arch.cr2 = val;
4072 break;
4073 case 3:
2390218b 4074 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4075 break;
4076 case 4:
a83b29c6 4077 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4078 break;
4079 case 8:
eea1cff9 4080 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4081 break;
4082 default:
4083 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4084 res = -1;
52a46617 4085 }
0f12244f
GN		 4086
4087 return res;
52a46617
GN		 4088}
4089
717746e3 4090static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4091{
717746e3 4092 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4093}
4094
4bff1e86 4095static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4096{
4bff1e86 4097 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4098}
4099
4bff1e86 4100static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4101{
4bff1e86 4102 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4103}
4104
1ac9d0cf
AK		 4105static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4106{
4107 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4108}
4109
4110static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4111{
4112 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4113}
4114
4bff1e86
AK		 4115static unsigned long emulator_get_cached_segment_base(
4116 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4117{
4bff1e86 4118 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4119}
4120
1aa36616
AK		 4121static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4122 struct desc_struct *desc, u32 *base3,
4123 int seg)
2dafc6c2
GN		 4124{
4125 struct kvm_segment var;
4126
4bff1e86 4127 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4128 *selector = var.selector;
2dafc6c2
GN		 4129
4130 if (var.unusable)
4131 return false;
4132
4133 if (var.g)
4134 var.limit >>= 12;
4135 set_desc_limit(desc, var.limit);
4136 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4137#ifdef CONFIG_X86_64
4138 if (base3)
4139 *base3 = var.base >> 32;
4140#endif
2dafc6c2
GN		 4141 desc->type = var.type;
4142 desc->s = var.s;
4143 desc->dpl = var.dpl;
4144 desc->p = var.present;
4145 desc->avl = var.avl;
4146 desc->l = var.l;
4147 desc->d = var.db;
4148 desc->g = var.g;
4149
4150 return true;
4151}
4152
1aa36616
AK		 4153static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4154 struct desc_struct *desc, u32 base3,
4155 int seg)
2dafc6c2 4156{
4bff1e86 4157 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4158 struct kvm_segment var;
4159
1aa36616 4160 var.selector = selector;
2dafc6c2 4161 var.base = get_desc_base(desc);
5601d05b
GN		 4162#ifdef CONFIG_X86_64
4163 var.base |= ((u64)base3) << 32;
4164#endif
2dafc6c2
GN		 4165 var.limit = get_desc_limit(desc);
4166 if (desc->g)
4167 var.limit = (var.limit << 12) | 0xfff;
4168 var.type = desc->type;
4169 var.present = desc->p;
4170 var.dpl = desc->dpl;
4171 var.db = desc->d;
4172 var.s = desc->s;
4173 var.l = desc->l;
4174 var.g = desc->g;
4175 var.avl = desc->avl;
4176 var.present = desc->p;
4177 var.unusable = !var.present;
4178 var.padding = 0;
4179
4180 kvm_set_segment(vcpu, &var, seg);
4181 return;
4182}
4183
717746e3
AK		 4184static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4185 u32 msr_index, u64 *pdata)
4186{
4187 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4188}
4189
4190static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4191 u32 msr_index, u64 data)
4192{
4193 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4194}
4195
222d21aa
AK		 4196static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4197 u32 pmc, u64 *pdata)
4198{
4199 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4200}
4201
6c3287f7
AK		 4202static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4203{
4204 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4205}
4206
5037f6f3
AK		 4207static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4208{
4209 preempt_disable();
5197b808 4210 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4211 /*
4212 * CR0.TS may reference the host fpu state, not the guest fpu state,
4213 * so it may be clear at this point.
4214 */
4215 clts();
4216}
4217
4218static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4219{
4220 preempt_enable();
4221}
4222
2953538e 4223static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4224 struct x86_instruction_info *info,
c4f035c6
AK		 4225 enum x86_intercept_stage stage)
4226{
2953538e 4227 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4228}
4229
bdb42f5a
SB		 4230static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4231 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4232{
4233 struct kvm_cpuid_entry2 *cpuid = NULL;
4234
4235 if (eax && ecx)
4236 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4237 *eax, *ecx);
4238
4239 if (cpuid) {
4240 *eax = cpuid->eax;
4241 *ecx = cpuid->ecx;
4242 if (ebx)
4243 *ebx = cpuid->ebx;
4244 if (edx)
4245 *edx = cpuid->edx;
4246 return true;
4247 }
4248
4249 return false;
4250}
4251
14af3f3c 4252static struct x86_emulate_ops emulate_ops = {
1871c602 4253 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4254 .write_std = kvm_write_guest_virt_system,
1871c602 4255 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4256 .read_emulated = emulator_read_emulated,
4257 .write_emulated = emulator_write_emulated,
4258 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4259 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4260 .pio_in_emulated = emulator_pio_in_emulated,
4261 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4262 .get_segment = emulator_get_segment,
4263 .set_segment = emulator_set_segment,
5951c442 4264 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4265 .get_gdt = emulator_get_gdt,
160ce1f1 4266 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4267 .set_gdt = emulator_set_gdt,
4268 .set_idt = emulator_set_idt,
52a46617
GN		 4269 .get_cr = emulator_get_cr,
4270 .set_cr = emulator_set_cr,
9c537244 4271 .cpl = emulator_get_cpl,
35aa5375
GN		 4272 .get_dr = emulator_get_dr,
4273 .set_dr = emulator_set_dr,
717746e3
AK		 4274 .set_msr = emulator_set_msr,
4275 .get_msr = emulator_get_msr,
222d21aa 4276 .read_pmc = emulator_read_pmc,
6c3287f7 4277 .halt = emulator_halt,
bcaf5cc5 4278 .wbinvd = emulator_wbinvd,
d6aa1000 4279 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4280 .get_fpu = emulator_get_fpu,
4281 .put_fpu = emulator_put_fpu,
c4f035c6 4282 .intercept = emulator_intercept,
bdb42f5a 4283 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4284};
4285
5fdbf976
MT		 4286static void cache_all_regs(struct kvm_vcpu *vcpu)
4287{
4288 kvm_register_read(vcpu, VCPU_REGS_RAX);
4289 kvm_register_read(vcpu, VCPU_REGS_RSP);
4290 kvm_register_read(vcpu, VCPU_REGS_RIP);
4291 vcpu->arch.regs_dirty = ~0;
4292}
4293
95cb2295
GN		 4294static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4295{
4296 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4297 /*
4298 * an sti; sti; sequence only disable interrupts for the first
4299 * instruction. So, if the last instruction, be it emulated or
4300 * not, left the system with the INT_STI flag enabled, it
4301 * means that the last instruction is an sti. We should not
4302 * leave the flag on in this case. The same goes for mov ss
4303 */
4304 if (!(int_shadow & mask))
4305 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4306}
4307
54b8486f
GN		 4308static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4309{
4310 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4311 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4312 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4313 else if (ctxt->exception.error_code_valid)
4314 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4315 ctxt->exception.error_code);
54b8486f 4316 else
da9cb575 4317 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4318}
4319
9dac77fa 4320static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4321 const unsigned long *regs)
4322{
9dac77fa
AK		 4323 memset(&ctxt->twobyte, 0,
4324 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4325 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4326
9dac77fa
AK		 4327 ctxt->fetch.start = 0;
4328 ctxt->fetch.end = 0;
4329 ctxt->io_read.pos = 0;
4330 ctxt->io_read.end = 0;
4331 ctxt->mem_read.pos = 0;
4332 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4333}
4334
8ec4722d
MG		 4335static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4336{
adf52235 4337 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4338 int cs_db, cs_l;
4339
2aab2c5b
GN		 4340 /*
4341 * TODO: fix emulate.c to use guest_read/write_register
4342 * instead of direct ->regs accesses, can save hundred cycles
4343 * on Intel for instructions that don't read/change RSP, for
4344 * for example.
4345 */
8ec4722d
MG		 4346 cache_all_regs(vcpu);
4347
4348 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4349
adf52235
TY		 4350 ctxt->eflags = kvm_get_rflags(vcpu);
4351 ctxt->eip = kvm_rip_read(vcpu);
4352 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4353 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4354 cs_l ? X86EMUL_MODE_PROT64 :
4355 cs_db ? X86EMUL_MODE_PROT32 :
4356 X86EMUL_MODE_PROT16;
4357 ctxt->guest_mode = is_guest_mode(vcpu);
4358
9dac77fa 4359 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4360 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4361}
4362
71f9833b 4363int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4364{
9d74191a 4365 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4366 int ret;
4367
4368 init_emulate_ctxt(vcpu);
4369
9dac77fa
AK		 4370 ctxt->op_bytes = 2;
4371 ctxt->ad_bytes = 2;
4372 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4373 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4374
4375 if (ret != X86EMUL_CONTINUE)
4376 return EMULATE_FAIL;
4377
9dac77fa
AK		 4378 ctxt->eip = ctxt->_eip;
4379 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4380 kvm_rip_write(vcpu, ctxt->eip);
4381 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4382
4383 if (irq == NMI_VECTOR)
7460fb4a 4384 vcpu->arch.nmi_pending = 0;
63995653
MG		 4385 else
4386 vcpu->arch.interrupt.pending = false;
4387
4388 return EMULATE_DONE;
4389}
4390EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4391
6d77dbfc
GN		 4392static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4393{
fc3a9157
JR		 4394 int r = EMULATE_DONE;
4395
6d77dbfc
GN		 4396 ++vcpu->stat.insn_emulation_fail;
4397 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4398 if (!is_guest_mode(vcpu)) {
4399 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4400 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4401 vcpu->run->internal.ndata = 0;
4402 r = EMULATE_FAIL;
4403 }
6d77dbfc 4404 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4405
4406 return r;
6d77dbfc
GN		 4407}
4408
a6f177ef
GN		 4409static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4410{
4411 gpa_t gpa;
4412
68be0803
GN		 4413 if (tdp_enabled)
4414 return false;
4415
a6f177ef
GN		 4416 /*
4417 * if emulation was due to access to shadowed page table
4418 * and it failed try to unshadow page and re-entetr the
4419 * guest to let CPU execute the instruction.
4420 */
4421 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4422 return true;
4423
4424 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4425
4426 if (gpa == UNMAPPED_GVA)
4427 return true; /* let cpu generate fault */
4428
4429 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4430 return true;
4431
4432 return false;
4433}
4434
1cb3f3ae
XG		 4435static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4436 unsigned long cr2, int emulation_type)
4437{
4438 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4439 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4440
4441 last_retry_eip = vcpu->arch.last_retry_eip;
4442 last_retry_addr = vcpu->arch.last_retry_addr;
4443
4444 /*
4445 * If the emulation is caused by #PF and it is non-page_table
4446 * writing instruction, it means the VM-EXIT is caused by shadow
4447 * page protected, we can zap the shadow page and retry this
4448 * instruction directly.
4449 *
4450 * Note: if the guest uses a non-page-table modifying instruction
4451 * on the PDE that points to the instruction, then we will unmap
4452 * the instruction and go to an infinite loop. So, we cache the
4453 * last retried eip and the last fault address, if we meet the eip
4454 * and the address again, we can break out of the potential infinite
4455 * loop.
4456 */
4457 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4458
4459 if (!(emulation_type & EMULTYPE_RETRY))
4460 return false;
4461
4462 if (x86_page_table_writing_insn(ctxt))
4463 return false;
4464
4465 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4466 return false;
4467
4468 vcpu->arch.last_retry_eip = ctxt->eip;
4469 vcpu->arch.last_retry_addr = cr2;
4470
4471 if (!vcpu->arch.mmu.direct_map)
4472 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4473
4474 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4475
4476 return true;
4477}
4478
51d8b661
AP		 4479int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4480 unsigned long cr2,
dc25e89e
AP		 4481 int emulation_type,
4482 void *insn,
4483 int insn_len)
bbd9b64e 4484{
95cb2295 4485 int r;
9d74191a 4486 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4487 bool writeback = true;
bbd9b64e 4488
26eef70c 4489 kvm_clear_exception_queue(vcpu);
8d7d8102 4490
571008da 4491 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4492 init_emulate_ctxt(vcpu);
9d74191a
TY		 4493 ctxt->interruptibility = 0;
4494 ctxt->have_exception = false;
4495 ctxt->perm_ok = false;
bbd9b64e 4496
9d74191a 4497 ctxt->only_vendor_specific_insn
4005996e
AK		 4498 = emulation_type & EMULTYPE_TRAP_UD;
4499
9d74191a 4500 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4501
e46479f8 4502 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4503 ++vcpu->stat.insn_emulation;
1d2887e2 4504 if (r != EMULATION_OK) {
4005996e
AK		 4505 if (emulation_type & EMULTYPE_TRAP_UD)
4506 return EMULATE_FAIL;
a6f177ef 4507 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4508 return EMULATE_DONE;
6d77dbfc
GN		 4509 if (emulation_type & EMULTYPE_SKIP)
4510 return EMULATE_FAIL;
4511 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4512 }
4513 }
4514
ba8afb6b 4515 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4516 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4517 return EMULATE_DONE;
4518 }
4519
1cb3f3ae
XG		 4520 if (retry_instruction(ctxt, cr2, emulation_type))
4521 return EMULATE_DONE;
4522
7ae441ea 4523 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4524 changes registers values during IO operation */
7ae441ea
GN		 4525 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4526 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4527 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4528 }
4d2179e1 4529
5cd21917 4530restart:
9d74191a 4531 r = x86_emulate_insn(ctxt);
bbd9b64e 4532
775fde86
JR		 4533 if (r == EMULATION_INTERCEPTED)
4534 return EMULATE_DONE;
4535
d2ddd1c4 4536 if (r == EMULATION_FAILED) {
a6f177ef 4537 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4538 return EMULATE_DONE;
4539
6d77dbfc 4540 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4541 }
4542
9d74191a 4543 if (ctxt->have_exception) {
54b8486f 4544 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4545 r = EMULATE_DONE;
4546 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4547 if (!vcpu->arch.pio.in)
4548 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4549 else
4550 writeback = false;
e85d28f8 4551 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4552 } else if (vcpu->mmio_needed) {
4553 if (!vcpu->mmio_is_write)
4554 writeback = false;
e85d28f8 4555 r = EMULATE_DO_MMIO;
7ae441ea 4556 } else if (r == EMULATION_RESTART)
5cd21917 4557 goto restart;
d2ddd1c4
GN		 4558 else
4559 r = EMULATE_DONE;
f850e2e6 4560
7ae441ea 4561 if (writeback) {
9d74191a
TY		 4562 toggle_interruptibility(vcpu, ctxt->interruptibility);
4563 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4564 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4565 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4566 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4567 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4568 } else
4569 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4570
4571 return r;
de7d789a 4572}
51d8b661 4573EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4574
cf8f70bf 4575int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4576{
cf8f70bf 4577 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4578 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4579 size, port, &val, 1);
cf8f70bf 4580 /* do not return to emulator after return from userspace */
7972995b 4581 vcpu->arch.pio.count = 0;
de7d789a
CO		 4582 return ret;
4583}
cf8f70bf 4584EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4585
8cfdc000
ZA		 4586static void tsc_bad(void *info)
4587{
0a3aee0d 4588 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4589}
4590
4591static void tsc_khz_changed(void *data)
c8076604 4592{
8cfdc000
ZA		 4593 struct cpufreq_freqs *freq = data;
4594 unsigned long khz = 0;
4595
4596 if (data)
4597 khz = freq->new;
4598 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4599 khz = cpufreq_quick_get(raw_smp_processor_id());
4600 if (!khz)
4601 khz = tsc_khz;
0a3aee0d 4602 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4603}
4604
c8076604
GH		 4605static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4606 void *data)
4607{
4608 struct cpufreq_freqs *freq = data;
4609 struct kvm *kvm;
4610 struct kvm_vcpu *vcpu;
4611 int i, send_ipi = 0;
4612
8cfdc000
ZA		 4613 /*
4614 * We allow guests to temporarily run on slowing clocks,
4615 * provided we notify them after, or to run on accelerating
4616 * clocks, provided we notify them before. Thus time never
4617 * goes backwards.
4618 *
4619 * However, we have a problem. We can't atomically update
4620 * the frequency of a given CPU from this function; it is
4621 * merely a notifier, which can be called from any CPU.
4622 * Changing the TSC frequency at arbitrary points in time
4623 * requires a recomputation of local variables related to
4624 * the TSC for each VCPU. We must flag these local variables
4625 * to be updated and be sure the update takes place with the
4626 * new frequency before any guests proceed.
4627 *
4628 * Unfortunately, the combination of hotplug CPU and frequency
4629 * change creates an intractable locking scenario; the order
4630 * of when these callouts happen is undefined with respect to
4631 * CPU hotplug, and they can race with each other. As such,
4632 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4633 * undefined; you can actually have a CPU frequency change take
4634 * place in between the computation of X and the setting of the
4635 * variable. To protect against this problem, all updates of
4636 * the per_cpu tsc_khz variable are done in an interrupt
4637 * protected IPI, and all callers wishing to update the value
4638 * must wait for a synchronous IPI to complete (which is trivial
4639 * if the caller is on the CPU already). This establishes the
4640 * necessary total order on variable updates.
4641 *
4642 * Note that because a guest time update may take place
4643 * anytime after the setting of the VCPU's request bit, the
4644 * correct TSC value must be set before the request. However,
4645 * to ensure the update actually makes it to any guest which
4646 * starts running in hardware virtualization between the set
4647 * and the acquisition of the spinlock, we must also ping the
4648 * CPU after setting the request bit.
4649 *
4650 */
4651
c8076604
GH		 4652 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4653 return 0;
4654 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4655 return 0;
8cfdc000
ZA		 4656
4657 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4658
e935b837 4659 raw_spin_lock(&kvm_lock);
c8076604 4660 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4661 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4662 if (vcpu->cpu != freq->cpu)
4663 continue;
c285545f 4664 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4665 if (vcpu->cpu != smp_processor_id())
8cfdc000 4666 send_ipi = 1;
c8076604
GH		 4667 }
4668 }
e935b837 4669 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4670
4671 if (freq->old < freq->new && send_ipi) {
4672 /*
4673 * We upscale the frequency. Must make the guest
4674 * doesn't see old kvmclock values while running with
4675 * the new frequency, otherwise we risk the guest sees
4676 * time go backwards.
4677 *
4678 * In case we update the frequency for another cpu
4679 * (which might be in guest context) send an interrupt
4680 * to kick the cpu out of guest context. Next time
4681 * guest context is entered kvmclock will be updated,
4682 * so the guest will not see stale values.
4683 */
8cfdc000 4684 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4685 }
4686 return 0;
4687}
4688
4689static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4690 .notifier_call = kvmclock_cpufreq_notifier
4691};
4692
4693static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4694 unsigned long action, void *hcpu)
4695{
4696 unsigned int cpu = (unsigned long)hcpu;
4697
4698 switch (action) {
4699 case CPU_ONLINE:
4700 case CPU_DOWN_FAILED:
4701 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4702 break;
4703 case CPU_DOWN_PREPARE:
4704 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4705 break;
4706 }
4707 return NOTIFY_OK;
4708}
4709
4710static struct notifier_block kvmclock_cpu_notifier_block = {
4711 .notifier_call = kvmclock_cpu_notifier,
4712 .priority = -INT_MAX
c8076604
GH		 4713};
4714
b820cc0c
ZA		 4715static void kvm_timer_init(void)
4716{
4717 int cpu;
4718
c285545f 4719 max_tsc_khz = tsc_khz;
8cfdc000 4720 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4721 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4722#ifdef CONFIG_CPU_FREQ
4723 struct cpufreq_policy policy;
4724 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4725 cpu = get_cpu();
4726 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4727 if (policy.cpuinfo.max_freq)
4728 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4729 put_cpu();
c285545f 4730#endif
b820cc0c
ZA		 4731 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4732 CPUFREQ_TRANSITION_NOTIFIER);
4733 }
c285545f 4734 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4735 for_each_online_cpu(cpu)
4736 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4737}
4738
ff9d07a0
ZY		 4739static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4740
f5132b01 4741int kvm_is_in_guest(void)
ff9d07a0 4742{
086c9855 4743 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4744}
4745
4746static int kvm_is_user_mode(void)
4747{
4748 int user_mode = 3;
dcf46b94 4749
086c9855
AS		 4750 if (__this_cpu_read(current_vcpu))
4751 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4752
ff9d07a0
ZY		 4753 return user_mode != 0;
4754}
4755
4756static unsigned long kvm_get_guest_ip(void)
4757{
4758 unsigned long ip = 0;
dcf46b94 4759
086c9855
AS		 4760 if (__this_cpu_read(current_vcpu))
4761 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4762
ff9d07a0
ZY		 4763 return ip;
4764}
4765
4766static struct perf_guest_info_callbacks kvm_guest_cbs = {
4767 .is_in_guest = kvm_is_in_guest,
4768 .is_user_mode = kvm_is_user_mode,
4769 .get_guest_ip = kvm_get_guest_ip,
4770};
4771
4772void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4773{
086c9855 4774 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4775}
4776EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4777
4778void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4779{
086c9855 4780 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4781}
4782EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4783
ce88decf
XG		 4784static void kvm_set_mmio_spte_mask(void)
4785{
4786 u64 mask;
4787 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4788
4789 /*
4790 * Set the reserved bits and the present bit of an paging-structure
4791 * entry to generate page fault with PFER.RSV = 1.
4792 */
4793 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4794 mask |= 1ull;
4795
4796#ifdef CONFIG_X86_64
4797 /*
4798 * If reserved bit is not supported, clear the present bit to disable
4799 * mmio page fault.
4800 */
4801 if (maxphyaddr == 52)
4802 mask &= ~1ull;
4803#endif
4804
4805 kvm_mmu_set_mmio_spte_mask(mask);
4806}
4807
f8c16bba 4808int kvm_arch_init(void *opaque)
043405e1 4809{
b820cc0c 4810 int r;
f8c16bba
ZX		 4811 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4812
f8c16bba
ZX		 4813 if (kvm_x86_ops) {
4814 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4815 r = -EEXIST;
4816 goto out;
f8c16bba
ZX		 4817 }
4818
4819 if (!ops->cpu_has_kvm_support()) {
4820 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4821 r = -EOPNOTSUPP;
4822 goto out;
f8c16bba
ZX		 4823 }
4824 if (ops->disabled_by_bios()) {
4825 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4826 r = -EOPNOTSUPP;
4827 goto out;
f8c16bba
ZX		 4828 }
4829
97db56ce
AK		 4830 r = kvm_mmu_module_init();
4831 if (r)
4832 goto out;
4833
ce88decf 4834 kvm_set_mmio_spte_mask();
97db56ce
AK		 4835 kvm_init_msr_list();
4836
f8c16bba 4837 kvm_x86_ops = ops;
7b52345e 4838 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4839 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4840
b820cc0c 4841 kvm_timer_init();
c8076604 4842
ff9d07a0
ZY		 4843 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4844
2acf923e
DC		 4845 if (cpu_has_xsave)
4846 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4847
f8c16bba 4848 return 0;
56c6d28a
ZX		 4849
4850out:
56c6d28a 4851 return r;
043405e1 4852}
8776e519 4853
f8c16bba
ZX		 4854void kvm_arch_exit(void)
4855{
ff9d07a0
ZY		 4856 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4857
888d256e
JK		 4858 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4859 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4860 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4861 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4862 kvm_x86_ops = NULL;
56c6d28a
ZX		 4863 kvm_mmu_module_exit();
4864}
f8c16bba 4865
8776e519
HB		 4866int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4867{
4868 ++vcpu->stat.halt_exits;
4869 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4870 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4871 return 1;
4872 } else {
4873 vcpu->run->exit_reason = KVM_EXIT_HLT;
4874 return 0;
4875 }
4876}
4877EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4878
55cd8e5a
GN		 4879int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4880{
4881 u64 param, ingpa, outgpa, ret;
4882 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4883 bool fast, longmode;
4884 int cs_db, cs_l;
4885
4886 /*
4887 * hypercall generates UD from non zero cpl and real mode
4888 * per HYPER-V spec
4889 */
3eeb3288 4890 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4891 kvm_queue_exception(vcpu, UD_VECTOR);
4892 return 0;
4893 }
4894
4895 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4896 longmode = is_long_mode(vcpu) && cs_l == 1;
4897
4898 if (!longmode) {
ccd46936
GN		 4899 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4900 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4901 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4902 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4903 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4904 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4905 }
4906#ifdef CONFIG_X86_64
4907 else {
4908 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4909 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4910 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4911 }
4912#endif
4913
4914 code = param & 0xffff;
4915 fast = (param >> 16) & 0x1;
4916 rep_cnt = (param >> 32) & 0xfff;
4917 rep_idx = (param >> 48) & 0xfff;
4918
4919 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4920
c25bc163
GN		 4921 switch (code) {
4922 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4923 kvm_vcpu_on_spin(vcpu);
4924 break;
4925 default:
4926 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4927 break;
4928 }
55cd8e5a
GN		 4929
4930 ret = res | (((u64)rep_done & 0xfff) << 32);
4931 if (longmode) {
4932 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4933 } else {
4934 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4935 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4936 }
4937
4938 return 1;
4939}
4940
8776e519
HB		 4941int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4942{
4943 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4944 int r = 1;
8776e519 4945
55cd8e5a
GN		 4946 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4947 return kvm_hv_hypercall(vcpu);
4948
5fdbf976
MT		 4949 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4950 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4951 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4952 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4953 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4954
229456fc 4955 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4956
8776e519
HB		 4957 if (!is_long_mode(vcpu)) {
4958 nr &= 0xFFFFFFFF;
4959 a0 &= 0xFFFFFFFF;
4960 a1 &= 0xFFFFFFFF;
4961 a2 &= 0xFFFFFFFF;
4962 a3 &= 0xFFFFFFFF;
4963 }
4964
07708c4a
JK		 4965 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4966 ret = -KVM_EPERM;
4967 goto out;
4968 }
4969
8776e519 4970 switch (nr) {
b93463aa
AK		 4971 case KVM_HC_VAPIC_POLL_IRQ:
4972 ret = 0;
4973 break;
8776e519
HB		 4974 default:
4975 ret = -KVM_ENOSYS;
4976 break;
4977 }
07708c4a 4978out:
5fdbf976 4979 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4980 ++vcpu->stat.hypercalls;
2f333bcb 4981 return r;
8776e519
HB		 4982}
4983EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4984
d6aa1000 4985int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 4986{
d6aa1000 4987 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 4988 char instruction[3];
5fdbf976 4989 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4990
8776e519
HB		 4991 /*
4992 * Blow out the MMU to ensure that no other VCPU has an active mapping
4993 * to ensure that the updated hypercall appears atomically across all
4994 * VCPUs.
4995 */
4996 kvm_mmu_zap_all(vcpu->kvm);
4997
8776e519 4998 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4999
9d74191a 5000 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5001}
5002
b6c7a5dc
HB		 5003/*
5004 * Check if userspace requested an interrupt window, and that the
5005 * interrupt window is open.
5006 *
5007 * No need to exit to userspace if we already have an interrupt queued.
5008 */
851ba692 5009static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5010{
8061823a 5011 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5012 vcpu->run->request_interrupt_window &&
5df56646 5013 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5014}
5015
851ba692 5016static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5017{
851ba692
AK		 5018 struct kvm_run *kvm_run = vcpu->run;
5019
91586a3b 5020 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5021 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5022 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5023 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5024 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5025 else
b6c7a5dc 5026 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5027 kvm_arch_interrupt_allowed(vcpu) &&
5028 !kvm_cpu_has_interrupt(vcpu) &&
5029 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5030}
5031
b93463aa
AK		 5032static void vapic_enter(struct kvm_vcpu *vcpu)
5033{
5034 struct kvm_lapic *apic = vcpu->arch.apic;
5035 struct page *page;
5036
5037 if (!apic || !apic->vapic_addr)
5038 return;
5039
5040 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5041
5042 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5043}
5044
5045static void vapic_exit(struct kvm_vcpu *vcpu)
5046{
5047 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5048 int idx;
b93463aa
AK		 5049
5050 if (!apic || !apic->vapic_addr)
5051 return;
5052
f656ce01 5053 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5054 kvm_release_page_dirty(apic->vapic_page);
5055 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5056 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5057}
5058
95ba8273
GN		 5059static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5060{
5061 int max_irr, tpr;
5062
5063 if (!kvm_x86_ops->update_cr8_intercept)
5064 return;
5065
88c808fd
AK		 5066 if (!vcpu->arch.apic)
5067 return;
5068
8db3baa2
GN		 5069 if (!vcpu->arch.apic->vapic_addr)
5070 max_irr = kvm_lapic_find_highest_irr(vcpu);
5071 else
5072 max_irr = -1;
95ba8273
GN		 5073
5074 if (max_irr != -1)
5075 max_irr >>= 4;
5076
5077 tpr = kvm_lapic_get_cr8(vcpu);
5078
5079 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5080}
5081
851ba692 5082static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5083{
5084 /* try to reinject previous events if any */
b59bb7bd 5085 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5086 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5087 vcpu->arch.exception.has_error_code,
5088 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5089 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5090 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5091 vcpu->arch.exception.error_code,
5092 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5093 return;
5094 }
5095
95ba8273
GN		 5096 if (vcpu->arch.nmi_injected) {
5097 kvm_x86_ops->set_nmi(vcpu);
5098 return;
5099 }
5100
5101 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5102 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5103 return;
5104 }
5105
5106 /* try to inject new event if pending */
5107 if (vcpu->arch.nmi_pending) {
5108 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5109 --vcpu->arch.nmi_pending;
95ba8273
GN		 5110 vcpu->arch.nmi_injected = true;
5111 kvm_x86_ops->set_nmi(vcpu);
5112 }
5113 } else if (kvm_cpu_has_interrupt(vcpu)) {
5114 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5115 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5116 false);
5117 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5118 }
5119 }
5120}
5121
2acf923e
DC		 5122static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5123{
5124 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5125 !vcpu->guest_xcr0_loaded) {
5126 /* kvm_set_xcr() also depends on this */
5127 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5128 vcpu->guest_xcr0_loaded = 1;
5129 }
5130}
5131
5132static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5133{
5134 if (vcpu->guest_xcr0_loaded) {
5135 if (vcpu->arch.xcr0 != host_xcr0)
5136 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5137 vcpu->guest_xcr0_loaded = 0;
5138 }
5139}
5140
7460fb4a
AK		 5141static void process_nmi(struct kvm_vcpu *vcpu)
5142{
5143 unsigned limit = 2;
5144
5145 /*
5146 * x86 is limited to one NMI running, and one NMI pending after it.
5147 * If an NMI is already in progress, limit further NMIs to just one.
5148 * Otherwise, allow two (and we'll inject the first one immediately).
5149 */
5150 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5151 limit = 1;
5152
5153 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5154 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5155 kvm_make_request(KVM_REQ_EVENT, vcpu);
5156}
5157
851ba692 5158static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5159{
5160 int r;
6a8b1d13 5161 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5162 vcpu->run->request_interrupt_window;
d6185f20 5163 bool req_immediate_exit = 0;
b6c7a5dc 5164
3e007509 5165 if (vcpu->requests) {
a8eeb04a 5166 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5167 kvm_mmu_unload(vcpu);
a8eeb04a 5168 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5169 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5170 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5171 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5172 if (unlikely(r))
5173 goto out;
5174 }
a8eeb04a 5175 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5176 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5177 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5178 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5179 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5180 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5181 r = 0;
5182 goto out;
5183 }
a8eeb04a 5184 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5185 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5186 r = 0;
5187 goto out;
5188 }
a8eeb04a 5189 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5190 vcpu->fpu_active = 0;
5191 kvm_x86_ops->fpu_deactivate(vcpu);
5192 }
af585b92
GN		 5193 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5194 /* Page is swapped out. Do synthetic halt */
5195 vcpu->arch.apf.halted = true;
5196 r = 1;
5197 goto out;
5198 }
c9aaa895
GC		 5199 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5200 record_steal_time(vcpu);
7460fb4a
AK		 5201 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5202 process_nmi(vcpu);
d6185f20
NHE		 5203 req_immediate_exit =
5204 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5205 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5206 kvm_handle_pmu_event(vcpu);
5207 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5208 kvm_deliver_pmi(vcpu);
2f52d58c 5209 }
b93463aa 5210
3e007509
AK		 5211 r = kvm_mmu_reload(vcpu);
5212 if (unlikely(r))
5213 goto out;
5214
b463a6f7
AK		 5215 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5216 inject_pending_event(vcpu);
5217
5218 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5219 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5220 kvm_x86_ops->enable_nmi_window(vcpu);
5221 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5222 kvm_x86_ops->enable_irq_window(vcpu);
5223
5224 if (kvm_lapic_enabled(vcpu)) {
5225 update_cr8_intercept(vcpu);
5226 kvm_lapic_sync_to_vapic(vcpu);
5227 }
5228 }
5229
b6c7a5dc
HB		 5230 preempt_disable();
5231
5232 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5233 if (vcpu->fpu_active)
5234 kvm_load_guest_fpu(vcpu);
2acf923e 5235 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5236
6b7e2d09
XG		 5237 vcpu->mode = IN_GUEST_MODE;
5238
5239 /* We should set ->mode before check ->requests,
5240 * see the comment in make_all_cpus_request.
5241 */
5242 smp_mb();
b6c7a5dc 5243
d94e1dc9 5244 local_irq_disable();
32f88400 5245
6b7e2d09 5246 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5247 || need_resched() || signal_pending(current)) {
6b7e2d09 5248 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5249 smp_wmb();
6c142801
AK		 5250 local_irq_enable();
5251 preempt_enable();
b463a6f7 5252 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5253 r = 1;
5254 goto out;
5255 }
5256
f656ce01 5257 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5258
d6185f20
NHE		 5259 if (req_immediate_exit)
5260 smp_send_reschedule(vcpu->cpu);
5261
b6c7a5dc
HB		 5262 kvm_guest_enter();
5263
42dbaa5a 5264 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5265 set_debugreg(0, 7);
5266 set_debugreg(vcpu->arch.eff_db[0], 0);
5267 set_debugreg(vcpu->arch.eff_db[1], 1);
5268 set_debugreg(vcpu->arch.eff_db[2], 2);
5269 set_debugreg(vcpu->arch.eff_db[3], 3);
5270 }
b6c7a5dc 5271
229456fc 5272 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5273 kvm_x86_ops->run(vcpu);
b6c7a5dc 5274
24f1e32c
FW		 5275 /*
5276 * If the guest has used debug registers, at least dr7
5277 * will be disabled while returning to the host.
5278 * If we don't have active breakpoints in the host, we don't
5279 * care about the messed up debug address registers. But if
5280 * we have some of them active, restore the old state.
5281 */
59d8eb53 5282 if (hw_breakpoint_active())
24f1e32c 5283 hw_breakpoint_restore();
42dbaa5a 5284
d5c1785d 5285 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5286
6b7e2d09 5287 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5288 smp_wmb();
b6c7a5dc
HB		 5289 local_irq_enable();
5290
5291 ++vcpu->stat.exits;
5292
5293 /*
5294 * We must have an instruction between local_irq_enable() and
5295 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5296 * the interrupt shadow. The stat.exits increment will do nicely.
5297 * But we need to prevent reordering, hence this barrier():
5298 */
5299 barrier();
5300
5301 kvm_guest_exit();
5302
5303 preempt_enable();
5304
f656ce01 5305 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5306
b6c7a5dc
HB		 5307 /*
5308 * Profile KVM exit RIPs:
5309 */
5310 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5311 unsigned long rip = kvm_rip_read(vcpu);
5312 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5313 }
5314
298101da 5315
b93463aa
AK		 5316 kvm_lapic_sync_from_vapic(vcpu);
5317
851ba692 5318 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5319out:
5320 return r;
5321}
b6c7a5dc 5322
09cec754 5323
851ba692 5324static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5325{
5326 int r;
f656ce01 5327 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5328
5329 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5330 pr_debug("vcpu %d received sipi with vector # %x\n",
5331 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5332 kvm_lapic_reset(vcpu);
5f179287 5333 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5334 if (r)
5335 return r;
5336 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5337 }
5338
f656ce01 5339 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5340 vapic_enter(vcpu);
5341
5342 r = 1;
5343 while (r > 0) {
af585b92
GN		 5344 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5345 !vcpu->arch.apf.halted)
851ba692 5346 r = vcpu_enter_guest(vcpu);
d7690175 5347 else {
f656ce01 5348 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5349 kvm_vcpu_block(vcpu);
f656ce01 5350 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5351 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5352 {
5353 switch(vcpu->arch.mp_state) {
5354 case KVM_MP_STATE_HALTED:
d7690175 5355 vcpu->arch.mp_state =
09cec754
GN		 5356 KVM_MP_STATE_RUNNABLE;
5357 case KVM_MP_STATE_RUNNABLE:
af585b92 5358 vcpu->arch.apf.halted = false;
09cec754
GN		 5359 break;
5360 case KVM_MP_STATE_SIPI_RECEIVED:
5361 default:
5362 r = -EINTR;
5363 break;
5364 }
5365 }
d7690175
MT		 5366 }
5367
09cec754
GN		 5368 if (r <= 0)
5369 break;
5370
5371 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5372 if (kvm_cpu_has_pending_timer(vcpu))
5373 kvm_inject_pending_timer_irqs(vcpu);
5374
851ba692 5375 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5376 r = -EINTR;
851ba692 5377 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5378 ++vcpu->stat.request_irq_exits;
5379 }
af585b92
GN		 5380
5381 kvm_check_async_pf_completion(vcpu);
5382
09cec754
GN		 5383 if (signal_pending(current)) {
5384 r = -EINTR;
851ba692 5385 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5386 ++vcpu->stat.signal_exits;
5387 }
5388 if (need_resched()) {
f656ce01 5389 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5390 kvm_resched(vcpu);
f656ce01 5391 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5392 }
b6c7a5dc
HB		 5393 }
5394
f656ce01 5395 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5396
b93463aa
AK		 5397 vapic_exit(vcpu);
5398
b6c7a5dc
HB		 5399 return r;
5400}
5401
5287f194
AK		 5402static int complete_mmio(struct kvm_vcpu *vcpu)
5403{
5404 struct kvm_run *run = vcpu->run;
5405 int r;
5406
5407 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5408 return 1;
5409
5410 if (vcpu->mmio_needed) {
5287f194 5411 vcpu->mmio_needed = 0;
cef4dea0 5412 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5413 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5414 run->mmio.data, 8);
cef4dea0
AK		 5415 vcpu->mmio_index += 8;
5416 if (vcpu->mmio_index < vcpu->mmio_size) {
5417 run->exit_reason = KVM_EXIT_MMIO;
5418 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5419 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5420 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5421 run->mmio.is_write = vcpu->mmio_is_write;
5422 vcpu->mmio_needed = 1;
5423 return 0;
5424 }
5425 if (vcpu->mmio_is_write)
5426 return 1;
5427 vcpu->mmio_read_completed = 1;
5287f194
AK		 5428 }
5429 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5430 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5431 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5432 if (r != EMULATE_DONE)
5433 return 0;
5434 return 1;
5435}
5436
b6c7a5dc
HB		 5437int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5438{
5439 int r;
5440 sigset_t sigsaved;
5441
e5c30142
AK		 5442 if (!tsk_used_math(current) && init_fpu(current))
5443 return -ENOMEM;
5444
ac9f6dc0
AK		 5445 if (vcpu->sigset_active)
5446 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5447
a4535290 5448 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5449 kvm_vcpu_block(vcpu);
d7690175 5450 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5451 r = -EAGAIN;
5452 goto out;
b6c7a5dc
HB		 5453 }
5454
b6c7a5dc 5455 /* re-sync apic's tpr */
eea1cff9
AP		 5456 if (!irqchip_in_kernel(vcpu->kvm)) {
5457 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5458 r = -EINVAL;
5459 goto out;
5460 }
5461 }
b6c7a5dc 5462
5287f194
AK		 5463 r = complete_mmio(vcpu);
5464 if (r <= 0)
5465 goto out;
5466
851ba692 5467 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5468
5469out:
f1d86e46 5470 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5471 if (vcpu->sigset_active)
5472 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5473
b6c7a5dc
HB		 5474 return r;
5475}
5476
5477int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5478{
7ae441ea
GN		 5479 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5480 /*
5481 * We are here if userspace calls get_regs() in the middle of
5482 * instruction emulation. Registers state needs to be copied
5483 * back from emulation context to vcpu. Usrapace shouldn't do
5484 * that usually, but some bad designed PV devices (vmware
5485 * backdoor interface) need this to work
5486 */
9dac77fa
AK		 5487 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5488 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5489 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5490 }
5fdbf976
MT		 5491 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5492 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5493 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5494 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5495 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5496 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5497 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5498 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5499#ifdef CONFIG_X86_64
5fdbf976
MT		 5500 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5501 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5502 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5503 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5504 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5505 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5506 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5507 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5508#endif
5509
5fdbf976 5510 regs->rip = kvm_rip_read(vcpu);
91586a3b 5511 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5512
b6c7a5dc
HB		 5513 return 0;
5514}
5515
5516int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5517{
7ae441ea
GN		 5518 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5519 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5520
5fdbf976
MT		 5521 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5522 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5523 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5524 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5525 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5526 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5527 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5528 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5529#ifdef CONFIG_X86_64
5fdbf976
MT		 5530 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5531 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5532 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5533 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5534 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5535 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5536 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5537 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5538#endif
5539
5fdbf976 5540 kvm_rip_write(vcpu, regs->rip);
91586a3b 5541 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5542
b4f14abd
JK		 5543 vcpu->arch.exception.pending = false;
5544
3842d135
AK		 5545 kvm_make_request(KVM_REQ_EVENT, vcpu);
5546
b6c7a5dc
HB		 5547 return 0;
5548}
5549
b6c7a5dc
HB		 5550void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5551{
5552 struct kvm_segment cs;
5553
3e6e0aab 5554 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5555 *db = cs.db;
5556 *l = cs.l;
5557}
5558EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5559
5560int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5561 struct kvm_sregs *sregs)
5562{
89a27f4d 5563 struct desc_ptr dt;
b6c7a5dc 5564
3e6e0aab
GT		 5565 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5566 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5567 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5568 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5569 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5570 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5571
3e6e0aab
GT		 5572 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5573 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5574
5575 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5576 sregs->idt.limit = dt.size;
5577 sregs->idt.base = dt.address;
b6c7a5dc 5578 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5579 sregs->gdt.limit = dt.size;
5580 sregs->gdt.base = dt.address;
b6c7a5dc 5581
4d4ec087 5582 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5583 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5584 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5585 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5586 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5587 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5588 sregs->apic_base = kvm_get_apic_base(vcpu);
5589
923c61bb 5590 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5591
36752c9b 5592 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5593 set_bit(vcpu->arch.interrupt.nr,
5594 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5595
b6c7a5dc
HB		 5596 return 0;
5597}
5598
62d9f0db
MT		 5599int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5600 struct kvm_mp_state *mp_state)
5601{
62d9f0db 5602 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5603 return 0;
5604}
5605
5606int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5607 struct kvm_mp_state *mp_state)
5608{
62d9f0db 5609 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5610 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5611 return 0;
5612}
5613
e269fb21
JK		 5614int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5615 bool has_error_code, u32 error_code)
b6c7a5dc 5616{
9d74191a 5617 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5618 int ret;
e01c2426 5619
8ec4722d 5620 init_emulate_ctxt(vcpu);
c697518a 5621
9d74191a
TY		 5622 ret = emulator_task_switch(ctxt, tss_selector, reason,
5623 has_error_code, error_code);
c697518a 5624
c697518a 5625 if (ret)
19d04437 5626 return EMULATE_FAIL;
37817f29 5627
9dac77fa 5628 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5629 kvm_rip_write(vcpu, ctxt->eip);
5630 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5631 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5632 return EMULATE_DONE;
37817f29
IE		 5633}
5634EXPORT_SYMBOL_GPL(kvm_task_switch);
5635
b6c7a5dc
HB		 5636int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5637 struct kvm_sregs *sregs)
5638{
5639 int mmu_reset_needed = 0;
63f42e02 5640 int pending_vec, max_bits, idx;
89a27f4d 5641 struct desc_ptr dt;
b6c7a5dc 5642
89a27f4d
GN		 5643 dt.size = sregs->idt.limit;
5644 dt.address = sregs->idt.base;
b6c7a5dc 5645 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5646 dt.size = sregs->gdt.limit;
5647 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5648 kvm_x86_ops->set_gdt(vcpu, &dt);
5649
ad312c7c 5650 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5651 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5652 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5653 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5654
2d3ad1f4 5655 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5656
f6801dff 5657 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5658 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5659 kvm_set_apic_base(vcpu, sregs->apic_base);
5660
4d4ec087 5661 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5662 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5663 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5664
fc78f519 5665 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5666 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5667 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5668 kvm_update_cpuid(vcpu);
63f42e02
XG		 5669
5670 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5671 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5672 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5673 mmu_reset_needed = 1;
5674 }
63f42e02 5675 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5676
5677 if (mmu_reset_needed)
5678 kvm_mmu_reset_context(vcpu);
5679
923c61bb
GN		 5680 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5681 pending_vec = find_first_bit(
5682 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5683 if (pending_vec < max_bits) {
66fd3f7f 5684 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5685 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5686 }
5687
3e6e0aab
GT		 5688 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5689 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5690 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5691 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5692 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5693 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5694
3e6e0aab
GT		 5695 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5696 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5697
5f0269f5
ME		 5698 update_cr8_intercept(vcpu);
5699
9c3e4aab 5700 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5701 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5702 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5703 !is_protmode(vcpu))
9c3e4aab
MT		 5704 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5705
3842d135
AK		 5706 kvm_make_request(KVM_REQ_EVENT, vcpu);
5707
b6c7a5dc
HB		 5708 return 0;
5709}
5710
d0bfb940
JK		 5711int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5712 struct kvm_guest_debug *dbg)
b6c7a5dc 5713{
355be0b9 5714 unsigned long rflags;
ae675ef0 5715 int i, r;
b6c7a5dc 5716
4f926bf2
JK		 5717 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5718 r = -EBUSY;
5719 if (vcpu->arch.exception.pending)
2122ff5e 5720 goto out;
4f926bf2
JK		 5721 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5722 kvm_queue_exception(vcpu, DB_VECTOR);
5723 else
5724 kvm_queue_exception(vcpu, BP_VECTOR);
5725 }
5726
91586a3b
JK		 5727 /*
5728 * Read rflags as long as potentially injected trace flags are still
5729 * filtered out.
5730 */
5731 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5732
5733 vcpu->guest_debug = dbg->control;
5734 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5735 vcpu->guest_debug = 0;
5736
5737 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5738 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5739 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5740 vcpu->arch.switch_db_regs =
5741 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5742 } else {
5743 for (i = 0; i < KVM_NR_DB_REGS; i++)
5744 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5745 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5746 }
5747
f92653ee
JK		 5748 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5749 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5750 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5751
91586a3b
JK		 5752 /*
5753 * Trigger an rflags update that will inject or remove the trace
5754 * flags.
5755 */
5756 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5757
355be0b9 5758 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5759
4f926bf2 5760 r = 0;
d0bfb940 5761
2122ff5e 5762out:
b6c7a5dc
HB		 5763
5764 return r;
5765}
5766
8b006791
ZX		 5767/*
5768 * Translate a guest virtual address to a guest physical address.
5769 */
5770int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5771 struct kvm_translation *tr)
5772{
5773 unsigned long vaddr = tr->linear_address;
5774 gpa_t gpa;
f656ce01 5775 int idx;
8b006791 5776
f656ce01 5777 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5778 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5779 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5780 tr->physical_address = gpa;
5781 tr->valid = gpa != UNMAPPED_GVA;
5782 tr->writeable = 1;
5783 tr->usermode = 0;
8b006791
ZX		 5784
5785 return 0;
5786}
5787
d0752060
HB		 5788int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5789{
98918833
SY		 5790 struct i387_fxsave_struct *fxsave =
5791 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5792
d0752060
HB		 5793 memcpy(fpu->fpr, fxsave->st_space, 128);
5794 fpu->fcw = fxsave->cwd;
5795 fpu->fsw = fxsave->swd;
5796 fpu->ftwx = fxsave->twd;
5797 fpu->last_opcode = fxsave->fop;
5798 fpu->last_ip = fxsave->rip;
5799 fpu->last_dp = fxsave->rdp;
5800 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5801
d0752060
HB		 5802 return 0;
5803}
5804
5805int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5806{
98918833
SY		 5807 struct i387_fxsave_struct *fxsave =
5808 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5809
d0752060
HB		 5810 memcpy(fxsave->st_space, fpu->fpr, 128);
5811 fxsave->cwd = fpu->fcw;
5812 fxsave->swd = fpu->fsw;
5813 fxsave->twd = fpu->ftwx;
5814 fxsave->fop = fpu->last_opcode;
5815 fxsave->rip = fpu->last_ip;
5816 fxsave->rdp = fpu->last_dp;
5817 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5818
d0752060
HB		 5819 return 0;
5820}
5821
10ab25cd 5822int fx_init(struct kvm_vcpu *vcpu)
d0752060 5823{
10ab25cd
JK		 5824 int err;
5825
5826 err = fpu_alloc(&vcpu->arch.guest_fpu);
5827 if (err)
5828 return err;
5829
98918833 5830 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5831
2acf923e
DC		 5832 /*
5833 * Ensure guest xcr0 is valid for loading
5834 */
5835 vcpu->arch.xcr0 = XSTATE_FP;
5836
ad312c7c 5837 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5838
5839 return 0;
d0752060
HB		 5840}
5841EXPORT_SYMBOL_GPL(fx_init);
5842
98918833
SY		 5843static void fx_free(struct kvm_vcpu *vcpu)
5844{
5845 fpu_free(&vcpu->arch.guest_fpu);
5846}
5847
d0752060
HB		 5848void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5849{
2608d7a1 5850 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5851 return;
5852
2acf923e
DC		 5853 /*
5854 * Restore all possible states in the guest,
5855 * and assume host would use all available bits.
5856 * Guest xcr0 would be loaded later.
5857 */
5858 kvm_put_guest_xcr0(vcpu);
d0752060 5859 vcpu->guest_fpu_loaded = 1;
7cf30855 5860 unlazy_fpu(current);
98918833 5861 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5862 trace_kvm_fpu(1);
d0752060 5863}
d0752060
HB		 5864
5865void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5866{
2acf923e
DC		 5867 kvm_put_guest_xcr0(vcpu);
5868
d0752060
HB		 5869 if (!vcpu->guest_fpu_loaded)
5870 return;
5871
5872 vcpu->guest_fpu_loaded = 0;
98918833 5873 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5874 ++vcpu->stat.fpu_reload;
a8eeb04a 5875 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5876 trace_kvm_fpu(0);
d0752060 5877}
e9b11c17
ZX		 5878
5879void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5880{
12f9a48f 5881 kvmclock_reset(vcpu);
7f1ea208 5882
f5f48ee1 5883 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5884 fx_free(vcpu);
e9b11c17
ZX		 5885 kvm_x86_ops->vcpu_free(vcpu);
5886}
5887
5888struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5889 unsigned int id)
5890{
6755bae8
ZA		 5891 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5892 printk_once(KERN_WARNING
5893 "kvm: SMP vm created on host with unstable TSC; "
5894 "guest TSC will not be reliable\n");
26e5215f
AK		 5895 return kvm_x86_ops->vcpu_create(kvm, id);
5896}
e9b11c17 5897
26e5215f
AK		 5898int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5899{
5900 int r;
e9b11c17 5901
0bed3b56 5902 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5903 vcpu_load(vcpu);
5904 r = kvm_arch_vcpu_reset(vcpu);
5905 if (r == 0)
5906 r = kvm_mmu_setup(vcpu);
5907 vcpu_put(vcpu);
e9b11c17 5908
26e5215f 5909 return r;
e9b11c17
ZX		 5910}
5911
d40ccc62 5912void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5913{
344d9588
GN		 5914 vcpu->arch.apf.msr_val = 0;
5915
e9b11c17
ZX		 5916 vcpu_load(vcpu);
5917 kvm_mmu_unload(vcpu);
5918 vcpu_put(vcpu);
5919
98918833 5920 fx_free(vcpu);
e9b11c17
ZX		 5921 kvm_x86_ops->vcpu_free(vcpu);
5922}
5923
5924int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5925{
7460fb4a
AK		 5926 atomic_set(&vcpu->arch.nmi_queued, 0);
5927 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 5928 vcpu->arch.nmi_injected = false;
5929
42dbaa5a
JK		 5930 vcpu->arch.switch_db_regs = 0;
5931 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5932 vcpu->arch.dr6 = DR6_FIXED_1;
5933 vcpu->arch.dr7 = DR7_FIXED_1;
5934
3842d135 5935 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5936 vcpu->arch.apf.msr_val = 0;
c9aaa895 5937 vcpu->arch.st.msr_val = 0;
3842d135 5938
12f9a48f
GC		 5939 kvmclock_reset(vcpu);
5940
af585b92
GN		 5941 kvm_clear_async_pf_completion_queue(vcpu);
5942 kvm_async_pf_hash_reset(vcpu);
5943 vcpu->arch.apf.halted = false;
3842d135 5944
f5132b01
GN		 5945 kvm_pmu_reset(vcpu);
5946
e9b11c17
ZX		 5947 return kvm_x86_ops->vcpu_reset(vcpu);
5948}
5949
10474ae8 5950int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5951{
ca84d1a2
ZA		 5952 struct kvm *kvm;
5953 struct kvm_vcpu *vcpu;
5954 int i;
18863bdd
AK		 5955
5956 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5957 list_for_each_entry(kvm, &vm_list, vm_list)
5958 kvm_for_each_vcpu(i, vcpu, kvm)
5959 if (vcpu->cpu == smp_processor_id())
c285545f 5960 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5961 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5962}
5963
5964void kvm_arch_hardware_disable(void *garbage)
5965{
5966 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5967 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5968}
5969
5970int kvm_arch_hardware_setup(void)
5971{
5972 return kvm_x86_ops->hardware_setup();
5973}
5974
5975void kvm_arch_hardware_unsetup(void)
5976{
5977 kvm_x86_ops->hardware_unsetup();
5978}
5979
5980void kvm_arch_check_processor_compat(void *rtn)
5981{
5982 kvm_x86_ops->check_processor_compatibility(rtn);
5983}
5984
5985int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5986{
5987 struct page *page;
5988 struct kvm *kvm;
5989 int r;
5990
5991 BUG_ON(vcpu->kvm == NULL);
5992 kvm = vcpu->kvm;
5993
9aabc88f 5994 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 5995 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5996 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5997 else
a4535290 5998 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5999
6000 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6001 if (!page) {
6002 r = -ENOMEM;
6003 goto fail;
6004 }
ad312c7c 6005 vcpu->arch.pio_data = page_address(page);
e9b11c17 6006
1e993611 6007 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6008
e9b11c17
ZX		 6009 r = kvm_mmu_create(vcpu);
6010 if (r < 0)
6011 goto fail_free_pio_data;
6012
6013 if (irqchip_in_kernel(kvm)) {
6014 r = kvm_create_lapic(vcpu);
6015 if (r < 0)
6016 goto fail_mmu_destroy;
6017 }
6018
890ca9ae
HY		 6019 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6020 GFP_KERNEL);
6021 if (!vcpu->arch.mce_banks) {
6022 r = -ENOMEM;
443c39bc 6023 goto fail_free_lapic;
890ca9ae
HY		 6024 }
6025 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6026
f5f48ee1
SY		 6027 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6028 goto fail_free_mce_banks;
6029
af585b92 6030 kvm_async_pf_hash_reset(vcpu);
f5132b01 6031 kvm_pmu_init(vcpu);
af585b92 6032
e9b11c17 6033 return 0;
f5f48ee1
SY		 6034fail_free_mce_banks:
6035 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6036fail_free_lapic:
6037 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6038fail_mmu_destroy:
6039 kvm_mmu_destroy(vcpu);
6040fail_free_pio_data:
ad312c7c 6041 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6042fail:
6043 return r;
6044}
6045
6046void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6047{
f656ce01
MT		 6048 int idx;
6049
f5132b01 6050 kvm_pmu_destroy(vcpu);
36cb93fd 6051 kfree(vcpu->arch.mce_banks);
e9b11c17 6052 kvm_free_lapic(vcpu);
f656ce01 6053 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6054 kvm_mmu_destroy(vcpu);
f656ce01 6055 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6056 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6057}
d19a9cd2 6058
e08b9637 6059int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6060{
e08b9637
CO		 6061 if (type)
6062 return -EINVAL;
6063
f05e70ac 6064 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6065 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6066
5550af4d
SY		 6067 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6068 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6069
038f8c11 6070 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6071
d89f5eff 6072 return 0;
d19a9cd2
ZX		 6073}
6074
6075static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6076{
6077 vcpu_load(vcpu);
6078 kvm_mmu_unload(vcpu);
6079 vcpu_put(vcpu);
6080}
6081
6082static void kvm_free_vcpus(struct kvm *kvm)
6083{
6084 unsigned int i;
988a2cae 6085 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6086
6087 /*
6088 * Unpin any mmu pages first.
6089 */
af585b92
GN		 6090 kvm_for_each_vcpu(i, vcpu, kvm) {
6091 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6092 kvm_unload_vcpu_mmu(vcpu);
af585b92 6093 }
988a2cae
GN		 6094 kvm_for_each_vcpu(i, vcpu, kvm)
6095 kvm_arch_vcpu_free(vcpu);
6096
6097 mutex_lock(&kvm->lock);
6098 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6099 kvm->vcpus[i] = NULL;
d19a9cd2 6100
988a2cae
GN		 6101 atomic_set(&kvm->online_vcpus, 0);
6102 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6103}
6104
ad8ba2cd
SY		 6105void kvm_arch_sync_events(struct kvm *kvm)
6106{
ba4cef31 6107 kvm_free_all_assigned_devices(kvm);
aea924f6 6108 kvm_free_pit(kvm);
ad8ba2cd
SY		 6109}
6110
d19a9cd2
ZX		 6111void kvm_arch_destroy_vm(struct kvm *kvm)
6112{
6eb55818 6113 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6114 kfree(kvm->arch.vpic);
6115 kfree(kvm->arch.vioapic);
d19a9cd2 6116 kvm_free_vcpus(kvm);
3d45830c
AK		 6117 if (kvm->arch.apic_access_page)
6118 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6119 if (kvm->arch.ept_identity_pagetable)
6120 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6121}
0de10343 6122
f7784b8e
MT		 6123int kvm_arch_prepare_memory_region(struct kvm *kvm,
6124 struct kvm_memory_slot *memslot,
0de10343 6125 struct kvm_memory_slot old,
f7784b8e 6126 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6127 int user_alloc)
6128{
f7784b8e 6129 int npages = memslot->npages;
7ac77099
AK		 6130 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6131
6132 /* Prevent internal slot pages from being moved by fork()/COW. */
6133 if (memslot->id >= KVM_MEMORY_SLOTS)
6134 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6135
6136 /*To keep backward compatibility with older userspace,
6137 *x86 needs to hanlde !user_alloc case.
6138 */
6139 if (!user_alloc) {
6140 if (npages && !old.rmap) {
604b38ac
AA		 6141 unsigned long userspace_addr;
6142
72dc67a6 6143 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6144 userspace_addr = do_mmap(NULL, 0,
6145 npages * PAGE_SIZE,
6146 PROT_READ | PROT_WRITE,
7ac77099 6147 map_flags,
604b38ac 6148 0);
72dc67a6 6149 up_write(&current->mm->mmap_sem);
0de10343 6150
604b38ac
AA		 6151 if (IS_ERR((void *)userspace_addr))
6152 return PTR_ERR((void *)userspace_addr);
6153
604b38ac 6154 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6155 }
6156 }
6157
f7784b8e
MT		 6158
6159 return 0;
6160}
6161
6162void kvm_arch_commit_memory_region(struct kvm *kvm,
6163 struct kvm_userspace_memory_region *mem,
6164 struct kvm_memory_slot old,
6165 int user_alloc)
6166{
6167
48c0e4e9 6168 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6169
6170 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6171 int ret;
6172
6173 down_write(&current->mm->mmap_sem);
6174 ret = do_munmap(current->mm, old.userspace_addr,
6175 old.npages * PAGE_SIZE);
6176 up_write(&current->mm->mmap_sem);
6177 if (ret < 0)
6178 printk(KERN_WARNING
6179 "kvm_vm_ioctl_set_memory_region: "
6180 "failed to munmap memory\n");
6181 }
6182
48c0e4e9
XG		 6183 if (!kvm->arch.n_requested_mmu_pages)
6184 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6185
7c8a83b7 6186 spin_lock(&kvm->mmu_lock);
48c0e4e9 6187 if (nr_mmu_pages)
0de10343 6188 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6189 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6190 spin_unlock(&kvm->mmu_lock);
0de10343 6191}
1d737c8a 6192
34d4cb8f
MT		 6193void kvm_arch_flush_shadow(struct kvm *kvm)
6194{
6195 kvm_mmu_zap_all(kvm);
8986ecc0 6196 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6197}
6198
1d737c8a
ZX		 6199int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6200{
af585b92
GN		 6201 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6202 !vcpu->arch.apf.halted)
6203 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6204 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6205 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6206 (kvm_arch_interrupt_allowed(vcpu) &&
6207 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6208}
5736199a 6209
5736199a
ZX		 6210void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6211{
32f88400
MT		 6212 int me;
6213 int cpu = vcpu->cpu;
5736199a
ZX		 6214
6215 if (waitqueue_active(&vcpu->wq)) {
6216 wake_up_interruptible(&vcpu->wq);
6217 ++vcpu->stat.halt_wakeup;
6218 }
32f88400
MT		 6219
6220 me = get_cpu();
6221 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6222 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6223 smp_send_reschedule(cpu);
e9571ed5 6224 put_cpu();
5736199a 6225}
78646121
GN		 6226
6227int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6228{
6229 return kvm_x86_ops->interrupt_allowed(vcpu);
6230}
229456fc 6231
f92653ee
JK		 6232bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6233{
6234 unsigned long current_rip = kvm_rip_read(vcpu) +
6235 get_segment_base(vcpu, VCPU_SREG_CS);
6236
6237 return current_rip == linear_rip;
6238}
6239EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6240
94fe45da
JK		 6241unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6242{
6243 unsigned long rflags;
6244
6245 rflags = kvm_x86_ops->get_rflags(vcpu);
6246 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6247 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6248 return rflags;
6249}
6250EXPORT_SYMBOL_GPL(kvm_get_rflags);
6251
6252void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6253{
6254 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6255 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6256 rflags |= X86_EFLAGS_TF;
94fe45da 6257 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6258 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6259}
6260EXPORT_SYMBOL_GPL(kvm_set_rflags);
6261
56028d08
GN		 6262void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6263{
6264 int r;
6265
fb67e14f 6266 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6267 is_error_page(work->page))
56028d08
GN		 6268 return;
6269
6270 r = kvm_mmu_reload(vcpu);
6271 if (unlikely(r))
6272 return;
6273
fb67e14f
XG		 6274 if (!vcpu->arch.mmu.direct_map &&
6275 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6276 return;
6277
56028d08
GN		 6278 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6279}
6280
af585b92
GN		 6281static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6282{
6283 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6284}
6285
6286static inline u32 kvm_async_pf_next_probe(u32 key)
6287{
6288 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6289}
6290
6291static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6292{
6293 u32 key = kvm_async_pf_hash_fn(gfn);
6294
6295 while (vcpu->arch.apf.gfns[key] != ~0)
6296 key = kvm_async_pf_next_probe(key);
6297
6298 vcpu->arch.apf.gfns[key] = gfn;
6299}
6300
6301static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6302{
6303 int i;
6304 u32 key = kvm_async_pf_hash_fn(gfn);
6305
6306 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6307 (vcpu->arch.apf.gfns[key] != gfn &&
6308 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6309 key = kvm_async_pf_next_probe(key);
6310
6311 return key;
6312}
6313
6314bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6315{
6316 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6317}
6318
6319static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6320{
6321 u32 i, j, k;
6322
6323 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6324 while (true) {
6325 vcpu->arch.apf.gfns[i] = ~0;
6326 do {
6327 j = kvm_async_pf_next_probe(j);
6328 if (vcpu->arch.apf.gfns[j] == ~0)
6329 return;
6330 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6331 /*
6332 * k lies cyclically in ]i,j]
6333 * | i.k.j |
6334 * |....j i.k.| or |.k..j i...|
6335 */
6336 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6337 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6338 i = j;
6339 }
6340}
6341
7c90705b
GN		 6342static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6343{
6344
6345 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6346 sizeof(val));
6347}
6348
af585b92
GN		 6349void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6350 struct kvm_async_pf *work)
6351{
6389ee94
AK		 6352 struct x86_exception fault;
6353
7c90705b 6354 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6355 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6356
6357 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6358 (vcpu->arch.apf.send_user_only &&
6359 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6360 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6361 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6362 fault.vector = PF_VECTOR;
6363 fault.error_code_valid = true;
6364 fault.error_code = 0;
6365 fault.nested_page_fault = false;
6366 fault.address = work->arch.token;
6367 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6368 }
af585b92
GN		 6369}
6370
6371void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6372 struct kvm_async_pf *work)
6373{
6389ee94
AK		 6374 struct x86_exception fault;
6375
7c90705b
GN		 6376 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6377 if (is_error_page(work->page))
6378 work->arch.token = ~0; /* broadcast wakeup */
6379 else
6380 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6381
6382 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6383 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6384 fault.vector = PF_VECTOR;
6385 fault.error_code_valid = true;
6386 fault.error_code = 0;
6387 fault.nested_page_fault = false;
6388 fault.address = work->arch.token;
6389 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6390 }
e6d53e3b 6391 vcpu->arch.apf.halted = false;
7c90705b
GN		 6392}
6393
6394bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6395{
6396 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6397 return true;
6398 else
6399 return !kvm_event_needs_reinjection(vcpu) &&
6400 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6401}
6402
229456fc
MT		 6403EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6404EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6405EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6406EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6407EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6408EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6409EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6410EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6411EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6412EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6413EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6414EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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